| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: FNXPCIEXactorSignalInterface.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include <vera_defines.vrh> |
| 36 | |
| 37 | // XactorFmwork and XactorComponents libraries |
| 38 | #include "XactorBasePacket.vrh" |
| 39 | #include "XactorBaseSignalInterface.vrh" |
| 40 | #include "XactorCtrl.vrh" |
| 41 | #include "XactorUtilities.vrh" |
| 42 | #include "XactorDefines.vri" |
| 43 | #include "XactorClk.port.vri" |
| 44 | |
| 45 | // DenaliPCIE libary |
| 46 | #include "DenaliPCIE.vri" |
| 47 | |
| 48 | // FNXPCIEXactor library |
| 49 | #include "FNXPCIEXactorDefines.vri" |
| 50 | #include "FNXPCIEXactorPorts.vri" |
| 51 | // report library |
| 52 | #include "cReport.vrh" |
| 53 | #include "FNXPCIEXactorReportMacros.vri" |
| 54 | class FNXPCIEXactorSignalInterface extends XactorBaseSignalInterface { |
| 55 | // Inherited Members |
| 56 | // MyReport declared in XactorBaseSignalInterface |
| 57 | |
| 58 | // Base Class and Method Names For QR Macros |
| 59 | local string ClassName = "FNXPCIEXtrSgnlIntf"; |
| 60 | local string MethodName = null; |
| 61 | |
| 62 | local string XactorName; // Name of transactor |
| 63 | local integer PortNum; // PCIE Port Number |
| 64 | |
| 65 | local FNXPCIEXactorUtilities Util; // Xactor Utilities |
| 66 | |
| 67 | local FNXPCIEXactorAssertCovDatabase AssertCovDatabase; // Assertion Coverage Database |
| 68 | local FNXPCIEXactorStatsDatabase StatsDatabase; // Statistics Database |
| 69 | local FNXPCIEXactorReplayMonitor ReplayMonitor; // Replay Buffer Monitor |
| 70 | |
| 71 | local XactorCtrl xtrCtrl; |
| 72 | local XactorClk ClkPort; // Clock port |
| 73 | local FNXPCIEXactorDenaliClkPort DenaliClkPort; // Denali PCIE Clock Port |
| 74 | local FNXPCIEXactorDenaliDevice PCIEDevice; // Denali PCIE Device Reference For This Transactor |
| 75 | local FNXPCIEXactorMiscPort MiscPort; // 3/4/04 |
| 76 | local integer mToLinks; // To Links Mailbox |
| 77 | local integer mTLPsFromLinks; // TLPs From Links Mailbox |
| 78 | local integer mDLLPsFromLinks; // DLLPs From Links Mailbox |
| 79 | local integer mRetryExpectPipe; // Mailbox: Pipeline to Pass Retry Expects From Denali Callbacks to Xactor Builder |
| 80 | local integer mbluntendTXdata; // EP blunt end data transmit fifo |
| 81 | |
| 82 | |
| 83 | local bit sampleDllpToLink = 0; |
| 84 | local integer mDLLPsToLinks; // DLLPs To Links Mailbox |
| 85 | |
| 86 | local event eLinkUp; |
| 87 | local event eDLLActive; |
| 88 | local event eDLLPToLink; |
| 89 | local FNXPCIEXactorPacket sampledDllpPktToLink; |
| 90 | |
| 91 | // public members |
| 92 | bit ExpectOn; // Boolean: Enable/Disable Passing Sampled Packets to Expect Manager |
| 93 | bit TlpDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated TLP Discarding |
| 94 | bit ReplayMonitorOn; // Boolean: Enable/Disable Passing Packets to Replay Monitor |
| 95 | bit AckDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated ACK Discarding |
| 96 | bit FCDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated All Flow Control Discarding |
| 97 | bit FCPostDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated Posted Flow Control Discarding |
| 98 | bit FCNonPostDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated Non Posted Flow Control Discarding |
| 99 | bit FCCplDiscardOn; // Boolean: Enable/Disable Auto-Denali Generated Completion Flow Control Discarding |
| 100 | bit [8:0] linkNmbrTS1; //Used to pass in a new link number driven in TS1s bit[8]=kchar |
| 101 | bit [8:0] linkNmbrTS2; //Used to pass in a new link number driven in TS2s bit[8]=kchar |
| 102 | bit [8:0] laneNmbrTS1; //Used to pass in a new lane number driven in TS1s bit[8]=kchar |
| 103 | bit [8:0] laneNmbrTS2; //Used to pass in a new lane number driven in TS2s bit[8]=kchar |
| 104 | integer expectNullPkt = 0; //Keeps track of how many NULL packets are expected |
| 105 | |
| 106 | bit [11:0] currentSeqNum = 0; |
| 107 | bit [11:0] transmittedSeqNum = 0; |
| 108 | |
| 109 | // extended sync |
| 110 | integer fts_os_set_count; // use to count the fts os during RC TX_L0s.FTS extended sync scenario |
| 111 | bit count_4096FTS_1SKP = 0; |
| 112 | bit blunt_end = 0; |
| 113 | |
| 114 | task new( integer ExpectFifo, // incoming TLP transactions Fifo |
| 115 | integer DllpExpectFifo, // incoming DLLP transactions Fifo |
| 116 | integer DriveFifo, // outgoing TLP/DLLP transactions Fifo |
| 117 | integer RetryPktFifo, // retried TLP transactions Fifo |
| 118 | ReportClass _MyReport, // Reference to report object |
| 119 | string _XactorName, // Name of transactor |
| 120 | XactorCtrl _XactorCtrl, // Used to support disable/enable/reset Xactor |
| 121 | XactorClk _ClkPort, // Clock port |
| 122 | FNXPCIEXactorDenaliClkPort _DenaliClkPort, // Denali PCIE Clock Port |
| 123 | FNXPCIEXactorDenaliDevice _PCIEDevice, // Denali PCIE Device reference |
| 124 | FNXPCIEXactorMiscPort _MiscPort, // Port for Denali reset and Receive Detect signals |
| 125 | FNXPCIEXactorUtilities _Util, // Xactor Utilities |
| 126 | FNXPCIEXactorAssertCovDatabase _AssertCovDatabase, // Assertion Coverage Database |
| 127 | integer _PortNum, // PCIE Port Number |
| 128 | integer Bluntend_TX_fifo // EP blunt end data transmit fifo |
| 129 | ); |
| 130 | |
| 131 | // public methods |
| 132 | task WriteDenaliReg( integer iDenReg, bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data ); |
| 133 | function bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] ReadDenaliReg( integer iDenReg ); |
| 134 | task SetupBAR32( integer denReg, |
| 135 | integer addrWidth, |
| 136 | bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] baseAddr ); |
| 137 | task SetupBAR64( integer denRegLower, |
| 138 | integer denRegUpper, |
| 139 | integer addrWidth, |
| 140 | bit [FNX_PCIE_XTR_PCI_BAR_WIDTH*2-1:0] baseAddr ); |
| 141 | task SetReqID( bit [FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH-1:0] busNum, |
| 142 | bit [FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH-1:0] devNum, |
| 143 | bit [FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH-1:0] funcNum, |
| 144 | integer regOffset = 0 ); |
| 145 | task SuppressDenaliErr( denaliPcieErrorTypeT denErr ); |
| 146 | task tempSuppressDenaliErr( denaliPcieErrorTypeT denErr ); |
| 147 | task unSuppressDenaliErr( denaliPcieErrorTypeT denErr ); |
| 148 | task WaitLinkUp(); |
| 149 | task WaitDLLActive(); |
| 150 | function string GetEpilogueStr(); |
| 151 | task SetRcvDetMode( bit _rcvDetMode ); |
| 152 | task SetRcvDetLanes( bit[FNX_PCIE_XTR_RCV_DET_LANES_WIDTH-1:0] _rcvDetLanes ); |
| 153 | task SetDenaliReset( bit _denaliReset ); |
| 154 | task ResetReplayMonitor(); |
| 155 | task EnableSampleDllpToLink(); |
| 156 | task DisableSampleDllpToLink(); |
| 157 | task SampleDllpPktToLink( XactorBasePacket Pkt, integer Window ); |
| 158 | task SetElecIdleLanes( bit[FNX_PCIE_XTR_RCV_DET_LANES_WIDTH-1:0] _elecIdleLanes ); |
| 159 | task TransmitFTSToLink( integer nmbrFts ); |
| 160 | task TransmitSKPToLink( integer nmbrSkp ); |
| 161 | // task Transmit_symbol_ToLink( integer nmbrSymbol ); |
| 162 | // task TransmitOrdersetToLink( integer nmbrFts, bit [31:0] orderset ); |
| 163 | // task TransmitOrdersetToLink( integer nmbrFts, denaliPcieOrderedSet orderset ); |
| 164 | task Transmit_symbol_ToLink( integer nmbrSymbol , bit [8:0] symbol); |
| 165 | task TransmitTS1ToLink( integer nmbrTS1 ); |
| 166 | |
| 167 | ////////////////////////////////////////////////////////////// |
| 168 | // Begin -> private methods |
| 169 | // |
| 170 | local task DrivePackets(); |
| 171 | local task ProcessRegCbs(); |
| 172 | local task ProcessPktCbs(); |
| 173 | |
| 174 | // assertion coverage processiong methods |
| 175 | local task ProcessPktCb_assert_pass( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 176 | |
| 177 | // xmit callback processing methods |
| 178 | local task ProcessPktCb_TL_user_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 179 | local task ProcessPktCb_TL_user_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 180 | local task ProcessPktCb_TL_transmit_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 181 | local task ProcessPktCb_TL_transmit_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 182 | local task ProcessPktCb_TL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 183 | local task ProcessPktCb_DL_TX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 184 | local task ProcessPktCb_DL_TX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 185 | local task ProcessPktCb_DL_to_PL( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 186 | local task ProcessPktCb_PL_TX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 187 | local task ProcessPktCb_PL_TX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 188 | local task ProcessPktCb_TX_trans_done( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 189 | |
| 190 | // xmit replay buffer callback processing methods |
| 191 | local task ProcessPktCb_DL_TX_retry_buffer_enter( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 192 | local task ProcessPktCb_DL_TX_retry_buffer_exit( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 193 | local task ProcessPktCb_DL_TX_retry_buffer_purge( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 194 | |
| 195 | // receive callback processing methods |
| 196 | local task ProcessPktCb_PL_RX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 197 | local task ProcessPktCb_PL_RX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 198 | local task ProcessPktCb_DL_RX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 199 | local task ProcessPktCb_DL_RX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 200 | local task ProcessPktCb_PL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 201 | local task ProcessPktCb_DL_to_TL( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 202 | local task ProcessPktCb_TL_RX_packet( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 203 | |
| 204 | // completion callback processing methods |
| 205 | local task ProcessPktCb_TL_TX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 206 | local task ProcessPktCb_TL_TX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 207 | local task ProcessPktCb_TL_RX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 208 | local task ProcessPktCb_TL_RX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 209 | |
| 210 | // error callback processing methods |
| 211 | local task ProcessPktCb_TX_error( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 212 | local task ProcessPktCb_RX_error( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 213 | local task ProcessPktCb_error( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 214 | local task ProcessPktCb_unknown( FNXPCIEXactorPktCbRecord pktCbRecord ); |
| 215 | |
| 216 | // register callback processing methods |
| 217 | local task ProcessRegCbLTSSMState( FNXPCIEXactorRegCbRecord regCbRecord ); |
| 218 | local task ProcessRegCbDLCMSMState( FNXPCIEXactorRegCbRecord regCbRecord ); |
| 219 | local task ProcessRegCbTLPortState( FNXPCIEXactorRegCbRecord regCbRecord ); |
| 220 | local task ProcessRegCbDevCtrl( FNXPCIEXactorRegCbRecord regCbRecord ); |
| 221 | local task ProcessRegCbLinkState( FNXPCIEXactorRegCbRecord regCbRecord ); |
| 222 | // |
| 223 | // End -> private methods |
| 224 | ////////////////////////////////////////////////////////////// |
| 225 | |
| 226 | } // end of signal interface sub-class |
| 227 | |
| 228 | // constructor |
| 229 | task FNXPCIEXactorSignalInterface::new( integer ExpectFifo, // incoming TLP transactions Fifo |
| 230 | integer DllpExpectFifo, // incoming DLLP transactions Fifo |
| 231 | integer DriveFifo, // outgoing TLP/DLLP transactions Fifo |
| 232 | integer RetryPktFifo, // retried TLP transactions Fifo |
| 233 | ReportClass _MyReport, // Reference to report object |
| 234 | string _XactorName, // Name of transactor |
| 235 | XactorCtrl _XactorCtrl, // Used to support disable/enable/reset Xactor |
| 236 | XactorClk _ClkPort, // Clock port |
| 237 | FNXPCIEXactorDenaliClkPort _DenaliClkPort, // Denali PCIE Clock Port |
| 238 | FNXPCIEXactorDenaliDevice _PCIEDevice, // Denali PCIE Device reference |
| 239 | FNXPCIEXactorMiscPort _MiscPort, // Port for Denali reset and Receive Detect signals |
| 240 | FNXPCIEXactorUtilities _Util, // Xactor Utilities |
| 241 | FNXPCIEXactorAssertCovDatabase _AssertCovDatabase, // Assertion Coverage Database |
| 242 | integer _PortNum, // PCIE Port Number |
| 243 | integer Bluntend_TX_fifo // EP blunt end data transmit fifo |
| 244 | ) |
| 245 | { |
| 246 | MyReport = _MyReport; |
| 247 | XactorName = _XactorName; |
| 248 | xtrCtrl = _XactorCtrl; |
| 249 | ClkPort = _ClkPort; |
| 250 | DenaliClkPort = _DenaliClkPort; |
| 251 | PCIEDevice = _PCIEDevice; |
| 252 | Util = _Util; |
| 253 | AssertCovDatabase = _AssertCovDatabase; |
| 254 | PortNum = _PortNum; |
| 255 | MiscPort = _MiscPort; |
| 256 | |
| 257 | mToLinks = DriveFifo; |
| 258 | mTLPsFromLinks = ExpectFifo; |
| 259 | mDLLPsFromLinks = DllpExpectFifo; |
| 260 | mRetryExpectPipe = RetryPktFifo; |
| 261 | mbluntendTXdata = Bluntend_TX_fifo; |
| 262 | |
| 263 | //N2 DMT Bypass Link Train ExpectOn = 0; |
| 264 | ExpectOn = 1; |
| 265 | TlpDiscardOn = 1; |
| 266 | ReplayMonitorOn = 1; |
| 267 | sampleDllpToLink = 0; |
| 268 | AckDiscardOn = 0; |
| 269 | FCDiscardOn = 0; |
| 270 | FCPostDiscardOn = 0; |
| 271 | FCNonPostDiscardOn = 0; |
| 272 | FCCplDiscardOn = 0; |
| 273 | linkNmbrTS1 = 9'h100; |
| 274 | linkNmbrTS2 = 9'h100; |
| 275 | laneNmbrTS1 = 9'h100; |
| 276 | laneNmbrTS2 = 9'h100; |
| 277 | |
| 278 | |
| 279 | StatsDatabase = new( MyReport, XactorName ); |
| 280 | ReplayMonitor = new( MyReport, XactorName, Util, PortNum ); |
| 281 | // 9/16/04 Not sure why ReplayMonitor instantiated twice here - could have been a clearcase merge problem |
| 282 | // ReplayMonitor = new( MyReport, XactorName, Util, PortNum ); |
| 283 | |
| 284 | //Drive the rcvDetMode to fast simulation and rcvDetLanes to all 8 lanes as default |
| 285 | MiscPort.$rcvDetMode = 1'b0; //0 = 20nSec , 1 = 100 uSec |
| 286 | MiscPort.$rcvDetLanes = 8'hzz; //1 bit for each of the 8 lanes, 1 means a receiver is detected on that lane |
| 287 | MiscPort.$denaliReset = 1'b1; //Default to driven |
| 288 | MiscPort.$elecIdleLanes = 8'h00; //bit for each of the 8 lanes, |
| 289 | //1 means lane forced to electrical idle |
| 290 | |
| 291 | // extended sync |
| 292 | fts_os_set_count = 0; // use to count the fts os during RC TX_L0s.FTS extended sync scenario |
| 293 | // count_4096FTS_1SKP = 0; |
| 294 | |
| 295 | fork |
| 296 | { DrivePackets(); } |
| 297 | { ProcessPktCbs(); } |
| 298 | { ProcessRegCbs(); } |
| 299 | join none |
| 300 | } |
| 301 | |
| 302 | task FNXPCIEXactorSignalInterface::DrivePackets() |
| 303 | { |
| 304 | denaliPciePacket denPkt; |
| 305 | FNXPCIEXactorPacket fnxPkt; |
| 306 | FNXPCIEXactorUserData userData; |
| 307 | bit cast_ok; |
| 308 | integer status; |
| 309 | string MethodName = "DrivePackets"; |
| 310 | |
| 311 | while (1) { // continously process packets to be driven |
| 312 | |
| 313 | if (xtrCtrl.GetDisableFlag() === 1'b0 ) { // ensure xactor is enabled |
| 314 | |
| 315 | @(posedge ClkPort.$XClk); |
| 316 | |
| 317 | // retreive next packet to be driven |
| 318 | mailbox_get( WAIT, mToLinks, fnxPkt ); |
| 319 | |
| 320 | // Create Denali Packet To Be Driven From FNX PCIE Packet |
| 321 | denPkt = fnxPkt.CreateDenaliPkt(); |
| 322 | |
| 323 | // Place FNX PCIE Packet Into User Data of Denali Packet |
| 324 | userData = new(); |
| 325 | userData.SetPkt( fnxPkt ); |
| 326 | denPkt.setUserData( userData ); |
| 327 | |
| 328 | |
| 329 | // inject Null TLP if this error injection is activated |
| 330 | if (fnxPkt.DenaliErr == PCIE_EI_TLP_NULL) { |
| 331 | denPkt.setErrInject( PCIE_EI_TLP_NULL ); |
| 332 | PCIEX_QR_D3("AC: just call setErrInject(PCIE_EI_TlP_NULL) \n"); |
| 333 | } |
| 334 | |
| 335 | // inject ECRC if this error injection is activated |
| 336 | if (fnxPkt.DenaliErr == PCIE_EI_TLP_ENABLE_ECRC) { |
| 337 | denPkt.setErrInject( PCIE_EI_TLP_ENABLE_ECRC); |
| 338 | denPkt.setErrInject( PCIE_EI_RELAX_CHK ); |
| 339 | PCIEX_QR_D3("AC: just call setErrInject(PCIE_EI_TLP_ENABLE_ECRC) \n"); |
| 340 | } |
| 341 | |
| 342 | |
| 343 | |
| 344 | |
| 345 | // Add Denali Packet to Denali's User Queue |
| 346 | // status = PCIEDevice.transAdd( denPkt, 0 ); |
| 347 | if( !fnxPkt.DriveImmediately ){ |
| 348 | status = PCIEDevice.transAdd( denPkt, 0, DENALI_ARG_trans_append ); |
| 349 | } |
| 350 | else{ |
| 351 | status = PCIEDevice.transAdd( denPkt, 0, DENALI_ARG_trans_prepend ); |
| 352 | } |
| 353 | |
| 354 | // UNCOMMENT FOR DENALI DEBUG |
| 355 | // printf("<><>DENALI<><> Added to User Queue:\n"); |
| 356 | // denPkt.printInfo(); |
| 357 | |
| 358 | if(status != 0){ |
| 359 | PCIEX_QR_ERR( "%s-> Failed to Add Packet to Denali User Queue:\n%s", |
| 360 | XactorName, Util.DenaliPktToStr(denPkt,PortNum) ); |
| 361 | } |
| 362 | else if( fnxPkt.DriveImmediately ){ |
| 363 | PCIEX_QR_D3( "%s-> Added Packet to Beginning of Denali User Queue:\n%s", |
| 364 | XactorName, Util.DenaliPktToStr(denPkt,PortNum) ); |
| 365 | |
| 366 | |
| 367 | } |
| 368 | else{ |
| 369 | PCIEX_QR_D3( "%s-> Added Packet to End of Denali User Queue:\n%s", |
| 370 | XactorName, Util.DenaliPktToStr(denPkt,PortNum) ); |
| 371 | } |
| 372 | } |
| 373 | else // advance edge, then re-check enable |
| 374 | @(posedge ClkPort.$XClk); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | // process register callbacks received from Denali Xactor |
| 379 | task FNXPCIEXactorSignalInterface::ProcessRegCbs() |
| 380 | { |
| 381 | FNXPCIEXactorRegCbRecord regCbRecord; |
| 382 | string MethodName = "ProcessRegCbs"; |
| 383 | |
| 384 | while (1) { |
| 385 | |
| 386 | if (xtrCtrl.GetDisableFlag() === 1'b0 ) { // ensure xactor is enabled |
| 387 | |
| 388 | // blocks until next callback record is popped from malibox |
| 389 | regCbRecord = PCIEDevice.PopRegCbRecord(); |
| 390 | |
| 391 | PCIEX_QR_D2( "%s-> Callback Dequeued:\n %s", |
| 392 | XactorName, regCbRecord.GetStr() ); |
| 393 | |
| 394 | case (regCbRecord.Reg) { |
| 395 | PCIE_REG_DEN_LTSSM_STATE : ProcessRegCbLTSSMState( regCbRecord ); |
| 396 | PCIE_REG_DEN_DLCMSM_STATE : ProcessRegCbDLCMSMState( regCbRecord ); |
| 397 | PCIE_REG_DEN_LINK_ST : ProcessRegCbLinkState( regCbRecord ); |
| 398 | PCIE_REG_DEN_TLPORT_STATE : ProcessRegCbTLPortState( regCbRecord ); |
| 399 | PCIE_REG_DEN_DEV_CTRL : ProcessRegCbDevCtrl( regCbRecord ); |
| 400 | default : PCIEX_QR_D3( "%s-> Register Callback Has No Handler:\n %s", |
| 401 | XactorName, regCbRecord.GetStr() ); |
| 402 | } |
| 403 | |
| 404 | // Signal Callback Has Been Processed |
| 405 | regCbRecord.MarkProcessed(); |
| 406 | } |
| 407 | else // advance edge, then re-check enable |
| 408 | @(posedge ClkPort.$XClk); |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | |
| 413 | // process packet callbacks received from Denali Xactor |
| 414 | task FNXPCIEXactorSignalInterface::ProcessPktCbs() |
| 415 | { |
| 416 | FNXPCIEXactorPktCbRecord pktCbRecord; |
| 417 | string MethodName = "ProcessPktCbs"; |
| 418 | |
| 419 | while (1) { |
| 420 | |
| 421 | if (xtrCtrl.GetDisableFlag() === 1'b0 ) { // ensure xactor is enabled |
| 422 | |
| 423 | // blocks until next callback record is popped from malibox |
| 424 | pktCbRecord = PCIEDevice.PopPktCbRecord(); |
| 425 | |
| 426 | PCIEX_QR_D2( "%s-> Callback Dequeued:\n %s | Denali Packet Contents:\n%s", |
| 427 | XactorName, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) ); |
| 428 | |
| 429 | // UNCOMMENT FOR DENALI DEBUG |
| 430 | // printf("<><>DENALI<><> Callback Packet:\n"); |
| 431 | // pktCbRecord.Pkt.printInfo(); |
| 432 | |
| 433 | case (pktCbRecord.Rsn) { |
| 434 | // assertion coverage callbacks |
| 435 | PCIE_CB_assert_pass : ProcessPktCb_assert_pass( pktCbRecord ); |
| 436 | // xmit callbacks |
| 437 | PCIE_CB_TL_user_queue_enter : ProcessPktCb_TL_user_queue_enter( pktCbRecord ); |
| 438 | PCIE_CB_TL_user_queue_exit : ProcessPktCb_TL_user_queue_exit( pktCbRecord ); |
| 439 | PCIE_CB_TL_transmit_queue_enter : ProcessPktCb_TL_transmit_queue_enter( pktCbRecord ); |
| 440 | PCIE_CB_TL_transmit_queue_exit : ProcessPktCb_TL_transmit_queue_exit( pktCbRecord ); |
| 441 | PCIE_CB_TL_to_DL : ProcessPktCb_TL_to_DL( pktCbRecord ); |
| 442 | PCIE_CB_DL_TX_queue_enter : ProcessPktCb_DL_TX_queue_enter( pktCbRecord ); |
| 443 | PCIE_CB_DL_TX_queue_exit : ProcessPktCb_DL_TX_queue_exit( pktCbRecord ); |
| 444 | PCIE_CB_DL_to_PL : ProcessPktCb_DL_to_PL( pktCbRecord ); |
| 445 | PCIE_CB_PL_TX_start_packet : ProcessPktCb_PL_TX_start_packet( pktCbRecord ); |
| 446 | PCIE_CB_PL_TX_end_packet : ProcessPktCb_PL_TX_end_packet( pktCbRecord ); |
| 447 | PCIE_CB_TX_trans_done : ProcessPktCb_TX_trans_done( pktCbRecord ); |
| 448 | // replay callbacks |
| 449 | PCIE_CB_DL_TX_retry_buffer_enter : ProcessPktCb_DL_TX_retry_buffer_enter( pktCbRecord ); |
| 450 | PCIE_CB_DL_TX_retry_buffer_exit : ProcessPktCb_DL_TX_retry_buffer_exit( pktCbRecord ); |
| 451 | PCIE_CB_DL_TX_retry_buffer_purge : ProcessPktCb_DL_TX_retry_buffer_purge( pktCbRecord ); |
| 452 | // receive callbacks |
| 453 | PCIE_CB_PL_RX_start_packet : ProcessPktCb_PL_RX_start_packet( pktCbRecord ); |
| 454 | PCIE_CB_PL_RX_end_packet : ProcessPktCb_PL_RX_end_packet( pktCbRecord ); |
| 455 | PCIE_CB_DL_RX_queue_enter : ProcessPktCb_DL_RX_queue_enter( pktCbRecord ); |
| 456 | PCIE_CB_DL_RX_queue_exit : ProcessPktCb_DL_RX_queue_exit( pktCbRecord ); |
| 457 | PCIE_CB_PL_to_DL : ProcessPktCb_PL_to_DL( pktCbRecord ); |
| 458 | PCIE_CB_DL_to_TL : ProcessPktCb_DL_to_TL( pktCbRecord ); |
| 459 | PCIE_CB_TL_RX_packet : ProcessPktCb_TL_RX_packet( pktCbRecord ); |
| 460 | // completion callbacks |
| 461 | PCIE_CB_TL_TX_completion_queue_enter : ProcessPktCb_TL_TX_completion_queue_enter( pktCbRecord ); |
| 462 | PCIE_CB_TL_TX_completion_queue_exit : ProcessPktCb_TL_TX_completion_queue_exit( pktCbRecord ); |
| 463 | PCIE_CB_TL_RX_completion_queue_enter : ProcessPktCb_TL_RX_completion_queue_enter( pktCbRecord ); |
| 464 | PCIE_CB_TL_RX_completion_queue_exit : ProcessPktCb_TL_RX_completion_queue_exit( pktCbRecord ); |
| 465 | // error callbacks |
| 466 | PCIE_CB_TX_error : ProcessPktCb_TX_error( pktCbRecord ); |
| 467 | PCIE_CB_RX_error : ProcessPktCb_RX_error( pktCbRecord ); |
| 468 | PCIE_CB_error : ProcessPktCb_error( pktCbRecord ); |
| 469 | PCIE_CB_unknown : ProcessPktCb_unknown( pktCbRecord ); |
| 470 | // default -> no handler |
| 471 | default : PCIEX_QR_D3( "%s-> Callback Has No Handler:\n %s", |
| 472 | XactorName, pktCbRecord.GetStr() ); |
| 473 | } |
| 474 | |
| 475 | // Signal Callback Has Been Processed |
| 476 | pktCbRecord.MarkProcessed(); |
| 477 | } |
| 478 | else // advance edge, then re-check enable |
| 479 | @(posedge ClkPort.$XClk); |
| 480 | } |
| 481 | } |
| 482 | |
| 483 | task FNXPCIEXactorSignalInterface::ProcessPktCb_assert_pass( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 484 | { |
| 485 | string MethodName = "PPktCb_assert_pass"; |
| 486 | |
| 487 | AssertCovDatabase.Add( pktCbRecord.covPt ); |
| 488 | } |
| 489 | |
| 490 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_user_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 491 | { |
| 492 | FNXPCIEXactorUserData userData; |
| 493 | denaliPcieTlpPacket tlpPkt; |
| 494 | |
| 495 | denaliPcieTlpMsgPacket tlpMsgPkt; |
| 496 | denaliPcieTlpMsgTypeT msg_type; |
| 497 | |
| 498 | integer status; |
| 499 | string MethodName = "PPktCb_TL_user_queue_enter"; |
| 500 | |
| 501 | |
| 502 | // status = 1 if cast_assign is successful |
| 503 | status = (cast_assign( tlpMsgPkt, pktCbRecord.Pkt, CHECK) ); |
| 504 | // printf("tlpMsgPkt cast_assign status = %d \n", status); |
| 505 | |
| 506 | // get the message type if this is a message package |
| 507 | if (status == 1) { |
| 508 | msg_type = tlpMsgPkt.getMessageType(); |
| 509 | } |
| 510 | |
| 511 | // Discard Any TLPs Internally Generated By Denali Transactor (Excluding Replays) |
| 512 | if (cast_assign( tlpPkt, pktCbRecord.Pkt, CHECK) ) { // is a Denali TLP |
| 513 | |
| 514 | |
| 515 | if (TlpDiscardOn) { |
| 516 | // only discard if not msg || if msg is not = PME_TO_ack or PM_PME |
| 517 | |
| 518 | |
| 519 | // if ((status == 0 ) || (status == 1 && msg_type !== DENALI_PCIE_TL_MSG_PME_TO_Ack)) { |
| 520 | if (status == 1 && (msg_type == DENALI_PCIE_TL_MSG_PME_TO_Ack |
| 521 | || msg_type == DENALI_PCIE_TL_MSG_PM_PME )) { |
| 522 | PCIEX_QR_D1( "%s-> AC: PME_To_ACk message, so did not discard:\n%s", |
| 523 | XactorName, pktCbRecord.GetStr() ); |
| 524 | } |
| 525 | |
| 526 | else { |
| 527 | // not PME_TO_ACK nor PM_PME msg \n"); |
| 528 | |
| 529 | |
| 530 | // Mark TLP Packet to Be Discarded |
| 531 | userData = new(); |
| 532 | userData.SetDiscard(); |
| 533 | tlpPkt.setUserData( userData ); |
| 534 | tlpPkt.setErrInject( PCIE_EI_DISCARD ); // Set TLP to Be Discarded |
| 535 | status = tlpPkt.transSet(); // Pass Changes to Denali C Model |
| 536 | |
| 537 | if (status != 0) |
| 538 | PCIEX_QR_ERR( "%s-> transSet() Failed(%0d) For Callback:\n %s\n Denali Packet Contents:\n%s", |
| 539 | XactorName, status, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) ); |
| 540 | else |
| 541 | PCIEX_QR_D1( "%s-> Flagged Denali Generated TLP to be Discarded:\n%s", |
| 542 | XactorName, pktCbRecord.GetStr() ); |
| 543 | } |
| 544 | // else { |
| 545 | // PME_To_ACk message, so did not discard:\n%s", |
| 546 | // XactorName, pktCbRecord.GetStr() ); |
| 547 | // } |
| 548 | |
| 549 | } |
| 550 | } |
| 551 | |
| 552 | } |
| 553 | |
| 554 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_user_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 555 | { |
| 556 | FNXPCIEXactorPacket fnxPkt; |
| 557 | FNXPCIEXactorUserData userData; |
| 558 | denaliPciePacket denPkt; |
| 559 | denaliPcieDllpPacket dllpPkt; |
| 560 | integer status; |
| 561 | string MethodName = "PPktCb_TL_user_queue_exit"; |
| 562 | |
| 563 | if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor |
| 564 | |
| 565 | // Retrieve FNX PCIE Packet From Denali Packet's User Data |
| 566 | cast_assign( userData, pktCbRecord.Pkt.getUserData() ); |
| 567 | fnxPkt = userData.GetPkt(); |
| 568 | |
| 569 | if (fnxPkt != null) { |
| 570 | |
| 571 | // Set Denali Error Injection Type If Not NONE (After RELAX_CHK Is Cleared) |
| 572 | if (fnxPkt.DenaliErr !== PCIE_EI_NONE) { |
| 573 | if (cast_assign( denPkt, pktCbRecord.Pkt, CHECK ) ) |
| 574 | denPkt.setErrInject( fnxPkt.DenaliErr ); |
| 575 | PCIEX_QR_D3("AC: just call denPkt.setErrInject(%s) TL_user_queue_exit \n", fnxPkt.DenaliErr); |
| 576 | |
| 577 | status = denPkt.transSet(); // Pass Changes to Denali C Model |
| 578 | } |
| 579 | } |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_transmit_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 584 | { |
| 585 | string MethodName = "PPktCb_TL_transmit_queue_enter"; |
| 586 | |
| 587 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 588 | XactorName, pktCbRecord.GetStr() ); |
| 589 | } |
| 590 | |
| 591 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_transmit_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 592 | { |
| 593 | string MethodName = "PPktCb_TL_transmit_queue_exit"; |
| 594 | |
| 595 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 596 | XactorName, pktCbRecord.GetStr() ); |
| 597 | } |
| 598 | |
| 599 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 600 | { |
| 601 | denaliPcieTlpPacket tlpPkt; |
| 602 | FNXPCIEXactorPacket fnxPkt; |
| 603 | FNXPCIEXactorUserData userData; |
| 604 | string MethodName = "PPktCb_TL_to_DL"; |
| 605 | |
| 606 | if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor |
| 607 | |
| 608 | // Retrieve FNX PCIE Packet From Denali Packet's User Data |
| 609 | cast_assign( userData, pktCbRecord.Pkt.getUserData() ); |
| 610 | fnxPkt = userData.GetPkt(); |
| 611 | |
| 612 | if (fnxPkt != null) { |
| 613 | |
| 614 | // Retrieve Tag and ECRC for TLPs if Set to be Generated |
| 615 | if (cast_assign( tlpPkt, pktCbRecord.Pkt, CHECK)) { |
| 616 | |
| 617 | if ( fnxPkt.GenTag ) // Retrieve Tag |
| 618 | fnxPkt.ReqTag = tlpPkt.getTransactionIdTag(); |
| 619 | |
| 620 | if ( fnxPkt.GenECRC ) // Retrieve ECRC |
| 621 | fnxPkt.ECRC = tlpPkt.getEcrc(); |
| 622 | |
| 623 | fnxPkt.PktDisplay( RTYP_FNX_PCIE_XTR_DEBUG_2, psprintf("%s %s-> Packet Updated:", PCIEX_QR_PREFIX, XactorName )); |
| 624 | } |
| 625 | } |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_TX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 630 | { |
| 631 | |
| 632 | string MethodName = "PPktCb_DL_TX_queue_enter"; |
| 633 | |
| 634 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 635 | XactorName, pktCbRecord.GetStr() ); |
| 636 | } |
| 637 | |
| 638 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_TX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 639 | { |
| 640 | string MethodName = "PPktCb_DL_TX_queue_exit"; |
| 641 | |
| 642 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 643 | XactorName, pktCbRecord.GetStr() ); |
| 644 | } |
| 645 | |
| 646 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_to_PL( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 647 | { |
| 648 | denaliPcieDlpPacket dlpPkt; |
| 649 | denaliPcieDllpPacket dllpPkt; |
| 650 | denaliPciePlPacket plPkt; |
| 651 | denaliPcieDllpTypeT dllpType; |
| 652 | FNXPCIEXactorPacket fnxPkt; |
| 653 | FNXPCIEXactorUserData userData; |
| 654 | integer status; |
| 655 | bit [FNX_PCIE_XTR_DLL_FRM_LCRC_32_WIDTH-1:0] DLLLCRC32; |
| 656 | bit [FNX_PCIE_XTR_DLL_FRM_LCRC_32_WIDTH-1:0] temp_DLLLCRC32; |
| 657 | string MethodName = "PPktCb_DL_to_PL"; |
| 658 | |
| 659 | if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor |
| 660 | |
| 661 | // Retrieve FNX PCIE Packet From Denali Packet's User Data |
| 662 | cast_assign( userData, pktCbRecord.Pkt.getUserData() ); |
| 663 | fnxPkt = userData.GetPkt(); |
| 664 | |
| 665 | if (fnxPkt != null) { |
| 666 | |
| 667 | /////////////////////////////////////////////////////// |
| 668 | // Begin -> Update TLP |
| 669 | // |
| 670 | // Retrieve DLL Framing Fields From Denali and Place in FNXPCIEXactorPacket |
| 671 | if (fnxPkt.isTlp()) { |
| 672 | if (cast_assign(dlpPkt, pktCbRecord.Pkt, CHECK)) { |
| 673 | |
| 674 | if ( fnxPkt.GenLCRC32 ) // Retrieve 32-bit LCRC |
| 675 | { |
| 676 | fnxPkt.DLLFrmLCRC32 = dlpPkt.getLcrc(); |
| 677 | DLLLCRC32 = fnxPkt.DLLFrmLCRC32; |
| 678 | } |
| 679 | |
| 680 | if ( fnxPkt.GenSeqNum ) // Retrieve Seq Number |
| 681 | fnxPkt.DLLFrmSeqNum = dlpPkt.getTlpSeqNum(); |
| 682 | |
| 683 | fnxPkt.PktDisplay( RTYP_FNX_PCIE_XTR_DEBUG_2, psprintf("%s %s-> Packet initial Updated:", PCIEX_QR_PREFIX, XactorName )); |
| 684 | |
| 685 | |
| 686 | |
| 687 | //: //================================================================= |
| 688 | // added for invert 32-bit LCRC, and injection of END/EDB symbols |
| 689 | //: //================================================================= |
| 690 | //: if( fnxPkt.invertLCRC32) // invert the 32-bit LCRC |
| 691 | //: { |
| 692 | //: fnxPkt.DLLFrmLCRC32 = ~(DLLLCRC32); |
| 693 | //: dlpPkt.setLcrc(fnxPkt.DLLFrmLCRC32); |
| 694 | //: status = dlpPkt.transSet(); // Pass Changes to Denali C Model |
| 695 | //: temp_DLLLCRC32 = dlpPkt.getLcrc(); |
| 696 | // fnxPkt.invertLCRC32 = 0; // once set, then remove the force setting |
| 697 | //: // let the non force version from retry buffer go through on replay |
| 698 | // at time %d, invertLCRC32 is set = %d, fnx.LCRC32 = %0d'h%h dlpPkt.LCRC32 = %h\n", get_time(LO), fnxPkt.invertLCRC32, |
| 699 | //: FNX_PCIE_XTR_DLL_FRM_LCRC_32_WIDTH, fnxPkt.DLLFrmLCRC32, temp_DLLLCRC32 ); |
| 700 | //: } |
| 701 | |
| 702 | } |
| 703 | |
| 704 | //FNXPCIEXactorSignalInterface.vr: fnxPkt.set_endsymbol_EDB = %d \n", fnxPkt.set_endsymbol_EDB) ; |
| 705 | |
| 706 | // // processing end symbol |
| 707 | // if (cast_assign( plPkt, pktCbRecord.Pkt, CHECK )) { |
| 708 | // fnxPkt.EndFrame = plPkt.getEndFrame(); |
| 709 | // inside cast_assign of pktCbRecord.Pkt \n"); |
| 710 | // if (fnxPkt.set_endsymbol_EDB) // end symbol = EDB |
| 711 | // { |
| 712 | // fnxPkt.EndFrame = PCIE_EDB_SYMBOL; |
| 713 | // fnxPkt.EndFrame = 9'h1FE; |
| 714 | // plPkt.setEndFrame(fnxPkt.EndFrame); |
| 715 | // status = plPkt.transSet(); // Pass Changes to Denali C Model |
| 716 | // fnxPkt.set_endsymbol_EDB = 0; // once set, then remove the force setting |
| 717 | // // let the non force version from retry buffer go through on replay |
| 718 | // set_endsymbol_EDB is set = %d, EndFrame = %s \n", fnxPkt.set_endsymbol_EDB, |
| 719 | // fnxPkt.EndFrame ); |
| 720 | // } |
| 721 | // |
| 722 | // } // end process end symbol |
| 723 | |
| 724 | |
| 725 | |
| 726 | } |
| 727 | // End -> Update TLP |
| 728 | /////////////////////////////////////////////////////// |
| 729 | |
| 730 | /////////////////////////////////////////////////////// |
| 731 | // Begin -> Update DLLP |
| 732 | // |
| 733 | // Retrieve DLL Generated Fields From Denali and Place in FNXPCIEXactorPacket |
| 734 | if (fnxPkt.isDllp()) { |
| 735 | if (cast_assign(dllpPkt, pktCbRecord.Pkt, CHECK)) { |
| 736 | |
| 737 | if (fnxPkt.GenLCRC16) |
| 738 | fnxPkt.DllpLCRC16 = dllpPkt.getLcrc(); |
| 739 | } |
| 740 | } |
| 741 | // End -> Update DLLP |
| 742 | /////////////////////////////////////////////////////// |
| 743 | |
| 744 | } |
| 745 | }else{ //// packet was generated by Denali |
| 746 | if (cast_assign(dllpPkt, pktCbRecord.Pkt, CHECK)) { |
| 747 | |
| 748 | // Discard Any Dllp ACKs Internally Generated By Denali Transactor |
| 749 | dllpType = dllpPkt.getDllpType(); |
| 750 | if( AckDiscardOn && ( dllpType == DENALI_PCIE_DL_ACK) ){ |
| 751 | |
| 752 | dllpPkt.setErrInject( PCIE_EI_DISCARD ); // Set DLLP to Be Discarded |
| 753 | status = dllpPkt.transSet(); // Pass Changes to Denali C Model |
| 754 | if (status != 0) |
| 755 | PCIEX_QR_ERR( "%s:ProcessPktCb_DL_to_PL-> transSet() Failed(%0d) For Callback:\n %s\n Denali Packet Contents:\n%s", XactorName, status, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) ); |
| 756 | else |
| 757 | PCIEX_QR_D1( "%s-> Flagged Denali Generated Dllp ACK to be Discarded:\n%s", XactorName, pktCbRecord.GetStr() ); |
| 758 | } |
| 759 | |
| 760 | if( (FCDiscardOn && (( dllpType == DENALI_PCIE_DL_UPDATE_FC_P) || |
| 761 | ( dllpType == DENALI_PCIE_DL_UPDATE_FC_NP) || |
| 762 | ( dllpType == DENALI_PCIE_DL_UPDATE_FC_CPL) )) |
| 763 | ||(FCPostDiscardOn && (( dllpType == DENALI_PCIE_DL_UPDATE_FC_P))) |
| 764 | ||(FCNonPostDiscardOn && (( dllpType == DENALI_PCIE_DL_UPDATE_FC_NP))) |
| 765 | ||(FCCplDiscardOn && (( dllpType == DENALI_PCIE_DL_UPDATE_FC_CPL))) ){ |
| 766 | |
| 767 | dllpPkt.setErrInject( PCIE_EI_DISCARD ); // Set DLLP to Be Discarded |
| 768 | status = dllpPkt.transSet(); // Pass Changes to Denali C Model |
| 769 | if (status != 0) |
| 770 | PCIEX_QR_ERR( "%s:ProcessPktCb_DL_to_PL-> transSet() Failed(%0d) For Callback:\n %s\n Denali Packet Contents:\n%s", XactorName, status, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) ); |
| 771 | else |
| 772 | PCIEX_QR_D1( "%s-> Flagged Denali Generated Dllp FC to be Discarded:\n%s", XactorName, pktCbRecord.GetStr() ); |
| 773 | } |
| 774 | } |
| 775 | } |
| 776 | } |
| 777 | |
| 778 | |
| 779 | |
| 780 | |
| 781 | task FNXPCIEXactorSignalInterface::ProcessPktCb_PL_TX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 782 | { |
| 783 | string MethodName = "PPktCb_PL_TX_start_packet"; |
| 784 | FNXPCIEXactorPacket fnxPkt; |
| 785 | FNXPCIEXactorUserData userData; |
| 786 | denaliPcieTrainingSet tsPkt; |
| 787 | |
| 788 | denaliPciePlPacket plPkt; |
| 789 | denaliPcieDlpPacket dlpPkt; |
| 790 | |
| 791 | bit[8:0] linkNumber[*]; |
| 792 | bit[8:0] linkNmbr; |
| 793 | bit[8:0] laneNumber[*]; |
| 794 | bit[8:0] laneNmbr; |
| 795 | integer size; |
| 796 | integer i; |
| 797 | integer status; |
| 798 | |
| 799 | if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor |
| 800 | |
| 801 | //Keep track of sequence numbers |
| 802 | if (cast_assign(dlpPkt, pktCbRecord.Pkt, CHECK)) { |
| 803 | currentSeqNum = dlpPkt.getTlpSeqNum(); |
| 804 | if( currentSeqNum == (transmittedSeqNum + 1)%4096 ){ //This |
| 805 | transmittedSeqNum += 1; |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | // Retrieve FNX PCIE Packet From Denali Packet's User Data |
| 810 | cast_assign( userData, pktCbRecord.Pkt.getUserData() ); |
| 811 | fnxPkt = userData.GetPkt(); |
| 812 | |
| 813 | // processing end symbol |
| 814 | //FNXPCIEXactorSignalInterface.vr: fnxPkt.set_endsymbol_EDB = %d \n", fnxPkt.set_endsymbol_EDB) ; |
| 815 | if (cast_assign( plPkt, pktCbRecord.Pkt, CHECK )) { |
| 816 | fnxPkt.EndFrame = plPkt.getEndFrame(); |
| 817 | if (fnxPkt.set_endsymbol_EDB) // end symbol = EDB |
| 818 | { |
| 819 | // fnxPkt.EndFrame = PCIE_EDB_SYMBOL; |
| 820 | fnxPkt.EndFrame = 9'h1FE; |
| 821 | plPkt.setEndFrame(fnxPkt.EndFrame); |
| 822 | status = plPkt.transSet(); // Pass Changes to Denali C Model |
| 823 | fnxPkt.set_endsymbol_EDB = 0; // once set, then remove the force setting so during retry, it will not force EDB on again |
| 824 | // let the non force version from retry buffer go through on replay |
| 825 | printf("AC: at time = %d, set_endsymbol_EDB is set = %d, EndFrame = %h \n", get_time(LO), fnxPkt.set_endsymbol_EDB, |
| 826 | fnxPkt.EndFrame ); |
| 827 | } |
| 828 | |
| 829 | } // end process end symbol |
| 830 | |
| 831 | |
| 832 | |
| 833 | // Mark Packet As Starting To Be Driven |
| 834 | fnxPkt.TriggerDriveStart(); |
| 835 | } |
| 836 | else{ |
| 837 | //If enabled change the Link number transmitted for TSx's |
| 838 | if( cast_assign( tsPkt, pktCbRecord.Pkt, CHECK) ){ |
| 839 | if( (tsPkt.getOsType() == DENALI_PCIE_PL__ts1_set) && linkNmbrTS1 !== 9'h100 ){ |
| 840 | |
| 841 | tsPkt.getLinkNumber( linkNumber ); |
| 842 | size = linkNumber.size(); |
| 843 | for( i=0; i<size; i++ ){ |
| 844 | linkNumber[i] = linkNmbrTS1; |
| 845 | } |
| 846 | |
| 847 | //Pass the array to the TS packet |
| 848 | tsPkt.setLinkNumber( linkNumber ); |
| 849 | //Make sure the TS packet is updated |
| 850 | status = pktCbRecord.Pkt.transSet(); // Pass Changes to Denali C Model |
| 851 | if( status != 0 ){ |
| 852 | PCIEX_QR_ERR( "%s:ProcessPktCb_PL_TX_start_packet-> transSet() Failed(%0d) For Callback:\n", XactorName, status ); |
| 853 | } |
| 854 | else{ |
| 855 | PCIEX_QR_D1( "%s->Changed link Number to %0h in TS1 !\n% s", MethodName, linkNmbrTS1 ); |
| 856 | } |
| 857 | } //End TS1 |
| 858 | if( (tsPkt.getOsType() == DENALI_PCIE_PL__ts2_set) && linkNmbrTS2 !== 9'h100 ){ |
| 859 | tsPkt.getLinkNumber( linkNumber ); |
| 860 | size = linkNumber.size(); |
| 861 | for( i=0; i<size; i++ ){ |
| 862 | linkNumber[i] = linkNmbrTS2; |
| 863 | } |
| 864 | |
| 865 | //Pass the array to the TS packet |
| 866 | tsPkt.setLinkNumber( linkNumber ); |
| 867 | //Make sure the TS packet is updated |
| 868 | status = pktCbRecord.Pkt.transSet(); // Pass Changes to Denali C Model |
| 869 | if( status != 0 ){ |
| 870 | PCIEX_QR_ERR( "%s:ProcessPktCb_PL_TX_start_packet-> transSet() Failed(%0d) For Callback:\n", XactorName, status ); |
| 871 | } |
| 872 | else{ |
| 873 | PCIEX_QR_D1( "%s->Changed link Number to %0h in TS2 !\n% s", MethodName, linkNmbrTS2 ); |
| 874 | } |
| 875 | } //End TS2 |
| 876 | |
| 877 | if( (tsPkt.getOsType() == DENALI_PCIE_PL__ts1_set) && laneNmbrTS1 !== 9'h100 ){ |
| 878 | |
| 879 | tsPkt.getLaneNumber( laneNumber ); |
| 880 | size = laneNumber.size(); |
| 881 | for( i=0; i<size; i++ ){ |
| 882 | if( laneNmbrTS1[8] ){ |
| 883 | laneNumber[i] = laneNmbrTS1; //for Kchars |
| 884 | } |
| 885 | else{ |
| 886 | laneNumber[i] = laneNmbrTS1 + i; |
| 887 | } |
| 888 | } |
| 889 | |
| 890 | //Pass the array to the TS packet |
| 891 | tsPkt.setLaneNumber( laneNumber ); |
| 892 | //Make sure the TS packet is updated |
| 893 | status = pktCbRecord.Pkt.transSet(); // Pass Changes to Denali C Model |
| 894 | if( status != 0 ){ |
| 895 | PCIEX_QR_ERR( "%s:ProcessPktCb_PL_TX_start_packet-> transSet() Failed(%0d) For Callback setLaneNumber:\n", XactorName, status ); |
| 896 | } |
| 897 | else{ |
| 898 | PCIEX_QR_D1( "%s->Changed lane Number to %0h in TS1 !\n% s", MethodName, laneNmbrTS1 ); |
| 899 | } |
| 900 | } //End TS1 |
| 901 | if( (tsPkt.getOsType() == DENALI_PCIE_PL__ts2_set) && laneNmbrTS2 !== 9'h100 ){ |
| 902 | |
| 903 | tsPkt.getLaneNumber( laneNumber ); |
| 904 | size = laneNumber.size(); |
| 905 | for( i=0; i<size; i++ ){ |
| 906 | if( laneNmbrTS2[8] ){ |
| 907 | laneNumber[i] = laneNmbrTS2; //for Kchars |
| 908 | } |
| 909 | else{ |
| 910 | laneNumber[i] = laneNmbrTS2 + i; |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | //Pass the array to the TS packet |
| 915 | tsPkt.setLaneNumber( laneNumber ); |
| 916 | //Make sure the TS packet is updated |
| 917 | status = pktCbRecord.Pkt.transSet(); // Pass Changes to Denali C Model |
| 918 | if( status != 0 ){ |
| 919 | PCIEX_QR_ERR( "%s:ProcessPktCb_PL_TX_start_packet-> transSet() Failed(%0d) For Callback setLaneNumber:\n", XactorName, status ); |
| 920 | } |
| 921 | else{ |
| 922 | PCIEX_QR_D1( "%s->Changed lane Number to %0h in TS2 !\n% s", MethodName, laneNmbrTS2 ); |
| 923 | } |
| 924 | } //End TS2 |
| 925 | |
| 926 | } |
| 927 | } |
| 928 | } |
| 929 | |
| 930 | task FNXPCIEXactorSignalInterface::ProcessPktCb_PL_TX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 931 | { |
| 932 | FNXPCIEXactorPacket fnxPkt; |
| 933 | FNXPCIEXactorUserData userData; |
| 934 | denaliPcieDllpPacket dllpPkt; |
| 935 | denaliPciePllpPacket pllpPkt; |
| 936 | denaliPcieDllpTypeT dllpType; |
| 937 | bit [8:0] pktData[*], dllpData[*]; |
| 938 | |
| 939 | denaliPciePlPacket plPkt; |
| 940 | string tmpStr; |
| 941 | integer i; |
| 942 | |
| 943 | |
| 944 | integer status; |
| 945 | string MethodName = "PPktCb_PL_TX_end_packet"; |
| 946 | |
| 947 | // for blunt end |
| 948 | denaliPcieRawPacket rawPkt; |
| 949 | bit [8:0] TX_rawpktdata[*]; |
| 950 | |
| 951 | if (blunt_end) { |
| 952 | if (cast_assign(rawPkt, pktCbRecord.Pkt, CHECK)) { // packet is a Raw packet |
| 953 | printf("AC: blunt_end, packet is rawdata \n"); |
| 954 | |
| 955 | // place transmit data info mailbox for comparison with RX data |
| 956 | if (rawPkt.getPktType() == DENALI_PCIE__RawData) { // packet is a Raw data |
| 957 | |
| 958 | // do not put into mailbox the first 3 COMs |
| 959 | rawPkt.getPktData( TX_rawpktdata ); |
| 960 | if (TX_rawpktdata[0] == PCIE_SYMBOL_K28__5 ) { |
| 961 | printf("AC: time = %d, blunt end rawdata == COM, remember to not put into mailbox \n", get_time(LO)); |
| 962 | } |
| 963 | // place data into mailbox |
| 964 | // mailbox_put(mbluntendTXdata, TX_rawdata); |
| 965 | mailbox_put(mbluntendTXdata, rawPkt); |
| 966 | rawPkt.printInfo(); |
| 967 | printf("AC: blunt end transmit data is put into mbluntendTXdata mailbox"); |
| 968 | |
| 969 | } |
| 970 | } |
| 971 | |
| 972 | |
| 973 | } // blunt end |
| 974 | |
| 975 | else { |
| 976 | if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor |
| 977 | |
| 978 | // Retrieve FNX PCIE Packet From Denali Packet's User Data |
| 979 | cast_assign( userData, pktCbRecord.Pkt.getUserData() ); |
| 980 | fnxPkt = userData.GetPkt(); |
| 981 | |
| 982 | // Mark Packet As Done Being Driven and Update Statistics Database |
| 983 | if (fnxPkt != null) { |
| 984 | |
| 985 | // // nullify if EDB and invertLCRC |
| 986 | // if (fnxPkt.set_endsymbol_EDB && fnxPkt.invertLCRC32) // end symbol = EDB |
| 987 | // { |
| 988 | // if (cast_assign( plPkt, pktCbRecord.Pkt, CHECK)) { |
| 989 | // tlpPkt.setErrInject( PCIE_EI_DISCARD ); // Set TLP to Be Discarded |
| 990 | // status = tlpPkt.transSet(); // Pass Changes to Denali C Model |
| 991 | // plPkt.setErrInject( PCIE_EI_DISCARD ); // Set TLP to Be Discarded |
| 992 | // status = plPkt.transSet(); // Pass Changes to Denali C Model |
| 993 | // %s, null package \n"); |
| 994 | // } |
| 995 | // } |
| 996 | |
| 997 | |
| 998 | fnxPkt.TriggerDriveEnd(); |
| 999 | PCIEX_QR_D3("AC: FNXSgnIntf.PL_TX_end_packet: packet driven \n"); |
| 1000 | if( fnxPkt.ReplayInProgress ){ |
| 1001 | |
| 1002 | fnxPkt.TriggerReplayEnd(); |
| 1003 | fnxPkt.ReplayCnt += 1; |
| 1004 | fnxPkt.ReplayInProgress = 0; |
| 1005 | } |
| 1006 | StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_XMIT ); |
| 1007 | } |
| 1008 | |
| 1009 | |
| 1010 | //Need to know when testbench has driven specific packets |
| 1011 | // especially NAKs |
| 1012 | if( sampleDllpToLink ){ |
| 1013 | if (cast_assign( pllpPkt, pktCbRecord.Pkt, CHECK)) { |
| 1014 | |
| 1015 | // Retrieve Raw DLLP Packet Byte Stream |
| 1016 | fnxPkt = new( MyReport, XactorName, Util, PortNum ); |
| 1017 | pllpPkt.getPktData( pktData ); |
| 1018 | |
| 1019 | // Create DLLP Data Stream From PL Data Stream |
| 1020 | dllpData = new[FNX_PCIE_XTR_NUM_DLLP_BYTES]; |
| 1021 | for (i=1; i <= FNX_PCIE_XTR_NUM_DLLP_BYTES; i++) |
| 1022 | dllpData[i-1] = pktData[i]; |
| 1023 | |
| 1024 | // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields |
| 1025 | fnxPkt.ParseDLLPByteStream( dllpData ); |
| 1026 | |
| 1027 | //Add packet to fifo that upper level testbench can get access to |
| 1028 | if( sampleDllpToLink ){ |
| 1029 | //Make sure packet starts off clean |
| 1030 | sampledDllpPktToLink.PktReset(); |
| 1031 | //Copy the packet so it can be passed |
| 1032 | sampledDllpPktToLink.PktCopy( fnxPkt ); |
| 1033 | |
| 1034 | //Trigger event to notify a dllp packet has been sent to the DUT |
| 1035 | trigger( ONE_BLAST, eDLLPToLink ); |
| 1036 | } |
| 1037 | } |
| 1038 | } |
| 1039 | } |
| 1040 | else { // packet was driven by Denali |
| 1041 | // If Denali Packet is DLLP Print Contents at Debug Level 1 |
| 1042 | if (cast_assign( pllpPkt, pktCbRecord.Pkt, CHECK)) { |
| 1043 | |
| 1044 | // Retrieve Raw DLLP Packet Byte Stream |
| 1045 | fnxPkt = new( MyReport, XactorName, Util, PortNum ); |
| 1046 | pllpPkt.getPktData( pktData ); |
| 1047 | |
| 1048 | // Create DLLP Data Stream From PL Data Stream |
| 1049 | dllpData = new[FNX_PCIE_XTR_NUM_DLLP_BYTES]; |
| 1050 | for (i=1; i <= FNX_PCIE_XTR_NUM_DLLP_BYTES; i++) |
| 1051 | dllpData[i-1] = pktData[i]; |
| 1052 | |
| 1053 | // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields |
| 1054 | fnxPkt.ParseDLLPByteStream( dllpData ); |
| 1055 | |
| 1056 | //Add packet to fifo that upper level testbench can get access to |
| 1057 | if( sampleDllpToLink ){ |
| 1058 | //Make sure packet starts off clean |
| 1059 | sampledDllpPktToLink.PktReset(); |
| 1060 | //Copy the packet so it can be passed |
| 1061 | sampledDllpPktToLink.PktCopy( fnxPkt ); |
| 1062 | |
| 1063 | //Trigger event to notify a dllp packet has been sent to the DUT |
| 1064 | trigger( ONE_BLAST, eDLLPToLink ); |
| 1065 | } |
| 1066 | |
| 1067 | StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_XMIT ); |
| 1068 | |
| 1069 | PCIEX_QR_D2( "%s-> Denali DLLP Driven.\n%s", XactorName, fnxPkt.PktToStr() ); |
| 1070 | } |
| 1071 | } |
| 1072 | } // else blunt end |
| 1073 | } |
| 1074 | |
| 1075 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TX_trans_done( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1076 | { |
| 1077 | string MethodName = "PPktCb_TX_trans_done"; |
| 1078 | |
| 1079 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1080 | XactorName, pktCbRecord.GetStr() ); |
| 1081 | } |
| 1082 | |
| 1083 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_TX_retry_buffer_enter( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1084 | { |
| 1085 | string MethodName = "PPktCb_DL_TX_retry_buffer_enter"; |
| 1086 | |
| 1087 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1088 | XactorName, pktCbRecord.GetStr() ); |
| 1089 | } |
| 1090 | |
| 1091 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_TX_retry_buffer_exit( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1092 | { |
| 1093 | FNXPCIEXactorPacket fnxPkt; |
| 1094 | FNXPCIEXactorUserData userData; |
| 1095 | string MethodName = "PPktCb_DL_TX_retry_buffer_exit"; |
| 1096 | |
| 1097 | |
| 1098 | denaliPcieTlpPacket tlpPkt; |
| 1099 | integer status; |
| 1100 | |
| 1101 | //XXXXXXXXXXXXXXXXXXXXx review |
| 1102 | //Remove any errors that were injected in the original packet |
| 1103 | // if (cast_assign( tlpPkt, pktCbRecord.Pkt, CHECK) ) { // is a Denali TLP |
| 1104 | |
| 1105 | pktCbRecord.Pkt.setErrInject( PCIE_EI_NONE ); // Clear any injected Errors |
| 1106 | status = pktCbRecord.Pkt.transSet(); // Pass Changes to Denali C Model |
| 1107 | if (status != 0) |
| 1108 | PCIEX_QR_ERR( "%s:ProcessPktCb_DL_TX_retry_buffer_exit-> transSet() Failed(%0d) For Callback:\n %s\n Denali Packet Contents:\n%s", XactorName, status, pktCbRecord.GetStr(), Util.DenaliPktToStr(pktCbRecord.Pkt,PortNum) ); |
| 1109 | else |
| 1110 | PCIEX_QR_D1( "%s-> setErrInject( PCIE_EI_NONE ) for TX_retry_buffer_exit successful!\n%s", XactorName, pktCbRecord.GetStr() ); |
| 1111 | |
| 1112 | // } |
| 1113 | |
| 1114 | //XXXXXXXXXXXXXXXXXXx review |
| 1115 | |
| 1116 | if ( pktCbRecord.Pkt.getUserData() != null ) { // packet was driven by FNX Xactor |
| 1117 | |
| 1118 | // Retrieve FNX PCIE Packet From Denali Packet's User Data |
| 1119 | cast_assign( userData, pktCbRecord.Pkt.getUserData() ); |
| 1120 | fnxPkt = userData.GetPkt(); |
| 1121 | |
| 1122 | if (fnxPkt != null) |
| 1123 | fnxPkt.ReplayInProgress = 1; //Used to help signal replayed packet is reTransmitted |
| 1124 | fnxPkt.PktDisplay( RTYP_FNX_PCIE_XTR_INFO, psprintf("%s %s-> Retrying Packet:", PCIEX_QR_PREFIX, XactorName )); |
| 1125 | } |
| 1126 | } |
| 1127 | |
| 1128 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_TX_retry_buffer_purge( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1129 | { |
| 1130 | string MethodName = "PPktCb_DL_TX_retry_buffer_purge"; |
| 1131 | |
| 1132 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1133 | XactorName, pktCbRecord.GetStr() ); |
| 1134 | } |
| 1135 | |
| 1136 | task FNXPCIEXactorSignalInterface::ProcessPktCb_PL_RX_start_packet( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1137 | { |
| 1138 | // for blunt end |
| 1139 | denaliPcieRawPacket rawPkt; |
| 1140 | bit [8:0] RX_rawpktdata[*]; |
| 1141 | // bit [8:0] expected_bluntendPktdata[*]; |
| 1142 | denaliPcieRawPacket expected_bluntendPkt; |
| 1143 | |
| 1144 | // for extended sync |
| 1145 | // denaliPcieTrainingSet osPkt; |
| 1146 | denaliPcieOrderedSet osPkt; |
| 1147 | |
| 1148 | |
| 1149 | bit bluntend_compare_start = 0; |
| 1150 | |
| 1151 | |
| 1152 | string MethodName = "PPktCb_PL_RX_start_packet"; |
| 1153 | |
| 1154 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1155 | XactorName, pktCbRecord.GetStr() ); |
| 1156 | |
| 1157 | if (blunt_end) { |
| 1158 | if (cast_assign(rawPkt, pktCbRecord.Pkt, CHECK)) { // packet is a Raw |
| 1159 | printf("AC: blunt_end, RX packet is rawdata \n"); |
| 1160 | |
| 1161 | if (rawPkt.getPktType() == DENALI_PCIE__RawData) { // packet is a Raw data |
| 1162 | |
| 1163 | // compare RX data with transmitted data in mailbox |
| 1164 | rawPkt.getPktData( RX_rawpktdata ); |
| 1165 | rawPkt.printInfo(); |
| 1166 | |
| 1167 | mailbox_get(NO_WAIT, mbluntendTXdata, expected_bluntendPkt); |
| 1168 | |
| 1169 | if (rawPkt == expected_bluntendPkt) { |
| 1170 | printf("AC: RX bluntend data match transmitted data \n"); |
| 1171 | } |
| 1172 | else { |
| 1173 | printf("AC: RX bluntend data did not match transmitted data \n"); |
| 1174 | } |
| 1175 | // check symbol for trigger data |
| 1176 | if (RX_rawpktdata[0] == PCIE_SYMBOL_K28__5 ) { |
| 1177 | bluntend_compare_start = 1; |
| 1178 | printf("AC: time = %d, blunt end rawdata == COM, remember to compare only after this trigger \n", get_time(LO) |
| 1179 | ); |
| 1180 | } |
| 1181 | |
| 1182 | } |
| 1183 | } |
| 1184 | |
| 1185 | |
| 1186 | } // blunt end |
| 1187 | |
| 1188 | // extended sync |
| 1189 | if (count_4096FTS_1SKP) { |
| 1190 | // determine if OS is received and there are 4096 FTS then 1 SKP |
| 1191 | if( cast_assign( osPkt, pktCbRecord.Pkt, CHECK) ){ |
| 1192 | |
| 1193 | osPkt.printInfo(); |
| 1194 | |
| 1195 | |
| 1196 | // note: skip does arrive in between 4096 FTS |
| 1197 | |
| 1198 | |
| 1199 | if ((osPkt.getOsType() == DENALI_PCIE_PL__skip_set) && fts_os_set_count == 4095){ |
| 1200 | PCIEX_QR_D3("%s: Received %d FTS os set and 1 skip os set", MethodName, fts_os_set_count ); |
| 1201 | } |
| 1202 | |
| 1203 | if( (osPkt.getOsType() == DENALI_PCIE_PL__fts_set)){ |
| 1204 | fts_os_set_count++; |
| 1205 | PCIEX_QR_D3("%s: AC: time = %d, Receive FTS os set count = %d", MethodName, get_time(LO), fts_os_set_count ); |
| 1206 | |
| 1207 | } //End TS1 |
| 1208 | } |
| 1209 | |
| 1210 | } // end count_4096FTS_1SKP = 1 |
| 1211 | |
| 1212 | // reset fts_os_set_count when not counting 4096FTS, to allow diag to run loop |
| 1213 | if (count_4096FTS_1SKP == 0) { |
| 1214 | fts_os_set_count = 0 ; |
| 1215 | } |
| 1216 | |
| 1217 | |
| 1218 | } |
| 1219 | |
| 1220 | task FNXPCIEXactorSignalInterface::ProcessPktCb_PL_RX_end_packet( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1221 | { |
| 1222 | string MethodName = "PPktCb_PL_RX_end_packet"; |
| 1223 | |
| 1224 | // for extended sync |
| 1225 | denaliPcieTrainingSet osPkt; |
| 1226 | |
| 1227 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1228 | XactorName, pktCbRecord.GetStr() ); |
| 1229 | |
| 1230 | |
| 1231 | |
| 1232 | } |
| 1233 | |
| 1234 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_RX_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1235 | { |
| 1236 | denaliPcieRawPacket rawPkt; |
| 1237 | FNXPCIEXactorPacket fnxPkt; |
| 1238 | bit [8:0] pktData[*]; |
| 1239 | string MethodName = "PPktCb_DL_RX_queue_enter"; |
| 1240 | |
| 1241 | // ProcessPktCb_DL_RX_queue_enter at time %d \n", get_time(LO)); |
| 1242 | if (cast_assign(rawPkt, pktCbRecord.Pkt, CHECK)) { // packet is a Raw |
| 1243 | |
| 1244 | if (rawPkt.getPktType() == DENALI_PCIE__RawDllp) { // packet is a RawDllp |
| 1245 | |
| 1246 | // Retrieve Raw DLLP Packet Byte Stream |
| 1247 | fnxPkt = new( MyReport, XactorName, Util, PortNum ); |
| 1248 | rawPkt.getPktData( pktData ); |
| 1249 | |
| 1250 | // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields |
| 1251 | fnxPkt.ParseDLLPByteStream( pktData ); |
| 1252 | |
| 1253 | PCIEX_QR_D2( "%s-> Received RAW DLLP:\n%s", |
| 1254 | XactorName, Util.ByteStreamToStr( pktData, fnxPkt.GetPktPrefixStr(), "Byte Stream" ) ); |
| 1255 | |
| 1256 | // Place Received & Parsed DLLP Packet Into mDLLPsFromLinks Mailbox |
| 1257 | if (ExpectOn) mailbox_put( mDLLPsFromLinks, fnxPkt ); |
| 1258 | |
| 1259 | // Update Statistics Database |
| 1260 | StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_RCV ); |
| 1261 | } |
| 1262 | } |
| 1263 | } |
| 1264 | |
| 1265 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_RX_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1266 | { |
| 1267 | // NOTE: In Denali Release pcie,v3.1_11122003 RAW TLPs Do NOT Propagate to |
| 1268 | // The DL_to_TL Callback Point, So Pick TLPs Off at RX_queue_exit Cbk Point |
| 1269 | denaliPcieRawDlpPacket rawDlpPkt; |
| 1270 | FNXPCIEXactorPacket fnxPkt; |
| 1271 | denaliPciePacket denPkt; |
| 1272 | integer status; |
| 1273 | bit [8:0] pktData[*]; |
| 1274 | string MethodName = "PPktCb_DL_RX_queue_exit"; |
| 1275 | |
| 1276 | //N2 DMT Bypass Link Train |
| 1277 | // return; |
| 1278 | |
| 1279 | if (cast_assign(rawDlpPkt, pktCbRecord.Pkt, CHECK)) { // packet is a RawDLP |
| 1280 | |
| 1281 | if( cast_assign( denPkt, pktCbRecord.Pkt, CHECK ) ){ |
| 1282 | //If this is a NULL packet then just drop it |
| 1283 | //review N2 - Tried to get Denali to drop incoming NULL Packets but I |
| 1284 | // couldn't get ot to work!!! |
| 1285 | if( denPkt.getErr() == PCIE_PL_NONFATAL_FRAME_NULL_TLP ){ |
| 1286 | //Drop the packet from further processing |
| 1287 | denPkt.setErrInject( PCIE_EI_DISCARD ); |
| 1288 | status = denPkt.transSet(); // Pass Changes to Denali C Model |
| 1289 | if( status != 0 ){ |
| 1290 | PCIEX_QR_ERR( "%s:%s-> transSet() Failed(%0d) :\n", XactorName,MethodName , status ); |
| 1291 | } |
| 1292 | } |
| 1293 | else{ |
| 1294 | // Retrieve Raw TLP Packet Byte Stream (includes DLL Framing Fields) |
| 1295 | fnxPkt = new( MyReport, XactorName, Util, PortNum ); |
| 1296 | rawDlpPkt.getPktData( pktData ); |
| 1297 | |
| 1298 | // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields |
| 1299 | fnxPkt.ParseTLPByteStream( pktData ); |
| 1300 | |
| 1301 | // Place Received & Parsed TLP Packet Into mTLPsFromLinks Mailbox |
| 1302 | if (ExpectOn) mailbox_put( mTLPsFromLinks, fnxPkt ); |
| 1303 | |
| 1304 | // Pass Received TLP to Replay Monitor |
| 1305 | if (ReplayMonitorOn) |
| 1306 | ReplayMonitor.UpdateTlp( fnxPkt ); |
| 1307 | |
| 1308 | // Update Statistics Database |
| 1309 | StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_RCV ); |
| 1310 | |
| 1311 | } |
| 1312 | } |
| 1313 | } |
| 1314 | |
| 1315 | /* |
| 1316 | if (cast_assign(rawDlpPkt, pktCbRecord.Pkt, CHECK)) { // packet is a RawDLP |
| 1317 | |
| 1318 | // Retrieve Raw TLP Packet Byte Stream (includes DLL Framing Fields) |
| 1319 | fnxPkt = new( MyReport, XactorName, Util, PortNum ); |
| 1320 | rawDlpPkt.getPktData( pktData ); |
| 1321 | |
| 1322 | // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields |
| 1323 | fnxPkt.ParseTLPByteStream( pktData ); |
| 1324 | |
| 1325 | PCIEX_QR_D2( "%s-> Received RAW TLP:\n%s", |
| 1326 | XactorName, Util.ByteStreamToStr(pktData, fnxPkt.GetPktPrefixStr(), "Byte Stream" ) ); |
| 1327 | |
| 1328 | // Place Received & Parsed TLP Packet Into mTLPsFromLinks Mailbox |
| 1329 | if (ExpectOn) mailbox_put( mTLPsFromLinks, fnxPkt ); |
| 1330 | |
| 1331 | // Update Statistics Database |
| 1332 | StatsDatabase.UpdatePkt( fnxPkt, FNX_PCIE_XTR_STAT_DIR_RCV ); |
| 1333 | } |
| 1334 | */ |
| 1335 | } |
| 1336 | |
| 1337 | task FNXPCIEXactorSignalInterface::ProcessPktCb_PL_to_DL( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1338 | { |
| 1339 | denaliPcieRawDlpPacket rawDlpPkt; |
| 1340 | denaliPciePacket denPkt; |
| 1341 | FNXPCIEXactorPacket fnxPkt; |
| 1342 | bit [8:0] pktData[*]; |
| 1343 | integer status; |
| 1344 | string MethodName = "PPktCb_PL_to_DL"; |
| 1345 | |
| 1346 | //N2 DMT Bypass Link Train |
| 1347 | // return; |
| 1348 | |
| 1349 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1350 | XactorName, pktCbRecord.GetStr() ); |
| 1351 | /* //Moved to DL_RX_queue_exit |
| 1352 | if (cast_assign(rawDlpPkt, pktCbRecord.Pkt, CHECK)) { // packet is a RawDLP |
| 1353 | |
| 1354 | if( cast_assign( denPkt, pktCbRecord.Pkt, CHECK ) ){ |
| 1355 | //If this is a NULL packet then just drop it |
| 1356 | if( denPkt.getErr() == PCIE_PL_NONFATAL_FRAME_NULL_TLP ){ |
| 1357 | //Drop the packet from further processing |
| 1358 | denPkt.setErrInject( PCIE_EI_DISCARD ); |
| 1359 | status = denPkt.transSet(); // Pass Changes to Denali C Model |
| 1360 | if( status != 0 ){ |
| 1361 | PCIEX_QR_ERR( "%s:%s-> transSet() Failed(%0d) :\n", XactorName,MethodName , status ); |
| 1362 | } |
| 1363 | } |
| 1364 | else{ |
| 1365 | // Retrieve Raw TLP Packet Byte Stream (includes DLL Framing Fields) |
| 1366 | fnxPkt = new( MyReport, XactorName, Util, PortNum ); |
| 1367 | rawDlpPkt.getPktData( pktData ); |
| 1368 | |
| 1369 | // Pass Raw Byte Stream to FNX PCIE Packet for Parsing in Packet Fields |
| 1370 | fnxPkt.ParseTLPByteStream( pktData ); |
| 1371 | |
| 1372 | // Pass Received TLP to Replay Monitor |
| 1373 | if (ReplayMonitorOn) |
| 1374 | ReplayMonitor.UpdateTlp( fnxPkt ); |
| 1375 | |
| 1376 | } |
| 1377 | } |
| 1378 | } |
| 1379 | */ |
| 1380 | } |
| 1381 | |
| 1382 | task FNXPCIEXactorSignalInterface::ProcessPktCb_DL_to_TL( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1383 | { |
| 1384 | string MethodName = "PPktCb_DL_to_TL"; |
| 1385 | |
| 1386 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1387 | XactorName, pktCbRecord.GetStr() ); |
| 1388 | } |
| 1389 | |
| 1390 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_RX_packet( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1391 | { |
| 1392 | string MethodName = "PPktCb_TL_RX_packet"; |
| 1393 | |
| 1394 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1395 | XactorName, pktCbRecord.GetStr() ); |
| 1396 | } |
| 1397 | |
| 1398 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TX_error( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1399 | { |
| 1400 | denaliPcieRawPacket rawPkt; |
| 1401 | integer status; |
| 1402 | string MethodName = "PPktCb_TX_error"; |
| 1403 | |
| 1404 | |
| 1405 | // this method: works |
| 1406 | if (cast_assign(rawPkt, pktCbRecord.Pkt, CHECK)) { // packet is a Raw |
| 1407 | |
| 1408 | if (rawPkt.getPktType() == DENALI_PCIE__RawData) { // packet is a Raw data |
| 1409 | if (rawPkt.getErr() == PCIE_PL_NONFATAL_FRAME_NULL_TLP) { |
| 1410 | PCIEX_QR_I( "AC: Null Error %s intentionally set, sim continues", |
| 1411 | pktCbRecord.GetStr() ); |
| 1412 | } |
| 1413 | else { |
| 1414 | PCIEX_QR_ERR( "%s-> Error Callback %s Received", |
| 1415 | XactorName, pktCbRecord.GetStr() ); |
| 1416 | } |
| 1417 | } |
| 1418 | } |
| 1419 | |
| 1420 | |
| 1421 | // PCIEX_QR_ERR( "%s-> Error Callback %s Received", |
| 1422 | // XactorName, pktCbRecord.GetStr() ); |
| 1423 | } |
| 1424 | |
| 1425 | task FNXPCIEXactorSignalInterface::ProcessPktCb_RX_error( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1426 | { |
| 1427 | denaliPciePacket denPkt; |
| 1428 | integer status; |
| 1429 | string MethodName = "PPktCb_RX_error"; |
| 1430 | |
| 1431 | //Check if this is a null packet error and if one is expected |
| 1432 | if( expectNullPkt ){ |
| 1433 | if( cast_assign( denPkt, pktCbRecord.Pkt, CHECK ) ){ |
| 1434 | if( denPkt.getErr() == PCIE_PL_NONFATAL_FRAME_NULL_TLP ){ |
| 1435 | //Drop the packet from further processing |
| 1436 | denPkt.setErrInject( PCIE_EI_DISCARD ); |
| 1437 | status = denPkt.transSet(); // Pass Changes to Denali C Model |
| 1438 | if( status != 0 ){ |
| 1439 | PCIEX_QR_ERR( "%s:%s-> transSet() Failed(%0d) :\n", XactorName,MethodName, status ); |
| 1440 | } |
| 1441 | |
| 1442 | |
| 1443 | PCIEX_QR_D3( "%s-> %s Expected NULL packet Received", |
| 1444 | XactorName, pktCbRecord.GetStr() ); |
| 1445 | expectNullPkt -= 1; |
| 1446 | } |
| 1447 | } |
| 1448 | } |
| 1449 | else{ |
| 1450 | |
| 1451 | PCIEX_QR_ERR( "%s-> Error Callback %s Received", |
| 1452 | XactorName, pktCbRecord.GetStr() ); |
| 1453 | } |
| 1454 | } |
| 1455 | |
| 1456 | task FNXPCIEXactorSignalInterface::ProcessPktCb_error( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1457 | { |
| 1458 | string MethodName = "PPktCb_error"; |
| 1459 | |
| 1460 | PCIEX_QR_ERR( "%s-> Error Callback %s Received", |
| 1461 | XactorName, pktCbRecord.GetStr() ); |
| 1462 | } |
| 1463 | |
| 1464 | task FNXPCIEXactorSignalInterface::ProcessPktCb_unknown( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1465 | { |
| 1466 | string MethodName = "PPktCb_unknown"; |
| 1467 | |
| 1468 | PCIEX_QR_ERR( "%s-> Error Callback %s Received", |
| 1469 | XactorName, pktCbRecord.GetStr() ); |
| 1470 | } |
| 1471 | |
| 1472 | task FNXPCIEXactorSignalInterface::ProcessRegCbLTSSMState( FNXPCIEXactorRegCbRecord regCbRecord ) |
| 1473 | { |
| 1474 | string MethodName = "ProcessRegCbLTSSMState"; |
| 1475 | denaliPcieLtssmStateT oldSt, newSt; |
| 1476 | integer iOldSt, iNewSt; |
| 1477 | |
| 1478 | iOldSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LTSSM_STATE_OLD_SLC]; |
| 1479 | iNewSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LTSSM_STATE_NEW_SLC]; |
| 1480 | cast_assign( oldSt, iOldSt ); |
| 1481 | cast_assign( newSt, iNewSt ); |
| 1482 | PCIEX_QR_I( "%s-> Denali LTSSM State Updated:\n New=%s Old=%s, time = %d", |
| 1483 | XactorName, newSt, oldSt, get_time(LO) ); |
| 1484 | } |
| 1485 | |
| 1486 | task FNXPCIEXactorSignalInterface::ProcessRegCbDLCMSMState( FNXPCIEXactorRegCbRecord regCbRecord ) |
| 1487 | { |
| 1488 | string MethodName = "ProcessRegCbDLCMSMState"; |
| 1489 | denaliPcieDlcmsmStateT oldSt, newSt; |
| 1490 | integer iOldSt, iNewSt; |
| 1491 | |
| 1492 | iOldSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DLCMSM_STATE_OLD_SLC]; |
| 1493 | iNewSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DLCMSM_STATE_NEW_SLC]; |
| 1494 | cast_assign( oldSt, iOldSt ); |
| 1495 | cast_assign( newSt, iNewSt ); |
| 1496 | |
| 1497 | // Trigger eDLLActive Event if DLCMSM State is Active |
| 1498 | if (newSt === PCIE_DLCMSM_STATE_DL_Active) |
| 1499 | trigger( ONE_BLAST, eDLLActive ); |
| 1500 | |
| 1501 | PCIEX_QR_I( "%s-> Denali DLCMSM State Updated:\n New=%s Old=%s", |
| 1502 | XactorName, newSt, oldSt ); |
| 1503 | } |
| 1504 | |
| 1505 | task FNXPCIEXactorSignalInterface::ProcessRegCbTLPortState( FNXPCIEXactorRegCbRecord regCbRecord ) |
| 1506 | { |
| 1507 | string MethodName = "ProcessRegCbTLPortState"; |
| 1508 | denaliPciePortStateT oldSt, newSt; |
| 1509 | integer iOldSt, iNewSt; |
| 1510 | |
| 1511 | iOldSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_TLPORT_STATE_OLD_SLC]; |
| 1512 | iNewSt = regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_TLPORT_STATE_NEW_SLC]; |
| 1513 | cast_assign( oldSt, iOldSt ); |
| 1514 | cast_assign( newSt, iNewSt ); |
| 1515 | PCIEX_QR_I( "%s-> Denali TLPORT State Updated:\n New=%s Old=%s", |
| 1516 | XactorName, newSt, oldSt ); |
| 1517 | } |
| 1518 | |
| 1519 | task FNXPCIEXactorSignalInterface::ProcessRegCbDevCtrl( FNXPCIEXactorRegCbRecord regCbRecord ) |
| 1520 | { |
| 1521 | string MethodName = "ProcessRegCbDevCtrl"; |
| 1522 | PCIEX_QR_I( "%s-> Denali Device Control Updated:\n BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h", |
| 1523 | XactorName, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DEV_CTRL_BUS_NUM_SLC], |
| 1524 | FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DEV_CTRL_DEVICE_NUM_SLC], |
| 1525 | FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_DEV_CTRL_FUNC_NUM_SLC] ); |
| 1526 | } |
| 1527 | |
| 1528 | task FNXPCIEXactorSignalInterface::ProcessRegCbLinkState( FNXPCIEXactorRegCbRecord regCbRecord ) |
| 1529 | { |
| 1530 | string MethodName = "ProcessRegCbLinkState"; |
| 1531 | string tmp1, tmp2; |
| 1532 | |
| 1533 | // Trigger eLinkUp Event if Bit is Set |
| 1534 | if (regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_UP_SLC] === 1'b1) |
| 1535 | trigger( ONE_BLAST, eLinkUp ); |
| 1536 | |
| 1537 | sprintf( tmp1, "LinkUp=%b LinkWidth=%0d'h%h LinkNum=%0d'h%h LaneNum=%0d'h%h", |
| 1538 | regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_UP_SLC], |
| 1539 | FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_WIDTH_SLC], |
| 1540 | FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_NUM_SLC], |
| 1541 | FNX_PCIE_XTR_REG_DEN_LINK_ST_LANE_NUM_WIDTH, regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LANE_NUM_SLC] ); |
| 1542 | sprintf( tmp2, "LanesReversed=%b Scrambling=%b LinkToSucc: LO=%b LOs=%b L1=%b L2=%b", |
| 1543 | regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LANES_REVERSED_SLC], |
| 1544 | regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_SCRAMBLING_SLC], |
| 1545 | regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_LO_SUCC_SLC], |
| 1546 | regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_LOS_SUCC_SLC], |
| 1547 | regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_L1_SUCC_SLC], |
| 1548 | regCbRecord.Data[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_TO_L2_SUCC_SLC] ); |
| 1549 | PCIEX_QR_I( "%s-> Denali Link State Updated:\n %s\n %s", |
| 1550 | XactorName, tmp1, tmp2 ); |
| 1551 | } |
| 1552 | |
| 1553 | task FNXPCIEXactorSignalInterface::WaitLinkUp() |
| 1554 | { |
| 1555 | string MethodName = "WaitLinkUp"; |
| 1556 | bit[FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] lnkStData; |
| 1557 | |
| 1558 | PCIEX_QR_I( "%s-> Start.", XactorName ); |
| 1559 | |
| 1560 | // Read Denali Reg And Check If Link Is Already Up, If Not Wait For eLinkUp |
| 1561 | // Trigger by Link State Callback Handler |
| 1562 | lnkStData = ReadDenaliReg( PCIE_REG_DEN_LINK_ST ); |
| 1563 | if (lnkStData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_UP_SLC] !== 1) |
| 1564 | sync( ANY, eLinkUp ); |
| 1565 | |
| 1566 | PCIEX_QR_I( "%s-> Done. Link is Up. REG_DEN_LINK_ST=%0h", XactorName,lnkStData ); |
| 1567 | } |
| 1568 | |
| 1569 | task FNXPCIEXactorSignalInterface::WaitDLLActive() |
| 1570 | { |
| 1571 | string MethodName = "WaitDLLActive"; |
| 1572 | bit[FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] dlcmsmStData; |
| 1573 | |
| 1574 | PCIEX_QR_I( "%s-> Start.", XactorName ); |
| 1575 | |
| 1576 | // Read Denali Reg And Check If Link Is Already Up, If Not Wait For eDLLActive |
| 1577 | // Trigger by DLCMSMS State Callback Handler |
| 1578 | dlcmsmStData = ReadDenaliReg( PCIE_REG_DEN_DLCMSM_STATE ); |
| 1579 | if (dlcmsmStData[FNX_PCIE_XTR_REG_DEN_DLCMSM_STATE_NEW_SLC] !== PCIE_DLCMSM_STATE_DL_Active) |
| 1580 | sync( ANY, eDLLActive ); |
| 1581 | |
| 1582 | PCIEX_QR_I( "%s-> Done. DLL is Active.", XactorName ); |
| 1583 | } |
| 1584 | |
| 1585 | task FNXPCIEXactorSignalInterface::WriteDenaliReg( integer iDenReg, bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data ) |
| 1586 | { |
| 1587 | string MethodName = "WriteDenaliReg"; |
| 1588 | integer id; |
| 1589 | |
| 1590 | // Get Denali Device Id Used in Register DDV Operations to Configuration Space |
| 1591 | void = DenaliDDVgetIdByName( {PCIEDevice.getInstName(),"(cfg_0_0)"}, id ); |
| 1592 | |
| 1593 | if (DenaliDDVwrite( id, iDenReg, data ) == 0) |
| 1594 | PCIEX_QR_D2( "%s-> Updated Reg=%s Data=32'h%h id=%0d", |
| 1595 | XactorName, Util.denaliRegNumToStr(iDenReg), data, id ); |
| 1596 | else |
| 1597 | PCIEX_QR_ERR( "%s-> Update for Reg=%s Data=32'h%h id=%0d Failed.", |
| 1598 | XactorName, Util.denaliRegNumToStr(iDenReg), data, id ); |
| 1599 | } |
| 1600 | |
| 1601 | function bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] FNXPCIEXactorSignalInterface::ReadDenaliReg( integer iDenReg ) |
| 1602 | { |
| 1603 | string MethodName = "ReadDenaliReg"; |
| 1604 | integer id; |
| 1605 | |
| 1606 | // Get Denali Device Id Used in Register DDV Operations to Configuration Space |
| 1607 | void = DenaliDDVgetIdByName( {PCIEDevice.getInstName(),"(cfg_0_0)"}, id ); |
| 1608 | |
| 1609 | if (DenaliDDVread( id, iDenReg, ReadDenaliReg) == 0) |
| 1610 | PCIEX_QR_D3( "%s-> Reg=%s Read Data=32'h%h", |
| 1611 | XactorName, Util.denaliRegNumToStr(iDenReg), ReadDenaliReg ); |
| 1612 | else |
| 1613 | PCIEX_QR_ERR( "%s-> Read of Reg=%s Failed.", |
| 1614 | XactorName, Util.denaliRegNumToStr(iDenReg) ); |
| 1615 | } |
| 1616 | |
| 1617 | task FNXPCIEXactorSignalInterface::SetupBAR32( integer denReg, |
| 1618 | integer addrWidth, |
| 1619 | bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] baseAddr ) |
| 1620 | { |
| 1621 | string MethodName = "SetupBAR32"; |
| 1622 | bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] barLowerData; |
| 1623 | bit [FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH-1:0] lowerAddr; |
| 1624 | integer i; |
| 1625 | |
| 1626 | // 32-bit BAR is For a 32-bit Non-Prefecthable Memory Decoder |
| 1627 | // NOTE: 32-bit BAR's by PCI Definition Must NOT be Prefecthable |
| 1628 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_MEM; |
| 1629 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_TYPE_32_BIT; |
| 1630 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_PREFETCHABLE_SLC ] = FNX_PCIE_XTR_PCI_BAR_NOT_PREFETCHABLE; |
| 1631 | |
| 1632 | // Ensure Address Width is In Valid Range |
| 1633 | if ((addrWidth < 8) || (addrWidth > FNX_PCIE_XTR_PCI_BAR_WIDTH)) { |
| 1634 | PCIEX_QR_ERR( "%s-> Invalid 32-bit addrWidth=%0d Specified.", |
| 1635 | XactorName, addrWidth ); |
| 1636 | return; |
| 1637 | } |
| 1638 | |
| 1639 | // Ensure Base Address Doesn't Have Lowest 4 Bits Set |
| 1640 | if (baseAddr[3:0] !== 4'h0) { |
| 1641 | PCIEX_QR_ERR( "%s-> Invalid 32-bit BaseAddr=%h Specified.", |
| 1642 | XactorName, baseAddr ); |
| 1643 | return; |
| 1644 | } |
| 1645 | |
| 1646 | // Pass Size of 32-bit BAR to Denali Device |
| 1647 | lowerAddr = { FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH {1'b0} }; |
| 1648 | for (i=0; i < (FNX_PCIE_XTR_PCI_BAR_WIDTH - addrWidth); i++) |
| 1649 | lowerAddr[FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH-i-1] = 1'b1; |
| 1650 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = lowerAddr; |
| 1651 | WriteDenaliReg( denReg, barLowerData ); |
| 1652 | |
| 1653 | // Pass Base Address of 32-bit BAR to Denali Device |
| 1654 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = baseAddr[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ]; |
| 1655 | WriteDenaliReg( denReg, barLowerData ); |
| 1656 | |
| 1657 | PCIEX_QR_I( "%s-> Setup 32-bit BAR=%s: Width=%0d Base=%h", |
| 1658 | XactorName, Util.denaliRegNumToStr(denReg), addrWidth, baseAddr ); |
| 1659 | } |
| 1660 | |
| 1661 | task FNXPCIEXactorSignalInterface::SetupBAR64( integer denRegLower, |
| 1662 | integer denRegUpper, |
| 1663 | integer addrWidth, |
| 1664 | bit [FNX_PCIE_XTR_PCI_BAR_WIDTH*2-1:0] baseAddr ) |
| 1665 | { |
| 1666 | string MethodName = "SetupBAR64"; |
| 1667 | bit [FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] barLowerData, barUpperData; |
| 1668 | bit [FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH-1:0] lowerAddr; |
| 1669 | bit [FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_WIDTH-1:0] upperAddr; |
| 1670 | integer i; |
| 1671 | |
| 1672 | // 64-bit BAR is For a 64-bit Prefecthable Memory Decoder |
| 1673 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_DECODER_TYPE_MEM; |
| 1674 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_TYPE_SLC ] = FNX_PCIE_XTR_PCI_BAR_TYPE_64_BIT; |
| 1675 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_PREFETCHABLE_SLC ] = FNX_PCIE_XTR_PCI_BAR_PREFETCHABLE; |
| 1676 | |
| 1677 | // Ensure Address Width is In Valid Range |
| 1678 | // NOTE: PCIE Requires 64-bit Addresses Are Beyond 4GB Memory Space |
| 1679 | if ((addrWidth <= FNX_PCIE_XTR_PCI_BAR_WIDTH) || (addrWidth > FNX_PCIE_XTR_PCI_BAR_WIDTH*2)) { |
| 1680 | PCIEX_QR_ERR( "%s-> Invalid 64-bit AddrWidth=%0d Specified.", |
| 1681 | XactorName, addrWidth ); |
| 1682 | return; |
| 1683 | } |
| 1684 | |
| 1685 | // Ensure Base Address Doesn't Have Lowest 32 Bits Set |
| 1686 | // NOTE: PCIE Requires 64-bit Addresses Are Beyond 4GB Memory Space |
| 1687 | if (baseAddr[FNX_PCIE_XTR_PCI_BAR_WIDTH-1:0] !== {FNX_PCIE_XTR_PCI_BAR_WIDTH {1'b0}} ) { |
| 1688 | PCIEX_QR_ERR( "%s-> Invalid 64-bit BaseAddr=%h Specified.", |
| 1689 | XactorName, baseAddr ); |
| 1690 | return; |
| 1691 | } |
| 1692 | |
| 1693 | // Pass Size of 64-bit BAR to Denali Device |
| 1694 | lowerAddr = {FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_WIDTH {1'b0}}; |
| 1695 | upperAddr = { FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_WIDTH {1'b0} }; |
| 1696 | for (i=0; i < (FNX_PCIE_XTR_PCI_BAR_WIDTH*2 - addrWidth); i++) |
| 1697 | upperAddr[FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_WIDTH-i-1] = 1'b1; |
| 1698 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = lowerAddr; |
| 1699 | barUpperData[ FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_SLC ] = upperAddr; |
| 1700 | WriteDenaliReg( denRegLower, barLowerData ); |
| 1701 | WriteDenaliReg( denRegUpper, barUpperData ); |
| 1702 | |
| 1703 | // Pass Base Address of 64-bit BAR to Denali Device |
| 1704 | barLowerData[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ] = baseAddr[ FNX_PCIE_XTR_PCI_BAR_LOWER_ADDR_SLC ]; |
| 1705 | barUpperData[ FNX_PCIE_XTR_PCI_BAR_UPPER_ADDR_SLC ] = baseAddr[ FNX_PCIE_XTR_PCI_BAR_WIDTH*2-1:FNX_PCIE_XTR_PCI_BAR_WIDTH ]; |
| 1706 | WriteDenaliReg( denRegLower, barLowerData ); |
| 1707 | WriteDenaliReg( denRegUpper, barUpperData ); |
| 1708 | |
| 1709 | PCIEX_QR_I( "%s-> Setup 64-bit BAR={%s,%s} : Width=%0d Base=%h", |
| 1710 | XactorName, Util.denaliRegNumToStr(denRegLower), Util.denaliRegNumToStr(denRegUpper), addrWidth, baseAddr ); |
| 1711 | } |
| 1712 | |
| 1713 | task FNXPCIEXactorSignalInterface::SetReqID( bit [FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH-1:0] busNum, |
| 1714 | bit [FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH-1:0] devNum, |
| 1715 | bit [FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH-1:0] funcNum, |
| 1716 | integer regOffset = 0 ) |
| 1717 | { |
| 1718 | string MethodName = "SetReqID"; |
| 1719 | bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data; |
| 1720 | |
| 1721 | data = 0; |
| 1722 | data[ FNX_PCIE_XTR_REG_DEN_DEV_CTRL_BUS_NUM_SLC ] = busNum; |
| 1723 | data[ FNX_PCIE_XTR_REG_DEN_DEV_CTRL_DEVICE_NUM_SLC ] = devNum; |
| 1724 | data[ FNX_PCIE_XTR_REG_DEN_DEV_CTRL_FUNC_NUM_SLC ] = funcNum; |
| 1725 | |
| 1726 | // Ensure Register Offset is Multiple of PCIE_REG_NUM_MAXIMUM |
| 1727 | if ((regOffset%PCIE_REG_NUM_MAXIMUM) != 0) { |
| 1728 | PCIEX_QR_ERR( "%s-> Invalid regOffset=%0d Specified.", |
| 1729 | XactorName, regOffset ); |
| 1730 | return; |
| 1731 | } |
| 1732 | |
| 1733 | WriteDenaliReg( PCIE_REG_DEN_DEV_CTRL+regOffset, data ); |
| 1734 | |
| 1735 | PCIEX_QR_I( "%s-> Set ReqID: BusNum=%0d'h%h DeviceNum=%0d'h%h FuncNum=%0d'h%h", |
| 1736 | XactorName, FNX_PCIE_XTR_REQ_BUS_NUM_WIDTH, busNum, |
| 1737 | FNX_PCIE_XTR_REQ_DEVICE_NUM_WIDTH, devNum, |
| 1738 | FNX_PCIE_XTR_REQ_FUNC_NUM_WIDTH, funcNum ); |
| 1739 | } |
| 1740 | |
| 1741 | task FNXPCIEXactorSignalInterface::SuppressDenaliErr( denaliPcieErrorTypeT denErr ) |
| 1742 | { |
| 1743 | string MethodName = "SuppressDenaliErr"; |
| 1744 | bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data; |
| 1745 | bit [FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_WIDTH-1:0] errId; |
| 1746 | |
| 1747 | // Suppress Specified Error and Disable Callbacks and Assertion Coverage on Both Xmit and Recv Side |
| 1748 | errId = denErr; |
| 1749 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_SLC] = errId; |
| 1750 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_CBK_CTRL_SLC] = PCIE_ERR_CONFIG_disable_callback; |
| 1751 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ASSERT_CTRL_SLC] = PCIE_ERR_CONFIG_disable_coverage; |
| 1752 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_DIRECTION_SLC] = PCIE_ERR_CONFIG_DIRECTION_TRX; |
| 1753 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_SEV_SLC] = PCIE_ERR_CONFIG_FORMAT_SILENT; |
| 1754 | |
| 1755 | // Write Data to Denali ERROR_CTRL Register |
| 1756 | WriteDenaliReg( PCIE_REG_DEN_ERROR_CTRL, data); |
| 1757 | |
| 1758 | PCIEX_QR_I( "%s -> Suppressed Err=%s", XactorName, denErr ); |
| 1759 | } |
| 1760 | |
| 1761 | task FNXPCIEXactorSignalInterface::tempSuppressDenaliErr( denaliPcieErrorTypeT denErr ) |
| 1762 | { |
| 1763 | string MethodName = "tempSuppressDenaliErr"; |
| 1764 | bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data; |
| 1765 | bit [FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_WIDTH-1:0] errId; |
| 1766 | |
| 1767 | // Suppress Specified Error and Disable Callbacks |
| 1768 | // BUT leave Assertion Coverage enabled |
| 1769 | errId = denErr; |
| 1770 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_SLC] = errId; |
| 1771 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_CBK_CTRL_SLC] = PCIE_ERR_CONFIG_disable_callback; |
| 1772 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ASSERT_CTRL_SLC] = PCIE_ERR_CONFIG_enable_coverage; |
| 1773 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_DIRECTION_SLC] = PCIE_ERR_CONFIG_DIRECTION_TRX; |
| 1774 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_SEV_SLC] = PCIE_ERR_CONFIG_FORMAT_INFO; |
| 1775 | |
| 1776 | // Write Data to Denali ERROR_CTRL Register |
| 1777 | WriteDenaliReg( PCIE_REG_DEN_ERROR_CTRL, data); |
| 1778 | |
| 1779 | PCIEX_QR_I( "%s -> tempSuppressed Err=%s", XactorName, denErr ); |
| 1780 | } |
| 1781 | |
| 1782 | task FNXPCIEXactorSignalInterface::unSuppressDenaliErr( denaliPcieErrorTypeT denErr ) |
| 1783 | { |
| 1784 | string MethodName = "unSuppressDenaliErr"; |
| 1785 | bit [FNX_PCIE_XTR_REG_DEN_WIDTH-1:0] data; |
| 1786 | bit [FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_WIDTH-1:0] errId; |
| 1787 | |
| 1788 | // Suppress Specified Error and Disable Callbacks |
| 1789 | // BUT leave Assertion Coverage enabled |
| 1790 | errId = denErr; |
| 1791 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ERR_ID_SLC] = errId; |
| 1792 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_CBK_CTRL_SLC] = PCIE_ERR_CONFIG_enable_callback; |
| 1793 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_ASSERT_CTRL_SLC] = PCIE_ERR_CONFIG_enable_coverage; |
| 1794 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_DIRECTION_SLC] = PCIE_ERR_CONFIG_DIRECTION_TRX; |
| 1795 | data[FNX_PCIE_XTR_REG_DEN_ERROR_CTRL_SEV_SLC] = PCIE_ERR_CONFIG_FORMAT_ERROR; |
| 1796 | |
| 1797 | // Write Data to Denali ERROR_CTRL Register |
| 1798 | WriteDenaliReg( PCIE_REG_DEN_ERROR_CTRL, data); |
| 1799 | |
| 1800 | PCIEX_QR_I( "%s -> unSuppressed Err=%s", XactorName, denErr ); |
| 1801 | } |
| 1802 | |
| 1803 | |
| 1804 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_TX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1805 | { |
| 1806 | string MethodName = "PPktCb_TL_TX_completion_queue_enter"; |
| 1807 | |
| 1808 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1809 | XactorName, pktCbRecord.GetStr() ); |
| 1810 | } |
| 1811 | |
| 1812 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_TX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1813 | { |
| 1814 | string MethodName = "PPktCb_TL_TX_completion_queue_exit"; |
| 1815 | |
| 1816 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1817 | XactorName, pktCbRecord.GetStr() ); |
| 1818 | } |
| 1819 | |
| 1820 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_RX_completion_queue_enter( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1821 | { |
| 1822 | string MethodName = "PPktCb_TL_RX_completion_queue_enter"; |
| 1823 | |
| 1824 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1825 | XactorName, pktCbRecord.GetStr() ); |
| 1826 | } |
| 1827 | |
| 1828 | task FNXPCIEXactorSignalInterface::ProcessPktCb_TL_RX_completion_queue_exit( FNXPCIEXactorPktCbRecord pktCbRecord ) |
| 1829 | { |
| 1830 | string MethodName = "PPktCb_TL_RX_completion_queue_exit"; |
| 1831 | |
| 1832 | PCIEX_QR_D3( "%s-> Callback Handler Is Empty:\n %s", |
| 1833 | XactorName, pktCbRecord.GetStr() ); |
| 1834 | } |
| 1835 | |
| 1836 | function string FNXPCIEXactorSignalInterface::GetEpilogueStr() |
| 1837 | { |
| 1838 | ReplayMonitor.UpdateStats(); |
| 1839 | GetEpilogueStr = { StatsDatabase.GetStr(), "\n", ReplayMonitor.GetStr() }; |
| 1840 | } |
| 1841 | |
| 1842 | task FNXPCIEXactorSignalInterface::SetRcvDetMode( bit _rcvDetMode ) |
| 1843 | { |
| 1844 | MiscPort.$rcvDetMode = _rcvDetMode; |
| 1845 | } |
| 1846 | |
| 1847 | task FNXPCIEXactorSignalInterface::SetRcvDetLanes( bit[FNX_PCIE_XTR_RCV_DET_LANES_WIDTH-1:0] _rcvDetLanes ) |
| 1848 | { |
| 1849 | MiscPort.$rcvDetLanes = _rcvDetLanes; |
| 1850 | } |
| 1851 | |
| 1852 | task FNXPCIEXactorSignalInterface::SetElecIdleLanes( bit[FNX_PCIE_XTR_RCV_DET_LANES_WIDTH-1:0] _elecIdleLanes ) |
| 1853 | { |
| 1854 | MiscPort.$elecIdleLanes = _elecIdleLanes; |
| 1855 | } |
| 1856 | |
| 1857 | task FNXPCIEXactorSignalInterface::SetDenaliReset( bit _denaliReset ) |
| 1858 | { |
| 1859 | MiscPort.$denaliReset = _denaliReset; |
| 1860 | } |
| 1861 | |
| 1862 | task FNXPCIEXactorSignalInterface::ResetReplayMonitor( ) |
| 1863 | { |
| 1864 | ReplayMonitor.Reset(); |
| 1865 | } |
| 1866 | |
| 1867 | task FNXPCIEXactorSignalInterface::EnableSampleDllpToLink( ) |
| 1868 | { |
| 1869 | //Enable sampling and create the packet object if it doesn't exist already |
| 1870 | sampleDllpToLink = 1; |
| 1871 | if( sampledDllpPktToLink == null ){ |
| 1872 | sampledDllpPktToLink = new( MyReport, XactorName, Util, PortNum ); |
| 1873 | } |
| 1874 | } |
| 1875 | |
| 1876 | task FNXPCIEXactorSignalInterface::DisableSampleDllpToLink( ) |
| 1877 | { |
| 1878 | sampleDllpToLink = 0; |
| 1879 | } |
| 1880 | |
| 1881 | task FNXPCIEXactorSignalInterface::SampleDllpPktToLink( XactorBasePacket Pkt, |
| 1882 | integer Window ) |
| 1883 | { |
| 1884 | |
| 1885 | string MethodName = "SampleDllpPktToLink"; |
| 1886 | bit Success = 0; |
| 1887 | |
| 1888 | fork { |
| 1889 | sync(ANY, eDLLPToLink); |
| 1890 | Pkt.PktCopy(sampledDllpPktToLink); |
| 1891 | Success = 1'b1; |
| 1892 | } |
| 1893 | { |
| 1894 | while (Window && !Success) { |
| 1895 | Window--; |
| 1896 | @(negedge ClkPort.$XClk); |
| 1897 | } |
| 1898 | if (!Success) |
| 1899 | PCIEX_QR_ERR( "%s-> Timeout. No DLLP Transmitted to the DUT.", XactorName ); |
| 1900 | else |
| 1901 | Pkt.PktDisplay( RTYP_INFO, psprintf("%s %s -> Transaction Sampled", PCIEX_QR_PREFIX, XactorName ) ); |
| 1902 | } |
| 1903 | join any |
| 1904 | } |
| 1905 | |
| 1906 | |
| 1907 | task FNXPCIEXactorSignalInterface::TransmitFTSToLink( integer nmbrFts ){ |
| 1908 | denaliPcieOrderedSet ftsPkt; |
| 1909 | integer i; |
| 1910 | integer status; |
| 1911 | |
| 1912 | for( i=0; i<nmbrFts; i++ ){ |
| 1913 | // Create Denali Packet To Be Driven |
| 1914 | ftsPkt = new( DENALI_PCIE_PL__fts_set ); |
| 1915 | |
| 1916 | // Add Denali Packet to Denali's User Queue |
| 1917 | status = PCIEDevice.transAdd( ftsPkt, 0, DENALI_ARG_trans_append ); |
| 1918 | if( status != 0 ){ |
| 1919 | PCIEX_QR_ERR( "%s:TransmitFTSToLink-> transAdd() Failed(%0d) :\n", XactorName, status ); |
| 1920 | } |
| 1921 | } |
| 1922 | } |
| 1923 | |
| 1924 | task FNXPCIEXactorSignalInterface::TransmitSKPToLink( integer nmbrSkp ){ |
| 1925 | denaliPcieOrderedSet skpPkt; |
| 1926 | integer i; |
| 1927 | integer status; |
| 1928 | |
| 1929 | for( i=0; i<nmbrSkp; i++ ){ |
| 1930 | // Create Denali Packet To Be Driven |
| 1931 | skpPkt = new( DENALI_PCIE_PL__skip_set ); |
| 1932 | |
| 1933 | // Add Denali Packet to Denali's User Queue |
| 1934 | status = PCIEDevice.transAdd( skpPkt, 0, DENALI_ARG_trans_append ); |
| 1935 | if( status != 0 ){ |
| 1936 | PCIEX_QR_ERR( "%s:TransmitSKPToLink-> transAdd() Failed(%0d) :\n", XactorName, status ); |
| 1937 | } |
| 1938 | } |
| 1939 | } |
| 1940 | |
| 1941 | task FNXPCIEXactorSignalInterface::TransmitTS1ToLink( integer nmbrTS1 ){ |
| 1942 | denaliPcieOrderedSet ftsPkt; |
| 1943 | integer i; |
| 1944 | integer status; |
| 1945 | |
| 1946 | for( i=0; i<nmbrTS1; i++ ){ |
| 1947 | // Create Denali Packet To Be Driven |
| 1948 | ftsPkt = new( DENALI_PCIE_PL__ts1_set ); |
| 1949 | |
| 1950 | // Add Denali Packet to Denali's User Queue |
| 1951 | status = PCIEDevice.transAdd( ftsPkt, 0, DENALI_ARG_trans_append ); |
| 1952 | if( status != 0 ){ |
| 1953 | PCIEX_QR_ERR( "%s:TransmitTS1ToLink-> transAdd() Failed(%0d) :\n", XactorName, status ); |
| 1954 | } |
| 1955 | } |
| 1956 | } |
| 1957 | |
| 1958 | |
| 1959 | // task FNXPCIEXactorSignalInterface::TransmitOrdersetToLink( integer nmbrFts, bit [31:0] orderset ){ |
| 1960 | // task FNXPCIEXactorSignalInterface::TransmitOrdersetToLink( integer nmbrFts, denaliPcieOrderedSet orderset ){ |
| 1961 | // denaliPcieOrderedSet ftsPkt; |
| 1962 | // integer i; |
| 1963 | // integer status; |
| 1964 | // |
| 1965 | // for( i=0; i<nmbrFts; i++ ){ |
| 1966 | // // Create Denali Packet To Be Driven |
| 1967 | // ftsPkt = new( orderset ); |
| 1968 | // ftsPkt = new( DENALI_PCIE_PL__ts1_set ); |
| 1969 | // |
| 1970 | // // Add Denali Packet to Denali's User Queue |
| 1971 | // status = PCIEDevice.transAdd( ftsPkt, 0, DENALI_ARG_trans_append ); |
| 1972 | // if( status != 0 ){ |
| 1973 | // PCIEX_QR_ERR( "%s:TransmitFTSToLink-> transAdd() Failed(%0d) :\n", XactorName, status ); |
| 1974 | // } |
| 1975 | // } |
| 1976 | // } |
| 1977 | |
| 1978 | |
| 1979 | task FNXPCIEXactorSignalInterface::Transmit_symbol_ToLink( integer nmbrSymbol, bit[8:0] symbol ){ |
| 1980 | // denaliPcieOrderedSet ftsPkt; |
| 1981 | denaliPcieRawPacket rawPkt; |
| 1982 | denaliPciePacket pkt; |
| 1983 | |
| 1984 | integer i, j; |
| 1985 | integer status; |
| 1986 | bit[8:0] PkttData[*]; |
| 1987 | bit[8:0] data[*]; |
| 1988 | |
| 1989 | for( i=0; i<nmbrSymbol; i++ ){ |
| 1990 | printf("AC: i = %d \n", i); |
| 1991 | // Create Denali Packet To Be Driven |
| 1992 | rawPkt = new( DENALI_PCIE__RawData ); |
| 1993 | // rawPkt.pktDataLen.setPktDataLen = 1; |
| 1994 | rawPkt.setPktDataLen(1); |
| 1995 | // for (j=1; j<=8; j++) { |
| 1996 | // PktData[j] = 9'b110111100; |
| 1997 | // } |
| 1998 | // rawPkt.setPktData(PCIE_SYMBOL_K28__5); // PCIE_SYMBOL_K28__5 |
| 1999 | // rawPkt.setPktData(PktData); // PCIE_SYMBOL_K28__5 ERROR: runtime: illegal array index |
| 2000 | // rawPkt.setPktData(PktData[0]); // PCIE_SYMBOL_K28__5 "FNXPCIEXactor.vr", line 7196 : Data type error for array arg on argument #1 |
| 2001 | // rawPkt.pktData[0] = PCIE_SYMBOL_K28__5; // Member "pktData" not found |
| 2002 | // rawPkt.getPktData(PktData); // PCIE_SYMBOL_K28__5 "FNXPCIEXactor.vr", line 7196 : Data type error for array arg on argument #1 |
| 2003 | // pkt.PktData = PCIE_SYMBOL_K28__5; //Member "PktData" not found |
| 2004 | |
| 2005 | |
| 2006 | // data=new[1]; |
| 2007 | // data[0] = PCIE_SYMBOL_K28__5; |
| 2008 | |
| 2009 | data=new[8]; |
| 2010 | for (j=0; j<8; j++) { |
| 2011 | printf("AC: j = %d \n", j); |
| 2012 | // data[j] = PCIE_SYMBOL_K28__5; |
| 2013 | data[j] = symbol; |
| 2014 | } |
| 2015 | |
| 2016 | rawPkt.setPktData(data); |
| 2017 | |
| 2018 | // Add Denali Packet to Denali's User Queue |
| 2019 | status = PCIEDevice.transAdd( rawPkt, 0, DENALI_ARG_trans_append ); |
| 2020 | if( status != 0 ){ |
| 2021 | PCIEX_QR_ERR( "AC: %s:Transmit_symbol_ToLink-> transAdd() Failed(%0d) at time %d :\n", XactorName, status, get_time(LO) ); |
| 2022 | } |
| 2023 | else { |
| 2024 | printf("AC: rawPkt transAdd complete \n"); |
| 2025 | } |
| 2026 | } |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | |
| 2031 | } |
| 2032 | |
| 2033 | |
| 2034 | |
| 2035 | |