| 1 | |
| 2 | +incdir+$DV_ROOT/design/dmu/dmu_l/dmu/rtl |
| 3 | +incdir+$DV_ROOT/design/peu/peu_l/peu/rtl |
| 4 | +incdir+$DV_ROOT/design/pcie_common/include/rtl |
| 5 | +incdir+$DV_ROOT/design/pcie_common/csr/rtl |
| 6 | |
| 7 | +incdir+$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/ |
| 8 | $DV_ROOT/design/peu/peu_l/peu/rtl/peu.h |
| 9 | $DV_ROOT/design/pcie_common/include/rtl/pcie.h |
| 10 | $DV_ROOT/design/pcie_common/csr/rtl/pcie_csr_defines.h |
| 11 | |
| 12 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/pcie_defs.vh |
| 13 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_defs.vh |
| 14 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_hdr.vh |
| 15 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_lib.vh |
| 16 | // AT, 12/20/04: Not needed $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/adm_defs.vh |
| 17 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_user.vh |
| 18 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/port_cfg.vh |
| 19 | |
| 20 | $DV_ROOT/design/plp/plp_l/plp/rtl/plp.vp |
| 21 | $DV_ROOT/design/plp/plp_tlg_l/plp_tlg/rtl/plp_tlg.vp |
| 22 | // $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm.vp |
| 23 | // $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm_pl_reg.vp |
| 24 | // $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm_reg_decode.vp |
| 25 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_1sx16.vp |
| 26 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_1sx16.vp |
| 27 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_slv_1s.vp |
| 28 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_slv_1sx16.vp |
| 29 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_link_1sx16.vp |
| 30 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_pipe.vp |
| 31 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_pkt_finder_1sx16.vp |
| 32 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_seq_finder_1s.vp |
| 33 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_seq_finder_1sx16.vp |
| 34 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/scramble.vp |
| 35 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/scramble_x16.vp |
| 36 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_1sx16.vp |
| 37 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_byte_xmt_1sx16.vp |
| 38 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_ltssm.vp |
| 39 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_pipe.vp |
| 40 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_128b.vp |
| 41 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_dlp_extract.vp |
| 42 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_link_cntrl.vp |
| 43 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_tlp_extract_128b.vp |
| 44 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_128b.vp |
| 45 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_control_128b.vp |
| 46 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_dllp_gen.vp |
| 47 | // Rmvd from Cascade 2.1 Rls: $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_insert_crc.vp |
| 48 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_retrybuf_128b.vp |
| 49 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_tlp_gen_128b.vp |
| 50 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_128b.vp |
| 51 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc.vp |
| 52 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_arb.vp |
| 53 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_decode.vp |
| 54 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_gen.vp |
| 55 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/loopback_1s.vp |
| 56 | $DV_ROOT/design/plp/plp_phy_l/plp_phy/rtl/phy_1s.vp |
| 57 | $DV_ROOT/verif/model/verilog/pcie/ept/phy_1sx16.v |
| 58 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/pipe2phy_1s.vp |
| 59 | // $DV_ROOT/design/plp/plp_phy_l/plp_phy/rtl/pipe_multilane.vp |
| 60 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_8b10b_1s.vp |
| 61 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_cdet_1s.vp |
| 62 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_elasbuf_1s.vp |
| 63 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/sdm_1s.vp |
| 64 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/xphy_8b10b_1s.vp |
| 65 | //$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/serdes_1s.vp |
| 66 | //$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/rphy_deser_1s.vp |
| 67 | //$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/xphy_ser_1s.vp |
| 68 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/crc_128b.vp |
| 69 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/decode8b10b.vp |
| 70 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/delay_n.vp |
| 71 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/encode8b10b.vp |
| 72 | // $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/sync.vp |
| 73 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/cx_pl_16A.vp |
| 74 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_reverse.vp |
| 75 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_reverse.vp |
| 76 | $DV_ROOT/design/peu/peu_l/peu/rtl/peu.v |
| 77 | |
| 78 | |
| 79 | $DV_ROOT/libs/n2sram/async/n2_com_64x132async_dp_cust_l/n2_com_64x132async_dp_cust/rtl/n2_com_64x132async_dp_cust_array.v |
| 80 | $DV_ROOT/libs/n2sram/async/n2_com_64x132async_dp_cust_l/n2_com_64x132async_dp_cust/rtl/n2_com_64x132async_dp_cust.v |
| 81 | $DV_ROOT/libs/n2sram/async/n2_com_256x132async_dp_cust_l/n2_com_256x132async_dp_cust/rtl/n2_com_256x132async_dp_cust_array.v |
| 82 | $DV_ROOT/libs/n2sram/async/n2_com_256x132async_dp_cust_l/n2_com_256x132async_dp_cust/rtl/n2_com_256x132async_dp_cust.v |
| 83 | $DV_ROOT/libs/n2sram/dp/n2_peu_dp_256x138s_cust_l/n2_peu_dp_256x138s_cust/rtl/n2_peu_dp_256x138s_cust_array.v |
| 84 | $DV_ROOT/libs/n2sram/dp/n2_peu_dp_256x138s_cust_l/n2_peu_dp_256x138s_cust/rtl/n2_peu_dp_256x138s_cust.v |
| 85 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_defines.h |
| 86 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_defines.h |
| 87 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ctl_entry.v |
| 88 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ctl.v |
| 89 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_sts_entry.v |
| 90 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_sts.v |
| 91 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_trn_off_entry.v |
| 92 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_trn_off.v |
| 93 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ici_entry.v |
| 94 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ici.v |
| 95 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_diag_entry.v |
| 96 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_diag.v |
| 97 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_log_entry.v |
| 98 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_log.v |
| 99 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_int_en_entry.v |
| 100 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_int_en.v |
| 101 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_err_entry.v |
| 102 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_err.v |
| 103 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr1_entry.v |
| 104 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr1.v |
| 105 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr2_entry.v |
| 106 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr2.v |
| 107 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr1_entry.v |
| 108 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr1.v |
| 109 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr2_entry.v |
| 110 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr2.v |
| 111 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prfc_entry.v |
| 112 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prfc.v |
| 113 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf0_entry.v |
| 114 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf0.v |
| 115 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf1_entry.v |
| 116 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf1.v |
| 117 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf2_entry.v |
| 118 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf2.v |
| 119 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_a_entry.v |
| 120 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_a.v |
| 121 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_b_entry.v |
| 122 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_b.v |
| 123 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_cap_entry.v |
| 124 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_cap.v |
| 125 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_ctl_entry.v |
| 126 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_ctl.v |
| 127 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_sts_entry.v |
| 128 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_sts.v |
| 129 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_cap_entry.v |
| 130 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_cap.v |
| 131 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_ctl_entry.v |
| 132 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_ctl.v |
| 133 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_sts_entry.v |
| 134 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_sts.v |
| 135 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_log_entry.v |
| 136 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_log.v |
| 137 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_int_en_entry.v |
| 138 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_int_en.v |
| 139 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_err_entry.v |
| 140 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_err.v |
| 141 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr1_entry.v |
| 142 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr1.v |
| 143 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr2_entry.v |
| 144 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr2.v |
| 145 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr1_entry.v |
| 146 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr1.v |
| 147 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr2_entry.v |
| 148 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr2.v |
| 149 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_log_entry.v |
| 150 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_log.v |
| 151 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_int_en_entry.v |
| 152 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_int_en.v |
| 153 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_err_entry.v |
| 154 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_err.v |
| 155 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csrpipe_50.v |
| 156 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csrpipe_5.v |
| 157 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_peu_dlpl_serdes_rev_entry.v |
| 158 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_peu_dlpl_serdes_rev.v |
| 159 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_thresh_entry.v |
| 160 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_thresh.v |
| 161 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_timer_entry.v |
| 162 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_timer.v |
| 163 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_tim_thresh_entry.v |
| 164 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_tim_thresh.v |
| 165 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_timer_entry.v |
| 166 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_timer.v |
| 167 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ven_dllp_msg_entry.v |
| 168 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ven_dllp_msg.v |
| 169 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_force_ltssm_entry.v |
| 170 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_force_ltssm.v |
| 171 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_cfg_entry.v |
| 172 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_cfg.v |
| 173 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_ctl_entry.v |
| 174 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_ctl.v |
| 175 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lane_skew_entry.v |
| 176 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lane_skew.v |
| 177 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_num_entry.v |
| 178 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_num.v |
| 179 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_timer_entry.v |
| 180 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_timer.v |
| 181 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_pll_entry.v |
| 182 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_pll.v |
| 183 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_ctl_entry.v |
| 184 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_ctl.v |
| 185 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_status_entry.v |
| 186 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_status.v |
| 187 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_ctl_entry.v |
| 188 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_ctl.v |
| 189 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_status_entry.v |
| 190 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_status.v |
| 191 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_macro_test_cfg_entry.v |
| 192 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_macro_test_cfg.v |
| 193 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_core_status_entry.v |
| 194 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_core_status.v |
| 195 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_int_en_entry.v |
| 196 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_int_en.v |
| 197 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_log_en_entry.v |
| 198 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_log_en.v |
| 199 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_sts_clr_entry.v |
| 200 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_sts_clr.v |
| 201 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_default_grp.v |
| 202 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_stage_mux_only.v |
| 203 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_addr_decode.v |
| 204 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr.v |
| 205 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_csr.v |
| 206 | $DV_ROOT/design/ptl/ptl_l/ptl/rtl/ptl.h |
| 207 | $DV_ROOT/design/ptl/ptl_l/ptl/rtl/ptl.v |
| 208 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb.v |
| 209 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr.v |
| 210 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_ahb.v |
| 211 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr.v |
| 212 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_rio.v |
| 213 | $DV_ROOT/design/ptl/ptl_sbs_l/ptl_sbs/rtl/ptl_sbs.v |
| 214 | $DV_ROOT/design/ptl/ptl_mb0_l/ptl_mb0/rtl/ptl_mb0.v |
| 215 | $DV_ROOT/design/ptl/ptl_edb_l/ptl_edb/rtl/ptl_edb.v |
| 216 | $DV_ROOT/design/ptl/ptl_ehb_l/ptl_ehb/rtl/ptl_ehb.v |
| 217 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl.h |
| 218 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl.v |
| 219 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_hcs.v |
| 220 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_hps.v |
| 221 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_fcs.v |
| 222 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_rcs.v |
| 223 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_lcs.v |
| 224 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_dbg.v |
| 225 | $DV_ROOT/design/ptl/ptl_idb_l/ptl_idb/rtl/ptl_idb.v |
| 226 | $DV_ROOT/design/ptl/ptl_ihb_l/ptl_ihb/rtl/ptl_ihb.v |
| 227 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl.h |
| 228 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl.v |
| 229 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_idc.v |
| 230 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ifc.v |
| 231 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ihc.v |
| 232 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ihp.v |
| 233 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ipp.v |
| 234 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_itc.v |
| 235 | $DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc.v |
| 236 | $DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc_tpm.v |
| 237 | $DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc_lpm.v |
| 238 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb.h |
| 239 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb.v |
| 240 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb_rar.v |
| 241 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb_ctrl.v |
| 242 | |
| 243 | // |
| 244 | $DV_ROOT/design/psr/psr_l/psr/rtl/psr.v |
| 245 | //make serdes files libraries, so they disappear when using PEP |
| 246 | -v $DV_ROOT/design/psr/psr_l/psr/rtl/wiz6c2b8n5d2t.v |
| 247 | -v $DV_ROOT/design/psr/psr_l/psr/rtl/WIZ6C2XXN5X2.vp |
| 248 | -v $DV_ROOT/design/psr/psr_l/psr/rtl/NIAGARA2_REFCLK_BOTTOM1.v |
| 249 | -v $DV_ROOT/libs/serdes/ljcb/ljcb_l/iclkrx18gat/rtl/iclkrx18gat.v |