| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcusat_fbdimm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mcusat_fbdimm( |
| 36 | fbdimm0_ps, fbdimm0_ps_bar, fbdimm0_pn , fbdimm0_pn_bar, // channel 0 interface |
| 37 | fbdimm1_ps, fbdimm1_ps_bar, fbdimm1_pn , fbdimm1_pn_bar, // channel 1 interface |
| 38 | fbdimm2_ps, fbdimm2_ps_bar, fbdimm2_pn , fbdimm2_pn_bar, // channel 2 interface |
| 39 | fbdimm3_ps, fbdimm3_ps_bar, fbdimm3_pn , fbdimm3_pn_bar, // channel 3 interface |
| 40 | fbdimm4_ps, fbdimm4_ps_bar, fbdimm4_pn , fbdimm4_pn_bar, // channel 4 interface |
| 41 | fbdimm5_ps, fbdimm5_ps_bar, fbdimm5_pn , fbdimm5_pn_bar, // channel 5 interface |
| 42 | fbdimm6_ps, fbdimm6_ps_bar, fbdimm6_pn , fbdimm6_pn_bar, // channel 6 interface |
| 43 | fbdimm7_ps, fbdimm7_ps_bar, fbdimm7_pn , fbdimm7_pn_bar, // channel 7 interface |
| 44 | fbdimm_sclk, chmon_rst |
| 45 | ); |
| 46 | |
| 47 | |
| 48 | input [9:0] fbdimm0_ps; // to primary fbdimm models |
| 49 | input [9:0] fbdimm0_ps_bar; // to primary fbdimm models |
| 50 | output [13:0] fbdimm0_pn; // to primary fbdimm models |
| 51 | output [13:0] fbdimm0_pn_bar; // to primary fbdimm models |
| 52 | |
| 53 | input [9:0] fbdimm1_ps; // to primary fbdimm models |
| 54 | input [9:0] fbdimm1_ps_bar; // to primary fbdimm models |
| 55 | output [13:0] fbdimm1_pn; // to primary fbdimm models |
| 56 | output [13:0] fbdimm1_pn_bar; // to primary fbdimm models |
| 57 | |
| 58 | input [9:0] fbdimm2_ps; // to primary fbdimm models |
| 59 | input [9:0] fbdimm2_ps_bar; // to primary fbdimm models |
| 60 | output [13:0] fbdimm2_pn; // to primary fbdimm models |
| 61 | output [13:0] fbdimm2_pn_bar; // to primary fbdimm models |
| 62 | |
| 63 | input [9:0] fbdimm3_ps; // to primary fbdimm models |
| 64 | input [9:0] fbdimm3_ps_bar; // to primary fbdimm models |
| 65 | output [13:0] fbdimm3_pn; // to primary fbdimm models |
| 66 | output [13:0] fbdimm3_pn_bar; // to primary fbdimm models |
| 67 | |
| 68 | input [9:0] fbdimm4_ps; // to primary fbdimm models |
| 69 | input [9:0] fbdimm4_ps_bar; // to primary fbdimm models |
| 70 | output [13:0] fbdimm4_pn; // to primary fbdimm models |
| 71 | output [13:0] fbdimm4_pn_bar; // to primary fbdimm models |
| 72 | |
| 73 | input [9:0] fbdimm5_ps; // to primary fbdimm models |
| 74 | input [9:0] fbdimm5_ps_bar; // to primary fbdimm models |
| 75 | output [13:0] fbdimm5_pn; // to primary fbdimm models |
| 76 | output [13:0] fbdimm5_pn_bar; // to primary fbdimm models |
| 77 | |
| 78 | input [9:0] fbdimm6_ps; // to primary fbdimm models |
| 79 | input [9:0] fbdimm6_ps_bar; // to primary fbdimm models |
| 80 | output [13:0] fbdimm6_pn; // to primary fbdimm models |
| 81 | output [13:0] fbdimm6_pn_bar; // to primary fbdimm models |
| 82 | |
| 83 | input [9:0] fbdimm7_ps; // to primary fbdimm models |
| 84 | input [9:0] fbdimm7_ps_bar; // to primary fbdimm models |
| 85 | output [13:0] fbdimm7_pn; // to primary fbdimm models |
| 86 | output [13:0] fbdimm7_pn_bar; // to primary fbdimm models |
| 87 | |
| 88 | input fbdimm_sclk; |
| 89 | input chmon_rst; |
| 90 | |
| 91 | reg [1:0] ch_err_enable; |
| 92 | |
| 93 | |
| 94 | `ifdef ENABLE_FBD_CH_MON |
| 95 | // FBD Channel Monitor |
| 96 | parameter NB_LINK = 14; |
| 97 | parameter SB_LINK = 10; |
| 98 | wire chmon_rst; |
| 99 | wire ch_mon_clk; |
| 100 | `endif |
| 101 | |
| 102 | `ifdef AXIS_DDR2_MODEL |
| 103 | //axis ddr2 model |
| 104 | wire [71:0] dq0; |
| 105 | wire [71:0] dq1; |
| 106 | wire [71:0] dq2; |
| 107 | wire [71:0] dq3; |
| 108 | wire [71:0] dq4; |
| 109 | wire [71:0] dq5; |
| 110 | wire [71:0] dq6; |
| 111 | wire [71:0] dq7; |
| 112 | wire dqs0; |
| 113 | wire dqs1; |
| 114 | wire dqs2; |
| 115 | wire dqs3; |
| 116 | |
| 117 | n2_dimm axis_dimm ( |
| 118 | .CK0 (`FBD_CH_PATH0.fbdimm0.dram_clk), |
| 119 | .bCK0 (~ `FBD_CH_PATH0.fbdimm0.dram_clk), |
| 120 | .bCS0 (`FBD_CH_PATH0.fbdimm0.bcs[1]), |
| 121 | .bRAS0 (`FBD_CH_PATH0.fbdimm0.bras[1]), |
| 122 | .bCAS0 (`FBD_CH_PATH0.fbdimm0.bcas[1]), |
| 123 | .bWE0 (`FBD_CH_PATH0.fbdimm0.bwe[1]), |
| 124 | .BA0 (`FBD_CH_PATH0.fbdimm0.ba), |
| 125 | .Addr0 (`FBD_CH_PATH0.fbdimm0.addr), |
| 126 | .DQ0 ({dq1,dq0}), |
| 127 | .DQS0 (dqs0), |
| 128 | |
| 129 | .CK1 (`FBD_CH_PATH2.fbdimm0.dram_clk), |
| 130 | .bCK1 (~ `FBD_CH_PATH2.fbdimm0.dram_clk), |
| 131 | .bCS1 (`FBD_CH_PATH2.fbdimm0.bcs[1]), |
| 132 | .bRAS1 (`FBD_CH_PATH2.fbdimm0.bras[1]), |
| 133 | .bCAS1 (`FBD_CH_PATH2.fbdimm0.bcas[1]), |
| 134 | .bWE1 (`FBD_CH_PATH2.fbdimm0.bwe[1]), |
| 135 | .BA1 (`FBD_CH_PATH2.fbdimm0.ba), |
| 136 | .Addr1 (`FBD_CH_PATH2.fbdimm0.addr), |
| 137 | .DQ1 ({dq3,dq2}), |
| 138 | .DQS1 (dqs1), |
| 139 | |
| 140 | .CK2 (`FBD_CH_PATH4.fbdimm0.dram_clk), |
| 141 | .bCK2 (~ `FBD_CH_PATH4.fbdimm0.dram_clk), |
| 142 | .bCS2 (`FBD_CH_PATH4.fbdimm0.bcs[1]), |
| 143 | .bRAS2 (`FBD_CH_PATH4.fbdimm0.bras[1]), |
| 144 | .bCAS2 (`FBD_CH_PATH4.fbdimm0.bcas[1]), |
| 145 | .bWE2 (`FBD_CH_PATH4.fbdimm0.bwe[1]), |
| 146 | .BA2 (`FBD_CH_PATH4.fbdimm0.ba), |
| 147 | .Addr2 (`FBD_CH_PATH4.fbdimm0.addr), |
| 148 | .DQ2 ({dq5,dq4}), |
| 149 | .DQS2 (dqs2), |
| 150 | |
| 151 | .CK3 (`FBD_CH_PATH6.fbdimm0.dram_clk), |
| 152 | .bCK3 (~ `FBD_CH_PATH6.fbdimm0.dram_clk), |
| 153 | .bCS3 (`FBD_CH_PATH6.fbdimm0.bcs[1]), |
| 154 | .bRAS3 (`FBD_CH_PATH6.fbdimm0.bras[1]), |
| 155 | .bCAS3 (`FBD_CH_PATH6.fbdimm0.bcas[1]), |
| 156 | .bWE3 (`FBD_CH_PATH6.fbdimm0.bwe[1]), |
| 157 | .BA3 (`FBD_CH_PATH6.fbdimm0.ba), |
| 158 | .Addr3 (`FBD_CH_PATH6.fbdimm0.addr), |
| 159 | .DQ3 ({dq7,dq6}), |
| 160 | .DQS3 (dqs3) |
| 161 | ); |
| 162 | |
| 163 | //axis ddr2 model doesn't use these for write cycles, so xmr only works from here into amb code |
| 164 | assign `FBD_CH_PATH0.fbdimm0.dqs={19{dqs0}}; |
| 165 | assign `FBD_CH_PATH1.fbdimm0.dqs={19{dqs0}}; |
| 166 | assign `FBD_CH_PATH2.fbdimm0.dqs={19{dqs1}}; |
| 167 | assign `FBD_CH_PATH3.fbdimm0.dqs={19{dqs1}}; |
| 168 | assign `FBD_CH_PATH4.fbdimm0.dqs={19{dqs2}}; |
| 169 | assign `FBD_CH_PATH5.fbdimm0.dqs={19{dqs2}}; |
| 170 | assign `FBD_CH_PATH6.fbdimm0.dqs={19{dqs3}}; |
| 171 | assign `FBD_CH_PATH7.fbdimm0.dqs={19{dqs3}}; |
| 172 | |
| 173 | `endif |
| 174 | |
| 175 | //-------------------------------- |
| 176 | // INSTANTIATING FB-DIMM CHANNELS |
| 177 | //-------------------------------- |
| 178 | |
| 179 | fbdimm_ch_mem fbdimm_mem0 ( |
| 180 | .XXPS (fbdimm0_ps), |
| 181 | .XXPS_BAR (fbdimm0_ps_bar), |
| 182 | .XXPN (fbdimm0_pn), |
| 183 | .XXPN_BAR (fbdimm0_pn_bar), |
| 184 | `ifdef AXIS_DDR2_MODEL |
| 185 | .dq (dq0), |
| 186 | `endif |
| 187 | .XXERR_EN (ch_err_enable[0]), |
| 188 | .XXCLK (fbdimm_sclk)); |
| 189 | |
| 190 | `ifndef SNG_CHANNEL |
| 191 | fbdimm_ch_mem fbdimm_mem1 ( |
| 192 | .XXPS (fbdimm1_ps), |
| 193 | .XXPS_BAR (fbdimm1_ps_bar), |
| 194 | .XXPN (fbdimm1_pn), |
| 195 | .XXPN_BAR (fbdimm1_pn_bar), |
| 196 | `ifdef AXIS_DDR2_MODEL |
| 197 | .dq (dq1), |
| 198 | `endif |
| 199 | .XXERR_EN (ch_err_enable[1]), |
| 200 | .XXCLK (fbdimm_sclk)); |
| 201 | `endif |
| 202 | |
| 203 | fbdimm_ch_mem fbdimm_mem2 ( |
| 204 | .XXPS (fbdimm2_ps), |
| 205 | .XXPS_BAR (fbdimm2_ps_bar), |
| 206 | .XXPN (fbdimm2_pn), |
| 207 | .XXPN_BAR (fbdimm2_pn_bar), |
| 208 | `ifdef AXIS_DDR2_MODEL |
| 209 | .dq (dq2), |
| 210 | `endif |
| 211 | .XXERR_EN (ch_err_enable[0]), |
| 212 | .XXCLK (fbdimm_sclk)); |
| 213 | |
| 214 | `ifndef SNG_CHANNEL |
| 215 | fbdimm_ch_mem fbdimm_mem3 ( |
| 216 | .XXPS (fbdimm3_ps), |
| 217 | .XXPS_BAR (fbdimm3_ps_bar), |
| 218 | .XXPN (fbdimm3_pn), |
| 219 | .XXPN_BAR (fbdimm3_pn_bar), |
| 220 | `ifdef AXIS_DDR2_MODEL |
| 221 | .dq (dq3), |
| 222 | `endif |
| 223 | .XXERR_EN (ch_err_enable[1]), |
| 224 | .XXCLK (fbdimm_sclk)); |
| 225 | `endif |
| 226 | |
| 227 | fbdimm_ch_mem fbdimm_mem4 ( |
| 228 | .XXPS (fbdimm4_ps), |
| 229 | .XXPS_BAR (fbdimm4_ps_bar), |
| 230 | .XXPN (fbdimm4_pn), |
| 231 | .XXPN_BAR (fbdimm4_pn_bar), |
| 232 | `ifdef AXIS_DDR2_MODEL |
| 233 | .dq (dq4), |
| 234 | `endif |
| 235 | .XXERR_EN (ch_err_enable[0]), |
| 236 | .XXCLK (fbdimm_sclk)); |
| 237 | |
| 238 | `ifndef SNG_CHANNEL |
| 239 | fbdimm_ch_mem fbdimm_mem5 ( |
| 240 | .XXPS (fbdimm5_ps), |
| 241 | .XXPS_BAR (fbdimm5_ps_bar), |
| 242 | .XXPN (fbdimm5_pn), |
| 243 | .XXPN_BAR (fbdimm5_pn_bar), |
| 244 | `ifdef AXIS_DDR2_MODEL |
| 245 | .dq (dq5), |
| 246 | `endif |
| 247 | .XXERR_EN (ch_err_enable[1]), |
| 248 | .XXCLK (fbdimm_sclk)); |
| 249 | `endif |
| 250 | |
| 251 | fbdimm_ch_mem fbdimm_mem6 ( |
| 252 | .XXPS (fbdimm6_ps), |
| 253 | .XXPS_BAR (fbdimm6_ps_bar), |
| 254 | .XXPN (fbdimm6_pn), |
| 255 | .XXPN_BAR (fbdimm6_pn_bar), |
| 256 | `ifdef AXIS_DDR2_MODEL |
| 257 | .dq (dq6), |
| 258 | `endif |
| 259 | .XXERR_EN (ch_err_enable[0]), |
| 260 | .XXCLK (fbdimm_sclk)); |
| 261 | |
| 262 | `ifndef SNG_CHANNEL |
| 263 | fbdimm_ch_mem fbdimm_mem7 ( |
| 264 | .XXPS (fbdimm7_ps), |
| 265 | .XXPS_BAR (fbdimm7_ps_bar), |
| 266 | .XXPN (fbdimm7_pn), |
| 267 | .XXPN_BAR (fbdimm7_pn_bar), |
| 268 | `ifdef AXIS_DDR2_MODEL |
| 269 | .dq (dq7), |
| 270 | `endif |
| 271 | .XXERR_EN (ch_err_enable[1]), |
| 272 | .XXCLK (fbdimm_sclk)); |
| 273 | `endif |
| 274 | |
| 275 | `ifdef ENABLE_FBD_CH_MON |
| 276 | channel_mon #(SB_LINK,NB_LINK) ch_mon0 ( |
| 277 | .ps (fbdimm0_ps), |
| 278 | .ps_bar (fbdimm0_ps_bar), |
| 279 | .pn (fbdimm0_pn), |
| 280 | .rst (chmon_rst), |
| 281 | .sclk (ch_mon_clk)); |
| 282 | |
| 283 | `ifndef SNG_CHANNEL |
| 284 | channel_mon #(SB_LINK,NB_LINK) ch_mon1 ( |
| 285 | .ps (fbdimm1_ps), |
| 286 | .ps_bar (fbdimm1_ps_bar), |
| 287 | .pn (fbdimm1_pn), |
| 288 | .rst (chmon_rst), |
| 289 | .sclk (ch_mon_clk)); |
| 290 | `endif |
| 291 | |
| 292 | channel_mon #(SB_LINK,NB_LINK) ch_mon2 ( |
| 293 | .ps (fbdimm2_ps), |
| 294 | .ps_bar (fbdimm2_ps_bar), |
| 295 | .pn (fbdimm2_pn), |
| 296 | .rst (chmon_rst), |
| 297 | .sclk (ch_mon_clk)); |
| 298 | |
| 299 | `ifndef SNG_CHANNEL |
| 300 | channel_mon #(SB_LINK,NB_LINK) ch_mon3 ( |
| 301 | .ps (fbdimm3_ps), |
| 302 | .ps_bar (fbdimm3_ps_bar), |
| 303 | .pn (fbdimm3_pn), |
| 304 | .rst (chmon_rst), |
| 305 | .sclk (ch_mon_clk)); |
| 306 | `endif |
| 307 | |
| 308 | channel_mon #(SB_LINK,NB_LINK) ch_mon4 ( |
| 309 | .ps (fbdimm4_ps), |
| 310 | .ps_bar (fbdimm4_ps_bar), |
| 311 | .pn (fbdimm4_pn), |
| 312 | .rst (chmon_rst), |
| 313 | .sclk (ch_mon_clk)); |
| 314 | |
| 315 | `ifndef SNG_CHANNEL |
| 316 | channel_mon #(SB_LINK,NB_LINK) ch_mon5 ( |
| 317 | .ps (fbdimm5_ps), |
| 318 | .ps_bar (fbdimm5_ps_bar), |
| 319 | .pn (fbdimm5_pn), |
| 320 | .rst (chmon_rst), |
| 321 | .sclk (ch_mon_clk)); |
| 322 | `endif |
| 323 | |
| 324 | channel_mon #(SB_LINK,NB_LINK) ch_mon6 ( |
| 325 | .ps (fbdimm6_ps), |
| 326 | .ps_bar (fbdimm6_ps_bar), |
| 327 | .pn (fbdimm6_pn), |
| 328 | .rst (chmon_rst), |
| 329 | .sclk (ch_mon_clk)); |
| 330 | |
| 331 | `ifndef SNG_CHANNEL |
| 332 | channel_mon #(SB_LINK,NB_LINK) ch_mon7 ( |
| 333 | .ps (fbdimm7_ps), |
| 334 | .ps_bar (fbdimm7_ps_bar), |
| 335 | .pn (fbdimm7_pn), |
| 336 | .rst (chmon_rst), |
| 337 | .sclk (ch_mon_clk)); |
| 338 | `endif |
| 339 | |
| 340 | assign ch_mon_clk = tb_top.dram_12x_clk; |
| 341 | |
| 342 | `endif |
| 343 | |
| 344 | initial |
| 345 | begin |
| 346 | if ($test$plusargs("CHNL0_ERR_ENABLE")) |
| 347 | ch_err_enable[0] = 1'b1; |
| 348 | else |
| 349 | ch_err_enable[0] = 1'b0; |
| 350 | |
| 351 | if ($test$plusargs("CHNL1_ERR_ENABLE")) |
| 352 | ch_err_enable[1] = 1'b1; |
| 353 | else |
| 354 | ch_err_enable[1] = 1'b0; |
| 355 | end |
| 356 | |
| 357 | endmodule |