| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: rng.if.vri |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #ifndef INC_RNG_IF_VRI |
| 36 | #define INC_RNG_IF_VRI |
| 37 | |
| 38 | #include "fc_top_defines.vri" |
| 39 | |
| 40 | port RNG_port { // signals are listed in alphabetical order |
| 41 | l2clk; |
| 42 | |
| 43 | anlg_char_out; // connected to pkg pin RNG_ANLG_CHAR_OUT |
| 44 | anlg_sel; // connected to ccu.rng_anlg_sel <= sig names are different |
| 45 | bypass; // connected to ccu.rng_bypass <= sig names are different |
| 46 | ch_sel; // connected to ccu.rng_ch_sel <= sig names are different |
| 47 | rng_arst_l; // connectee to ccu.rng_arst_l |
| 48 | rng_data; // connected to ccu.rng_data |
| 49 | stop; // tied to 0 |
| 50 | vcoctrl_sel; // connected to ccu.rng_vcoctrl_sel <= sig names are different |
| 51 | vdd_hv15; // connected to pkg pin VDD_RNG_HV |
| 52 | vreg_selbg_l; // connected to pkg pin VREG_SELBG_L |
| 53 | } |
| 54 | |
| 55 | interface rng_if { |
| 56 | input l2clk CLOCK verilog_node "`CPU.rng.l2clk"; |
| 57 | |
| 58 | input anlg_char_out PSAMPLE #-1 verilog_node "`CPU.rng.anlg_char_out"; |
| 59 | input [1:0] anlg_sel PSAMPLE #-1 verilog_node "`CPU.rng.anlg_sel"; |
| 60 | input bypass PSAMPLE #-1 verilog_node "`CPU.rng.bypass"; |
| 61 | input [1:0] ch_sel PSAMPLE #-1 verilog_node "`CPU.rng.ch_sel"; |
| 62 | input rng_arst_l PSAMPLE #-1 verilog_node "`CPU.rng.rng_arst_l"; |
| 63 | input rng_data PSAMPLE #-1 verilog_node "`CPU.rng.rng_data"; |
| 64 | input stop PSAMPLE #-1 verilog_node "`CPU.rng.stop"; |
| 65 | input [1:0] vcoctrl_sel PSAMPLE #-1 verilog_node "`CPU.rng.vcoctrl_sel"; |
| 66 | input vdd_hv15 PSAMPLE #-1 verilog_node "`CPU.rng.vdd_hv15"; |
| 67 | input vreg_selbg_l PSAMPLE #-1 verilog_node "`CPU.rng.vreg_selbg_l"; |
| 68 | } |
| 69 | |
| 70 | bind RNG_port rng_bind { |
| 71 | l2clk rng_if.l2clk; |
| 72 | |
| 73 | anlg_char_out rng_if. anlg_char_out; |
| 74 | anlg_sel rng_if.anlg_sel; |
| 75 | bypass rng_if.bypass; |
| 76 | ch_sel rng_if.ch_sel; |
| 77 | rng_arst_l rng_if.rng_arst_l; |
| 78 | rng_data rng_if.rng_data; |
| 79 | stop rng_if.stop; |
| 80 | vcoctrl_sel rng_if.vcoctrl_sel; |
| 81 | vdd_hv15 rng_if.vdd_hv15; |
| 82 | vreg_selbg_l rng_if.vreg_selbg_l; |
| 83 | } |
| 84 | |
| 85 | //====== RNG's n2_rng_sampler_cust module ============ |
| 86 | |
| 87 | port RNG_sampler_port { |
| 88 | l2clk; |
| 89 | raw_data; // outputs from noise cells |
| 90 | amux_off; |
| 91 | amux_sel0; |
| 92 | amux_sel1; |
| 93 | amux_sel2; |
| 94 | vcoctrl_sel0; |
| 95 | vcoctrl_sel1; |
| 96 | vcoctrl_sel2; |
| 97 | } |
| 98 | |
| 99 | interface rng_sampler_if { |
| 100 | input l2clk CLOCK verilog_node "`CPU.rng.l2clk"; |
| 101 | |
| 102 | inout [2:0] raw_data NHOLD #1 PSAMPLE #-1 verilog_node "`CPU.rng.xs.raw_data"; |
| 103 | |
| 104 | input amux_off PSAMPLE #-1 verilog_node "`CPU.rng.xs.amux_off"; |
| 105 | input [1:0] amux_sel0 PSAMPLE #-1 verilog_node "`CPU.rng.xs.amux_sel0"; |
| 106 | input [1:0] amux_sel1 PSAMPLE #-1 verilog_node "`CPU.rng.xs.amux_sel1"; |
| 107 | input [1:0] amux_sel2 PSAMPLE #-1 verilog_node "`CPU.rng.xs.amux_sel2"; |
| 108 | input [3:0] vcoctrl_sel0 PSAMPLE #-1 verilog_node "`CPU.rng.xs.vcoctrl_sel0"; |
| 109 | input [3:0] vcoctrl_sel1 PSAMPLE #-1 verilog_node "`CPU.rng.xs.vcoctrl_sel1"; |
| 110 | input [3:0] vcoctrl_sel2 PSAMPLE #-1 verilog_node "`CPU.rng.xs.vcoctrl_sel2"; |
| 111 | } |
| 112 | |
| 113 | bind RNG_sampler_port rng_sampler_bind { |
| 114 | l2clk rng_sampler_if.l2clk; |
| 115 | raw_data rng_sampler_if.raw_data; |
| 116 | amux_off rng_sampler_if.amux_off; |
| 117 | amux_sel0 rng_sampler_if.amux_sel0; |
| 118 | amux_sel1 rng_sampler_if.amux_sel1; |
| 119 | amux_sel2 rng_sampler_if.amux_sel2; |
| 120 | vcoctrl_sel0 rng_sampler_if.vcoctrl_sel0; |
| 121 | vcoctrl_sel1 rng_sampler_if.vcoctrl_sel1; |
| 122 | vcoctrl_sel2 rng_sampler_if.vcoctrl_sel2; |
| 123 | } |
| 124 | |
| 125 | #endif |