| 1 | #define DL_INACTIVE 0 |
| 2 | #define DL_INIT 1 |
| 3 | #define DL_ACTIVE 2 |
| 4 | |
| 5 | #define FC_INIT1 1 |
| 6 | #define FC_INIT2 2 |
| 7 | |
| 8 | #define INITFC1_P 1 |
| 9 | #define INITFC1_NP 2 |
| 10 | #define INITFC1_CPL 3 |
| 11 | #define INITFC2_P 4 |
| 12 | #define INITFC2_NP 5 |
| 13 | #define INITFC2_CPL 6 |
| 14 | |
| 15 | #define MASK0 0x0 |
| 16 | #define MASK1 0x1 |
| 17 | #define MASK2 0x2 |
| 18 | #define MASK3 0x3 |
| 19 | |
| 20 | #define SDP_CONTROL 0xc |
| 21 | |
| 22 | #define DLLP_INITFC1_P 0x40 |
| 23 | #define DLLP_INITFC1_NP 0x50 |
| 24 | #define DLLP_INITFC1_CPL 0x60 |
| 25 | |
| 26 | #define DLLP_INITFC2_P 0xc0 |
| 27 | #define DLLP_INITFC2_NP 0xd0 |
| 28 | #define DLLP_INITFC2_CPL 0xe0 |
| 29 | |
| 30 | #define DLLP_UPDATEFC_P 0x80 |
| 31 | #define DLLP_UPDATEFC_NP 0x90 |
| 32 | #define DLLP_UPDATEFC_CPL 0xa0 |
| 33 | |
| 34 | #define DLLP_PM_ENTER_L1 0x20 |
| 35 | #define DLLP_PM_ENTER_L23 0x21 |
| 36 | #define DLLP_PM_ACT_SR_L1 0x23 |
| 37 | #define DLLP_PM_REQ_ACK 0x24 |
| 38 | #define DLLP_VENDOR 0x30 |
| 39 | #define DLLP_INITFC1_P_NOVC 0x8 |
| 40 | #define DLLP_INITFC1_NP_NOVC 0xa |
| 41 | #define DLLP_INITFC1_CPL_NOVC 0xc |
| 42 | #define DLLP_INITFC2_P_NOVC 0x18 |
| 43 | #define DLLP_INITFC2_NP_NOVC 0x1a |
| 44 | #define DLLP_INITFC2_CPL_NOVC 0x1c |
| 45 | #define DLLP_UPDATEFC_P_NOVC 0x10 |
| 46 | #define DLLP_UPDATEFC_NP_NOVC 0x12 |
| 47 | #define DLLP_UPDATEFC_CPL_NOVC 0x14 |
| 48 | |
| 49 | |
| 50 | #define DATA0 0x0 |
| 51 | #define ALLONES 0xff |
| 52 | |