| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ilu_intf.hpp |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #ifndef INC_ilu_intf_hpp__ |
| 36 | #define INC_ilu_intf_hpp__ |
| 37 | |
| 38 | #include <systemc.h> |
| 39 | |
| 40 | #include "pcie_common/config.hpp" |
| 41 | #include "peu_defines.hpp" |
| 42 | |
| 43 | #include "pcie_common/csr_if_port.hpp" |
| 44 | #include "pcie_common/pciePacket.hpp" |
| 45 | #include "pcie_common/data_port.hpp" |
| 46 | #include "pcie_common/peu_csr_defines.hpp" |
| 47 | #include "pcie_common/peu_defines.hpp" |
| 48 | #include "tlm.h" |
| 49 | USING_NAMESPACE(tlm); |
| 50 | |
| 51 | #include <queue> |
| 52 | |
| 53 | #define WAIT(__EV__) if(!POR_RESET) wait( __EV__ | reset_ev); \ |
| 54 | if(POR_RESET) {LOG_WARNING<<"ILU_INTF: WAIT execption thrown...";throw sc_exception();} |
| 55 | |
| 56 | namespace pcie { |
| 57 | |
| 58 | class ilu_intf : public sc_module |
| 59 | { |
| 60 | public: |
| 61 | ilu_intf ( sc_module_name module_name, sc_event *parent_global_event, uint8 *parent_global_event_type ) : |
| 62 | sc_module(module_name), |
| 63 | in_pkt_port("Ingress_Port"), |
| 64 | req_pkt_port("Req_port"), |
| 65 | cmpl_pkt_port("Completion_port"), |
| 66 | cto_req_port("CTO_req_port"), |
| 67 | csr_port("CSR_PORT") |
| 68 | { |
| 69 | this->parent_global_event = parent_global_event; |
| 70 | this->parent_global_event_type = parent_global_event_type; |
| 71 | SC_METHOD(init); |
| 72 | SC_THREAD(ehb_write); |
| 73 | SC_THREAD(edb_write); |
| 74 | SC_THREAD(ihb_read); |
| 75 | SC_THREAD(idb_read); |
| 76 | SC_THREAD(proc_ce_int); |
| 77 | SC_THREAD(proc_ce_int_en); |
| 78 | SC_THREAD(proc_ue_int); |
| 79 | SC_THREAD(proc_ue_int_en); |
| 80 | SC_THREAD(proc_oe_int); |
| 81 | SC_THREAD(proc_oe_int_en); |
| 82 | SC_THREAD(ilu_credit_update_handler); |
| 83 | SC_THREAD(cto_req_handler); |
| 84 | SC_THREAD(mps_handler); |
| 85 | SC_THREAD(drain_handler); |
| 86 | SC_THREAD(pl_drain_catcher); |
| 87 | SC_THREAD(ilu_drain_catcher); |
| 88 | SC_THREAD(reset_handler); |
| 89 | } |
| 90 | SC_HAS_PROCESS( ilu_intf); |
| 91 | |
| 92 | void ehb_write(); |
| 93 | void edb_write(); |
| 94 | void ihb_read(); |
| 95 | void idb_read(); |
| 96 | void ingress_packet_handler(); |
| 97 | void egress_packet_handler(); |
| 98 | void ilu_credit_update_handler(); |
| 99 | void write_error_csr(uint8, uint8, uint8, char[]); |
| 100 | |
| 101 | void proc_ce_int(); |
| 102 | void proc_ce_int_en(); |
| 103 | void proc_ue_int(); |
| 104 | void proc_ue_int_en(); |
| 105 | void proc_oe_int(); |
| 106 | void proc_oe_int_en(); |
| 107 | |
| 108 | void cto_req_handler(); |
| 109 | void mps_handler(); |
| 110 | void drain_handler(); |
| 111 | void pl_drain_catcher(); |
| 112 | void ilu_drain_catcher(); |
| 113 | void reset_handler(); |
| 114 | void init(); |
| 115 | |
| 116 | |
| 117 | enum {OE,UE,CE}; |
| 118 | |
| 119 | sc_event ce_ev; |
| 120 | sc_event ce_en_ev; |
| 121 | sc_uint<64> ce_err; |
| 122 | sc_uint<64> ce_int_en; |
| 123 | sc_event ue_ev; |
| 124 | sc_event ue_en_ev; |
| 125 | sc_uint<64> ue_err; |
| 126 | sc_uint<64> ue_int_en; |
| 127 | sc_event oe_ev; |
| 128 | sc_event oe_en_ev; |
| 129 | sc_uint<64> oe_err; |
| 130 | sc_uint<64> oe_int_en; |
| 131 | sc_event dev_ctl_ev; |
| 132 | |
| 133 | sc_event drain_req_ev; |
| 134 | |
| 135 | typedef sc_bv<(P2D_IHB_DPAR_WDTH+P2D_IHB_DATA_WDTH)> ihb_entry_type; |
| 136 | typedef sc_bv<(P2D_IDB_DPAR_WDTH+P2D_IDB_DATA_WDTH)> idb_entry_type; |
| 137 | typedef sc_bv<(D2P_EHB_DPAR_WDTH+D2P_EHB_DATA_WDTH)> ehb_entry_type; |
| 138 | typedef sc_bv<(D2P_EDB_DPAR_WDTH+D2P_EDB_DATA_WDTH)> edb_entry_type; |
| 139 | |
| 140 | ihb_entry_type ihb_buffer[IHB_BUF_SIZE]; |
| 141 | idb_entry_type idb_buffer[IDB_BUF_SIZE]; |
| 142 | |
| 143 | ehb_entry_type ehb_buffer[EHB_BUF_SIZE]; |
| 144 | edb_entry_type edb_buffer[EDB_BUF_SIZE]; |
| 145 | |
| 146 | sc_uint<P2D_IHB_WPTR_WDTH> ihb_wptr; |
| 147 | bool ihb_empty; |
| 148 | bool drain_state; |
| 149 | sc_uint<D2P_EDB_ADDR_WDTH-1> ecd_waddr; |
| 150 | sc_uint<D2P_EDB_ADDR_WDTH-1> erd_waddr; |
| 151 | sc_uint<D2P_IHB_ADDR_WDTH> ihb_wr_addr; |
| 152 | sc_uint<D2P_IHB_ADDR_WDTH+1> nxt_ihb_wr_addr; |
| 153 | sc_uint<D2P_IDB_ADDR_WDTH> idb_wr_addr; |
| 154 | sc_uint<D2P_IDB_ADDR_WDTH> nxt_idb_wr_addr; |
| 155 | |
| 156 | data_in_port<RefPciePacket> in_pkt_port; |
| 157 | data_out_port<RefPciePacket> req_pkt_port; |
| 158 | data_out_port<RefPciePacket> cmpl_pkt_port; |
| 159 | sc_port<tlm_get_if <sc_uint<5> > > cto_req_port; |
| 160 | |
| 161 | csr_if_port< CSR_ADDR_T, CSR_DATA_T > csr_port; |
| 162 | |
| 163 | sc_in<bool> clk; |
| 164 | sc_in<bool> rst_l; |
| 165 | |
| 166 | /** |
| 167 | IHB Interface |
| 168 | */ |
| 169 | sc_in<bool> d2p_ihb_clk; // IHB clk |
| 170 | sc_in<bool> d2p_ihb_rd; // Read En |
| 171 | sc_in<sc_bv<D2P_IHB_ADDR_WDTH> > d2p_ihb_addr; // Addr |
| 172 | sc_out<sc_bv<P2D_IHB_DATA_WDTH> > p2d_ihb_data; // Data |
| 173 | sc_out<sc_bv<P2D_IHB_DPAR_WDTH> > p2d_ihb_dpar; // Data Parity |
| 174 | sc_out<sc_bv<P2D_IHB_WPTR_WDTH> > p2d_ihb_wptr; // Wr Ptr (GC) |
| 175 | |
| 176 | /** |
| 177 | IDB Interface |
| 178 | */ |
| 179 | sc_in<bool> d2p_idb_clk; // IDB clk |
| 180 | sc_in<bool> d2p_idb_rd; // Read En |
| 181 | sc_in<sc_bv<D2P_IDB_ADDR_WDTH> > d2p_idb_addr; // Addr |
| 182 | sc_out<sc_bv<P2D_IDB_DATA_WDTH> > p2d_idb_data; // Data |
| 183 | sc_out<sc_bv<P2D_IDB_DPAR_WDTH> > p2d_idb_dpar; // Data Parity |
| 184 | |
| 185 | /** |
| 186 | Ingress Buffer Credit Interface |
| 187 | */ |
| 188 | sc_in<bool> d2p_ibc_req; // Ingr cr req |
| 189 | sc_out<bool> p2d_ibc_ack; // Ack |
| 190 | sc_in<sc_bv<D2P_IBC_NHC_WDTH> > d2p_ibc_nhc; // NPH credits |
| 191 | sc_in<sc_bv<D2P_IBC_PHC_WDTH> > d2p_ibc_phc; // PH credits |
| 192 | sc_in<sc_bv<D2P_IBC_PDC_WDTH> > d2p_ibc_pdc; // PD credits |
| 193 | |
| 194 | /** |
| 195 | Completion Timeout Interface |
| 196 | */ |
| 197 | sc_out<bool> p2d_cto_req; |
| 198 | sc_out<sc_bv<P2D_CTO_TAG_WDTH> > p2d_cto_tag; |
| 199 | sc_in<bool> d2p_cto_ack; |
| 200 | |
| 201 | /** |
| 202 | Status Interface |
| 203 | */ |
| 204 | sc_out<bool> p2d_drain; // Drain signal to ILU |
| 205 | sc_out<sc_bv<P2D_MPS_WDTH> > p2d_mps; // Max Payld size |
| 206 | sc_out<bool> p2d_ue_int; // uncorrectable error |
| 207 | sc_out<bool> p2d_ce_int; // correctable error |
| 208 | sc_out<bool> p2d_oe_int; // other error |
| 209 | |
| 210 | /** |
| 211 | Buffer Management Interface (all pointer values are gray coded) |
| 212 | */ |
| 213 | sc_in<sc_bv<D2P_ECH_WPTR_WDTH> > d2p_ech_wptr; // Cpl buf EHB wr ptr |
| 214 | sc_out<sc_bv<P2D_ECH_RPTR_WDTH> > p2d_ech_rptr; // Cpl buf EHB rd ptr |
| 215 | sc_in<sc_bv<D2P_ERH_WPTR_WDTH> > d2p_erh_wptr; // Req buf EHB wr ptr |
| 216 | sc_out<sc_bv<P2D_ERH_RPTR_WDTH> > p2d_erh_rptr; // Req buf EHB rd ptr |
| 217 | sc_out<sc_bv<P2D_ECD_RPTR_WDTH> > p2d_ecd_rptr; // DMA cpl buf rd ptr |
| 218 | sc_out<sc_bv<P2D_ERD_RPTR_WDTH> > p2d_erd_rptr; // PIO Wr buf rd ptr |
| 219 | |
| 220 | /** |
| 221 | EHB Interfce |
| 222 | */ |
| 223 | // sc_in<bool> d2p_ehb_clk; // EHB Clk |
| 224 | sc_in<bool> d2p_ehb_we; // EHB Write |
| 225 | sc_in<sc_bv<D2P_EHB_ADDR_WDTH> > d2p_ehb_addr; // EHB Wr ptr |
| 226 | sc_in<sc_bv<D2P_EHB_DATA_WDTH> > d2p_ehb_data; // EHB record |
| 227 | sc_in<sc_bv<D2P_EHB_DPAR_WDTH> > d2p_ehb_dpar; // EHB Wd Parity |
| 228 | |
| 229 | /** |
| 230 | EDB Interfce |
| 231 | */ |
| 232 | // sc_in<bool> d2p_edb_clk; // EDB Clk |
| 233 | sc_in<bool> d2p_edb_we; // EDB Write |
| 234 | sc_in<sc_bv<D2P_EDB_ADDR_WDTH> > d2p_edb_addr; // EDB Wr ptr |
| 235 | sc_in<sc_bv<D2P_EDB_DATA_WDTH> > d2p_edb_data; // EDB record |
| 236 | sc_in<sc_bv<D2P_EDB_DPAR_WDTH> > d2p_edb_dpar; // EDB Wd Parity |
| 237 | |
| 238 | sc_process_handle ingress_packet_handler_ph; |
| 239 | sc_process_handle egress_packet_handler_ph; |
| 240 | sc_event *parent_global_event; //global event |
| 241 | uint8 *parent_global_event_type; //global event type |
| 242 | |
| 243 | bool SW_RESET; |
| 244 | bool POR_RESET; |
| 245 | bool RETRAIN_NO_RESET; |
| 246 | sc_event reset_ev; |
| 247 | |
| 248 | sc_uint<64> recovered_credits; |
| 249 | |
| 250 | }; |
| 251 | }; // namespace pcie |
| 252 | |
| 253 | #endif //INC_ilu_intf_hpp__ |