| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: deserializer.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `timescale 100ps / 10ps |
| 36 | `ifdef LINK_1 |
| 37 | `define LINK_WIDTH 1 |
| 38 | `else |
| 39 | `ifdef LINK_2 |
| 40 | `define LINK_WIDTH 2 |
| 41 | `else |
| 42 | `ifdef LINK_4 |
| 43 | `define LINK_WIDTH 4 |
| 44 | `else |
| 45 | `ifdef LINK_12 |
| 46 | `define LINK_WIDTH 12 |
| 47 | `else |
| 48 | `ifdef LINK_16 |
| 49 | `define LINK_WIDTH 16 |
| 50 | `else |
| 51 | `ifdef LINK_24 |
| 52 | `define LINK_WIDTH 24 |
| 53 | `else |
| 54 | `ifdef LINK_32 |
| 55 | `define LINK_WIDTH 32 |
| 56 | `else |
| 57 | `define LINK_WIDTH 8 |
| 58 | `endif |
| 59 | `endif |
| 60 | `endif |
| 61 | `endif |
| 62 | `endif |
| 63 | `endif |
| 64 | `endif |
| 65 | |
| 66 | |
| 67 | `define IDLE 0 |
| 68 | `define ACTIVE 1 |
| 69 | /// This module deserializes the data after it samples it from the bus |
| 70 | module deserializer( lane_in, |
| 71 | lane_in_bar, |
| 72 | lane_out0, |
| 73 | lane_out1, |
| 74 | lane_out2, |
| 75 | lane_out3, |
| 76 | lane_out4, |
| 77 | lane_out5, |
| 78 | lane_out6, |
| 79 | lane_out7, |
| 80 | lane_out8, |
| 81 | lane_out9, |
| 82 | lane_out0_b, |
| 83 | lane_out1_b, |
| 84 | lane_out2_b, |
| 85 | lane_out3_b, |
| 86 | lane_out4_b, |
| 87 | lane_out5_b, |
| 88 | lane_out6_b, |
| 89 | lane_out7_b, |
| 90 | lane_out8_b, |
| 91 | lane_out9_b, |
| 92 | frm_boundary, |
| 93 | init_done, |
| 94 | ts1_pattern_received, |
| 95 | data_rdy, |
| 96 | link_clk); |
| 97 | |
| 98 | |
| 99 | output [`LINK_WIDTH-1:0] lane_out0; |
| 100 | output [`LINK_WIDTH-1:0] lane_out1; |
| 101 | output [`LINK_WIDTH-1:0] lane_out2; |
| 102 | output [`LINK_WIDTH-1:0] lane_out3; |
| 103 | output [`LINK_WIDTH-1:0] lane_out4; |
| 104 | output [`LINK_WIDTH-1:0] lane_out5; |
| 105 | output [`LINK_WIDTH-1:0] lane_out6; |
| 106 | output [`LINK_WIDTH-1:0] lane_out7; |
| 107 | output [`LINK_WIDTH-1:0] lane_out8; |
| 108 | output [`LINK_WIDTH-1:0] lane_out9; |
| 109 | output [`LINK_WIDTH-1:0] lane_out0_b; |
| 110 | output [`LINK_WIDTH-1:0] lane_out1_b; |
| 111 | output [`LINK_WIDTH-1:0] lane_out2_b; |
| 112 | output [`LINK_WIDTH-1:0] lane_out3_b; |
| 113 | output [`LINK_WIDTH-1:0] lane_out4_b; |
| 114 | output [`LINK_WIDTH-1:0] lane_out5_b; |
| 115 | output [`LINK_WIDTH-1:0] lane_out6_b; |
| 116 | output [`LINK_WIDTH-1:0] lane_out7_b; |
| 117 | output [`LINK_WIDTH-1:0] lane_out8_b; |
| 118 | output [`LINK_WIDTH-1:0] lane_out9_b; |
| 119 | output data_rdy; |
| 120 | input [`LINK_WIDTH-1:0] lane_in; |
| 121 | input [`LINK_WIDTH-1:0] lane_in_bar; |
| 122 | input init_done; |
| 123 | |
| 124 | input link_clk; |
| 125 | input frm_boundary; |
| 126 | input ts1_pattern_received; |
| 127 | |
| 128 | reg [3:0] curr_state; |
| 129 | reg [1:0] curr_pl_state; |
| 130 | reg [`LINK_WIDTH-1:0] reg_out0; |
| 131 | reg [`LINK_WIDTH-1:0] reg_out1; |
| 132 | reg [`LINK_WIDTH-1:0] reg_out2; |
| 133 | reg [`LINK_WIDTH-1:0] reg_out3; |
| 134 | reg [`LINK_WIDTH-1:0] reg_out4; |
| 135 | reg [`LINK_WIDTH-1:0] reg_out5; |
| 136 | reg [`LINK_WIDTH-1:0] reg_out6; |
| 137 | reg [`LINK_WIDTH-1:0] reg_out7; |
| 138 | reg [`LINK_WIDTH-1:0] reg_out8; |
| 139 | reg [`LINK_WIDTH-1:0] reg_out9; |
| 140 | |
| 141 | reg [`LINK_WIDTH-1:0] reg_out0_b; |
| 142 | reg [`LINK_WIDTH-1:0] reg_out1_b; |
| 143 | reg [`LINK_WIDTH-1:0] reg_out2_b; |
| 144 | reg [`LINK_WIDTH-1:0] reg_out3_b; |
| 145 | reg [`LINK_WIDTH-1:0] reg_out4_b; |
| 146 | reg [`LINK_WIDTH-1:0] reg_out5_b; |
| 147 | reg [`LINK_WIDTH-1:0] reg_out6_b; |
| 148 | reg [`LINK_WIDTH-1:0] reg_out7_b; |
| 149 | reg [`LINK_WIDTH-1:0] reg_out8_b; |
| 150 | reg [`LINK_WIDTH-1:0] reg_out9_b; |
| 151 | |
| 152 | reg [`LINK_WIDTH-1:0] reg_in0; |
| 153 | reg [`LINK_WIDTH-1:0] reg_in1; |
| 154 | reg [`LINK_WIDTH-1:0] reg_in2; |
| 155 | reg [`LINK_WIDTH-1:0] reg_in3; |
| 156 | reg [`LINK_WIDTH-1:0] reg_in4; |
| 157 | reg [`LINK_WIDTH-1:0] reg_in5; |
| 158 | reg [`LINK_WIDTH-1:0] reg_in6; |
| 159 | reg [`LINK_WIDTH-1:0] reg_in7; |
| 160 | reg [`LINK_WIDTH-1:0] reg_in8; |
| 161 | reg [`LINK_WIDTH-1:0] reg_in9; |
| 162 | reg [`LINK_WIDTH-1:0] reg_in0_b; |
| 163 | |
| 164 | reg [`LINK_WIDTH-1:0] reg_in1_b; |
| 165 | reg [`LINK_WIDTH-1:0] reg_in2_b; |
| 166 | reg [`LINK_WIDTH-1:0] reg_in3_b; |
| 167 | reg [`LINK_WIDTH-1:0] reg_in4_b; |
| 168 | reg [`LINK_WIDTH-1:0] reg_in5_b; |
| 169 | reg [`LINK_WIDTH-1:0] reg_in6_b; |
| 170 | reg [`LINK_WIDTH-1:0] reg_in7_b; |
| 171 | reg [`LINK_WIDTH-1:0] reg_in8_b; |
| 172 | reg [`LINK_WIDTH-1:0] reg_in9_b; |
| 173 | reg [9:0] ireg_in; |
| 174 | reg [9:0] ireg_in_b; |
| 175 | reg [3:0] sym_counter; |
| 176 | reg [3:0] lock_counter; |
| 177 | reg [3:0] prev_sym_counter; |
| 178 | reg com_detected; |
| 179 | |
| 180 | |
| 181 | wire [`LINK_WIDTH-1:0] in_val; |
| 182 | wire [`LINK_WIDTH-1:0] in_val_bar; |
| 183 | reg data_rdy_reg; |
| 184 | |
| 185 | assign lane_out0 = reg_out0; |
| 186 | assign lane_out1 = reg_out1; |
| 187 | assign lane_out2 = reg_out2; |
| 188 | assign lane_out3 = reg_out3; |
| 189 | assign lane_out4 = reg_out4; |
| 190 | assign lane_out5 = reg_out5; |
| 191 | assign lane_out6 = reg_out6; |
| 192 | assign lane_out7 = reg_out7; |
| 193 | assign lane_out8 = reg_out8; |
| 194 | assign lane_out9 = reg_out9; |
| 195 | assign lane_out0_b = reg_out0_b; |
| 196 | assign lane_out1_b = reg_out1_b; |
| 197 | assign lane_out2_b = reg_out2_b; |
| 198 | assign lane_out3_b = reg_out3_b; |
| 199 | assign lane_out4_b = reg_out4_b; |
| 200 | assign lane_out5_b = reg_out5_b; |
| 201 | assign lane_out6_b = reg_out6_b; |
| 202 | assign lane_out7_b = reg_out7_b; |
| 203 | assign lane_out8_b = reg_out8_b; |
| 204 | assign lane_out9_b = reg_out9_b; |
| 205 | assign data_rdy = data_rdy_reg; |
| 206 | |
| 207 | assign in_val = lane_in; |
| 208 | assign in_val_bar = lane_in_bar; |
| 209 | |
| 210 | |
| 211 | initial |
| 212 | begin |
| 213 | curr_state = 4'h0; |
| 214 | curr_pl_state = 2'h0; |
| 215 | sym_counter = 4'h0; |
| 216 | lock_counter = 4'h0; |
| 217 | prev_sym_counter = 0; |
| 218 | end |
| 219 | |
| 220 | always @(negedge link_clk) |
| 221 | begin |
| 222 | if(sym_counter === 4'ha) |
| 223 | sym_counter <= 1; |
| 224 | else |
| 225 | sym_counter <= sym_counter + 1; |
| 226 | end |
| 227 | |
| 228 | always @(negedge link_clk) |
| 229 | begin |
| 230 | case(curr_pl_state) |
| 231 | `IDLE : begin |
| 232 | if(lane_in !== lane_in_bar) |
| 233 | curr_pl_state <= `ACTIVE; |
| 234 | end |
| 235 | |
| 236 | `ACTIVE : begin |
| 237 | if((lane_in === lane_in_bar) && init_done) |
| 238 | curr_pl_state <= `IDLE; |
| 239 | end |
| 240 | endcase |
| 241 | end |
| 242 | |
| 243 | /// data shifting logic |
| 244 | always @(posedge link_clk) |
| 245 | begin |
| 246 | if((curr_pl_state === `ACTIVE)) |
| 247 | begin |
| 248 | ireg_in[9:0] <= {in_val[0],ireg_in[9:1]}; |
| 249 | ireg_in_b[9:0] <= {in_val_bar[0],ireg_in_b[9:1]}; |
| 250 | end |
| 251 | end |
| 252 | |
| 253 | |
| 254 | always @(negedge link_clk) |
| 255 | begin |
| 256 | if(init_done || !ts1_pattern_received) |
| 257 | begin |
| 258 | case(curr_state) |
| 259 | 4'h0 : begin curr_state <= 1; end |
| 260 | 4'h1 : begin curr_state <= 2; end |
| 261 | 4'h2 : begin curr_state <= 3; end |
| 262 | 4'h3 : begin curr_state <= 4; end |
| 263 | 4'h4 : begin curr_state <= 5; end |
| 264 | 4'h5 : begin curr_state <= 6; end |
| 265 | 4'h6 : begin curr_state <= 7; end |
| 266 | 4'h7 : begin curr_state <= 8; end |
| 267 | 4'h8 : begin curr_state <= 9; end |
| 268 | 4'h9 : begin if(frm_boundary) curr_state <= 0; end |
| 269 | endcase |
| 270 | end |
| 271 | end |
| 272 | |
| 273 | /// Store the incoming data into registers |
| 274 | always @(negedge link_clk) |
| 275 | begin |
| 276 | reg_out0 <= reg_in0; |
| 277 | reg_out1 <= reg_in1; |
| 278 | reg_out2 <= reg_in2; |
| 279 | reg_out3 <= reg_in3; |
| 280 | reg_out4 <= reg_in4; |
| 281 | reg_out5 <= reg_in5; |
| 282 | reg_out6 <= reg_in6; |
| 283 | reg_out7 <= reg_in7; |
| 284 | reg_out8 <= reg_in8; |
| 285 | reg_out9 <= reg_in9; |
| 286 | reg_out0_b <= reg_in0_b; |
| 287 | reg_out1_b <= reg_in1_b; |
| 288 | reg_out2_b <= reg_in2_b; |
| 289 | reg_out3_b <= reg_in3_b; |
| 290 | reg_out4_b <= reg_in4_b; |
| 291 | reg_out5_b <= reg_in5_b; |
| 292 | reg_out6_b <= reg_in6_b; |
| 293 | reg_out7_b <= reg_in7_b; |
| 294 | reg_out8_b <= reg_in8_b; |
| 295 | reg_out9_b <= reg_in9_b; |
| 296 | end |
| 297 | |
| 298 | |
| 299 | /// Based on the current state counters assign values to registers |
| 300 | /// Reset current state counter if ini not yet done |
| 301 | always @(posedge link_clk) |
| 302 | begin |
| 303 | if(init_done || !ts1_pattern_received) |
| 304 | begin |
| 305 | case(curr_state) |
| 306 | 4'h0 : begin reg_in0 <= in_val; reg_in0_b <= in_val_bar; end |
| 307 | 4'h1 : begin reg_in1 <= in_val; reg_in1_b <= in_val_bar; end |
| 308 | 4'h2 : begin reg_in2 <= in_val; reg_in2_b <= in_val_bar; end |
| 309 | 4'h3 : begin reg_in3 <= in_val; reg_in3_b <= in_val_bar; end |
| 310 | 4'h4 : begin reg_in4 <= in_val; reg_in4_b <= in_val_bar; end |
| 311 | 4'h5 : begin reg_in5 <= in_val; reg_in5_b <= in_val_bar; end |
| 312 | 4'h6 : begin reg_in6 <= in_val; reg_in6_b <= in_val_bar; end |
| 313 | 4'h7 : begin reg_in7 <= in_val; reg_in7_b <= in_val_bar; end |
| 314 | 4'h8 : begin reg_in8 <= in_val; reg_in8_b <= in_val_bar; end |
| 315 | 4'h9 : begin reg_in9 <= in_val; reg_in9_b <= in_val_bar; end |
| 316 | endcase |
| 317 | end |
| 318 | else |
| 319 | curr_state <= 4'h0; |
| 320 | end |
| 321 | |
| 322 | endmodule |