| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fifo.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module fbd_fifo (rdata,wfull,rempty,wdata,winc,wclk,wrst_n,rinc,rclk,rrst_n,count); |
| 36 | parameter DSIZE = 72; |
| 37 | parameter ASIZE = 6; |
| 38 | |
| 39 | output [DSIZE-1:0] rdata; |
| 40 | output wfull; |
| 41 | output rempty; |
| 42 | input [DSIZE-1:0] wdata; |
| 43 | input winc,wclk,wrst_n; |
| 44 | input rinc,rclk,rrst_n; |
| 45 | output [ASIZE-1:0] count; |
| 46 | reg [ASIZE-1:0] count_reg; |
| 47 | |
| 48 | wire [ASIZE-1:0] waddr,raddr; |
| 49 | wire [ASIZE:0] wptr,rptr,wrptr2,rwptr2; |
| 50 | |
| 51 | wire [ASIZE-1:0] count = count_reg; |
| 52 | |
| 53 | |
| 54 | |
| 55 | sync_r2w #(ASIZE) sync_r2w ( .wrptr2(wrptr2), |
| 56 | .rptr(rptr), |
| 57 | .wclk(wclk), |
| 58 | .wrst_n(wrst_n)); |
| 59 | |
| 60 | sync_w2r #(ASIZE) sync_w2r( .rwptr2(rwptr2), |
| 61 | .wptr(wptr), |
| 62 | .rclk(rclk), |
| 63 | .rrst_n(rrst_n)); |
| 64 | |
| 65 | fifomem #(DSIZE,ASIZE) fifomem ( .rdata(rdata), |
| 66 | .wdata(wdata), |
| 67 | .waddr(waddr), |
| 68 | .raddr(raddr), |
| 69 | .wclken(winc), |
| 70 | .wclk(wclk)); |
| 71 | |
| 72 | rptr_empty #(ASIZE) rptr_empty ( .rempty(rempty), |
| 73 | .raddr(raddr), |
| 74 | .rptr(rptr), |
| 75 | .rwptr2(rwptr2), |
| 76 | .rinc(rinc), |
| 77 | .rclk(rclk), |
| 78 | .rrst_n(rrst_n)); |
| 79 | |
| 80 | wptr_full #(ASIZE) wptr_full ( .wfull(wfull), |
| 81 | .waddr(waddr), |
| 82 | .wptr(wptr), |
| 83 | .wrptr2(wrptr2), |
| 84 | .winc(winc), |
| 85 | .wclk(wclk), |
| 86 | .wrst_n(wrst_n)); |
| 87 | |
| 88 | |
| 89 | endmodule |
| 90 | |
| 91 | |
| 92 | module beh_fifo (rdata,wfull,rempty,wdata,winc,wclk,wrst_n,rinc,rclk,rrst_n,inv); |
| 93 | parameter DSIZE = 72; |
| 94 | parameter ASIZE = 6; |
| 95 | |
| 96 | output [DSIZE-1:0] rdata; |
| 97 | output wfull; |
| 98 | output rempty; |
| 99 | input [DSIZE-1:0] wdata; |
| 100 | input winc,wclk,wrst_n; |
| 101 | input rinc,rclk,rrst_n; |
| 102 | input inv; |
| 103 | wire [ASIZE-1:0] waddr,raddr; |
| 104 | reg [ASIZE:0] wptr,wrptr1,wrptr2,wrptr3; |
| 105 | reg [ASIZE:0] rptr,rwptr1,rwptr2,rwptr3; |
| 106 | |
| 107 | parameter MEMDEPTH = 1<<ASIZE; |
| 108 | |
| 109 | `ifdef AXIS |
| 110 | wire [DSIZE-1:0] axis_rdata ; |
| 111 | wire [DSIZE-1:0] axis_wdata = wdata; |
| 112 | wire axis_winc = winc; |
| 113 | wire axis_rinc = rinc; |
| 114 | wire axis_rclk = rclk; |
| 115 | wire axis_wclk = wclk; |
| 116 | wire [ASIZE-1:0] axis_rptr = (rinc && !rempty) ? rptr[ASIZE-1:0]+1 : rptr[ASIZE-1:0]; |
| 117 | wire [ASIZE-1:0] axis_wptr = wptr[ASIZE-1:0]; |
| 118 | |
| 119 | |
| 120 | `ifdef PALLADIUM |
| 121 | |
| 122 | reg [(DSIZE - 1):0] ex_mem [0:MEMDEPTH-1]; |
| 123 | reg [(DSIZE - 1):0] axis_rdata_reg; |
| 124 | |
| 125 | assign axis_rdata=axis_rdata_reg; |
| 126 | always @ (posedge axis_rclk) |
| 127 | axis_rdata_reg <= ex_mem[axis_rptr]; |
| 128 | |
| 129 | always @ (posedge axis_wclk) |
| 130 | begin |
| 131 | if (axis_winc) |
| 132 | ex_mem[axis_wptr] <= axis_wdata; |
| 133 | |
| 134 | end |
| 135 | |
| 136 | `else |
| 137 | axis_smem #(ASIZE,DSIZE,2,0) ex_mem ( {axis_rdata,{DSIZE{1'bz}}}, // output port |
| 138 | {{DSIZE{1'bz}},axis_wdata}, // input port |
| 139 | {axis_rptr,axis_wptr}, //address port |
| 140 | {1'b0,axis_winc}, // write enable |
| 141 | {1'b1,1'b1}, // chip enable |
| 142 | {axis_rclk,axis_wclk}, // clock |
| 143 | {{DSIZE{1'bz}},{DSIZE{1'bz}}} // write masks |
| 144 | ); |
| 145 | |
| 146 | `endif // PALLADIUM |
| 147 | |
| 148 | assign rdata = axis_rdata; |
| 149 | `else |
| 150 | reg [DSIZE-1:0] ex_mem [0:MEMDEPTH-1]; |
| 151 | `endif |
| 152 | |
| 153 | |
| 154 | `ifdef AXIS |
| 155 | initial begin |
| 156 | {rwptr3,rwptr2,rwptr1} = 0; |
| 157 | rptr = 0; |
| 158 | {wrptr3,wrptr2,wrptr1} =0; |
| 159 | wptr = 0; |
| 160 | end |
| 161 | |
| 162 | always@(posedge wclk) |
| 163 | begin |
| 164 | if ( !wrst_n || inv) wptr <= 0; |
| 165 | else if (winc && ~wfull) begin |
| 166 | wptr <= wptr+1; |
| 167 | end |
| 168 | end |
| 169 | |
| 170 | always@(posedge wclk) // or negedge wrst_n) |
| 171 | if (!wrst_n ) {wrptr3,wrptr2,wrptr1} <=0; |
| 172 | else if ( inv ) {wrptr3,wrptr2,wrptr1} <=0; |
| 173 | else {wrptr3,wrptr2,wrptr1} <= {wrptr2,wrptr1,rptr} ; |
| 174 | |
| 175 | always@(posedge rclk ) //or negedge rrst_n) |
| 176 | if (!rrst_n ) rptr <=0; |
| 177 | else if ( inv) rptr <=0; |
| 178 | else if ( rinc && !rempty ) rptr <= rptr+1; |
| 179 | |
| 180 | always@(posedge rclk ) //or negedge rrst_n) |
| 181 | if (!rrst_n ) {rwptr3,rwptr2,rwptr1} <=0; |
| 182 | else if ( inv ) {rwptr3,rwptr2,rwptr1} <=0; |
| 183 | else {rwptr3,rwptr2,rwptr1} <= {rwptr2,rwptr1,wptr} ; |
| 184 | |
| 185 | `else |
| 186 | // VCS control logic |
| 187 | |
| 188 | initial begin |
| 189 | {rwptr3,rwptr2,rwptr1} = 0; |
| 190 | rptr = 0; |
| 191 | {wrptr3,wrptr2,wrptr1} =0; |
| 192 | wptr = 0; |
| 193 | end |
| 194 | |
| 195 | |
| 196 | assign rdata=ex_mem[rptr[ASIZE-1:0]]; |
| 197 | |
| 198 | always@(posedge wclk) |
| 199 | begin |
| 200 | if ( !wrst_n || inv) wptr <= 0; |
| 201 | else if (winc && ~wfull) begin |
| 202 | ex_mem[wptr[ASIZE-1:0]] <= wdata; |
| 203 | wptr <= wptr+1; |
| 204 | end |
| 205 | end |
| 206 | |
| 207 | always@(posedge wclk) |
| 208 | if (!wrst_n || inv ) {wrptr3,wrptr2,wrptr1} <=0; |
| 209 | else {wrptr3,wrptr2,wrptr1} <= {wrptr2,wrptr1,rptr} ; |
| 210 | |
| 211 | always@(posedge rclk) |
| 212 | if (!rrst_n || inv) rptr <=0; |
| 213 | else if ( rinc && !rempty ) rptr <= rptr+1; |
| 214 | |
| 215 | always@(posedge rclk) |
| 216 | if (!rrst_n || inv ) {rwptr3,rwptr2,rwptr1} <=0; |
| 217 | else {rwptr3,rwptr2,rwptr1} <= {rwptr2,rwptr1,wptr} ; |
| 218 | |
| 219 | `endif |
| 220 | |
| 221 | assign rempty = (rptr[ASIZE:0] == rwptr3[ASIZE:0]) ? 1'b1 : 1'b0; |
| 222 | assign wfull = (( wptr[ASIZE-1:0] == wrptr3[ASIZE-1:0]) & ( wptr[ASIZE] != wrptr3[ASIZE])); |
| 223 | endmodule |
| 224 | |