| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: xgmii_tx_encoder_top.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module xgmii_tx_encoder_top ( |
| 36 | tx_clk, |
| 37 | tx_rst, |
| 38 | tx_enc_in, |
| 39 | tx_ctrl_in, |
| 40 | RDreg, |
| 41 | tx_10b_enc_out_a, |
| 42 | tx_10b_enc_out_b, |
| 43 | tx_10b_enc_out_c, |
| 44 | tx_10b_enc_out_d |
| 45 | ); |
| 46 | |
| 47 | input tx_clk; |
| 48 | input tx_rst; |
| 49 | input[31:0] tx_enc_in; |
| 50 | input[3:0] tx_ctrl_in; |
| 51 | |
| 52 | output RDreg; |
| 53 | |
| 54 | output [9:0] tx_10b_enc_out_a; |
| 55 | output [9:0] tx_10b_enc_out_b; |
| 56 | output [9:0] tx_10b_enc_out_c; |
| 57 | output [9:0] tx_10b_enc_out_d; |
| 58 | |
| 59 | |
| 60 | |
| 61 | wire even; |
| 62 | wire is16; |
| 63 | wire sp_tmp; |
| 64 | wire send0_A; |
| 65 | wire send1_A; |
| 66 | wire send2_A; |
| 67 | wire send3_A; |
| 68 | |
| 69 | reg r_send0_A; |
| 70 | reg r_send1_A; |
| 71 | reg r_send2_A; |
| 72 | reg r_send3_A; |
| 73 | |
| 74 | reg[7:0] idle_count; |
| 75 | reg [3:0]idle_cycle; |
| 76 | |
| 77 | reg lane0,lane1,lane2,lane3; |
| 78 | |
| 79 | reg trig; |
| 80 | reg trig_1; |
| 81 | |
| 82 | |
| 83 | |
| 84 | wire [9:0] tx_10b_enc_out_a_enc; |
| 85 | wire [9:0] tx_10b_enc_out_b_enc; |
| 86 | wire [9:0] tx_10b_enc_out_c_enc; |
| 87 | wire [9:0] tx_10b_enc_out_d_enc; |
| 88 | |
| 89 | reg [9:0] tx_10b_enc_out_a; |
| 90 | reg [9:0] tx_10b_enc_out_b; |
| 91 | reg [9:0] tx_10b_enc_out_c; |
| 92 | reg [9:0] tx_10b_enc_out_d; |
| 93 | |
| 94 | |
| 95 | |
| 96 | integer remote_fault_start_time, remote_fault_stop_time; |
| 97 | reg fault_sel; |
| 98 | wire[31:0] tx_8bit_to_enc; |
| 99 | wire[3:0] tx_ctrl_to_enc; |
| 100 | |
| 101 | initial begin |
| 102 | if($test$plusargs("remote_fault_start_time=")) |
| 103 | remote_fault_start_time = $util_get_plus_args_num("remote_fault_start_time="); |
| 104 | else remote_fault_start_time = 0; |
| 105 | if($test$plusargs("remote_fault_stop_time=")) |
| 106 | remote_fault_stop_time = $util_get_plus_args_num("remote_fault_stop_time="); |
| 107 | else remote_fault_stop_time = 0; |
| 108 | end |
| 109 | |
| 110 | //-vcs_run_args=+remote_fault_start_time=42940000 \ |
| 111 | //-vcs_run_args=+remote_fault_stop_time=42944000 \ |
| 112 | |
| 113 | always @(posedge tx_clk) |
| 114 | if(remote_fault_start_time>0 & |
| 115 | $stime > remote_fault_start_time & |
| 116 | $stime < remote_fault_stop_time) begin |
| 117 | fault_sel=1; |
| 118 | $display("Set fault_sel %m\n"); |
| 119 | end |
| 120 | else fault_sel=0; |
| 121 | |
| 122 | assign tx_8bit_to_enc = (fault_sel) ? {8'h2, 8'h0, 8'h0, 8'h9c} : tx_enc_in; |
| 123 | assign tx_ctrl_to_enc = tx_ctrl_in | {3'b0, fault_sel}; //only 9c is 'special' character |
| 124 | |
| 125 | |
| 126 | |
| 127 | `ifdef TEST_XAUI_DESKEW |
| 128 | |
| 129 | // 0 Delay |
| 130 | wire [9:0] tx_10b_enc_out_a_d0; |
| 131 | wire [9:0] tx_10b_enc_out_b_d0; |
| 132 | wire [9:0] tx_10b_enc_out_c_d0; |
| 133 | wire [9:0] tx_10b_enc_out_d_d0; |
| 134 | // 1 Delay |
| 135 | reg [9:0] tx_10b_enc_out_a_d1; |
| 136 | reg [9:0] tx_10b_enc_out_b_d1; |
| 137 | reg [9:0] tx_10b_enc_out_c_d1; |
| 138 | reg [9:0] tx_10b_enc_out_d_d1; |
| 139 | // 2 Delay |
| 140 | reg [9:0] tx_10b_enc_out_a_d2; |
| 141 | reg [9:0] tx_10b_enc_out_b_d2; |
| 142 | reg [9:0] tx_10b_enc_out_c_d2; |
| 143 | reg [9:0] tx_10b_enc_out_d_d2; |
| 144 | // 3 Delay |
| 145 | reg [9:0] tx_10b_enc_out_a_d3; |
| 146 | reg [9:0] tx_10b_enc_out_b_d3; |
| 147 | reg [9:0] tx_10b_enc_out_c_d3; |
| 148 | reg [9:0] tx_10b_enc_out_d_d3; |
| 149 | // 4 Delay |
| 150 | reg [9:0] tx_10b_enc_out_a_d4; |
| 151 | reg [9:0] tx_10b_enc_out_b_d4; |
| 152 | reg [9:0] tx_10b_enc_out_c_d4; |
| 153 | reg [9:0] tx_10b_enc_out_d_d4; |
| 154 | // 5 Delay |
| 155 | reg [9:0] tx_10b_enc_out_a_d5; |
| 156 | reg [9:0] tx_10b_enc_out_b_d5; |
| 157 | reg [9:0] tx_10b_enc_out_c_d5; |
| 158 | reg [9:0] tx_10b_enc_out_d_d5; |
| 159 | |
| 160 | reg [3:0] LANE0_CONFIG,LANE1_CONFIG,LANE2_CONFIG, LANE3_CONFIG; |
| 161 | |
| 162 | reg [8*60:1] lane0_arg,lane1_arg,lane2_arg,lane3_arg; |
| 163 | reg enable_skew; // Can be use when dynamically the configuration needs to be changed |
| 164 | |
| 165 | |
| 166 | initial begin |
| 167 | LANE0_CONFIG = 4'h0; |
| 168 | LANE1_CONFIG = 4'h0; |
| 169 | LANE2_CONFIG = 4'h0; |
| 170 | LANE3_CONFIG = 4'h0; |
| 171 | enable_skew =1; |
| 172 | |
| 173 | lane0_arg = "LANE0_CONFIG="; |
| 174 | if ($test$plusargs("LANE0_CONFIG=")) |
| 175 | LANE0_CONFIG = $util_get_plus_args_num(lane0_arg); |
| 176 | else LANE0_CONFIG = 4'h0; |
| 177 | |
| 178 | lane1_arg = "LANE1_CONFIG="; |
| 179 | if ($test$plusargs("LANE1_CONFIG=")) |
| 180 | LANE1_CONFIG = $util_get_plus_args_num(lane1_arg); |
| 181 | else LANE1_CONFIG = 4'h0; |
| 182 | |
| 183 | lane2_arg = "LANE2_CONFIG="; |
| 184 | if ($test$plusargs("LANE2_CONFIG=")) |
| 185 | LANE2_CONFIG = $util_get_plus_args_num(lane2_arg); |
| 186 | else LANE2_CONFIG = 4'h0; |
| 187 | |
| 188 | lane3_arg = "LANE3_CONFIG="; |
| 189 | if ($test$plusargs("LANE3_CONFIG=")) |
| 190 | LANE3_CONFIG = $util_get_plus_args_num(lane3_arg); |
| 191 | else LANE3_CONFIG = 4'h0; |
| 192 | |
| 193 | $display(" XAUI Skew Test Config: Lane0 = %d, Lane1 = %d, Lane2 = %d, Lane3 = %d",LANE0_CONFIG,LANE1_CONFIG,LANE2_CONFIG,LANE3_CONFIG); |
| 194 | |
| 195 | end |
| 196 | |
| 197 | assign tx_10b_enc_out_a_d0 = tx_10b_enc_out_a_enc; |
| 198 | assign tx_10b_enc_out_b_d0 = tx_10b_enc_out_b_enc; |
| 199 | assign tx_10b_enc_out_c_d0 = tx_10b_enc_out_c_enc; |
| 200 | assign tx_10b_enc_out_d_d0 = tx_10b_enc_out_d_enc; |
| 201 | |
| 202 | always@(posedge tx_clk) begin |
| 203 | if(tx_rst) begin |
| 204 | tx_10b_enc_out_a_d1 <= 10'h4ff; |
| 205 | tx_10b_enc_out_a_d2 <= 10'h4ff; |
| 206 | tx_10b_enc_out_a_d3 <= 10'h4ff; |
| 207 | tx_10b_enc_out_a_d4 <= 10'h4ff; |
| 208 | tx_10b_enc_out_a_d5 <= 10'h4ff; |
| 209 | |
| 210 | |
| 211 | tx_10b_enc_out_b_d1 <= 10'h4ff; |
| 212 | tx_10b_enc_out_b_d2 <= 10'h4ff; |
| 213 | tx_10b_enc_out_b_d3 <= 10'h4ff; |
| 214 | tx_10b_enc_out_b_d4 <= 10'h4ff; |
| 215 | tx_10b_enc_out_b_d5 <= 10'h4ff; |
| 216 | |
| 217 | tx_10b_enc_out_c_d1 <= 10'h4ff; |
| 218 | tx_10b_enc_out_c_d2 <= 10'h4ff; |
| 219 | tx_10b_enc_out_c_d3 <= 10'h4ff; |
| 220 | tx_10b_enc_out_c_d4 <= 10'h4ff; |
| 221 | tx_10b_enc_out_c_d5 <= 10'h4ff; |
| 222 | |
| 223 | tx_10b_enc_out_d_d1 <= 10'h4ff; |
| 224 | tx_10b_enc_out_d_d2 <= 10'h4ff; |
| 225 | tx_10b_enc_out_d_d3 <= 10'h4ff; |
| 226 | tx_10b_enc_out_d_d4 <= 10'h4ff; |
| 227 | tx_10b_enc_out_d_d5 <= 10'h4ff; |
| 228 | |
| 229 | |
| 230 | end else begin |
| 231 | tx_10b_enc_out_a_d1 <= tx_10b_enc_out_a_d0; |
| 232 | tx_10b_enc_out_a_d2 <= tx_10b_enc_out_a_d1; |
| 233 | tx_10b_enc_out_a_d3 <= tx_10b_enc_out_a_d2; |
| 234 | tx_10b_enc_out_a_d4 <= tx_10b_enc_out_a_d3; |
| 235 | tx_10b_enc_out_a_d5 <= tx_10b_enc_out_a_d4; |
| 236 | |
| 237 | tx_10b_enc_out_b_d1 <= tx_10b_enc_out_b_d0; |
| 238 | tx_10b_enc_out_b_d2 <= tx_10b_enc_out_b_d1; |
| 239 | tx_10b_enc_out_b_d3 <= tx_10b_enc_out_b_d2; |
| 240 | tx_10b_enc_out_b_d4 <= tx_10b_enc_out_b_d3; |
| 241 | tx_10b_enc_out_b_d5 <= tx_10b_enc_out_b_d4; |
| 242 | |
| 243 | tx_10b_enc_out_c_d1 <= tx_10b_enc_out_c_d0; |
| 244 | tx_10b_enc_out_c_d2 <= tx_10b_enc_out_c_d1; |
| 245 | tx_10b_enc_out_c_d3 <= tx_10b_enc_out_c_d2; |
| 246 | tx_10b_enc_out_c_d4 <= tx_10b_enc_out_c_d3; |
| 247 | tx_10b_enc_out_c_d5 <= tx_10b_enc_out_c_d4; |
| 248 | |
| 249 | tx_10b_enc_out_d_d1 <= tx_10b_enc_out_d_d0; |
| 250 | tx_10b_enc_out_d_d2 <= tx_10b_enc_out_d_d1; |
| 251 | tx_10b_enc_out_d_d3 <= tx_10b_enc_out_d_d2; |
| 252 | tx_10b_enc_out_d_d4 <= tx_10b_enc_out_d_d3; |
| 253 | tx_10b_enc_out_d_d5 <= tx_10b_enc_out_d_d4; |
| 254 | |
| 255 | end // else: !if(tx_rst) |
| 256 | end // always@ (posedge tx_clk) |
| 257 | |
| 258 | always@( tx_10b_enc_out_a_enc or tx_10b_enc_out_a_d0 or tx_10b_enc_out_a_d1 or tx_10b_enc_out_a_d2 or tx_10b_enc_out_a_d3 or tx_10b_enc_out_a_d4 or |
| 259 | tx_10b_enc_out_a_d5 or |
| 260 | |
| 261 | tx_10b_enc_out_b_enc or tx_10b_enc_out_b_d0 or tx_10b_enc_out_b_d1 or tx_10b_enc_out_b_d2 or tx_10b_enc_out_b_d3 or tx_10b_enc_out_b_d4 or |
| 262 | tx_10b_enc_out_b_d5 or |
| 263 | |
| 264 | tx_10b_enc_out_c_enc or tx_10b_enc_out_c_d0 or tx_10b_enc_out_c_d1 or tx_10b_enc_out_c_d2 or tx_10b_enc_out_c_d3 or tx_10b_enc_out_c_d4 or |
| 265 | tx_10b_enc_out_c_d5 or |
| 266 | |
| 267 | tx_10b_enc_out_d_enc or tx_10b_enc_out_d_d0 or tx_10b_enc_out_d_d1 or tx_10b_enc_out_d_d2 or tx_10b_enc_out_d_d3 or tx_10b_enc_out_d_d4 or |
| 268 | tx_10b_enc_out_d_d5 or |
| 269 | |
| 270 | LANE0_CONFIG or LANE1_CONFIG or LANE2_CONFIG or LANE3_CONFIG or enable_skew ) |
| 271 | |
| 272 | begin |
| 273 | |
| 274 | if(!enable_skew) begin |
| 275 | tx_10b_enc_out_a = tx_10b_enc_out_a_enc; |
| 276 | tx_10b_enc_out_b = tx_10b_enc_out_b_enc; |
| 277 | tx_10b_enc_out_c = tx_10b_enc_out_c_enc; |
| 278 | tx_10b_enc_out_d = tx_10b_enc_out_d_enc; |
| 279 | end |
| 280 | else begin |
| 281 | case(LANE0_CONFIG) |
| 282 | 4'b0000: begin |
| 283 | tx_10b_enc_out_a = tx_10b_enc_out_a_d0; |
| 284 | end |
| 285 | 4'b0001: begin |
| 286 | tx_10b_enc_out_a = tx_10b_enc_out_a_d1; |
| 287 | end |
| 288 | 4'b0010: begin |
| 289 | tx_10b_enc_out_a = tx_10b_enc_out_a_d2; |
| 290 | end |
| 291 | 4'b0011: begin |
| 292 | tx_10b_enc_out_a = tx_10b_enc_out_a_d3; |
| 293 | end |
| 294 | 4'b0100: begin |
| 295 | tx_10b_enc_out_a = tx_10b_enc_out_a_d4; |
| 296 | end |
| 297 | 4'b0101: begin |
| 298 | tx_10b_enc_out_a = tx_10b_enc_out_a_d5; |
| 299 | end |
| 300 | default: begin |
| 301 | $display(" ERROR Do You know What you are doing!! "); |
| 302 | end |
| 303 | endcase // case(LANE0_CONFIG) |
| 304 | |
| 305 | case(LANE1_CONFIG) |
| 306 | 4'b0000: begin |
| 307 | tx_10b_enc_out_b = tx_10b_enc_out_b_d0; |
| 308 | end |
| 309 | 4'b0001: begin |
| 310 | tx_10b_enc_out_b = tx_10b_enc_out_b_d1; |
| 311 | end |
| 312 | 4'b0010: begin |
| 313 | tx_10b_enc_out_b = tx_10b_enc_out_b_d2; |
| 314 | end |
| 315 | 4'b0011: begin |
| 316 | tx_10b_enc_out_b = tx_10b_enc_out_b_d3; |
| 317 | end |
| 318 | 4'b0100: begin |
| 319 | tx_10b_enc_out_b = tx_10b_enc_out_b_d4; |
| 320 | end |
| 321 | 4'b0101: begin |
| 322 | tx_10b_enc_out_b = tx_10b_enc_out_b_d5; |
| 323 | end |
| 324 | default: begin |
| 325 | $display(" ERROR Do You know What you are doing!! "); |
| 326 | end |
| 327 | endcase // case(LANE1_CONFIG) |
| 328 | |
| 329 | case(LANE2_CONFIG) |
| 330 | 4'b0000: begin |
| 331 | tx_10b_enc_out_c = tx_10b_enc_out_c_d0; |
| 332 | end |
| 333 | 4'b0001: begin |
| 334 | tx_10b_enc_out_c = tx_10b_enc_out_c_d1; |
| 335 | end |
| 336 | 4'b0010: begin |
| 337 | tx_10b_enc_out_c = tx_10b_enc_out_c_d2; |
| 338 | end |
| 339 | 4'b0011: begin |
| 340 | tx_10b_enc_out_c = tx_10b_enc_out_c_d3; |
| 341 | end |
| 342 | 4'b0100: begin |
| 343 | tx_10b_enc_out_c = tx_10b_enc_out_c_d4; |
| 344 | end |
| 345 | 4'b0101: begin |
| 346 | tx_10b_enc_out_c = tx_10b_enc_out_c_d5; |
| 347 | end |
| 348 | default: begin |
| 349 | $display(" ERROR Do You know What you are doing!! "); |
| 350 | end |
| 351 | endcase // case(LANE2_CONFIG) |
| 352 | |
| 353 | case(LANE3_CONFIG) |
| 354 | 4'b0000: begin |
| 355 | tx_10b_enc_out_d = tx_10b_enc_out_d_d0; |
| 356 | end |
| 357 | 4'b0001: begin |
| 358 | tx_10b_enc_out_d = tx_10b_enc_out_d_d1; |
| 359 | end |
| 360 | 4'b0010: begin |
| 361 | tx_10b_enc_out_d = tx_10b_enc_out_d_d2; |
| 362 | end |
| 363 | 4'b0011: begin |
| 364 | tx_10b_enc_out_d = tx_10b_enc_out_d_d3; |
| 365 | end |
| 366 | 4'b0100: begin |
| 367 | tx_10b_enc_out_d = tx_10b_enc_out_d_d4; |
| 368 | end |
| 369 | 4'b0101: begin |
| 370 | tx_10b_enc_out_d = tx_10b_enc_out_d_d5; |
| 371 | end |
| 372 | default: begin |
| 373 | $display(" ERROR Do You know What you are doing!! "); |
| 374 | end |
| 375 | endcase // case(LANE3_CONFIG) |
| 376 | |
| 377 | |
| 378 | end // else: !if(!enable_skew) |
| 379 | |
| 380 | end // always@ ( tx_10b_enc_out_a_enc or tx_10b_enc_out_a_d0 or tx_10b_enc_out_a_d1 or tx_10b_enc_out_a_d2 or tx_10b_enc_out_a_d3 or tx_10b_enc_out_a_d4 or... |
| 381 | |
| 382 | |
| 383 | `else |
| 384 | |
| 385 | always@(tx_10b_enc_out_a_enc) |
| 386 | tx_10b_enc_out_a = tx_10b_enc_out_a_enc; |
| 387 | always@(tx_10b_enc_out_b_enc) |
| 388 | tx_10b_enc_out_b = tx_10b_enc_out_b_enc; |
| 389 | always@(tx_10b_enc_out_c_enc) |
| 390 | tx_10b_enc_out_c = tx_10b_enc_out_c_enc; |
| 391 | always@(tx_10b_enc_out_d_enc) |
| 392 | tx_10b_enc_out_d = tx_10b_enc_out_d_enc; |
| 393 | |
| 394 | `endif |
| 395 | |
| 396 | |
| 397 | |
| 398 | |
| 399 | |
| 400 | |
| 401 | always @ (tx_ctrl_in or tx_enc_in ) |
| 402 | begin |
| 403 | if ((tx_ctrl_in[0] == 1) & (tx_enc_in[7:0] == 8'hfd)) |
| 404 | begin |
| 405 | lane0 =1; |
| 406 | lane1 =0; |
| 407 | lane2 =0; |
| 408 | lane3 =0; |
| 409 | end |
| 410 | else if ((tx_ctrl_in[1] == 1) & (tx_enc_in[15:8] == 8'hfd)) |
| 411 | begin |
| 412 | lane0 =0; |
| 413 | lane1 =1; |
| 414 | lane2 =0; |
| 415 | lane3 =0; |
| 416 | end |
| 417 | else if ((tx_ctrl_in[2] == 1) & (tx_enc_in[23:16] == 8'hfd)) |
| 418 | begin |
| 419 | lane0 =0; |
| 420 | lane1 =0; |
| 421 | lane2 =1; |
| 422 | lane3 =0; |
| 423 | end |
| 424 | else if ((tx_ctrl_in[3] == 1) & (tx_enc_in[31:24] == 8'hfd)) |
| 425 | begin |
| 426 | lane0 =0; |
| 427 | lane1 =0; |
| 428 | lane2 =0; |
| 429 | lane3 =1; |
| 430 | end |
| 431 | else |
| 432 | begin |
| 433 | lane0 =0; |
| 434 | lane1 =0; |
| 435 | lane2 =0; |
| 436 | lane3 =0; |
| 437 | end |
| 438 | end |
| 439 | |
| 440 | always @ (posedge tx_clk) |
| 441 | begin |
| 442 | if (lane0 == 1) |
| 443 | begin |
| 444 | repeat(1) @(posedge tx_clk) |
| 445 | trig = 1; |
| 446 | end |
| 447 | else if (lane1 == 1) |
| 448 | begin |
| 449 | repeat(1) @(posedge tx_clk) |
| 450 | trig = 1; |
| 451 | end |
| 452 | else if (lane2 == 1) |
| 453 | begin |
| 454 | repeat(1) @(posedge tx_clk) |
| 455 | trig = 1; |
| 456 | end |
| 457 | else if (lane3 == 1) |
| 458 | begin |
| 459 | trig = 1; |
| 460 | end |
| 461 | else |
| 462 | begin |
| 463 | trig = 0; |
| 464 | end |
| 465 | end |
| 466 | |
| 467 | |
| 468 | |
| 469 | |
| 470 | always @ (posedge tx_clk) |
| 471 | begin |
| 472 | if( tx_rst|(idle_count == 8'b1111_1111) | |
| 473 | ((tx_ctrl_in[0] == 1) & (tx_enc_in[7:0] == 8'hfb)) | |
| 474 | (lane0 == 1) | (lane1 == 1) | (lane2 == 1) | (lane3 ==1) ) |
| 475 | begin |
| 476 | idle_count = 0; |
| 477 | end |
| 478 | |
| 479 | else if( ((tx_ctrl_in[0] == 1) & (tx_enc_in[7:0] == 8'h07)) | |
| 480 | ((tx_ctrl_in[1] == 1) & (tx_enc_in[15:8] == 8'h07)) | |
| 481 | ((tx_ctrl_in[2] == 1) & (tx_enc_in[23:16] == 8'h07))| |
| 482 | ((tx_ctrl_in[3] == 1) & (tx_enc_in[31:24] == 8'h07)) ) |
| 483 | //((tx_ctrl_in[3] == 1) & (tx_enc_in[31:24] == 8'h07)) && (trig | trig1 ) ) |
| 484 | begin |
| 485 | idle_count = idle_count + 1; |
| 486 | end |
| 487 | else |
| 488 | begin |
| 489 | idle_count = idle_count ; |
| 490 | |
| 491 | end |
| 492 | end |
| 493 | |
| 494 | always @(tx_ctrl_in or tx_enc_in) |
| 495 | begin |
| 496 | if ((tx_ctrl_in[0] == 1) & (tx_enc_in[7:0] == 8'h07)) |
| 497 | begin |
| 498 | idle_cycle[0] = 1'b1; |
| 499 | //idle_cycle[3:1] = 3'b000; |
| 500 | end |
| 501 | else |
| 502 | idle_cycle[0] = 1'b0; |
| 503 | end |
| 504 | |
| 505 | always @(tx_ctrl_in or tx_enc_in) |
| 506 | begin |
| 507 | if ((tx_ctrl_in[1] == 1) & (tx_enc_in[15:8] == 8'h07)) |
| 508 | begin |
| 509 | //idle_cycle[0] = 1'b0; |
| 510 | idle_cycle[1] = 1'b1; |
| 511 | //idle_cycle[3:2] = 2'b00; |
| 512 | end |
| 513 | else |
| 514 | idle_cycle[1] = 1'b0; |
| 515 | end |
| 516 | |
| 517 | always @(tx_ctrl_in or tx_enc_in) |
| 518 | begin |
| 519 | if ((tx_ctrl_in[2] == 1) & (tx_enc_in[23:16] == 8'h07)) |
| 520 | begin |
| 521 | //idle_cycle[1:0] = 2'b00; |
| 522 | idle_cycle[2] = 1'b1; |
| 523 | //idle_cycle[3] = 1'b0; |
| 524 | end |
| 525 | else |
| 526 | idle_cycle[2] = 1'b0; |
| 527 | end |
| 528 | |
| 529 | always @(tx_ctrl_in or tx_enc_in) |
| 530 | begin |
| 531 | if ((tx_ctrl_in[3] == 1) & (tx_enc_in[31:24] == 8'h07)) |
| 532 | begin |
| 533 | //idle_cycle[2:0] = 3'b000; |
| 534 | idle_cycle[3] = 1'b1; |
| 535 | end |
| 536 | else |
| 537 | idle_cycle[3] = 1'b0; |
| 538 | end |
| 539 | |
| 540 | always @(lane0 or tx_ctrl_in or tx_enc_in ) |
| 541 | begin |
| 542 | if ( (lane0 == 1) & ( ((tx_ctrl_in[1] == 1) & (tx_enc_in[15:8])) | ((tx_ctrl_in[2] == 1) & (tx_enc_in[23:16] == 8'h07)) || ((tx_ctrl_in[3] == 1) & (tx_enc_in[31:24] == 8'h07)) ) ) |
| 543 | begin |
| 544 | r_send1_A = 1'b1; |
| 545 | r_send2_A = 1'b1; |
| 546 | r_send3_A = 1'b1; |
| 547 | end |
| 548 | else |
| 549 | begin |
| 550 | r_send1_A = 1'b0; |
| 551 | r_send2_A = 1'b0; |
| 552 | r_send3_A = 1'b0; |
| 553 | end |
| 554 | end |
| 555 | |
| 556 | |
| 557 | always @(lane1 or tx_ctrl_in or tx_enc_in ) |
| 558 | begin |
| 559 | if ( (lane1 == 1) & ( ((tx_ctrl_in[2] == 1) & (tx_enc_in[23:16] == 8'h07)) || ((tx_ctrl_in[3] == 1) & (tx_enc_in[31:24] == 8'h07)) ) ) |
| 560 | begin |
| 561 | r_send2_A = 1'b1; |
| 562 | r_send3_A = 1'b1; |
| 563 | end |
| 564 | else |
| 565 | begin |
| 566 | r_send2_A = 1'b0; |
| 567 | r_send3_A = 1'b0; |
| 568 | end |
| 569 | |
| 570 | end |
| 571 | |
| 572 | always @(lane2 or tx_ctrl_in or tx_enc_in ) |
| 573 | begin |
| 574 | if ( (lane2 == 1) & ((tx_ctrl_in[3] == 1) & (tx_enc_in[31:24] == 8'h07)) ) |
| 575 | r_send3_A = 1'b1; |
| 576 | else |
| 577 | r_send3_A = 1'b0; |
| 578 | end |
| 579 | |
| 580 | |
| 581 | // -- Adding these for creating random spacing between |A| |
| 582 | // characters |
| 583 | |
| 584 | reg [7:0] random_spacing_count; |
| 585 | reg [31:0] spacing; |
| 586 | reg [31:0] seed; |
| 587 | |
| 588 | |
| 589 | initial random_spacing_count =0; |
| 590 | initial seed =0; |
| 591 | |
| 592 | always@(posedge tx_clk) begin |
| 593 | spacing = $random(seed); |
| 594 | spacing = spacing %16; |
| 595 | random_spacing_count = spacing + 16; |
| 596 | end |
| 597 | |
| 598 | assign sp_tmp = tx_ctrl_in[3] | tx_ctrl_in[2] | tx_ctrl_in[1] | tx_ctrl_in[0]; |
| 599 | |
| 600 | assign even = ((idle_count %4 ==0 ) & (sp_tmp) )? 1:0; |
| 601 | // assign is16 = ((idle_count %16 ==0 ) & (sp_tmp))? 1:0; |
| 602 | assign is16 = ((idle_count %random_spacing_count ==0 ) & (sp_tmp))? 1:0; |
| 603 | |
| 604 | assign send0_A = 0; |
| 605 | assign send1_A = r_send1_A; |
| 606 | assign send2_A = r_send2_A; |
| 607 | assign send3_A = r_send3_A; |
| 608 | |
| 609 | |
| 610 | xgmii_tx_encoder #0 xgmii_A_enc ( |
| 611 | .tx_clk (tx_clk), |
| 612 | .tx_rst (tx_rst), |
| 613 | .idle_cycle (idle_cycle[0]), |
| 614 | .even (even), |
| 615 | .is16 (is16), |
| 616 | .eop (send0_A), |
| 617 | .tx_8b_enc_in (tx_8bit_to_enc[7:0]), |
| 618 | .special (tx_ctrl_to_enc[0]), |
| 619 | //.special (tx_ctrl_in[0]), |
| 620 | .RDreg (RDreg), |
| 621 | .tx_10b_enc_out (tx_10b_enc_out_a_enc[9:0]) |
| 622 | ); |
| 623 | |
| 624 | xgmii_tx_encoder #1 xgmii_B_enc ( |
| 625 | .tx_clk (tx_clk), |
| 626 | .tx_rst (tx_rst), |
| 627 | .idle_cycle (idle_cycle[1]), |
| 628 | .even (even), |
| 629 | .is16 (is16), |
| 630 | .eop (send1_A), |
| 631 | .tx_8b_enc_in (tx_8bit_to_enc[15:8]), |
| 632 | .special (tx_ctrl_to_enc[1]), |
| 633 | //.special (tx_ctrl_in[1]), |
| 634 | .RDreg (RDreg), |
| 635 | .tx_10b_enc_out (tx_10b_enc_out_b_enc[9:0]) |
| 636 | ); |
| 637 | |
| 638 | xgmii_tx_encoder #2 xgmii_C_enc ( |
| 639 | .tx_clk (tx_clk), |
| 640 | .tx_rst (tx_rst), |
| 641 | .idle_cycle (idle_cycle[2]), |
| 642 | .even (even), |
| 643 | .is16 (is16), |
| 644 | .eop (send2_A), |
| 645 | .tx_8b_enc_in (tx_8bit_to_enc[23:16]), |
| 646 | .special (tx_ctrl_to_enc[2]), |
| 647 | //.special (tx_ctrl_in[2]), |
| 648 | .RDreg (RDreg), |
| 649 | .tx_10b_enc_out (tx_10b_enc_out_c_enc[9:0]) |
| 650 | ); |
| 651 | |
| 652 | xgmii_tx_encoder #3 xgmii_D_enc ( |
| 653 | .tx_clk (tx_clk), |
| 654 | .tx_rst (tx_rst), |
| 655 | .idle_cycle (idle_cycle[3]), |
| 656 | .even (even), |
| 657 | .is16 (is16), |
| 658 | .eop (send3_A), |
| 659 | .tx_8b_enc_in (tx_8bit_to_enc[31:24]), |
| 660 | .special (tx_ctrl_to_enc[3]), |
| 661 | //.special (tx_ctrl_in[3]), |
| 662 | .RDreg (RDreg), |
| 663 | .tx_10b_enc_out (tx_10b_enc_out_d_enc[9:0]) |
| 664 | ); |
| 665 | |
| 666 | |
| 667 | |
| 668 | endmodule |
| 669 | |