| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: cpx_rep_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifndef FPGA |
| 36 | module cpx_rep_dp ( |
| 37 | mac0_rep_out, |
| 38 | mac1_rep_out, |
| 39 | mac2_rep_out, |
| 40 | mac3_rep_out, |
| 41 | mac4_rep_out, |
| 42 | mac5_rep_out, |
| 43 | mac6_rep_out, |
| 44 | scan_rep_out, |
| 45 | mac0_rep_in, |
| 46 | mac1_rep_in, |
| 47 | mac2_rep_in, |
| 48 | mac3_rep_in, |
| 49 | mac4_rep_in, |
| 50 | mac5_rep_in, |
| 51 | mac6_rep_in, |
| 52 | scan_rep_in); |
| 53 | wire [4:0] mac2_rep_0; |
| 54 | wire [4:0] mac3_rep_0; |
| 55 | wire [4:0] mac4_rep_0; |
| 56 | wire scan_rep7_out; |
| 57 | wire scan_rep5_out; |
| 58 | wire scan_rep3_out; |
| 59 | wire scan_rep1_out; |
| 60 | |
| 61 | |
| 62 | output [4:0] mac0_rep_out; |
| 63 | output [4:0] mac1_rep_out; |
| 64 | output [4:0] mac2_rep_out; |
| 65 | output [4:0] mac3_rep_out; |
| 66 | output [4:0] mac4_rep_out; |
| 67 | output [4:0] mac5_rep_out; |
| 68 | output [4:0] mac6_rep_out; |
| 69 | output scan_rep_out; |
| 70 | |
| 71 | |
| 72 | input [4:0] mac0_rep_in; |
| 73 | input [4:0] mac1_rep_in; |
| 74 | input [4:0] mac2_rep_in; |
| 75 | input [4:0] mac3_rep_in; |
| 76 | input [4:0] mac4_rep_in; |
| 77 | input [4:0] mac5_rep_in; |
| 78 | input [4:0] mac6_rep_in; |
| 79 | input scan_rep_in; |
| 80 | |
| 81 | |
| 82 | |
| 83 | |
| 84 | // io scache2 scache0 scache3 scache1 scache7 scache5 scache6 scache4 |
| 85 | // | | | | | | | | | |
| 86 | // v v v v v v v v v |
| 87 | // mac8- mac0 - mac1 -mac2 - mac3 - mac4 - mac5 - mac6 - mac7 |
| 88 | |
| 89 | |
| 90 | |
| 91 | // mac0 input go through 1 buffer |
| 92 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0 ( |
| 93 | .din ({mac0_rep_in[4:0]}), |
| 94 | .dout ({mac0_rep_out[4:0]}) |
| 95 | ); |
| 96 | |
| 97 | // mac1 input go through 1 buffer |
| 98 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1 ( |
| 99 | .din ({mac1_rep_in[4:0]}), |
| 100 | .dout ({mac1_rep_out[4:0]}) |
| 101 | ); |
| 102 | |
| 103 | |
| 104 | // mac2 input go through 2 buffers |
| 105 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0 ( |
| 106 | .din ({mac2_rep_in[4:0]}), |
| 107 | .dout ({mac2_rep_0[4:0]}) |
| 108 | ); |
| 109 | |
| 110 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1 ( |
| 111 | .din ({mac2_rep_0[4:0]}), |
| 112 | .dout ({mac2_rep_out[4:0]}) |
| 113 | ); |
| 114 | |
| 115 | // mac3 input go through 2 buffers |
| 116 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0 ( |
| 117 | .din ({mac3_rep_in[4:0]}), |
| 118 | .dout ({mac3_rep_0[4:0]}) |
| 119 | ); |
| 120 | |
| 121 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1 ( |
| 122 | .din ({mac3_rep_0[4:0]}), |
| 123 | .dout ({mac3_rep_out[4:0]}) |
| 124 | ); |
| 125 | |
| 126 | // mac4 input go through 2 buffers |
| 127 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0 ( |
| 128 | .din ({mac4_rep_in[4:0]}), |
| 129 | .dout ({mac4_rep_0[4:0]}) |
| 130 | ); |
| 131 | |
| 132 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1 ( |
| 133 | .din ({mac4_rep_0[4:0]}), |
| 134 | .dout ({mac4_rep_out[4:0]}) |
| 135 | ); |
| 136 | |
| 137 | // mac5 input go through 1 buffer |
| 138 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5 ( |
| 139 | .din ({mac5_rep_in[4:0]}), |
| 140 | .dout ({mac5_rep_out[4:0]}) |
| 141 | ); |
| 142 | |
| 143 | // mac6 input go through 1 buffer |
| 144 | cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6 ( |
| 145 | .din ({mac6_rep_in[4:0]}), |
| 146 | .dout ({mac6_rep_out[4:0]}) |
| 147 | ); |
| 148 | |
| 149 | |
| 150 | // repeat the scan chain |
| 151 | |
| 152 | // buffer on top of mac7 |
| 153 | cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan7 ( |
| 154 | .din (scan_rep_in), |
| 155 | .dout (scan_rep7_out) |
| 156 | ); |
| 157 | |
| 158 | // buffer on top of mac5 |
| 159 | cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan5 ( |
| 160 | .din (scan_rep7_out), |
| 161 | .dout (scan_rep5_out) |
| 162 | ); |
| 163 | |
| 164 | // buffer on top of mac3 |
| 165 | cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan3 ( |
| 166 | .din (scan_rep5_out), |
| 167 | .dout (scan_rep3_out) |
| 168 | ); |
| 169 | |
| 170 | // buffer on top of mac1 |
| 171 | cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan1 ( |
| 172 | .din (scan_rep3_out), |
| 173 | .dout (scan_rep1_out) |
| 174 | ); |
| 175 | |
| 176 | // buffer on top of mac8 |
| 177 | cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan8 ( |
| 178 | .din (scan_rep1_out), |
| 179 | .dout (scan_rep_out) |
| 180 | ); |
| 181 | |
| 182 | endmodule |
| 183 | |
| 184 | |
| 185 | // |
| 186 | // buff macro |
| 187 | // |
| 188 | // |
| 189 | |
| 190 | |
| 191 | |
| 192 | |
| 193 | |
| 194 | module cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 ( |
| 195 | din, |
| 196 | dout); |
| 197 | input [4:0] din; |
| 198 | output [4:0] dout; |
| 199 | |
| 200 | |
| 201 | |
| 202 | |
| 203 | |
| 204 | |
| 205 | buff #(5) d0_0 ( |
| 206 | .in(din[4:0]), |
| 207 | .out(dout[4:0]) |
| 208 | ); |
| 209 | |
| 210 | |
| 211 | |
| 212 | |
| 213 | |
| 214 | |
| 215 | |
| 216 | |
| 217 | endmodule |
| 218 | |
| 219 | |
| 220 | |
| 221 | |
| 222 | |
| 223 | // |
| 224 | // buff macro |
| 225 | // |
| 226 | // |
| 227 | |
| 228 | |
| 229 | |
| 230 | |
| 231 | |
| 232 | module cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 ( |
| 233 | din, |
| 234 | dout); |
| 235 | input [0:0] din; |
| 236 | output [0:0] dout; |
| 237 | |
| 238 | |
| 239 | |
| 240 | |
| 241 | |
| 242 | |
| 243 | buff #(1) d0_0 ( |
| 244 | .in(din[0:0]), |
| 245 | .out(dout[0:0]) |
| 246 | ); |
| 247 | |
| 248 | |
| 249 | |
| 250 | |
| 251 | |
| 252 | |
| 253 | |
| 254 | |
| 255 | endmodule |
| 256 | |
| 257 | |
| 258 | |
| 259 | `endif // `ifndef FPGA |
| 260 | |
| 261 | `ifdef FPGA |
| 262 | `timescale 1 ns / 100 ps |
| 263 | module cpx_rep_dp(mac0_rep_out, mac1_rep_out, mac2_rep_out, mac3_rep_out, |
| 264 | mac4_rep_out, mac5_rep_out, mac6_rep_out, scan_rep_out, mac0_rep_in, |
| 265 | mac1_rep_in, mac2_rep_in, mac3_rep_in, mac4_rep_in, mac5_rep_in, |
| 266 | mac6_rep_in, scan_rep_in); |
| 267 | |
| 268 | output [4:0] mac0_rep_out; |
| 269 | output [4:0] mac1_rep_out; |
| 270 | output [4:0] mac2_rep_out; |
| 271 | output [4:0] mac3_rep_out; |
| 272 | output [4:0] mac4_rep_out; |
| 273 | output [4:0] mac5_rep_out; |
| 274 | output [4:0] mac6_rep_out; |
| 275 | output scan_rep_out; |
| 276 | input [4:0] mac0_rep_in; |
| 277 | input [4:0] mac1_rep_in; |
| 278 | input [4:0] mac2_rep_in; |
| 279 | input [4:0] mac3_rep_in; |
| 280 | input [4:0] mac4_rep_in; |
| 281 | input [4:0] mac5_rep_in; |
| 282 | input [4:0] mac6_rep_in; |
| 283 | input scan_rep_in; |
| 284 | |
| 285 | wire [4:0] mac2_rep_0; |
| 286 | wire [4:0] mac3_rep_0; |
| 287 | wire [4:0] mac4_rep_0; |
| 288 | wire scan_rep7_out; |
| 289 | wire scan_rep5_out; |
| 290 | wire scan_rep3_out; |
| 291 | wire scan_rep1_out; |
| 292 | |
| 293 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0( |
| 294 | .din ({mac0_rep_in[4:0]}), |
| 295 | .dout ({mac0_rep_out[4:0]})); |
| 296 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1( |
| 297 | .din ({mac1_rep_in[4:0]}), |
| 298 | .dout ({mac1_rep_out[4:0]})); |
| 299 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0( |
| 300 | .din ({mac2_rep_in[4:0]}), |
| 301 | .dout ({mac2_rep_0[4:0]})); |
| 302 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1( |
| 303 | .din ({mac2_rep_0[4:0]}), |
| 304 | .dout ({mac2_rep_out[4:0]})); |
| 305 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0( |
| 306 | .din ({mac3_rep_in[4:0]}), |
| 307 | .dout ({mac3_rep_0[4:0]})); |
| 308 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1( |
| 309 | .din ({mac3_rep_0[4:0]}), |
| 310 | .dout ({mac3_rep_out[4:0]})); |
| 311 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0( |
| 312 | .din ({mac4_rep_in[4:0]}), |
| 313 | .dout ({mac4_rep_0[4:0]})); |
| 314 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1( |
| 315 | .din ({mac4_rep_0[4:0]}), |
| 316 | .dout ({mac4_rep_out[4:0]})); |
| 317 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5( |
| 318 | .din ({mac5_rep_in[4:0]}), |
| 319 | .dout ({mac5_rep_out[4:0]})); |
| 320 | buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6( |
| 321 | .din ({mac6_rep_in[4:0]}), |
| 322 | .dout ({mac6_rep_out[4:0]})); |
| 323 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan7( |
| 324 | .din (scan_rep_in), |
| 325 | .dout (scan_rep7_out)); |
| 326 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan5( |
| 327 | .din (scan_rep7_out), |
| 328 | .dout (scan_rep5_out)); |
| 329 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan3( |
| 330 | .din (scan_rep5_out), |
| 331 | .dout (scan_rep3_out)); |
| 332 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan1( |
| 333 | .din (scan_rep3_out), |
| 334 | .dout (scan_rep1_out)); |
| 335 | buff_macro__dbuff_32x__stack_none__width_1 buf_scan8( |
| 336 | .din (scan_rep1_out), |
| 337 | .dout (scan_rep_out)); |
| 338 | endmodule |
| 339 | |
| 340 | module buff_macro__dbuff_32x__stack_6l__width_5(din, dout); |
| 341 | |
| 342 | input [4:0] din; |
| 343 | output [4:0] dout; |
| 344 | |
| 345 | buff #(5) d0_0( |
| 346 | .in (din[4:0]), |
| 347 | .out (dout[4:0])); |
| 348 | endmodule |
| 349 | |
| 350 | |
| 351 | |
| 352 | `endif // `ifdef FPGA |
| 353 | |