| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: db0.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module db0 ( |
| 36 | tcu_pce_ov, |
| 37 | tcu_clk_stop, |
| 38 | tcu_aclk, |
| 39 | tcu_bclk, |
| 40 | tcu_scan_en, |
| 41 | tcu_atpg_mode, |
| 42 | cluster_arst_l, |
| 43 | ccu_io_out, |
| 44 | tcu_div_bypass, |
| 45 | scan_in, |
| 46 | scan_out, |
| 47 | dmu_ncu_wrack_vld, |
| 48 | dmu_ncu_wrack_tag, |
| 49 | dmu_ncu_data, |
| 50 | dmu_ncu_vld, |
| 51 | dmu_ncu_stall, |
| 52 | dmu_sii_hdr_vld, |
| 53 | dmu_sii_reqbypass, |
| 54 | dmu_sii_datareq, |
| 55 | dmu_sii_datareq16, |
| 56 | dmu_sii_data, |
| 57 | dmu_sii_be, |
| 58 | dmu_dbg0_debug_bus_a, |
| 59 | dmu_dbg0_debug_bus_b, |
| 60 | niu_ncu_vld, |
| 61 | niu_ncu_data, |
| 62 | niu_ncu_stall, |
| 63 | niu_sii_hdr_vld, |
| 64 | niu_sii_reqbypass, |
| 65 | niu_sii_datareq, |
| 66 | niu_sii_data, |
| 67 | niu_sio_dq, |
| 68 | l2t0_dbg0_sii_iq_dequeue, |
| 69 | l2t2_dbg0_sii_iq_dequeue, |
| 70 | l2t0_dbg0_sii_wib_dequeue, |
| 71 | l2t2_dbg0_sii_wib_dequeue, |
| 72 | l2t0_dbg0_err_event, |
| 73 | l2t2_dbg0_err_event, |
| 74 | l2t0_dbg0_pa_match, |
| 75 | l2t2_dbg0_pa_match, |
| 76 | l2t0_dbg0_xbar_vcid, |
| 77 | l2t2_dbg0_xbar_vcid, |
| 78 | l2b0_dbg0_sio_ctag_vld, |
| 79 | l2b1_dbg0_sio_ctag_vld, |
| 80 | l2b2_dbg0_sio_ctag_vld, |
| 81 | l2b3_dbg0_sio_ctag_vld, |
| 82 | l2b0_dbg0_sio_ack_type, |
| 83 | l2b1_dbg0_sio_ack_type, |
| 84 | l2b2_dbg0_sio_ack_type, |
| 85 | l2b3_dbg0_sio_ack_type, |
| 86 | l2b0_dbg0_sio_ack_dest, |
| 87 | l2b1_dbg0_sio_ack_dest, |
| 88 | l2b2_dbg0_sio_ack_dest, |
| 89 | l2b3_dbg0_sio_ack_dest, |
| 90 | spc0_dbg0_instr_cmt_grp0, |
| 91 | spc0_dbg0_instr_cmt_grp1, |
| 92 | spc2_dbg0_instr_cmt_grp0, |
| 93 | spc2_dbg0_instr_cmt_grp1, |
| 94 | gclk, |
| 95 | io_cmp_sync_en, |
| 96 | cmp_io2x_sync_en, |
| 97 | dbg0_dbg1_debug_data, |
| 98 | dbg0_dbg1_l2t0_sii_iq_dequeue, |
| 99 | dbg0_dbg1_l2t2_sii_iq_dequeue, |
| 100 | dbg0_dbg1_l2t0_sii_wib_dequeue, |
| 101 | dbg0_dbg1_l2t2_sii_wib_dequeue, |
| 102 | dbg0_dbg1_l2t0_err_event, |
| 103 | dbg0_dbg1_l2t2_err_event, |
| 104 | dbg0_dbg1_l2t0_pa_match, |
| 105 | dbg0_dbg1_l2t2_pa_match, |
| 106 | dbg0_dbg1_l2t0_xbar_vcid, |
| 107 | dbg0_dbg1_l2t2_xbar_vcid, |
| 108 | dbg0_dbg1_l2b0_sio_ctag_vld, |
| 109 | dbg0_dbg1_l2b1_sio_ctag_vld, |
| 110 | dbg0_dbg1_l2b2_sio_ctag_vld, |
| 111 | dbg0_dbg1_l2b3_sio_ctag_vld, |
| 112 | dbg0_dbg1_l2b0_sio_ack_type, |
| 113 | dbg0_dbg1_l2b1_sio_ack_type, |
| 114 | dbg0_dbg1_l2b2_sio_ack_type, |
| 115 | dbg0_dbg1_l2b3_sio_ack_type, |
| 116 | dbg0_dbg1_l2b0_sio_ack_dest, |
| 117 | dbg0_dbg1_l2b1_sio_ack_dest, |
| 118 | dbg0_dbg1_l2b2_sio_ack_dest, |
| 119 | dbg0_dbg1_l2b3_sio_ack_dest, |
| 120 | dbg0_dbg1_spc0_instr_cmt_grp0, |
| 121 | dbg0_dbg1_spc0_instr_cmt_grp1, |
| 122 | dbg0_dbg1_spc2_instr_cmt_grp0, |
| 123 | dbg0_dbg1_spc2_instr_cmt_grp1, |
| 124 | dbg0_mio_debug_bus_a, |
| 125 | dbg0_mio_debug_bus_b); |
| 126 | wire l2clk; |
| 127 | wire db0_clk_header_cmp_clk_scan_out; |
| 128 | wire aclk; |
| 129 | wire bclk; |
| 130 | wire ce_ovrd; |
| 131 | wire cmp_io2x_sync_en_out; |
| 132 | wire io_cmp_sync_en_out; |
| 133 | wire db0_clk_header_cmp_clk_scan_in; |
| 134 | wire iol2clk; |
| 135 | wire db0_clk_header_iol2clk_scan_out; |
| 136 | wire db0_clk_header_iol2clk_scan_in; |
| 137 | wire rtc_scanin; |
| 138 | wire rtc_scanout; |
| 139 | wire red_dp_scanin; |
| 140 | wire red_dp_scanout; |
| 141 | wire red_ctl_scanin; |
| 142 | wire red_ctl_scanout; |
| 143 | wire [331:0] red_rtc_rep_bus; |
| 144 | wire wr_en0; |
| 145 | wire wr_en1; |
| 146 | wire wr_en2; |
| 147 | wire wr_en3; |
| 148 | wire mux1_sel0; |
| 149 | wire mux1_sel1; |
| 150 | wire mux1_sel2; |
| 151 | wire mux2_sel0; |
| 152 | wire mux2_sel1; |
| 153 | wire mux2_sel2; |
| 154 | wire mux3_sel0; |
| 155 | wire mux3_sel1; |
| 156 | wire mux3_sel2; |
| 157 | wire mux4_sel0; |
| 158 | wire mux4_sel1; |
| 159 | wire mux4_sel2; |
| 160 | wire mux5_sel0; |
| 161 | wire mux5_sel1; |
| 162 | wire mux5_sel2; |
| 163 | wire mux5_sel3; |
| 164 | |
| 165 | |
| 166 | input tcu_pce_ov; |
| 167 | input tcu_clk_stop; |
| 168 | input tcu_aclk; |
| 169 | input tcu_bclk; |
| 170 | input tcu_scan_en; |
| 171 | input tcu_atpg_mode; |
| 172 | |
| 173 | // new signals after clock header insertion |
| 174 | |
| 175 | input cluster_arst_l; |
| 176 | input ccu_io_out; |
| 177 | input tcu_div_bypass; |
| 178 | |
| 179 | input scan_in; |
| 180 | output scan_out; |
| 181 | |
| 182 | |
| 183 | // interface with DMU |
| 184 | |
| 185 | input dmu_ncu_wrack_vld; //CSR Wr Ack from DMU to NCU |
| 186 | input [3:0] dmu_ncu_wrack_tag; //CSR Wr Tag [3:0] from DMU to NCU |
| 187 | input [31:0] dmu_ncu_data; //CSR read data from DMU to NCU |
| 188 | input dmu_ncu_vld; //CSR Data return valid from DMU to NCU |
| 189 | input dmu_ncu_stall; //Stall asserted by DMU to NCU |
| 190 | input dmu_sii_hdr_vld; //DMU requesting to send DMA/Pio Read return/Interrupt packet to SII |
| 191 | input dmu_sii_reqbypass; //DMU requesting to send packet to bypass queue of SII |
| 192 | input dmu_sii_datareq; //DMU requesting to send packet w/data to SII |
| 193 | input dmu_sii_datareq16; //DMU requesting to send packet w/16B only |
| 194 | input [127:0] dmu_sii_data; //Packet from DMU to SII |
| 195 | input [15:0] dmu_sii_be; //Packet byte enables from DMU to SII |
| 196 | input [7:0] dmu_dbg0_debug_bus_a; //Debug Bus A from DMU |
| 197 | input [7:0] dmu_dbg0_debug_bus_b; //Debug Bus B from DMU |
| 198 | |
| 199 | //interface with NIU |
| 200 | |
| 201 | input niu_ncu_vld; //CSR Data return/Interrupt valid from NIU to NCU |
| 202 | input [31:0] niu_ncu_data; //CSR data/ Interrupt packet from NIU to NCU |
| 203 | input niu_ncu_stall; //Stall asserted by NIU to NCU |
| 204 | input niu_sii_hdr_vld; //NIU requesting to send packet to SII |
| 205 | input niu_sii_reqbypass; //NIU requesting to send packet to bypass queue of SII |
| 206 | input niu_sii_datareq; //NIU requesting to send packet w/data to SII |
| 207 | input [127:0] niu_sii_data; //Packet from NIU to SII |
| 208 | input niu_sio_dq; //flow control or credit return signal from NIU to SIO |
| 209 | |
| 210 | // interface with L2T 0,2 |
| 211 | |
| 212 | input l2t0_dbg0_sii_iq_dequeue; //L2t 0 dequeue from IQ |
| 213 | input l2t2_dbg0_sii_iq_dequeue; //L2t 2 dequeue from IQ |
| 214 | input l2t0_dbg0_sii_wib_dequeue; //L2t 0 dequeue from IOWB |
| 215 | input l2t2_dbg0_sii_wib_dequeue; //L2t 2 dequeue from IOWB |
| 216 | input l2t0_dbg0_err_event; //An Error event occurred in l2t 0 |
| 217 | input l2t2_dbg0_err_event; //An Error event occurred in l2t 2 |
| 218 | input l2t0_dbg0_pa_match; //A PA match detected in l2t 0 |
| 219 | input l2t2_dbg0_pa_match; //A PA match detected in l2t 2 |
| 220 | input [5:0] l2t0_dbg0_xbar_vcid; //VCID[5:0] from Xbar to L2t 0 |
| 221 | input [5:0] l2t2_dbg0_xbar_vcid; //VCID[5:0] from Xbar to L2t 2 |
| 222 | |
| 223 | // interface with L2b 0,1,2,3 |
| 224 | |
| 225 | input l2b0_dbg0_sio_ctag_vld; //Ctag valid from L2b 0 to SIO |
| 226 | input l2b1_dbg0_sio_ctag_vld; //Ctag valid from L2b 1 to SIO |
| 227 | input l2b2_dbg0_sio_ctag_vld; //Ctag valid from L2b 2 to SIO |
| 228 | input l2b3_dbg0_sio_ctag_vld; //Ctag valid from L2b 3 to SIO |
| 229 | |
| 230 | input l2b0_dbg0_sio_ack_type; //Read or Wr ack from L2b 0 to SIO |
| 231 | input l2b1_dbg0_sio_ack_type; //Read or Wr ack from L2b 1 to SIO |
| 232 | input l2b2_dbg0_sio_ack_type; //Read or Wr ack from L2b 2 to SIO |
| 233 | input l2b3_dbg0_sio_ack_type; //Read or Wr ack from L2b 3 to SIO |
| 234 | |
| 235 | input l2b0_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 0 to SIO |
| 236 | input l2b1_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 1 to SIO |
| 237 | input l2b2_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 2 to SIO |
| 238 | input l2b3_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 3 to SIO |
| 239 | |
| 240 | // interface with Sparcs 0,2 |
| 241 | |
| 242 | input [1:0] spc0_dbg0_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 0 |
| 243 | input [1:0] spc0_dbg0_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 0 |
| 244 | input [1:0] spc2_dbg0_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 2 |
| 245 | input [1:0] spc2_dbg0_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 2 |
| 246 | |
| 247 | // interface with CCU |
| 248 | |
| 249 | input gclk; //Internal CMP clock from CCU |
| 250 | input io_cmp_sync_en; // IO to CMP sync enable |
| 251 | input cmp_io2x_sync_en; // CMP to IO2X sync enable |
| 252 | |
| 253 | // interface with DBG1 |
| 254 | |
| 255 | output [165:0] dbg0_dbg1_debug_data; // 166 bit debug data bus carrying repeatability signals to DBG1 |
| 256 | output dbg0_dbg1_l2t0_sii_iq_dequeue; //L2t 0 dequeue from IQ : flopped version |
| 257 | output dbg0_dbg1_l2t2_sii_iq_dequeue; //L2t 2 dequeue from IQ : flopped version |
| 258 | output dbg0_dbg1_l2t0_sii_wib_dequeue; //L2t 0 dequeue from IOWB : flopped version |
| 259 | output dbg0_dbg1_l2t2_sii_wib_dequeue; //L2t 2 dequeue from IOWB : flopped version |
| 260 | output dbg0_dbg1_l2t0_err_event; //An Error event occurred in l2t 0 : flopped version |
| 261 | output dbg0_dbg1_l2t2_err_event; //An Error event occurred in l2t 2 : flopped version |
| 262 | output dbg0_dbg1_l2t0_pa_match; //A PA match detected in l2t 0 : flopped version |
| 263 | output dbg0_dbg1_l2t2_pa_match; //A PA match detected in l2t 2 : flopped version |
| 264 | output [5:0] dbg0_dbg1_l2t0_xbar_vcid; //VCID[5:0] from Xbar to L2t 0 : flopped version |
| 265 | output [5:0] dbg0_dbg1_l2t2_xbar_vcid; //VCID[5:0] from Xbar to L2t 2 : flopped version |
| 266 | output dbg0_dbg1_l2b0_sio_ctag_vld; //Ctag valid from L2b 0 to SIO : flopped version |
| 267 | output dbg0_dbg1_l2b1_sio_ctag_vld; //Ctag valid from L2b 1 to SIO : flopped version |
| 268 | output dbg0_dbg1_l2b2_sio_ctag_vld; //Ctag valid from L2b 2 to SIO : flopped version |
| 269 | output dbg0_dbg1_l2b3_sio_ctag_vld; //Ctag valid from L2b 3 to SIO : flopped version |
| 270 | output dbg0_dbg1_l2b0_sio_ack_type; //Read or Wr ack from L2b 0 to SIO : flopped version |
| 271 | output dbg0_dbg1_l2b1_sio_ack_type; //Read or Wr ack from L2b 1 to SIO : flopped version |
| 272 | output dbg0_dbg1_l2b2_sio_ack_type; //Read or Wr ack from L2b 2 to SIO : flopped version |
| 273 | output dbg0_dbg1_l2b3_sio_ack_type; //Read or Wr ack from L2b 3 to SIO : flopped version |
| 274 | output dbg0_dbg1_l2b0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 0 to SIO : flopped version |
| 275 | output dbg0_dbg1_l2b1_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 1 to SIO : flopped version |
| 276 | output dbg0_dbg1_l2b2_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 2 to SIO : flopped version |
| 277 | output dbg0_dbg1_l2b3_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 3 to SIO : flopped version |
| 278 | |
| 279 | output [1:0] dbg0_dbg1_spc0_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 0 |
| 280 | output [1:0] dbg0_dbg1_spc0_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 0 |
| 281 | output [1:0] dbg0_dbg1_spc2_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 2 |
| 282 | output [1:0] dbg0_dbg1_spc2_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 2 |
| 283 | |
| 284 | |
| 285 | // interface with MIO |
| 286 | |
| 287 | output [7:0] dbg0_mio_debug_bus_a; //Flopped version of Debug Bus A from DMU |
| 288 | output [7:0] dbg0_mio_debug_bus_b; //Flopped version of Debug Bus A from DMU |
| 289 | |
| 290 | clkgen_db0_cmp db0_clk_header_cmp_clk |
| 291 | ( |
| 292 | .l2clk (l2clk ), |
| 293 | .scan_out (db0_clk_header_cmp_clk_scan_out), |
| 294 | .aclk (aclk ), |
| 295 | .bclk (bclk ), |
| 296 | .pce_ov (ce_ovrd ), |
| 297 | .wmr_protect ( ), |
| 298 | .wmr_ ( ), |
| 299 | .por_ ( ), |
| 300 | .aclk_wmr ( ), |
| 301 | .dr_sync_en ( ), |
| 302 | .io2x_sync_en (cmp_io2x_sync_en_out ), |
| 303 | .slow_cmp_sync_en (io_cmp_sync_en_out ), |
| 304 | .cmp_slow_sync_en ( ), |
| 305 | .tcu_clk_stop (tcu_clk_stop ), |
| 306 | .tcu_pce_ov (tcu_pce_ov ), |
| 307 | .rst_wmr_protect (1'b0 ), |
| 308 | .rst_wmr_ (1'b0 ), |
| 309 | .rst_por_ (1'b0 ), |
| 310 | .ccu_dr_sync_en (1'b0 ), |
| 311 | .ccu_io2x_sync_en (cmp_io2x_sync_en ), |
| 312 | .ccu_cmp_slow_sync_en (1'b0 ), |
| 313 | .ccu_slow_cmp_sync_en (io_cmp_sync_en ), |
| 314 | .tcu_div_bypass (1'b0 ), |
| 315 | .ccu_div_ph (1'b1 ), |
| 316 | .cluster_div_en (1'b0 ), |
| 317 | .gclk (gclk ), |
| 318 | .scan_en (tcu_scan_en ), |
| 319 | .clk_ext (1'b0 ), |
| 320 | .ccu_serdes_dtm (1'b0 ), |
| 321 | .cluster_arst_l (cluster_arst_l ), |
| 322 | .tcu_wr_inhibit (1'b0 ), |
| 323 | .tcu_atpg_mode (tcu_atpg_mode ), |
| 324 | .array_wr_inhibit ( ), |
| 325 | .tcu_aclk (tcu_aclk ), |
| 326 | .tcu_bclk (tcu_bclk ), |
| 327 | .scan_in (db0_clk_header_cmp_clk_scan_in) |
| 328 | ); |
| 329 | |
| 330 | |
| 331 | clkgen_db0_io db0_clk_header_iol2clk |
| 332 | ( |
| 333 | .l2clk (iol2clk ), |
| 334 | .scan_out (db0_clk_header_iol2clk_scan_out), |
| 335 | .aclk ( ), |
| 336 | .bclk ( ), |
| 337 | .pce_ov ( ), |
| 338 | .wmr_protect ( ), |
| 339 | .wmr_ ( ), |
| 340 | .por_ ( ), |
| 341 | .aclk_wmr ( ), |
| 342 | .slow_cmp_sync_en ( ), |
| 343 | .cmp_slow_sync_en ( ), |
| 344 | .tcu_clk_stop (tcu_clk_stop ), |
| 345 | .tcu_pce_ov (tcu_pce_ov ), |
| 346 | .rst_wmr_protect (1'b0 ), |
| 347 | .rst_wmr_ (1'b0 ), |
| 348 | .rst_por_ (1'b0 ), |
| 349 | .ccu_cmp_slow_sync_en (1'b0 ), |
| 350 | .ccu_slow_cmp_sync_en (1'b0 ), |
| 351 | .tcu_div_bypass (tcu_div_bypass ), |
| 352 | .ccu_div_ph (ccu_io_out ), |
| 353 | .cluster_div_en (1'b1 ), |
| 354 | .gclk (gclk ), |
| 355 | .clk_ext (1'b0 ), |
| 356 | .ccu_serdes_dtm (1'b0 ), |
| 357 | .cluster_arst_l (cluster_arst_l ), |
| 358 | .tcu_wr_inhibit (1'b0 ), |
| 359 | .tcu_atpg_mode (tcu_atpg_mode ), |
| 360 | .array_wr_inhibit ( ), |
| 361 | .tcu_aclk (tcu_aclk ), |
| 362 | .tcu_bclk (tcu_bclk ), |
| 363 | .scan_en (tcu_scan_en ), |
| 364 | .scan_in (db0_clk_header_iol2clk_scan_in) |
| 365 | ); |
| 366 | |
| 367 | db0_rtc_dp rtc ( |
| 368 | .scan_in(rtc_scanin), |
| 369 | .scan_out(rtc_scanout), |
| 370 | .tcu_pce_ov(ce_ovrd), |
| 371 | .tcu_clk_stop(1'b0), |
| 372 | .tcu_aclk(aclk), |
| 373 | .tcu_bclk(bclk), |
| 374 | .l2clk(l2clk), |
| 375 | .cmp_io2x_sync_en(cmp_io2x_sync_en_out), |
| 376 | .io_cmp_sync_en(io_cmp_sync_en_out), |
| 377 | .red_rtc_rep_bus(red_rtc_rep_bus[331:0]), |
| 378 | .tcu_scan_en(tcu_scan_en), |
| 379 | .l2t0_dbg0_sii_iq_dequeue(l2t0_dbg0_sii_iq_dequeue), |
| 380 | .l2t2_dbg0_sii_iq_dequeue(l2t2_dbg0_sii_iq_dequeue), |
| 381 | .l2t0_dbg0_sii_wib_dequeue(l2t0_dbg0_sii_wib_dequeue), |
| 382 | .l2t2_dbg0_sii_wib_dequeue(l2t2_dbg0_sii_wib_dequeue), |
| 383 | .l2t0_dbg0_err_event(l2t0_dbg0_err_event), |
| 384 | .l2t2_dbg0_err_event(l2t2_dbg0_err_event), |
| 385 | .l2t0_dbg0_pa_match(l2t0_dbg0_pa_match), |
| 386 | .l2t2_dbg0_pa_match(l2t2_dbg0_pa_match), |
| 387 | .l2t0_dbg0_xbar_vcid(l2t0_dbg0_xbar_vcid[5:0]), |
| 388 | .l2t2_dbg0_xbar_vcid(l2t2_dbg0_xbar_vcid[5:0]), |
| 389 | .l2b0_dbg0_sio_ctag_vld(l2b0_dbg0_sio_ctag_vld), |
| 390 | .l2b1_dbg0_sio_ctag_vld(l2b1_dbg0_sio_ctag_vld), |
| 391 | .l2b2_dbg0_sio_ctag_vld(l2b2_dbg0_sio_ctag_vld), |
| 392 | .l2b3_dbg0_sio_ctag_vld(l2b3_dbg0_sio_ctag_vld), |
| 393 | .l2b0_dbg0_sio_ack_type(l2b0_dbg0_sio_ack_type), |
| 394 | .l2b1_dbg0_sio_ack_type(l2b1_dbg0_sio_ack_type), |
| 395 | .l2b2_dbg0_sio_ack_type(l2b2_dbg0_sio_ack_type), |
| 396 | .l2b3_dbg0_sio_ack_type(l2b3_dbg0_sio_ack_type), |
| 397 | .l2b0_dbg0_sio_ack_dest(l2b0_dbg0_sio_ack_dest), |
| 398 | .l2b1_dbg0_sio_ack_dest(l2b1_dbg0_sio_ack_dest), |
| 399 | .l2b2_dbg0_sio_ack_dest(l2b2_dbg0_sio_ack_dest), |
| 400 | .l2b3_dbg0_sio_ack_dest(l2b3_dbg0_sio_ack_dest), |
| 401 | .spc0_dbg0_instr_cmt_grp0(spc0_dbg0_instr_cmt_grp0[1:0]), |
| 402 | .spc0_dbg0_instr_cmt_grp1(spc0_dbg0_instr_cmt_grp1[1:0]), |
| 403 | .spc2_dbg0_instr_cmt_grp0(spc2_dbg0_instr_cmt_grp0[1:0]), |
| 404 | .spc2_dbg0_instr_cmt_grp1(spc2_dbg0_instr_cmt_grp1[1:0]), |
| 405 | .dbg0_dbg1_debug_data(dbg0_dbg1_debug_data[165:0]), |
| 406 | .dbg0_dbg1_l2t0_sii_iq_dequeue(dbg0_dbg1_l2t0_sii_iq_dequeue), |
| 407 | .dbg0_dbg1_l2t2_sii_iq_dequeue(dbg0_dbg1_l2t2_sii_iq_dequeue), |
| 408 | .dbg0_dbg1_l2t0_sii_wib_dequeue(dbg0_dbg1_l2t0_sii_wib_dequeue), |
| 409 | .dbg0_dbg1_l2t2_sii_wib_dequeue(dbg0_dbg1_l2t2_sii_wib_dequeue), |
| 410 | .dbg0_dbg1_l2t0_err_event(dbg0_dbg1_l2t0_err_event), |
| 411 | .dbg0_dbg1_l2t2_err_event(dbg0_dbg1_l2t2_err_event), |
| 412 | .dbg0_dbg1_l2t0_pa_match(dbg0_dbg1_l2t0_pa_match), |
| 413 | .dbg0_dbg1_l2t2_pa_match(dbg0_dbg1_l2t2_pa_match), |
| 414 | .dbg0_dbg1_l2t0_xbar_vcid(dbg0_dbg1_l2t0_xbar_vcid[5:0]), |
| 415 | .dbg0_dbg1_l2t2_xbar_vcid(dbg0_dbg1_l2t2_xbar_vcid[5:0]), |
| 416 | .dbg0_dbg1_spc0_instr_cmt_grp0(dbg0_dbg1_spc0_instr_cmt_grp0[1:0]), |
| 417 | .dbg0_dbg1_spc0_instr_cmt_grp1(dbg0_dbg1_spc0_instr_cmt_grp1[1:0]), |
| 418 | .dbg0_dbg1_spc2_instr_cmt_grp0(dbg0_dbg1_spc2_instr_cmt_grp0[1:0]), |
| 419 | .dbg0_dbg1_spc2_instr_cmt_grp1(dbg0_dbg1_spc2_instr_cmt_grp1[1:0]), |
| 420 | .dbg0_dbg1_l2b0_sio_ctag_vld(dbg0_dbg1_l2b0_sio_ctag_vld), |
| 421 | .dbg0_dbg1_l2b1_sio_ctag_vld(dbg0_dbg1_l2b1_sio_ctag_vld), |
| 422 | .dbg0_dbg1_l2b2_sio_ctag_vld(dbg0_dbg1_l2b2_sio_ctag_vld), |
| 423 | .dbg0_dbg1_l2b3_sio_ctag_vld(dbg0_dbg1_l2b3_sio_ctag_vld), |
| 424 | .dbg0_dbg1_l2b0_sio_ack_type(dbg0_dbg1_l2b0_sio_ack_type), |
| 425 | .dbg0_dbg1_l2b1_sio_ack_type(dbg0_dbg1_l2b1_sio_ack_type), |
| 426 | .dbg0_dbg1_l2b2_sio_ack_type(dbg0_dbg1_l2b2_sio_ack_type), |
| 427 | .dbg0_dbg1_l2b3_sio_ack_type(dbg0_dbg1_l2b3_sio_ack_type), |
| 428 | .dbg0_dbg1_l2b0_sio_ack_dest(dbg0_dbg1_l2b0_sio_ack_dest), |
| 429 | .dbg0_dbg1_l2b1_sio_ack_dest(dbg0_dbg1_l2b1_sio_ack_dest), |
| 430 | .dbg0_dbg1_l2b2_sio_ack_dest(dbg0_dbg1_l2b2_sio_ack_dest), |
| 431 | .dbg0_dbg1_l2b3_sio_ack_dest(dbg0_dbg1_l2b3_sio_ack_dest) |
| 432 | ); |
| 433 | |
| 434 | db0_red_dp red_dp ( |
| 435 | .scan_in(red_dp_scanin), |
| 436 | .scan_out(red_dp_scanout), |
| 437 | .tcu_pce_ov(ce_ovrd), |
| 438 | .tcu_clk_stop(1'b0), |
| 439 | .tcu_aclk(aclk), |
| 440 | .tcu_bclk(bclk), |
| 441 | .iol2clk(iol2clk), |
| 442 | .tcu_scan_en(tcu_scan_en), |
| 443 | .red_rtc_rep_bus(red_rtc_rep_bus[331:0]), |
| 444 | .wr_en0(wr_en0), |
| 445 | .wr_en1(wr_en1), |
| 446 | .wr_en2(wr_en2), |
| 447 | .wr_en3(wr_en3), |
| 448 | .mux1_sel0(mux1_sel0), |
| 449 | .mux1_sel1(mux1_sel1), |
| 450 | .mux1_sel2(mux1_sel2), |
| 451 | .mux2_sel0(mux2_sel0), |
| 452 | .mux2_sel1(mux2_sel1), |
| 453 | .mux2_sel2(mux2_sel2), |
| 454 | .mux3_sel0(mux3_sel0), |
| 455 | .mux3_sel1(mux3_sel1), |
| 456 | .mux3_sel2(mux3_sel2), |
| 457 | .mux4_sel0(mux4_sel0), |
| 458 | .mux4_sel1(mux4_sel1), |
| 459 | .mux4_sel2(mux4_sel2), |
| 460 | .mux5_sel0(mux5_sel0), |
| 461 | .mux5_sel1(mux5_sel1), |
| 462 | .mux5_sel2(mux5_sel2), |
| 463 | .mux5_sel3(mux5_sel3), |
| 464 | .dmu_ncu_wrack_vld(dmu_ncu_wrack_vld), |
| 465 | .dmu_ncu_wrack_tag(dmu_ncu_wrack_tag[3:0]), |
| 466 | .dmu_ncu_data(dmu_ncu_data[31:0]), |
| 467 | .dmu_ncu_vld(dmu_ncu_vld), |
| 468 | .dmu_ncu_stall(dmu_ncu_stall), |
| 469 | .dmu_sii_hdr_vld(dmu_sii_hdr_vld), |
| 470 | .dmu_sii_reqbypass(dmu_sii_reqbypass), |
| 471 | .dmu_sii_datareq(dmu_sii_datareq), |
| 472 | .dmu_sii_datareq16(dmu_sii_datareq16), |
| 473 | .dmu_sii_data(dmu_sii_data[127:0]), |
| 474 | .dmu_sii_be(dmu_sii_be[15:0]), |
| 475 | .dmu_dbg0_debug_bus_a(dmu_dbg0_debug_bus_a[7:0]), |
| 476 | .dmu_dbg0_debug_bus_b(dmu_dbg0_debug_bus_b[7:0]), |
| 477 | .niu_ncu_vld(niu_ncu_vld), |
| 478 | .niu_ncu_data(niu_ncu_data[31:0]), |
| 479 | .niu_ncu_stall(niu_ncu_stall), |
| 480 | .niu_sii_hdr_vld(niu_sii_hdr_vld), |
| 481 | .niu_sii_reqbypass(niu_sii_reqbypass), |
| 482 | .niu_sii_datareq(niu_sii_datareq), |
| 483 | .niu_sii_data(niu_sii_data[127:0]), |
| 484 | .niu_sio_dq(niu_sio_dq), |
| 485 | .dbg0_mio_debug_bus_a(dbg0_mio_debug_bus_a[7:0]), |
| 486 | .dbg0_mio_debug_bus_b(dbg0_mio_debug_bus_b[7:0]) |
| 487 | ); |
| 488 | |
| 489 | db0_reduct_ctl red_ctl ( |
| 490 | .scan_in(red_ctl_scanin), |
| 491 | .scan_out(red_ctl_scanout), |
| 492 | .tcu_pce_ov(ce_ovrd), |
| 493 | .tcu_clk_stop(1'b0), |
| 494 | .tcu_aclk(aclk), |
| 495 | .tcu_bclk(bclk), |
| 496 | .iol2clk(iol2clk), |
| 497 | .tcu_scan_en(tcu_scan_en), |
| 498 | .dmu_ncu_vld(dmu_ncu_vld), |
| 499 | .wr_en0(wr_en0), |
| 500 | .wr_en1(wr_en1), |
| 501 | .wr_en2(wr_en2), |
| 502 | .wr_en3(wr_en3), |
| 503 | .mux1_sel0(mux1_sel0), |
| 504 | .mux1_sel1(mux1_sel1), |
| 505 | .mux1_sel2(mux1_sel2), |
| 506 | .mux2_sel0(mux2_sel0), |
| 507 | .mux2_sel1(mux2_sel1), |
| 508 | .mux2_sel2(mux2_sel2), |
| 509 | .mux3_sel0(mux3_sel0), |
| 510 | .mux3_sel1(mux3_sel1), |
| 511 | .mux3_sel2(mux3_sel2), |
| 512 | .mux4_sel0(mux4_sel0), |
| 513 | .mux4_sel1(mux4_sel1), |
| 514 | .mux4_sel2(mux4_sel2), |
| 515 | .mux5_sel0(mux5_sel0), |
| 516 | .mux5_sel1(mux5_sel1), |
| 517 | .mux5_sel2(mux5_sel2), |
| 518 | .mux5_sel3(mux5_sel3) |
| 519 | ); |
| 520 | |
| 521 | |
| 522 | // fixscan start: |
| 523 | assign db0_clk_header_cmp_clk_scan_in = scan_in ; |
| 524 | assign db0_clk_header_iol2clk_scan_in = db0_clk_header_cmp_clk_scan_out; |
| 525 | assign rtc_scanin = db0_clk_header_iol2clk_scan_out ; |
| 526 | assign red_dp_scanin = rtc_scanout ; |
| 527 | assign red_ctl_scanin = red_dp_scanout ; |
| 528 | assign scan_out = red_ctl_scanout ; |
| 529 | // fixscan end: |
| 530 | endmodule |
| 531 | |