| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: db0_red_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module db0_red_dp ( |
| 36 | iol2clk, |
| 37 | scan_in, |
| 38 | scan_out, |
| 39 | tcu_pce_ov, |
| 40 | tcu_clk_stop, |
| 41 | tcu_aclk, |
| 42 | tcu_bclk, |
| 43 | tcu_scan_en, |
| 44 | red_rtc_rep_bus, |
| 45 | wr_en0, |
| 46 | wr_en1, |
| 47 | wr_en2, |
| 48 | wr_en3, |
| 49 | mux1_sel0, |
| 50 | mux1_sel1, |
| 51 | mux1_sel2, |
| 52 | mux2_sel0, |
| 53 | mux2_sel1, |
| 54 | mux2_sel2, |
| 55 | mux3_sel0, |
| 56 | mux3_sel1, |
| 57 | mux3_sel2, |
| 58 | mux4_sel0, |
| 59 | mux4_sel1, |
| 60 | mux4_sel2, |
| 61 | mux5_sel0, |
| 62 | mux5_sel1, |
| 63 | mux5_sel2, |
| 64 | mux5_sel3, |
| 65 | dmu_ncu_wrack_vld, |
| 66 | dmu_ncu_wrack_tag, |
| 67 | dmu_ncu_data, |
| 68 | dmu_ncu_vld, |
| 69 | dmu_ncu_stall, |
| 70 | dmu_sii_hdr_vld, |
| 71 | dmu_sii_reqbypass, |
| 72 | dmu_sii_datareq, |
| 73 | dmu_sii_datareq16, |
| 74 | dmu_sii_data, |
| 75 | dmu_sii_be, |
| 76 | dmu_dbg0_debug_bus_a, |
| 77 | dmu_dbg0_debug_bus_b, |
| 78 | niu_ncu_vld, |
| 79 | niu_ncu_data, |
| 80 | niu_ncu_stall, |
| 81 | niu_sii_hdr_vld, |
| 82 | niu_sii_reqbypass, |
| 83 | niu_sii_datareq, |
| 84 | niu_sii_data, |
| 85 | niu_sio_dq, |
| 86 | dbg0_mio_debug_bus_a, |
| 87 | dbg0_mio_debug_bus_b); |
| 88 | wire pce_ov; |
| 89 | wire stop; |
| 90 | wire siclk; |
| 91 | wire soclk; |
| 92 | wire se; |
| 93 | wire [11:0] dmu_ncu_data_fnl; |
| 94 | wire ff_dmu_ncu_data_scanin; |
| 95 | wire ff_dmu_ncu_data_scanout; |
| 96 | wire dmu_ncu_vld_r; |
| 97 | wire [31:0] dmu_ncu_data_r; |
| 98 | wire ff_dmu_ncu_data_r0_scanin; |
| 99 | wire ff_dmu_ncu_data_r0_scanout; |
| 100 | wire ff_dmu_ncu_data_r1_scanin; |
| 101 | wire ff_dmu_ncu_data_r1_scanout; |
| 102 | wire ff_dmu_ncu_data_r2_scanin; |
| 103 | wire ff_dmu_ncu_data_r2_scanout; |
| 104 | wire ff_dmu_ncu_data_r3_scanin; |
| 105 | wire ff_dmu_ncu_data_r3_scanout; |
| 106 | wire ff_rep_bus_slice0_scanin; |
| 107 | wire ff_rep_bus_slice0_scanout; |
| 108 | wire ff_rep_bus_slice1_scanin; |
| 109 | wire ff_rep_bus_slice1_scanout; |
| 110 | wire ff_rep_bus_slice2_scanin; |
| 111 | wire ff_rep_bus_slice2_scanout; |
| 112 | wire ff_rep_bus_slice3_scanin; |
| 113 | wire ff_rep_bus_slice3_scanout; |
| 114 | wire ff_rep_bus_slice4_scanin; |
| 115 | wire ff_rep_bus_slice4_scanout; |
| 116 | wire ff_rep_bus_slice5_scanin; |
| 117 | wire ff_rep_bus_slice5_scanout; |
| 118 | wire ff_rep_bus_slice6_scanin; |
| 119 | wire ff_rep_bus_slice6_scanout; |
| 120 | wire ff_rep_bus_slice7_scanin; |
| 121 | wire ff_rep_bus_slice7_scanout; |
| 122 | wire ff_rep_bus_slice8_scanin; |
| 123 | wire ff_rep_bus_slice8_scanout; |
| 124 | wire ff_rep_bus_slice9_scanin; |
| 125 | wire ff_rep_bus_slice9_scanout; |
| 126 | |
| 127 | |
| 128 | input iol2clk; // Internal IO clock from CCU |
| 129 | |
| 130 | input scan_in; |
| 131 | output scan_out; |
| 132 | input tcu_pce_ov; |
| 133 | input tcu_clk_stop; |
| 134 | input tcu_aclk; |
| 135 | input tcu_bclk; |
| 136 | input tcu_scan_en; |
| 137 | |
| 138 | output [331:0] red_rtc_rep_bus; // repeatability bus |
| 139 | |
| 140 | input wr_en0; |
| 141 | input wr_en1; |
| 142 | input wr_en2; |
| 143 | input wr_en3; |
| 144 | |
| 145 | input mux1_sel0; |
| 146 | input mux1_sel1; |
| 147 | input mux1_sel2; |
| 148 | |
| 149 | input mux2_sel0; |
| 150 | input mux2_sel1; |
| 151 | input mux2_sel2; |
| 152 | |
| 153 | input mux3_sel0; |
| 154 | input mux3_sel1; |
| 155 | input mux3_sel2; |
| 156 | |
| 157 | input mux4_sel0; |
| 158 | input mux4_sel1; |
| 159 | input mux4_sel2; |
| 160 | |
| 161 | input mux5_sel0; |
| 162 | input mux5_sel1; |
| 163 | input mux5_sel2; |
| 164 | input mux5_sel3; |
| 165 | |
| 166 | input dmu_ncu_wrack_vld; //CSR Wr Ack from DMU to NCU |
| 167 | input [3:0] dmu_ncu_wrack_tag; //CSR Wr Tag [3:0] from DMU to NCU |
| 168 | input [31:0] dmu_ncu_data; //CSR read data from DMU to NCU |
| 169 | input dmu_ncu_vld; //CSR Data return valid from DMU to NCU |
| 170 | input dmu_ncu_stall; //Stall asserted by DMU to NCU |
| 171 | input dmu_sii_hdr_vld; //DMU requesting to send DMA/Pio Read return/Interrupt packet to SII |
| 172 | input dmu_sii_reqbypass; //DMU requesting to send packet to bypass queue of SII |
| 173 | input dmu_sii_datareq; //DMU requesting to send packet w/data to SII |
| 174 | input dmu_sii_datareq16; //DMU requesting to send packet w/16B only |
| 175 | input [127:0] dmu_sii_data; //Packet from DMU to SII |
| 176 | input [15:0] dmu_sii_be; //Packet byte enables from DMU to SII |
| 177 | input [7:0] dmu_dbg0_debug_bus_a; //Debug Bus A from DMU |
| 178 | input [7:0] dmu_dbg0_debug_bus_b; //Debug Bus B from DMU |
| 179 | |
| 180 | input niu_ncu_vld; //CSR Data return/Interrupt valid from NIU to NCU |
| 181 | input [31:0] niu_ncu_data; //CSR data/ Interrupt packet from NIU to NCU |
| 182 | input niu_ncu_stall; //Stall asserted by NIU to NCU |
| 183 | input niu_sii_hdr_vld; //NIU requesting to send packet to SII |
| 184 | input niu_sii_reqbypass; //NIU requesting to send packet to bypass queue of SII |
| 185 | input niu_sii_datareq; //NIU requesting to send packet w/data to SII |
| 186 | input [127:0] niu_sii_data; //Packet from NIU to SII |
| 187 | input niu_sio_dq; //flow control or credit return signal from NIU to SIO |
| 188 | |
| 189 | output [7:0] dbg0_mio_debug_bus_a; //Flopped version of Debug Bus A from DMU |
| 190 | output [7:0] dbg0_mio_debug_bus_b; //Flopped version of Debug Bus B from DMU |
| 191 | |
| 192 | // Scan reassigns |
| 193 | assign pce_ov = tcu_pce_ov; |
| 194 | assign stop = tcu_clk_stop; |
| 195 | assign siclk = tcu_aclk; |
| 196 | assign soclk = tcu_bclk; |
| 197 | assign se = tcu_scan_en; |
| 198 | |
| 199 | wire [11:0] dmu_ncu_data_reg0,dmu_ncu_data_reg1,dmu_ncu_data_reg2,dmu_ncu_data_reg3; |
| 200 | wire [35:0] dmu_ncu_data_0,dmu_ncu_data_1,dmu_ncu_data_2,dmu_ncu_data_3; |
| 201 | wire [165:0] dmu_data, niu_data; |
| 202 | |
| 203 | // flop dmu_ncu_data[31:0] and dmu_ncu_vld |
| 204 | |
| 205 | assign niu_data = {niu_ncu_vld,niu_ncu_data[31:0],niu_ncu_stall,niu_sii_hdr_vld, |
| 206 | niu_sii_reqbypass,niu_sii_datareq,niu_sio_dq,niu_sii_data[127:0]}; |
| 207 | |
| 208 | assign dmu_data = {dmu_ncu_data_fnl[11:0],dmu_ncu_wrack_vld,dmu_ncu_wrack_tag[3:0], |
| 209 | dmu_ncu_stall,dmu_sii_hdr_vld,dmu_sii_reqbypass,dmu_sii_datareq, |
| 210 | dmu_sii_datareq16,dmu_sii_be[15:0],dmu_sii_data[127:0] |
| 211 | }; |
| 212 | |
| 213 | |
| 214 | db0_red_dp_msff_macro__stack_34r__width_33 ff_dmu_ncu_data ( |
| 215 | .scan_in(ff_dmu_ncu_data_scanin), |
| 216 | .scan_out(ff_dmu_ncu_data_scanout), |
| 217 | .clk ( iol2clk ), |
| 218 | .en ( 1'b1 ), |
| 219 | .din ({dmu_ncu_vld,dmu_ncu_data[31:0]}), |
| 220 | .dout ({dmu_ncu_vld_r,dmu_ncu_data_r[31:0]}), |
| 221 | .se(se), |
| 222 | .siclk(siclk), |
| 223 | .soclk(soclk), |
| 224 | .pce_ov(pce_ov), |
| 225 | .stop(stop) |
| 226 | ); |
| 227 | |
| 228 | // flop dmu_ncu_vld_r,dmu_ncu_data_r[31:0] into 4 separate flops |
| 229 | // based on write enables coming from dbg0_red_ctl.sv |
| 230 | // these are the 4 data beats from dmu to ncu for csr |
| 231 | // data return |
| 232 | |
| 233 | db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r0 ( |
| 234 | .scan_in(ff_dmu_ncu_data_r0_scanin), |
| 235 | .scan_out(ff_dmu_ncu_data_r0_scanout), |
| 236 | .clk ( iol2clk ), |
| 237 | .en ( wr_en0 ), |
| 238 | .din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22], |
| 239 | dmu_ncu_vld_r,dmu_ncu_data_r[21:11], |
| 240 | dmu_ncu_vld_r,dmu_ncu_data_r[10:0]} |
| 241 | ), |
| 242 | .dout (dmu_ncu_data_0[35:0]), |
| 243 | .se(se), |
| 244 | .siclk(siclk), |
| 245 | .soclk(soclk), |
| 246 | .pce_ov(pce_ov), |
| 247 | .stop(stop) |
| 248 | ); |
| 249 | |
| 250 | db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r1 ( |
| 251 | .scan_in(ff_dmu_ncu_data_r1_scanin), |
| 252 | .scan_out(ff_dmu_ncu_data_r1_scanout), |
| 253 | .clk ( iol2clk ), |
| 254 | .en ( wr_en1 ), |
| 255 | .din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22], |
| 256 | dmu_ncu_vld_r,dmu_ncu_data_r[21:11], |
| 257 | dmu_ncu_vld_r,dmu_ncu_data_r[10:0]} |
| 258 | ), |
| 259 | .dout (dmu_ncu_data_1[35:0]), |
| 260 | .se(se), |
| 261 | .siclk(siclk), |
| 262 | .soclk(soclk), |
| 263 | .pce_ov(pce_ov), |
| 264 | .stop(stop) |
| 265 | ); |
| 266 | db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r2 ( |
| 267 | .scan_in(ff_dmu_ncu_data_r2_scanin), |
| 268 | .scan_out(ff_dmu_ncu_data_r2_scanout), |
| 269 | .clk ( iol2clk ), |
| 270 | .en ( wr_en2 ), |
| 271 | .din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22], |
| 272 | dmu_ncu_vld_r,dmu_ncu_data_r[21:11], |
| 273 | dmu_ncu_vld_r,dmu_ncu_data_r[10:0]} |
| 274 | ), |
| 275 | .dout (dmu_ncu_data_2[35:0]), |
| 276 | .se(se), |
| 277 | .siclk(siclk), |
| 278 | .soclk(soclk), |
| 279 | .pce_ov(pce_ov), |
| 280 | .stop(stop) |
| 281 | ); |
| 282 | db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r3 ( |
| 283 | .scan_in(ff_dmu_ncu_data_r3_scanin), |
| 284 | .scan_out(ff_dmu_ncu_data_r3_scanout), |
| 285 | .clk ( iol2clk ), |
| 286 | .en ( wr_en3 ), |
| 287 | .din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22], |
| 288 | dmu_ncu_vld_r,dmu_ncu_data_r[21:11], |
| 289 | dmu_ncu_vld_r,dmu_ncu_data_r[10:0]} |
| 290 | ), |
| 291 | .dout (dmu_ncu_data_3[35:0]), |
| 292 | .se(se), |
| 293 | .siclk(siclk), |
| 294 | .soclk(soclk), |
| 295 | .pce_ov(pce_ov), |
| 296 | .stop(stop) |
| 297 | ); |
| 298 | |
| 299 | // Mux out the outputs of these 4 flop macros based on |
| 300 | // control signals from dbg0_red_ctl |
| 301 | |
| 302 | db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_1 |
| 303 | ( |
| 304 | .dout (dmu_ncu_data_reg0[11:0]), |
| 305 | .din0 (dmu_ncu_data_0[11:0]), |
| 306 | .din1 (dmu_ncu_data_0[23:12]), |
| 307 | .din2 (dmu_ncu_data_0[35:24]), |
| 308 | .sel0 (mux1_sel0), |
| 309 | .sel1 (mux1_sel1), |
| 310 | .sel2 (mux1_sel2) |
| 311 | ) ; |
| 312 | db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_2 |
| 313 | ( |
| 314 | .dout (dmu_ncu_data_reg1[11:0]), |
| 315 | .din0 (dmu_ncu_data_1[11:0]), |
| 316 | .din1 (dmu_ncu_data_1[23:12]), |
| 317 | .din2 (dmu_ncu_data_1[35:24]), |
| 318 | .sel0 (mux2_sel0), |
| 319 | .sel1 (mux2_sel1), |
| 320 | .sel2 (mux2_sel2) |
| 321 | ) ; |
| 322 | db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_3 |
| 323 | ( |
| 324 | .dout (dmu_ncu_data_reg2[11:0]), |
| 325 | .din0 (dmu_ncu_data_2[11:0]), |
| 326 | .din1 (dmu_ncu_data_2[23:12]), |
| 327 | .din2 (dmu_ncu_data_2[35:24]), |
| 328 | .sel0 (mux3_sel0), |
| 329 | .sel1 (mux3_sel1), |
| 330 | .sel2 (mux3_sel2) |
| 331 | ) ; |
| 332 | db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_4 |
| 333 | ( |
| 334 | .dout (dmu_ncu_data_reg3[11:0]), |
| 335 | .din0 (dmu_ncu_data_3[11:0]), |
| 336 | .din1 (dmu_ncu_data_3[23:12]), |
| 337 | .din2 (dmu_ncu_data_3[35:24]), |
| 338 | .sel0 (mux4_sel0), |
| 339 | .sel1 (mux4_sel1), |
| 340 | .sel2 (mux4_sel2) |
| 341 | ) ; |
| 342 | |
| 343 | db0_red_dp_mux_macro__mux_aonpe__ports_4__stack_12r__width_12 mux_5 |
| 344 | ( |
| 345 | .dout (dmu_ncu_data_fnl[11:0]), |
| 346 | .din0 (dmu_ncu_data_reg0[11:0]), |
| 347 | .din1 (dmu_ncu_data_reg1[11:0]), |
| 348 | .din2 (dmu_ncu_data_reg2[11:0]), |
| 349 | .din3 (dmu_ncu_data_reg3[11:0]), |
| 350 | .sel0 (mux5_sel0), |
| 351 | .sel1 (mux5_sel1), |
| 352 | .sel2 (mux5_sel2), |
| 353 | .sel3 (mux5_sel3) |
| 354 | ); |
| 355 | |
| 356 | // Output flops for rep_bus[331:0] , DMU data on 165:0,NIU on 331:166 |
| 357 | |
| 358 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice0 ( |
| 359 | .scan_in(ff_rep_bus_slice0_scanin), |
| 360 | .scan_out(ff_rep_bus_slice0_scanout), |
| 361 | .clk ( iol2clk ), |
| 362 | .en ( 1'b1 ), |
| 363 | .din (dmu_data[35:0] |
| 364 | ), |
| 365 | .dout (red_rtc_rep_bus[35:0]), |
| 366 | .se(se), |
| 367 | .siclk(siclk), |
| 368 | .soclk(soclk), |
| 369 | .pce_ov(pce_ov), |
| 370 | .stop(stop) |
| 371 | ); |
| 372 | |
| 373 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice1 ( |
| 374 | .scan_in(ff_rep_bus_slice1_scanin), |
| 375 | .scan_out(ff_rep_bus_slice1_scanout), |
| 376 | .clk ( iol2clk ), |
| 377 | .en ( 1'b1 ), |
| 378 | .din (dmu_data[71:36] |
| 379 | ), |
| 380 | .dout (red_rtc_rep_bus[71:36]), |
| 381 | .se(se), |
| 382 | .siclk(siclk), |
| 383 | .soclk(soclk), |
| 384 | .pce_ov(pce_ov), |
| 385 | .stop(stop) |
| 386 | ); |
| 387 | |
| 388 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice2 ( |
| 389 | .scan_in(ff_rep_bus_slice2_scanin), |
| 390 | .scan_out(ff_rep_bus_slice2_scanout), |
| 391 | .clk ( iol2clk ), |
| 392 | .en ( 1'b1 ), |
| 393 | .din (dmu_data[107:72] |
| 394 | ), |
| 395 | .dout (red_rtc_rep_bus[107:72]), |
| 396 | .se(se), |
| 397 | .siclk(siclk), |
| 398 | .soclk(soclk), |
| 399 | .pce_ov(pce_ov), |
| 400 | .stop(stop) |
| 401 | ); |
| 402 | |
| 403 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice3 ( |
| 404 | .scan_in(ff_rep_bus_slice3_scanin), |
| 405 | .scan_out(ff_rep_bus_slice3_scanout), |
| 406 | .clk ( iol2clk ), |
| 407 | .en ( 1'b1 ), |
| 408 | .din (dmu_data[143:108] |
| 409 | ), |
| 410 | .dout (red_rtc_rep_bus[143:108]), |
| 411 | .se(se), |
| 412 | .siclk(siclk), |
| 413 | .soclk(soclk), |
| 414 | .pce_ov(pce_ov), |
| 415 | .stop(stop) |
| 416 | ); |
| 417 | |
| 418 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice4 ( |
| 419 | .scan_in(ff_rep_bus_slice4_scanin), |
| 420 | .scan_out(ff_rep_bus_slice4_scanout), |
| 421 | .clk ( iol2clk ), |
| 422 | .en ( 1'b1 ), |
| 423 | .din ({niu_data[13:0],dmu_data[165:144]} |
| 424 | ), |
| 425 | .dout (red_rtc_rep_bus[179:144]), |
| 426 | .se(se), |
| 427 | .siclk(siclk), |
| 428 | .soclk(soclk), |
| 429 | .pce_ov(pce_ov), |
| 430 | .stop(stop) |
| 431 | ); |
| 432 | |
| 433 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice5 ( |
| 434 | .scan_in(ff_rep_bus_slice5_scanin), |
| 435 | .scan_out(ff_rep_bus_slice5_scanout), |
| 436 | .clk ( iol2clk ), |
| 437 | .en ( 1'b1 ), |
| 438 | .din (niu_data[49:14] |
| 439 | ), |
| 440 | .dout (red_rtc_rep_bus[215:180]), |
| 441 | .se(se), |
| 442 | .siclk(siclk), |
| 443 | .soclk(soclk), |
| 444 | .pce_ov(pce_ov), |
| 445 | .stop(stop) |
| 446 | ); |
| 447 | |
| 448 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice6 ( |
| 449 | .scan_in(ff_rep_bus_slice6_scanin), |
| 450 | .scan_out(ff_rep_bus_slice6_scanout), |
| 451 | .clk ( iol2clk ), |
| 452 | .en ( 1'b1 ), |
| 453 | .din (niu_data[85:50] |
| 454 | ), |
| 455 | .dout (red_rtc_rep_bus[251:216]), |
| 456 | .se(se), |
| 457 | .siclk(siclk), |
| 458 | .soclk(soclk), |
| 459 | .pce_ov(pce_ov), |
| 460 | .stop(stop) |
| 461 | ); |
| 462 | |
| 463 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice7 ( |
| 464 | .scan_in(ff_rep_bus_slice7_scanin), |
| 465 | .scan_out(ff_rep_bus_slice7_scanout), |
| 466 | .clk ( iol2clk ), |
| 467 | .en ( 1'b1 ), |
| 468 | .din (niu_data[121:86] |
| 469 | ), |
| 470 | .dout (red_rtc_rep_bus[287:252]), |
| 471 | .se(se), |
| 472 | .siclk(siclk), |
| 473 | .soclk(soclk), |
| 474 | .pce_ov(pce_ov), |
| 475 | .stop(stop) |
| 476 | ); |
| 477 | |
| 478 | db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice8 ( |
| 479 | .scan_in(ff_rep_bus_slice8_scanin), |
| 480 | .scan_out(ff_rep_bus_slice8_scanout), |
| 481 | .clk ( iol2clk ), |
| 482 | .en ( 1'b1 ), |
| 483 | .din (niu_data[157:122] |
| 484 | ), |
| 485 | .dout (red_rtc_rep_bus[323:288]), |
| 486 | .se(se), |
| 487 | .siclk(siclk), |
| 488 | .soclk(soclk), |
| 489 | .pce_ov(pce_ov), |
| 490 | .stop(stop) |
| 491 | ); |
| 492 | |
| 493 | db0_red_dp_msff_macro__stack_24r__width_24 ff_rep_bus_slice9 ( |
| 494 | .scan_in(ff_rep_bus_slice9_scanin), |
| 495 | .scan_out(ff_rep_bus_slice9_scanout), |
| 496 | .clk ( iol2clk ), |
| 497 | .en ( 1'b1 ), |
| 498 | .din ({dmu_dbg0_debug_bus_b[7:0], |
| 499 | dmu_dbg0_debug_bus_a[7:0], |
| 500 | niu_data[165:158]} |
| 501 | ), |
| 502 | .dout ({dbg0_mio_debug_bus_b[7:0], |
| 503 | dbg0_mio_debug_bus_a[7:0], |
| 504 | red_rtc_rep_bus[331:324]}), |
| 505 | .se(se), |
| 506 | .siclk(siclk), |
| 507 | .soclk(soclk), |
| 508 | .pce_ov(pce_ov), |
| 509 | .stop(stop) |
| 510 | ); |
| 511 | |
| 512 | // fixscan start: |
| 513 | assign ff_dmu_ncu_data_scanin = scan_in ; |
| 514 | assign ff_dmu_ncu_data_r0_scanin = ff_dmu_ncu_data_scanout ; |
| 515 | assign ff_dmu_ncu_data_r1_scanin = ff_dmu_ncu_data_r0_scanout; |
| 516 | assign ff_dmu_ncu_data_r2_scanin = ff_dmu_ncu_data_r1_scanout; |
| 517 | assign ff_dmu_ncu_data_r3_scanin = ff_dmu_ncu_data_r2_scanout; |
| 518 | assign ff_rep_bus_slice0_scanin = ff_dmu_ncu_data_r3_scanout; |
| 519 | assign ff_rep_bus_slice1_scanin = ff_rep_bus_slice0_scanout; |
| 520 | assign ff_rep_bus_slice2_scanin = ff_rep_bus_slice1_scanout; |
| 521 | assign ff_rep_bus_slice3_scanin = ff_rep_bus_slice2_scanout; |
| 522 | assign ff_rep_bus_slice4_scanin = ff_rep_bus_slice3_scanout; |
| 523 | assign ff_rep_bus_slice5_scanin = ff_rep_bus_slice4_scanout; |
| 524 | assign ff_rep_bus_slice6_scanin = ff_rep_bus_slice5_scanout; |
| 525 | assign ff_rep_bus_slice7_scanin = ff_rep_bus_slice6_scanout; |
| 526 | assign ff_rep_bus_slice8_scanin = ff_rep_bus_slice7_scanout; |
| 527 | assign ff_rep_bus_slice9_scanin = ff_rep_bus_slice8_scanout; |
| 528 | assign scan_out = ff_rep_bus_slice9_scanout; |
| 529 | // fixscan end: |
| 530 | endmodule |
| 531 | |
| 532 | |
| 533 | |
| 534 | |
| 535 | |
| 536 | |
| 537 | // any PARAMS parms go into naming of macro |
| 538 | |
| 539 | module db0_red_dp_msff_macro__stack_34r__width_33 ( |
| 540 | din, |
| 541 | clk, |
| 542 | en, |
| 543 | se, |
| 544 | scan_in, |
| 545 | siclk, |
| 546 | soclk, |
| 547 | pce_ov, |
| 548 | stop, |
| 549 | dout, |
| 550 | scan_out); |
| 551 | wire l1clk; |
| 552 | wire siclk_out; |
| 553 | wire soclk_out; |
| 554 | wire [31:0] so; |
| 555 | |
| 556 | input [32:0] din; |
| 557 | |
| 558 | |
| 559 | input clk; |
| 560 | input en; |
| 561 | input se; |
| 562 | input scan_in; |
| 563 | input siclk; |
| 564 | input soclk; |
| 565 | input pce_ov; |
| 566 | input stop; |
| 567 | |
| 568 | |
| 569 | |
| 570 | output [32:0] dout; |
| 571 | |
| 572 | |
| 573 | output scan_out; |
| 574 | |
| 575 | |
| 576 | |
| 577 | |
| 578 | cl_dp1_l1hdr_8x c0_0 ( |
| 579 | .l2clk(clk), |
| 580 | .pce(en), |
| 581 | .aclk(siclk), |
| 582 | .bclk(soclk), |
| 583 | .l1clk(l1clk), |
| 584 | .se(se), |
| 585 | .pce_ov(pce_ov), |
| 586 | .stop(stop), |
| 587 | .siclk_out(siclk_out), |
| 588 | .soclk_out(soclk_out) |
| 589 | ); |
| 590 | dff #(33) d0_0 ( |
| 591 | .l1clk(l1clk), |
| 592 | .siclk(siclk_out), |
| 593 | .soclk(soclk_out), |
| 594 | .d(din[32:0]), |
| 595 | .si({scan_in,so[31:0]}), |
| 596 | .so({so[31:0],scan_out}), |
| 597 | .q(dout[32:0]) |
| 598 | ); |
| 599 | |
| 600 | |
| 601 | |
| 602 | |
| 603 | |
| 604 | |
| 605 | |
| 606 | |
| 607 | |
| 608 | |
| 609 | |
| 610 | |
| 611 | |
| 612 | |
| 613 | |
| 614 | |
| 615 | |
| 616 | |
| 617 | |
| 618 | |
| 619 | endmodule |
| 620 | |
| 621 | |
| 622 | |
| 623 | |
| 624 | |
| 625 | |
| 626 | |
| 627 | |
| 628 | |
| 629 | |
| 630 | |
| 631 | |
| 632 | |
| 633 | // any PARAMS parms go into naming of macro |
| 634 | |
| 635 | module db0_red_dp_msff_macro__stack_36r__width_36 ( |
| 636 | din, |
| 637 | clk, |
| 638 | en, |
| 639 | se, |
| 640 | scan_in, |
| 641 | siclk, |
| 642 | soclk, |
| 643 | pce_ov, |
| 644 | stop, |
| 645 | dout, |
| 646 | scan_out); |
| 647 | wire l1clk; |
| 648 | wire siclk_out; |
| 649 | wire soclk_out; |
| 650 | wire [34:0] so; |
| 651 | |
| 652 | input [35:0] din; |
| 653 | |
| 654 | |
| 655 | input clk; |
| 656 | input en; |
| 657 | input se; |
| 658 | input scan_in; |
| 659 | input siclk; |
| 660 | input soclk; |
| 661 | input pce_ov; |
| 662 | input stop; |
| 663 | |
| 664 | |
| 665 | |
| 666 | output [35:0] dout; |
| 667 | |
| 668 | |
| 669 | output scan_out; |
| 670 | |
| 671 | |
| 672 | |
| 673 | |
| 674 | cl_dp1_l1hdr_8x c0_0 ( |
| 675 | .l2clk(clk), |
| 676 | .pce(en), |
| 677 | .aclk(siclk), |
| 678 | .bclk(soclk), |
| 679 | .l1clk(l1clk), |
| 680 | .se(se), |
| 681 | .pce_ov(pce_ov), |
| 682 | .stop(stop), |
| 683 | .siclk_out(siclk_out), |
| 684 | .soclk_out(soclk_out) |
| 685 | ); |
| 686 | dff #(36) d0_0 ( |
| 687 | .l1clk(l1clk), |
| 688 | .siclk(siclk_out), |
| 689 | .soclk(soclk_out), |
| 690 | .d(din[35:0]), |
| 691 | .si({scan_in,so[34:0]}), |
| 692 | .so({so[34:0],scan_out}), |
| 693 | .q(dout[35:0]) |
| 694 | ); |
| 695 | |
| 696 | |
| 697 | |
| 698 | |
| 699 | |
| 700 | |
| 701 | |
| 702 | |
| 703 | |
| 704 | |
| 705 | |
| 706 | |
| 707 | |
| 708 | |
| 709 | |
| 710 | |
| 711 | |
| 712 | |
| 713 | |
| 714 | |
| 715 | endmodule |
| 716 | |
| 717 | |
| 718 | |
| 719 | |
| 720 | |
| 721 | |
| 722 | |
| 723 | |
| 724 | |
| 725 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 726 | // also for pass-gate with decoder |
| 727 | |
| 728 | |
| 729 | |
| 730 | |
| 731 | |
| 732 | // any PARAMS parms go into naming of macro |
| 733 | |
| 734 | module db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 ( |
| 735 | din0, |
| 736 | sel0, |
| 737 | din1, |
| 738 | sel1, |
| 739 | din2, |
| 740 | sel2, |
| 741 | dout); |
| 742 | wire buffout0; |
| 743 | wire buffout1; |
| 744 | wire buffout2; |
| 745 | |
| 746 | input [11:0] din0; |
| 747 | input sel0; |
| 748 | input [11:0] din1; |
| 749 | input sel1; |
| 750 | input [11:0] din2; |
| 751 | input sel2; |
| 752 | output [11:0] dout; |
| 753 | |
| 754 | |
| 755 | |
| 756 | |
| 757 | |
| 758 | cl_dp1_muxbuff3_8x c0_0 ( |
| 759 | .in0(sel0), |
| 760 | .in1(sel1), |
| 761 | .in2(sel2), |
| 762 | .out0(buffout0), |
| 763 | .out1(buffout1), |
| 764 | .out2(buffout2) |
| 765 | ); |
| 766 | mux3s #(12) d0_0 ( |
| 767 | .sel0(buffout0), |
| 768 | .sel1(buffout1), |
| 769 | .sel2(buffout2), |
| 770 | .in0(din0[11:0]), |
| 771 | .in1(din1[11:0]), |
| 772 | .in2(din2[11:0]), |
| 773 | .dout(dout[11:0]) |
| 774 | ); |
| 775 | |
| 776 | |
| 777 | |
| 778 | |
| 779 | |
| 780 | |
| 781 | |
| 782 | |
| 783 | |
| 784 | |
| 785 | |
| 786 | |
| 787 | |
| 788 | endmodule |
| 789 | |
| 790 | |
| 791 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 792 | // also for pass-gate with decoder |
| 793 | |
| 794 | |
| 795 | |
| 796 | |
| 797 | |
| 798 | // any PARAMS parms go into naming of macro |
| 799 | |
| 800 | module db0_red_dp_mux_macro__mux_aonpe__ports_4__stack_12r__width_12 ( |
| 801 | din0, |
| 802 | sel0, |
| 803 | din1, |
| 804 | sel1, |
| 805 | din2, |
| 806 | sel2, |
| 807 | din3, |
| 808 | sel3, |
| 809 | dout); |
| 810 | wire buffout0; |
| 811 | wire buffout1; |
| 812 | wire buffout2; |
| 813 | wire buffout3; |
| 814 | |
| 815 | input [11:0] din0; |
| 816 | input sel0; |
| 817 | input [11:0] din1; |
| 818 | input sel1; |
| 819 | input [11:0] din2; |
| 820 | input sel2; |
| 821 | input [11:0] din3; |
| 822 | input sel3; |
| 823 | output [11:0] dout; |
| 824 | |
| 825 | |
| 826 | |
| 827 | |
| 828 | |
| 829 | cl_dp1_muxbuff4_8x c0_0 ( |
| 830 | .in0(sel0), |
| 831 | .in1(sel1), |
| 832 | .in2(sel2), |
| 833 | .in3(sel3), |
| 834 | .out0(buffout0), |
| 835 | .out1(buffout1), |
| 836 | .out2(buffout2), |
| 837 | .out3(buffout3) |
| 838 | ); |
| 839 | mux4s #(12) d0_0 ( |
| 840 | .sel0(buffout0), |
| 841 | .sel1(buffout1), |
| 842 | .sel2(buffout2), |
| 843 | .sel3(buffout3), |
| 844 | .in0(din0[11:0]), |
| 845 | .in1(din1[11:0]), |
| 846 | .in2(din2[11:0]), |
| 847 | .in3(din3[11:0]), |
| 848 | .dout(dout[11:0]) |
| 849 | ); |
| 850 | |
| 851 | |
| 852 | |
| 853 | |
| 854 | |
| 855 | |
| 856 | |
| 857 | |
| 858 | |
| 859 | |
| 860 | |
| 861 | |
| 862 | |
| 863 | endmodule |
| 864 | |
| 865 | |
| 866 | |
| 867 | |
| 868 | |
| 869 | |
| 870 | // any PARAMS parms go into naming of macro |
| 871 | |
| 872 | module db0_red_dp_msff_macro__stack_24r__width_24 ( |
| 873 | din, |
| 874 | clk, |
| 875 | en, |
| 876 | se, |
| 877 | scan_in, |
| 878 | siclk, |
| 879 | soclk, |
| 880 | pce_ov, |
| 881 | stop, |
| 882 | dout, |
| 883 | scan_out); |
| 884 | wire l1clk; |
| 885 | wire siclk_out; |
| 886 | wire soclk_out; |
| 887 | wire [22:0] so; |
| 888 | |
| 889 | input [23:0] din; |
| 890 | |
| 891 | |
| 892 | input clk; |
| 893 | input en; |
| 894 | input se; |
| 895 | input scan_in; |
| 896 | input siclk; |
| 897 | input soclk; |
| 898 | input pce_ov; |
| 899 | input stop; |
| 900 | |
| 901 | |
| 902 | |
| 903 | output [23:0] dout; |
| 904 | |
| 905 | |
| 906 | output scan_out; |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | cl_dp1_l1hdr_8x c0_0 ( |
| 912 | .l2clk(clk), |
| 913 | .pce(en), |
| 914 | .aclk(siclk), |
| 915 | .bclk(soclk), |
| 916 | .l1clk(l1clk), |
| 917 | .se(se), |
| 918 | .pce_ov(pce_ov), |
| 919 | .stop(stop), |
| 920 | .siclk_out(siclk_out), |
| 921 | .soclk_out(soclk_out) |
| 922 | ); |
| 923 | dff #(24) d0_0 ( |
| 924 | .l1clk(l1clk), |
| 925 | .siclk(siclk_out), |
| 926 | .soclk(soclk_out), |
| 927 | .d(din[23:0]), |
| 928 | .si({scan_in,so[22:0]}), |
| 929 | .so({so[22:0],scan_out}), |
| 930 | .q(dout[23:0]) |
| 931 | ); |
| 932 | |
| 933 | |
| 934 | |
| 935 | |
| 936 | |
| 937 | |
| 938 | |
| 939 | |
| 940 | |
| 941 | |
| 942 | |
| 943 | |
| 944 | |
| 945 | |
| 946 | |
| 947 | |
| 948 | |
| 949 | |
| 950 | |
| 951 | |
| 952 | endmodule |
| 953 | |
| 954 | |
| 955 | |
| 956 | |
| 957 | |
| 958 | |
| 959 | |
| 960 | |