| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: db0_reduct_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module db0_reduct_ctl ( |
| 36 | iol2clk, |
| 37 | scan_in, |
| 38 | scan_out, |
| 39 | tcu_pce_ov, |
| 40 | tcu_clk_stop, |
| 41 | tcu_aclk, |
| 42 | tcu_bclk, |
| 43 | tcu_scan_en, |
| 44 | dmu_ncu_vld, |
| 45 | wr_en0, |
| 46 | wr_en1, |
| 47 | wr_en2, |
| 48 | wr_en3, |
| 49 | mux1_sel0, |
| 50 | mux1_sel1, |
| 51 | mux1_sel2, |
| 52 | mux2_sel0, |
| 53 | mux2_sel1, |
| 54 | mux2_sel2, |
| 55 | mux3_sel0, |
| 56 | mux3_sel1, |
| 57 | mux3_sel2, |
| 58 | mux4_sel0, |
| 59 | mux4_sel1, |
| 60 | mux4_sel2, |
| 61 | mux5_sel0, |
| 62 | mux5_sel1, |
| 63 | mux5_sel2, |
| 64 | mux5_sel3); |
| 65 | wire pce_ov; |
| 66 | wire stop; |
| 67 | wire siclk; |
| 68 | wire soclk; |
| 69 | wire se; |
| 70 | wire dmu_ncu_vld_r; |
| 71 | wire ff_dmu_ncu_vld_scanin; |
| 72 | wire ff_dmu_ncu_vld_scanout; |
| 73 | wire l1clk; |
| 74 | wire reg0_vld_din; |
| 75 | wire reg0_vld; |
| 76 | wire reg1_vld; |
| 77 | wire reg2_vld; |
| 78 | wire reg3_vld; |
| 79 | wire reg0_vld_r; |
| 80 | wire reg0_vld_r2; |
| 81 | wire ff_reg0_vld_scanin; |
| 82 | wire ff_reg0_vld_scanout; |
| 83 | wire ff_reg0_vld_r_scanin; |
| 84 | wire ff_reg0_vld_r_scanout; |
| 85 | wire ff_reg0_vld_r2_scanin; |
| 86 | wire ff_reg0_vld_r2_scanout; |
| 87 | wire reg1_vld_din; |
| 88 | wire reg1_vld_r_din; |
| 89 | wire reg1_vld_r; |
| 90 | wire reg1_vld_r2; |
| 91 | wire ff_reg1_vld_scanin; |
| 92 | wire ff_reg1_vld_scanout; |
| 93 | wire ff_reg1_vld_r_scanin; |
| 94 | wire ff_reg1_vld_r_scanout; |
| 95 | wire ff_reg1_vld_r2_scanin; |
| 96 | wire ff_reg1_vld_r2_scanout; |
| 97 | wire reg2_vld_din; |
| 98 | wire reg2_vld_r_din; |
| 99 | wire reg2_vld_r; |
| 100 | wire reg2_vld_r2; |
| 101 | wire ff_reg2_vld_scanin; |
| 102 | wire ff_reg2_vld_scanout; |
| 103 | wire ff_reg2_vld_r_scanin; |
| 104 | wire ff_reg2_vld_r_scanout; |
| 105 | wire ff_reg2_vld_r2_scanin; |
| 106 | wire ff_reg2_vld_r2_scanout; |
| 107 | wire reg3_vld_din; |
| 108 | wire reg3_vld_r_din; |
| 109 | wire reg3_vld_r; |
| 110 | wire reg3_vld_r2; |
| 111 | wire ff_reg3_vld_scanin; |
| 112 | wire ff_reg3_vld_scanout; |
| 113 | wire ff_reg3_vld_r_scanin; |
| 114 | wire ff_reg3_vld_r_scanout; |
| 115 | wire ff_reg3_vld_r2_scanin; |
| 116 | wire ff_reg3_vld_r2_scanout; |
| 117 | wire spares_scanin; |
| 118 | wire spares_scanout; |
| 119 | |
| 120 | |
| 121 | input iol2clk; // Internal IO clock from CCU |
| 122 | |
| 123 | input scan_in; |
| 124 | output scan_out; |
| 125 | input tcu_pce_ov; |
| 126 | input tcu_clk_stop; |
| 127 | input tcu_aclk; |
| 128 | input tcu_bclk; |
| 129 | input tcu_scan_en; |
| 130 | |
| 131 | |
| 132 | input dmu_ncu_vld; //CSR Data return valid from DMU to NCU |
| 133 | |
| 134 | output wr_en0; |
| 135 | output wr_en1; |
| 136 | output wr_en2; |
| 137 | output wr_en3; |
| 138 | |
| 139 | output mux1_sel0; |
| 140 | output mux1_sel1; |
| 141 | output mux1_sel2; |
| 142 | |
| 143 | output mux2_sel0; |
| 144 | output mux2_sel1; |
| 145 | output mux2_sel2; |
| 146 | |
| 147 | output mux3_sel0; |
| 148 | output mux3_sel1; |
| 149 | output mux3_sel2; |
| 150 | |
| 151 | output mux4_sel0; |
| 152 | output mux4_sel1; |
| 153 | output mux4_sel2; |
| 154 | |
| 155 | output mux5_sel0; |
| 156 | output mux5_sel1; |
| 157 | output mux5_sel2; |
| 158 | output mux5_sel3; |
| 159 | |
| 160 | // Scan reassigns |
| 161 | assign pce_ov = tcu_pce_ov; |
| 162 | assign stop = tcu_clk_stop; |
| 163 | assign siclk = tcu_aclk; |
| 164 | assign soclk = tcu_bclk; |
| 165 | assign se = tcu_scan_en; |
| 166 | |
| 167 | // flop dmu_ncu_vld |
| 168 | |
| 169 | db0_reduct_ctl_msff_ctl_macro__width_1 ff_dmu_ncu_vld |
| 170 | (.dout(dmu_ncu_vld_r), |
| 171 | .scan_in(ff_dmu_ncu_vld_scanin), |
| 172 | .scan_out(ff_dmu_ncu_vld_scanout), |
| 173 | .l1clk(l1clk), |
| 174 | .din(dmu_ncu_vld), |
| 175 | .siclk(siclk), |
| 176 | .soclk(soclk) |
| 177 | ); |
| 178 | |
| 179 | |
| 180 | // Reg0 vld bits |
| 181 | |
| 182 | assign reg0_vld_din = (dmu_ncu_vld_r & |
| 183 | ~(reg0_vld | reg1_vld | reg2_vld | reg3_vld) |
| 184 | ) | reg0_vld; // set if dmu_ncu_vld_r is true |
| 185 | // and reg0_vld,reg1_vld,reg2_vld,reg3_vld are |
| 186 | // all 1'b0 |
| 187 | // held at 1 with reg0_vld until |
| 188 | // cleared |
| 189 | assign mux1_sel0 = reg0_vld & ~reg0_vld_r; |
| 190 | assign mux1_sel1 = reg0_vld_r & ~reg0_vld_r2; |
| 191 | assign mux1_sel2 = reg0_vld_r2; |
| 192 | |
| 193 | assign mux5_sel0 = mux1_sel0 | mux1_sel1 | mux1_sel2; |
| 194 | |
| 195 | assign wr_en0 = (dmu_ncu_vld_r & |
| 196 | ~(reg0_vld | reg1_vld | reg2_vld | reg3_vld)); |
| 197 | |
| 198 | // write to reg0 when none of the valid bits are on and dmu_ncu_vld_r is true |
| 199 | |
| 200 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg0_vld |
| 201 | (.dout(reg0_vld), |
| 202 | .scan_in(ff_reg0_vld_scanin), |
| 203 | .scan_out(ff_reg0_vld_scanout), |
| 204 | .clr(reg0_vld_r2), |
| 205 | .l1clk(l1clk), |
| 206 | .din(reg0_vld_din), |
| 207 | .siclk(siclk), |
| 208 | .soclk(soclk) |
| 209 | |
| 210 | ); |
| 211 | |
| 212 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg0_vld_r |
| 213 | (.dout(reg0_vld_r), |
| 214 | .scan_in(ff_reg0_vld_r_scanin), |
| 215 | .scan_out(ff_reg0_vld_r_scanout), |
| 216 | .clr(reg0_vld_r2), |
| 217 | .l1clk(l1clk), |
| 218 | .din(reg0_vld), |
| 219 | .siclk(siclk), |
| 220 | .soclk(soclk) |
| 221 | |
| 222 | ); |
| 223 | |
| 224 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg0_vld_r2 |
| 225 | (.dout(reg0_vld_r2), |
| 226 | .scan_in(ff_reg0_vld_r2_scanin), |
| 227 | .scan_out(ff_reg0_vld_r2_scanout), |
| 228 | .clr(reg0_vld_r2), |
| 229 | .l1clk(l1clk), |
| 230 | .din(reg0_vld_r), |
| 231 | .siclk(siclk), |
| 232 | .soclk(soclk) |
| 233 | |
| 234 | ); |
| 235 | |
| 236 | // Reg1 vld bits |
| 237 | |
| 238 | assign reg1_vld_din = (dmu_ncu_vld_r & reg0_vld ) | reg1_vld; // set if dmu_ncu_vld_r is true |
| 239 | // and reg0_vld is 1'b1 |
| 240 | // held at 1 with reg1_vld until |
| 241 | // cleared |
| 242 | |
| 243 | assign reg1_vld_r_din = reg1_vld & ~reg0_vld; // propagate the value of reg1_vld to reg1_vld_r |
| 244 | // only when reg0_vld = 0 |
| 245 | |
| 246 | assign mux2_sel0 = reg1_vld & ~reg1_vld_r & ~reg0_vld; |
| 247 | assign mux2_sel1 = reg1_vld_r & ~reg1_vld_r2; |
| 248 | assign mux2_sel2 = reg1_vld_r2; |
| 249 | |
| 250 | assign mux5_sel1 = mux2_sel0 | mux2_sel1 | mux2_sel2; |
| 251 | |
| 252 | assign wr_en1 = (dmu_ncu_vld_r & reg0_vld & ~reg1_vld); |
| 253 | |
| 254 | // write to reg1 when reg0 valid bit is true and dmu_ncu_vld_r is true |
| 255 | |
| 256 | |
| 257 | |
| 258 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg1_vld |
| 259 | (.dout(reg1_vld), |
| 260 | .scan_in(ff_reg1_vld_scanin), |
| 261 | .scan_out(ff_reg1_vld_scanout), |
| 262 | .clr(reg1_vld_r2), |
| 263 | .l1clk(l1clk), |
| 264 | .din(reg1_vld_din), |
| 265 | .siclk(siclk), |
| 266 | .soclk(soclk) |
| 267 | |
| 268 | ); |
| 269 | |
| 270 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg1_vld_r |
| 271 | (.dout(reg1_vld_r), |
| 272 | .scan_in(ff_reg1_vld_r_scanin), |
| 273 | .scan_out(ff_reg1_vld_r_scanout), |
| 274 | .clr(reg1_vld_r2), |
| 275 | .l1clk(l1clk), |
| 276 | .din(reg1_vld_r_din), |
| 277 | .siclk(siclk), |
| 278 | .soclk(soclk) |
| 279 | |
| 280 | ); |
| 281 | |
| 282 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg1_vld_r2 |
| 283 | (.dout(reg1_vld_r2), |
| 284 | .scan_in(ff_reg1_vld_r2_scanin), |
| 285 | .scan_out(ff_reg1_vld_r2_scanout), |
| 286 | .clr(reg1_vld_r2), |
| 287 | .l1clk(l1clk), |
| 288 | .din(reg1_vld_r), |
| 289 | .siclk(siclk), |
| 290 | .soclk(soclk) |
| 291 | |
| 292 | ); |
| 293 | |
| 294 | // Reg2 vld bits |
| 295 | |
| 296 | assign reg2_vld_din = (dmu_ncu_vld_r & reg1_vld ) | reg2_vld; // set if dmu_ncu_vld_r is true |
| 297 | // and reg1_vld is 1'b1 |
| 298 | // held at 1 with reg2_vld until |
| 299 | // cleared |
| 300 | |
| 301 | assign reg2_vld_r_din = reg2_vld & ~reg1_vld; // propagate the value of reg2_vld to reg2_vld_r |
| 302 | // only when reg1_vld = 0 |
| 303 | |
| 304 | assign mux3_sel0 = reg2_vld & ~reg2_vld_r & ~reg1_vld; |
| 305 | assign mux3_sel1 = reg2_vld_r & ~reg2_vld_r2; |
| 306 | assign mux3_sel2 = reg2_vld_r2; |
| 307 | |
| 308 | assign mux5_sel2 = mux3_sel0 | mux3_sel1 | mux3_sel2; |
| 309 | |
| 310 | assign wr_en2 = (dmu_ncu_vld_r & reg1_vld & ~reg2_vld); |
| 311 | |
| 312 | // write to reg2 when reg1 valid bit is true and dmu_ncu_vld_r is true |
| 313 | |
| 314 | |
| 315 | |
| 316 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg2_vld |
| 317 | (.dout(reg2_vld), |
| 318 | .scan_in(ff_reg2_vld_scanin), |
| 319 | .scan_out(ff_reg2_vld_scanout), |
| 320 | .clr(reg2_vld_r2), |
| 321 | .l1clk(l1clk), |
| 322 | .din(reg2_vld_din), |
| 323 | .siclk(siclk), |
| 324 | .soclk(soclk) |
| 325 | |
| 326 | ); |
| 327 | |
| 328 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg2_vld_r |
| 329 | (.dout(reg2_vld_r), |
| 330 | .scan_in(ff_reg2_vld_r_scanin), |
| 331 | .scan_out(ff_reg2_vld_r_scanout), |
| 332 | .clr(reg2_vld_r2), |
| 333 | .l1clk(l1clk), |
| 334 | .din(reg2_vld_r_din), |
| 335 | .siclk(siclk), |
| 336 | .soclk(soclk) |
| 337 | |
| 338 | ); |
| 339 | |
| 340 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg2_vld_r2 |
| 341 | (.dout(reg2_vld_r2), |
| 342 | .scan_in(ff_reg2_vld_r2_scanin), |
| 343 | .scan_out(ff_reg2_vld_r2_scanout), |
| 344 | .clr(reg2_vld_r2), |
| 345 | .l1clk(l1clk), |
| 346 | .din(reg2_vld_r), |
| 347 | .siclk(siclk), |
| 348 | .soclk(soclk) |
| 349 | |
| 350 | ); |
| 351 | |
| 352 | // Reg3 vld bits |
| 353 | |
| 354 | assign reg3_vld_din = (dmu_ncu_vld_r & reg2_vld ) | reg3_vld; // set if dmu_ncu_vld_r is true |
| 355 | // and reg2_vld is 1'b1 |
| 356 | // held at 1 with reg3_vld until |
| 357 | // cleared |
| 358 | |
| 359 | assign reg3_vld_r_din = reg3_vld & ~reg2_vld; // propagate the value of reg3_vld to reg3_vld_r |
| 360 | // only when reg2_vld = 0 |
| 361 | |
| 362 | assign mux4_sel0 = reg3_vld & ~reg3_vld_r & ~reg2_vld; |
| 363 | assign mux4_sel1 = reg3_vld_r & ~reg3_vld_r2; |
| 364 | assign mux4_sel2 = reg3_vld_r2; |
| 365 | |
| 366 | assign mux5_sel3 = mux4_sel0 | mux4_sel1 | mux4_sel2; |
| 367 | |
| 368 | assign wr_en3 = (dmu_ncu_vld_r & reg2_vld); |
| 369 | |
| 370 | // write to reg3 when reg2 valid bit is true and dmu_ncu_vld_r is true |
| 371 | |
| 372 | |
| 373 | |
| 374 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg3_vld |
| 375 | (.dout(reg3_vld), |
| 376 | .scan_in(ff_reg3_vld_scanin), |
| 377 | .scan_out(ff_reg3_vld_scanout), |
| 378 | .clr(reg3_vld_r2), |
| 379 | .l1clk(l1clk), |
| 380 | .din(reg3_vld_din), |
| 381 | .siclk(siclk), |
| 382 | .soclk(soclk) |
| 383 | |
| 384 | ); |
| 385 | |
| 386 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg3_vld_r |
| 387 | (.dout(reg3_vld_r), |
| 388 | .scan_in(ff_reg3_vld_r_scanin), |
| 389 | .scan_out(ff_reg3_vld_r_scanout), |
| 390 | .clr(reg3_vld_r2), |
| 391 | .l1clk(l1clk), |
| 392 | .din(reg3_vld_r_din), |
| 393 | .siclk(siclk), |
| 394 | .soclk(soclk) |
| 395 | |
| 396 | ); |
| 397 | |
| 398 | db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ff_reg3_vld_r2 |
| 399 | (.dout(reg3_vld_r2), |
| 400 | .scan_in(ff_reg3_vld_r2_scanin), |
| 401 | .scan_out(ff_reg3_vld_r2_scanout), |
| 402 | .clr(reg3_vld_r2), |
| 403 | .l1clk(l1clk), |
| 404 | .din(reg3_vld_r), |
| 405 | .siclk(siclk), |
| 406 | .soclk(soclk) |
| 407 | |
| 408 | ); |
| 409 | |
| 410 | // Spare gates |
| 411 | |
| 412 | db0_reduct_ctl_spare_ctl_macro__num_5 spares ( |
| 413 | .scan_in(spares_scanin), |
| 414 | .scan_out(spares_scanout), |
| 415 | .l1clk (l1clk), |
| 416 | .siclk(siclk), |
| 417 | .soclk(soclk) |
| 418 | ); |
| 419 | |
| 420 | /**** adding clock header ****/ |
| 421 | db0_reduct_ctl_l1clkhdr_ctl_macro clkgen ( |
| 422 | .l2clk (iol2clk), |
| 423 | .l1en (1'b1), |
| 424 | .l1clk (l1clk), |
| 425 | .pce_ov(pce_ov), |
| 426 | .stop(stop), |
| 427 | .se(se) |
| 428 | ); |
| 429 | |
| 430 | |
| 431 | // fixscan start: |
| 432 | assign ff_dmu_ncu_vld_scanin = scan_in ; |
| 433 | assign ff_reg0_vld_scanin = ff_dmu_ncu_vld_scanout ; |
| 434 | assign ff_reg0_vld_r_scanin = ff_reg0_vld_scanout ; |
| 435 | assign ff_reg0_vld_r2_scanin = ff_reg0_vld_r_scanout ; |
| 436 | assign ff_reg1_vld_scanin = ff_reg0_vld_r2_scanout ; |
| 437 | assign ff_reg1_vld_r_scanin = ff_reg1_vld_scanout ; |
| 438 | assign ff_reg1_vld_r2_scanin = ff_reg1_vld_r_scanout ; |
| 439 | assign ff_reg2_vld_scanin = ff_reg1_vld_r2_scanout ; |
| 440 | assign ff_reg2_vld_r_scanin = ff_reg2_vld_scanout ; |
| 441 | assign ff_reg2_vld_r2_scanin = ff_reg2_vld_r_scanout ; |
| 442 | assign ff_reg3_vld_scanin = ff_reg2_vld_r2_scanout ; |
| 443 | assign ff_reg3_vld_r_scanin = ff_reg3_vld_scanout ; |
| 444 | assign ff_reg3_vld_r2_scanin = ff_reg3_vld_r_scanout ; |
| 445 | assign spares_scanin = ff_reg3_vld_r2_scanout ; |
| 446 | assign scan_out = spares_scanout ; |
| 447 | // fixscan end: |
| 448 | endmodule |
| 449 | |
| 450 | |
| 451 | |
| 452 | |
| 453 | |
| 454 | |
| 455 | // any PARAMS parms go into naming of macro |
| 456 | |
| 457 | module db0_reduct_ctl_msff_ctl_macro__width_1 ( |
| 458 | din, |
| 459 | l1clk, |
| 460 | scan_in, |
| 461 | siclk, |
| 462 | soclk, |
| 463 | dout, |
| 464 | scan_out); |
| 465 | wire [0:0] fdin; |
| 466 | |
| 467 | input [0:0] din; |
| 468 | input l1clk; |
| 469 | input scan_in; |
| 470 | |
| 471 | |
| 472 | input siclk; |
| 473 | input soclk; |
| 474 | |
| 475 | output [0:0] dout; |
| 476 | output scan_out; |
| 477 | assign fdin[0:0] = din[0:0]; |
| 478 | |
| 479 | |
| 480 | |
| 481 | |
| 482 | |
| 483 | |
| 484 | dff #(1) d0_0 ( |
| 485 | .l1clk(l1clk), |
| 486 | .siclk(siclk), |
| 487 | .soclk(soclk), |
| 488 | .d(fdin[0:0]), |
| 489 | .si(scan_in), |
| 490 | .so(scan_out), |
| 491 | .q(dout[0:0]) |
| 492 | ); |
| 493 | |
| 494 | |
| 495 | |
| 496 | |
| 497 | |
| 498 | |
| 499 | |
| 500 | |
| 501 | |
| 502 | |
| 503 | |
| 504 | |
| 505 | endmodule |
| 506 | |
| 507 | |
| 508 | |
| 509 | |
| 510 | |
| 511 | |
| 512 | |
| 513 | |
| 514 | |
| 515 | |
| 516 | |
| 517 | |
| 518 | |
| 519 | // any PARAMS parms go into naming of macro |
| 520 | |
| 521 | module db0_reduct_ctl_msff_ctl_macro__clr_1__width_1 ( |
| 522 | din, |
| 523 | clr, |
| 524 | l1clk, |
| 525 | scan_in, |
| 526 | siclk, |
| 527 | soclk, |
| 528 | dout, |
| 529 | scan_out); |
| 530 | wire [0:0] fdin; |
| 531 | |
| 532 | input [0:0] din; |
| 533 | input clr; |
| 534 | input l1clk; |
| 535 | input scan_in; |
| 536 | |
| 537 | |
| 538 | input siclk; |
| 539 | input soclk; |
| 540 | |
| 541 | output [0:0] dout; |
| 542 | output scan_out; |
| 543 | assign fdin[0:0] = din[0:0] & ~{1{clr}}; |
| 544 | |
| 545 | |
| 546 | |
| 547 | |
| 548 | |
| 549 | |
| 550 | dff #(1) d0_0 ( |
| 551 | .l1clk(l1clk), |
| 552 | .siclk(siclk), |
| 553 | .soclk(soclk), |
| 554 | .d(fdin[0:0]), |
| 555 | .si(scan_in), |
| 556 | .so(scan_out), |
| 557 | .q(dout[0:0]) |
| 558 | ); |
| 559 | |
| 560 | |
| 561 | |
| 562 | |
| 563 | |
| 564 | |
| 565 | |
| 566 | |
| 567 | |
| 568 | |
| 569 | |
| 570 | |
| 571 | endmodule |
| 572 | |
| 573 | |
| 574 | |
| 575 | |
| 576 | |
| 577 | |
| 578 | |
| 579 | |
| 580 | |
| 581 | // Description: Spare gate macro for control blocks |
| 582 | // |
| 583 | // Param num controls the number of times the macro is added |
| 584 | // flops=0 can be used to use only combination spare logic |
| 585 | |
| 586 | |
| 587 | module db0_reduct_ctl_spare_ctl_macro__num_5 ( |
| 588 | l1clk, |
| 589 | scan_in, |
| 590 | siclk, |
| 591 | soclk, |
| 592 | scan_out); |
| 593 | wire si_0; |
| 594 | wire so_0; |
| 595 | wire spare0_flop_unused; |
| 596 | wire spare0_buf_32x_unused; |
| 597 | wire spare0_nand3_8x_unused; |
| 598 | wire spare0_inv_8x_unused; |
| 599 | wire spare0_aoi22_4x_unused; |
| 600 | wire spare0_buf_8x_unused; |
| 601 | wire spare0_oai22_4x_unused; |
| 602 | wire spare0_inv_16x_unused; |
| 603 | wire spare0_nand2_16x_unused; |
| 604 | wire spare0_nor3_4x_unused; |
| 605 | wire spare0_nand2_8x_unused; |
| 606 | wire spare0_buf_16x_unused; |
| 607 | wire spare0_nor2_16x_unused; |
| 608 | wire spare0_inv_32x_unused; |
| 609 | wire si_1; |
| 610 | wire so_1; |
| 611 | wire spare1_flop_unused; |
| 612 | wire spare1_buf_32x_unused; |
| 613 | wire spare1_nand3_8x_unused; |
| 614 | wire spare1_inv_8x_unused; |
| 615 | wire spare1_aoi22_4x_unused; |
| 616 | wire spare1_buf_8x_unused; |
| 617 | wire spare1_oai22_4x_unused; |
| 618 | wire spare1_inv_16x_unused; |
| 619 | wire spare1_nand2_16x_unused; |
| 620 | wire spare1_nor3_4x_unused; |
| 621 | wire spare1_nand2_8x_unused; |
| 622 | wire spare1_buf_16x_unused; |
| 623 | wire spare1_nor2_16x_unused; |
| 624 | wire spare1_inv_32x_unused; |
| 625 | wire si_2; |
| 626 | wire so_2; |
| 627 | wire spare2_flop_unused; |
| 628 | wire spare2_buf_32x_unused; |
| 629 | wire spare2_nand3_8x_unused; |
| 630 | wire spare2_inv_8x_unused; |
| 631 | wire spare2_aoi22_4x_unused; |
| 632 | wire spare2_buf_8x_unused; |
| 633 | wire spare2_oai22_4x_unused; |
| 634 | wire spare2_inv_16x_unused; |
| 635 | wire spare2_nand2_16x_unused; |
| 636 | wire spare2_nor3_4x_unused; |
| 637 | wire spare2_nand2_8x_unused; |
| 638 | wire spare2_buf_16x_unused; |
| 639 | wire spare2_nor2_16x_unused; |
| 640 | wire spare2_inv_32x_unused; |
| 641 | wire si_3; |
| 642 | wire so_3; |
| 643 | wire spare3_flop_unused; |
| 644 | wire spare3_buf_32x_unused; |
| 645 | wire spare3_nand3_8x_unused; |
| 646 | wire spare3_inv_8x_unused; |
| 647 | wire spare3_aoi22_4x_unused; |
| 648 | wire spare3_buf_8x_unused; |
| 649 | wire spare3_oai22_4x_unused; |
| 650 | wire spare3_inv_16x_unused; |
| 651 | wire spare3_nand2_16x_unused; |
| 652 | wire spare3_nor3_4x_unused; |
| 653 | wire spare3_nand2_8x_unused; |
| 654 | wire spare3_buf_16x_unused; |
| 655 | wire spare3_nor2_16x_unused; |
| 656 | wire spare3_inv_32x_unused; |
| 657 | wire si_4; |
| 658 | wire so_4; |
| 659 | wire spare4_flop_unused; |
| 660 | wire spare4_buf_32x_unused; |
| 661 | wire spare4_nand3_8x_unused; |
| 662 | wire spare4_inv_8x_unused; |
| 663 | wire spare4_aoi22_4x_unused; |
| 664 | wire spare4_buf_8x_unused; |
| 665 | wire spare4_oai22_4x_unused; |
| 666 | wire spare4_inv_16x_unused; |
| 667 | wire spare4_nand2_16x_unused; |
| 668 | wire spare4_nor3_4x_unused; |
| 669 | wire spare4_nand2_8x_unused; |
| 670 | wire spare4_buf_16x_unused; |
| 671 | wire spare4_nor2_16x_unused; |
| 672 | wire spare4_inv_32x_unused; |
| 673 | |
| 674 | |
| 675 | input l1clk; |
| 676 | input scan_in; |
| 677 | input siclk; |
| 678 | input soclk; |
| 679 | output scan_out; |
| 680 | |
| 681 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 682 | .siclk(siclk), |
| 683 | .soclk(soclk), |
| 684 | .si(si_0), |
| 685 | .so(so_0), |
| 686 | .d(1'b0), |
| 687 | .q(spare0_flop_unused)); |
| 688 | assign si_0 = scan_in; |
| 689 | |
| 690 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 691 | .out(spare0_buf_32x_unused)); |
| 692 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 693 | .in1(1'b1), |
| 694 | .in2(1'b1), |
| 695 | .out(spare0_nand3_8x_unused)); |
| 696 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 697 | .out(spare0_inv_8x_unused)); |
| 698 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 699 | .in01(1'b1), |
| 700 | .in10(1'b1), |
| 701 | .in11(1'b1), |
| 702 | .out(spare0_aoi22_4x_unused)); |
| 703 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 704 | .out(spare0_buf_8x_unused)); |
| 705 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 706 | .in01(1'b1), |
| 707 | .in10(1'b1), |
| 708 | .in11(1'b1), |
| 709 | .out(spare0_oai22_4x_unused)); |
| 710 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 711 | .out(spare0_inv_16x_unused)); |
| 712 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 713 | .in1(1'b1), |
| 714 | .out(spare0_nand2_16x_unused)); |
| 715 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 716 | .in1(1'b0), |
| 717 | .in2(1'b0), |
| 718 | .out(spare0_nor3_4x_unused)); |
| 719 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 720 | .in1(1'b1), |
| 721 | .out(spare0_nand2_8x_unused)); |
| 722 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 723 | .out(spare0_buf_16x_unused)); |
| 724 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 725 | .in1(1'b0), |
| 726 | .out(spare0_nor2_16x_unused)); |
| 727 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 728 | .out(spare0_inv_32x_unused)); |
| 729 | |
| 730 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 731 | .siclk(siclk), |
| 732 | .soclk(soclk), |
| 733 | .si(si_1), |
| 734 | .so(so_1), |
| 735 | .d(1'b0), |
| 736 | .q(spare1_flop_unused)); |
| 737 | assign si_1 = so_0; |
| 738 | |
| 739 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 740 | .out(spare1_buf_32x_unused)); |
| 741 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 742 | .in1(1'b1), |
| 743 | .in2(1'b1), |
| 744 | .out(spare1_nand3_8x_unused)); |
| 745 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 746 | .out(spare1_inv_8x_unused)); |
| 747 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 748 | .in01(1'b1), |
| 749 | .in10(1'b1), |
| 750 | .in11(1'b1), |
| 751 | .out(spare1_aoi22_4x_unused)); |
| 752 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 753 | .out(spare1_buf_8x_unused)); |
| 754 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 755 | .in01(1'b1), |
| 756 | .in10(1'b1), |
| 757 | .in11(1'b1), |
| 758 | .out(spare1_oai22_4x_unused)); |
| 759 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 760 | .out(spare1_inv_16x_unused)); |
| 761 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 762 | .in1(1'b1), |
| 763 | .out(spare1_nand2_16x_unused)); |
| 764 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 765 | .in1(1'b0), |
| 766 | .in2(1'b0), |
| 767 | .out(spare1_nor3_4x_unused)); |
| 768 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 769 | .in1(1'b1), |
| 770 | .out(spare1_nand2_8x_unused)); |
| 771 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 772 | .out(spare1_buf_16x_unused)); |
| 773 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 774 | .in1(1'b0), |
| 775 | .out(spare1_nor2_16x_unused)); |
| 776 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 777 | .out(spare1_inv_32x_unused)); |
| 778 | |
| 779 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 780 | .siclk(siclk), |
| 781 | .soclk(soclk), |
| 782 | .si(si_2), |
| 783 | .so(so_2), |
| 784 | .d(1'b0), |
| 785 | .q(spare2_flop_unused)); |
| 786 | assign si_2 = so_1; |
| 787 | |
| 788 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 789 | .out(spare2_buf_32x_unused)); |
| 790 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 791 | .in1(1'b1), |
| 792 | .in2(1'b1), |
| 793 | .out(spare2_nand3_8x_unused)); |
| 794 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 795 | .out(spare2_inv_8x_unused)); |
| 796 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 797 | .in01(1'b1), |
| 798 | .in10(1'b1), |
| 799 | .in11(1'b1), |
| 800 | .out(spare2_aoi22_4x_unused)); |
| 801 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 802 | .out(spare2_buf_8x_unused)); |
| 803 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 804 | .in01(1'b1), |
| 805 | .in10(1'b1), |
| 806 | .in11(1'b1), |
| 807 | .out(spare2_oai22_4x_unused)); |
| 808 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 809 | .out(spare2_inv_16x_unused)); |
| 810 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 811 | .in1(1'b1), |
| 812 | .out(spare2_nand2_16x_unused)); |
| 813 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 814 | .in1(1'b0), |
| 815 | .in2(1'b0), |
| 816 | .out(spare2_nor3_4x_unused)); |
| 817 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 818 | .in1(1'b1), |
| 819 | .out(spare2_nand2_8x_unused)); |
| 820 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 821 | .out(spare2_buf_16x_unused)); |
| 822 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 823 | .in1(1'b0), |
| 824 | .out(spare2_nor2_16x_unused)); |
| 825 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 826 | .out(spare2_inv_32x_unused)); |
| 827 | |
| 828 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 829 | .siclk(siclk), |
| 830 | .soclk(soclk), |
| 831 | .si(si_3), |
| 832 | .so(so_3), |
| 833 | .d(1'b0), |
| 834 | .q(spare3_flop_unused)); |
| 835 | assign si_3 = so_2; |
| 836 | |
| 837 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 838 | .out(spare3_buf_32x_unused)); |
| 839 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 840 | .in1(1'b1), |
| 841 | .in2(1'b1), |
| 842 | .out(spare3_nand3_8x_unused)); |
| 843 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 844 | .out(spare3_inv_8x_unused)); |
| 845 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 846 | .in01(1'b1), |
| 847 | .in10(1'b1), |
| 848 | .in11(1'b1), |
| 849 | .out(spare3_aoi22_4x_unused)); |
| 850 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 851 | .out(spare3_buf_8x_unused)); |
| 852 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 853 | .in01(1'b1), |
| 854 | .in10(1'b1), |
| 855 | .in11(1'b1), |
| 856 | .out(spare3_oai22_4x_unused)); |
| 857 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 858 | .out(spare3_inv_16x_unused)); |
| 859 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 860 | .in1(1'b1), |
| 861 | .out(spare3_nand2_16x_unused)); |
| 862 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 863 | .in1(1'b0), |
| 864 | .in2(1'b0), |
| 865 | .out(spare3_nor3_4x_unused)); |
| 866 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 867 | .in1(1'b1), |
| 868 | .out(spare3_nand2_8x_unused)); |
| 869 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 870 | .out(spare3_buf_16x_unused)); |
| 871 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 872 | .in1(1'b0), |
| 873 | .out(spare3_nor2_16x_unused)); |
| 874 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 875 | .out(spare3_inv_32x_unused)); |
| 876 | |
| 877 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), |
| 878 | .siclk(siclk), |
| 879 | .soclk(soclk), |
| 880 | .si(si_4), |
| 881 | .so(so_4), |
| 882 | .d(1'b0), |
| 883 | .q(spare4_flop_unused)); |
| 884 | assign si_4 = so_3; |
| 885 | |
| 886 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 887 | .out(spare4_buf_32x_unused)); |
| 888 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 889 | .in1(1'b1), |
| 890 | .in2(1'b1), |
| 891 | .out(spare4_nand3_8x_unused)); |
| 892 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 893 | .out(spare4_inv_8x_unused)); |
| 894 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 895 | .in01(1'b1), |
| 896 | .in10(1'b1), |
| 897 | .in11(1'b1), |
| 898 | .out(spare4_aoi22_4x_unused)); |
| 899 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 900 | .out(spare4_buf_8x_unused)); |
| 901 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 902 | .in01(1'b1), |
| 903 | .in10(1'b1), |
| 904 | .in11(1'b1), |
| 905 | .out(spare4_oai22_4x_unused)); |
| 906 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 907 | .out(spare4_inv_16x_unused)); |
| 908 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 909 | .in1(1'b1), |
| 910 | .out(spare4_nand2_16x_unused)); |
| 911 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 912 | .in1(1'b0), |
| 913 | .in2(1'b0), |
| 914 | .out(spare4_nor3_4x_unused)); |
| 915 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 916 | .in1(1'b1), |
| 917 | .out(spare4_nand2_8x_unused)); |
| 918 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 919 | .out(spare4_buf_16x_unused)); |
| 920 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 921 | .in1(1'b0), |
| 922 | .out(spare4_nor2_16x_unused)); |
| 923 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 924 | .out(spare4_inv_32x_unused)); |
| 925 | assign scan_out = so_4; |
| 926 | |
| 927 | |
| 928 | |
| 929 | endmodule |
| 930 | |
| 931 | |
| 932 | |
| 933 | |
| 934 | |
| 935 | |
| 936 | // any PARAMS parms go into naming of macro |
| 937 | |
| 938 | module db0_reduct_ctl_l1clkhdr_ctl_macro ( |
| 939 | l2clk, |
| 940 | l1en, |
| 941 | pce_ov, |
| 942 | stop, |
| 943 | se, |
| 944 | l1clk); |
| 945 | |
| 946 | |
| 947 | input l2clk; |
| 948 | input l1en; |
| 949 | input pce_ov; |
| 950 | input stop; |
| 951 | input se; |
| 952 | output l1clk; |
| 953 | |
| 954 | |
| 955 | |
| 956 | |
| 957 | |
| 958 | cl_sc1_l1hdr_8x c_0 ( |
| 959 | |
| 960 | |
| 961 | .l2clk(l2clk), |
| 962 | .pce(l1en), |
| 963 | .l1clk(l1clk), |
| 964 | .se(se), |
| 965 | .pce_ov(pce_ov), |
| 966 | .stop(stop) |
| 967 | ); |
| 968 | |
| 969 | |
| 970 | |
| 971 | endmodule |
| 972 | |
| 973 | |
| 974 | |
| 975 | |
| 976 | |
| 977 | |
| 978 | |
| 979 | |