| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_cmu_clst_aloc.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_cmu_clst_aloc ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | enq, |
| 39 | data_in, |
| 40 | deq, |
| 41 | data_out, |
| 42 | full, |
| 43 | empty, |
| 44 | overflow, |
| 45 | underflow |
| 46 | ); |
| 47 | |
| 48 | //************************************************ |
| 49 | // PARAMETERS |
| 50 | //************************************************ |
| 51 | parameter WIDTH = 5; // max width supported |
| 52 | parameter DEPTH = 16; // max depth supported |
| 53 | |
| 54 | integer i; |
| 55 | |
| 56 | //************************************************ |
| 57 | // PORTS |
| 58 | //************************************************ |
| 59 | |
| 60 | input clk; // The input clock |
| 61 | input rst_l; // synopsys sync_set_reset "rst_l" |
| 62 | |
| 63 | input enq; // enqueue into fifo |
| 64 | input [WIDTH - 1:0] data_in; // data to put in |
| 65 | |
| 66 | input deq; // dequeue outof fifo |
| 67 | output [WIDTH - 1:0] data_out; // data taken out |
| 68 | |
| 69 | output full; // full flag |
| 70 | output empty; // empty flag |
| 71 | output overflow; // overflow indicater |
| 72 | output underflow; // underflow indicater |
| 73 | |
| 74 | //************************************************ |
| 75 | // SIGNALS |
| 76 | //************************************************ |
| 77 | |
| 78 | reg [WIDTH - 1:0] sr [0 :DEPTH -1]; // fifo flops |
| 79 | reg [DEPTH :0] ld; // current load location |
| 80 | reg [DEPTH :0] next_ld; // next load location |
| 81 | |
| 82 | reg [DEPTH - 1:0] vld; // current location has valid data |
| 83 | reg [DEPTH - 1:0] next_vld; // next location to have valid data |
| 84 | |
| 85 | reg empty; // fifo is empty |
| 86 | reg overflow; // enqueue when fifo was full |
| 87 | reg underflow; // dequeue when fifo was empty |
| 88 | |
| 89 | // uncomment to add a contents counter |
| 90 | // reg [COUNT_WIDTH:0] count; // # valid contents in fifo |
| 91 | |
| 92 | // uncoment these line for debug |
| 93 | // wire [WIDTH -1:0] sr_out_7, sr_out_6, sr_out_5, sr_out_4, |
| 94 | // sr_out_3, sr_out_2, sr_out_1, sr_out_0; |
| 95 | // |
| 96 | // assign sr_out_0 = sr[DEPTH - 8]; |
| 97 | // assign sr_out_1 = sr[DEPTH - 7]; |
| 98 | // assign sr_out_2 = sr[DEPTH - 6]; |
| 99 | // assign sr_out_3 = sr[DEPTH - 5]; |
| 100 | // assign sr_out_4 = sr[DEPTH - 4]; |
| 101 | // assign sr_out_5 = sr[DEPTH - 3]; |
| 102 | // assign sr_out_6 = sr[DEPTH - 2]; |
| 103 | // assign sr_out_7 = sr[DEPTH - 1]; |
| 104 | |
| 105 | |
| 106 | wire [DEPTH -1 :0] vld_init; // to make vlint happy |
| 107 | |
| 108 | wire [WIDTH -1 :0] initf = 5'h0f; |
| 109 | wire [WIDTH -1 :0] inite = 5'h0e; |
| 110 | wire [WIDTH -1 :0] initd = 5'h0d; |
| 111 | wire [WIDTH -1 :0] initc = 5'h0c; |
| 112 | wire [WIDTH -1 :0] initb = 5'h0b; |
| 113 | wire [WIDTH -1 :0] inita = 5'h0a; |
| 114 | wire [WIDTH -1 :0] init9 = 5'h09; |
| 115 | wire [WIDTH -1 :0] init8 = 5'h08; |
| 116 | |
| 117 | wire [WIDTH -1 :0] init7 = 5'h07; |
| 118 | wire [WIDTH -1 :0] init6 = 5'h06; |
| 119 | wire [WIDTH -1 :0] init5 = 5'h05; |
| 120 | wire [WIDTH -1 :0] init4 = 5'h04; |
| 121 | wire [WIDTH -1 :0] init3 = 5'h03; |
| 122 | wire [WIDTH -1 :0] init2 = 5'h02; |
| 123 | wire [WIDTH -1 :0] init1 = 5'h01; |
| 124 | wire [WIDTH -1 :0] init0 = 5'h00; |
| 125 | |
| 126 | assign vld_init[DEPTH -1 :0] = vld[DEPTH -1 :0] << 1; // make vlint happy |
| 127 | |
| 128 | //************************************************ |
| 129 | // mux function just to make the code easier for |
| 130 | // synthesis (like we really want a 2:1 mux) |
| 131 | //************************************************ |
| 132 | |
| 133 | function [WIDTH -1:0] reg_mux; |
| 134 | input sel; |
| 135 | input [WIDTH -1:0] nxdata; |
| 136 | input [WIDTH -1:0] nxsrdata; |
| 137 | |
| 138 | begin |
| 139 | reg_mux = sel ? nxdata : nxsrdata; |
| 140 | end |
| 141 | endfunction |
| 142 | |
| 143 | |
| 144 | //************************************************ |
| 145 | // the fifo location always gets the value on |
| 146 | // next_ld. mux logic to make the code parameterized and |
| 147 | // easier for synthesis |
| 148 | //************************************************ |
| 149 | |
| 150 | |
| 151 | always @ (posedge clk) // make vlint happy |
| 152 | begin |
| 153 | if (!rst_l) begin |
| 154 | sr[15] <= initf; |
| 155 | sr[14] <= inite; |
| 156 | sr[13] <= initd; |
| 157 | sr[12] <= initc; |
| 158 | sr[11] <= initb; |
| 159 | sr[10] <= inita; |
| 160 | sr[9] <= init9; |
| 161 | sr[8] <= init8; |
| 162 | sr[7] <= init7; |
| 163 | sr[6] <= init6; |
| 164 | sr[5] <= init5; |
| 165 | sr[4] <= init4; |
| 166 | sr[3] <= init3; |
| 167 | sr[2] <= init2; |
| 168 | sr[1] <= init1; |
| 169 | sr[0] <= init0; |
| 170 | end |
| 171 | else begin |
| 172 | for (i = 0; i < DEPTH -1 ; i = i+1) |
| 173 | case ({enq, deq}) // synopsys parallel_case |
| 174 | 2'b00: sr[i] <= sr[i]; |
| 175 | 2'b01: sr[i] <= sr[i+1]; |
| 176 | 2'b10: sr[i] <= reg_mux(next_ld[i+1], data_in, sr[i]); |
| 177 | 2'b11: sr[i] <= reg_mux(next_ld[i+1], data_in, sr[i+1]); |
| 178 | default: sr[i] <= sr[i]; |
| 179 | endcase // case({enq, deq}) |
| 180 | for (i = DEPTH -1; i < DEPTH ; i = i+1) |
| 181 | case ({enq, deq}) // synopsys parallel_case |
| 182 | 2'b00: sr[i] <= sr[i]; |
| 183 | 2'b01: sr[i] <= data_in; |
| 184 | 2'b10: sr[i] <= reg_mux(next_ld[i+1], data_in, sr[i]); |
| 185 | 2'b11: sr[i] <= reg_mux(next_ld[i+1], data_in, sr[i]); |
| 186 | default: sr[i] <= sr[i]; |
| 187 | endcase // case({enq, deq}) |
| 188 | end // else: !if(!rst_l) |
| 189 | end // always @ (posedge clk) |
| 190 | |
| 191 | //********************************************* |
| 192 | // fifo load control updates when enq or deq |
| 193 | // valid |
| 194 | //********************************************* |
| 195 | |
| 196 | always @ (rst_l or ld or enq or deq) |
| 197 | begin |
| 198 | if (!rst_l) begin |
| 199 | next_ld = {1'b1,{(DEPTH){1'b0}}}; // to make vlint happy |
| 200 | end |
| 201 | else begin |
| 202 | case ({enq, deq}) // synopsys parallel_case |
| 203 | 2'b00: next_ld = ld; |
| 204 | 2'b01: next_ld = ld >> 1; |
| 205 | 2'b10: next_ld = ld << 1; |
| 206 | 2'b11: next_ld = ld; |
| 207 | default: next_ld = ld; |
| 208 | endcase // case({enq, deq}) |
| 209 | end // else: !if(!rst_l) |
| 210 | end // always @ (posedge clk) |
| 211 | |
| 212 | //********************************************* |
| 213 | // fifo valid contents marker updates when enq |
| 214 | // or deq valid |
| 215 | //********************************************* |
| 216 | |
| 217 | always @ (rst_l or vld or enq or deq or vld_init) |
| 218 | begin |
| 219 | if (!rst_l) begin |
| 220 | next_vld = {DEPTH {1'b1}}; |
| 221 | end |
| 222 | else begin |
| 223 | case ({enq, deq}) // synopsys parallel_case |
| 224 | 2'b00: next_vld = vld; |
| 225 | 2'b01: next_vld = vld >> 1; |
| 226 | 2'b10: next_vld = {vld_init[DEPTH -1 :1] , 1'b1}; // to make vlint happy |
| 227 | 2'b11: next_vld = vld; |
| 228 | default : next_vld = vld; |
| 229 | endcase // case({enq, deq}) |
| 230 | end // else: !if(!rst_l) |
| 231 | end // always @ (vld or enq or deq or vld_init) |
| 232 | |
| 233 | //************************************************ |
| 234 | // srfifo registered internal ld, vld |
| 235 | //************************************************ |
| 236 | |
| 237 | always @ (posedge clk) |
| 238 | begin |
| 239 | if (!rst_l) begin |
| 240 | ld <= {1'b1,{(DEPTH){1'b0}}}; // to make vlint happy |
| 241 | vld <= {DEPTH {1'b1}}; |
| 242 | end |
| 243 | else begin |
| 244 | ld <= next_ld; |
| 245 | vld <= next_vld; |
| 246 | end // else: !if(!rst_l) |
| 247 | end // always @ (posedge clk) |
| 248 | |
| 249 | |
| 250 | //************************************************ |
| 251 | // Outputs |
| 252 | //************************************************ |
| 253 | |
| 254 | always @ (posedge clk) |
| 255 | begin |
| 256 | if (!rst_l) begin |
| 257 | empty <= 1'b0; |
| 258 | underflow <= 1'b0; |
| 259 | overflow <= 1'b0; |
| 260 | end |
| 261 | else begin |
| 262 | empty <= enq ? 1'b0 : ((deq == 1'b1) & (vld[1] == 1'b0)) ? 1'b1 : empty; |
| 263 | underflow <= ((vld[0] == 1'b0) |
| 264 | && (vld_init[0] == 1'b0) |
| 265 | && (deq == 1'b1)) ? 1'b1 : underflow; |
| 266 | overflow <= (((vld[DEPTH -1] == 1'b1) & enq) ? 1'b1 : overflow); |
| 267 | end |
| 268 | end |
| 269 | |
| 270 | //************************************************ |
| 271 | // If deq is active high data_out gets the next |
| 272 | // valid contents of sr[0] |
| 273 | //************************************************ |
| 274 | |
| 275 | assign full = vld[DEPTH -1]; |
| 276 | assign data_out = sr[0]; |
| 277 | |
| 278 | endmodule |
| 279 | |