| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_ilu_eil_relgen.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_ilu_eil_relgen ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | y2k_rel_rcd, |
| 39 | y2k_rel_enq, |
| 40 | rcd_is_pio_mwr, |
| 41 | rcd_is_cpl_reg, |
| 42 | pio_tag, |
| 43 | data_start, |
| 44 | data_done, |
| 45 | n_y2k_buf_addr_cl, |
| 46 | y2k_buf_addr, |
| 47 | |
| 48 | k2y_dou_dptr, |
| 49 | k2y_dou_err, |
| 50 | k2y_dou_vld, |
| 51 | dou_sbd_vld_datafsm, |
| 52 | dou_sbd_vld_rcdbldr, |
| 53 | dou_sbd_err_rcdbldr, |
| 54 | |
| 55 | // debug signal |
| 56 | cpl_cl_done); |
| 57 | |
| 58 | |
| 59 | // synopsys sync_set_reset "rst_l" |
| 60 | |
| 61 | |
| 62 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 63 | |
| 64 | //------------------------------------------------------------------------ |
| 65 | // Clock and Reset Signals |
| 66 | //------------------------------------------------------------------------ |
| 67 | input clk; // input clock |
| 68 | input rst_l; // input reset |
| 69 | |
| 70 | //------------------------------------------------------------------------ |
| 71 | // release interface to RMU |
| 72 | //------------------------------------------------------------------------ |
| 73 | output y2k_rel_enq; // enqueue for release rcd |
| 74 | output [8:0] y2k_rel_rcd; // release rcd |
| 75 | |
| 76 | //------------------------------------------------------------------------ |
| 77 | // DOU DMA Rd Cpl Buffer status rcd interface with CLU |
| 78 | //------------------------------------------------------------------------ |
| 79 | input [`FIRE_DLC_DOU_DPTR_WDTH-1:0] k2y_dou_dptr; |
| 80 | input k2y_dou_err; |
| 81 | input k2y_dou_vld; |
| 82 | |
| 83 | //------------------------------------------------------------------------ |
| 84 | // internal signals |
| 85 | //------------------------------------------------------------------------ |
| 86 | input rcd_is_pio_mwr; // rcd is PIO MWr, from *_rcdbldr.v |
| 87 | input rcd_is_cpl_reg; // rcd is cpl from rcdbldr |
| 88 | input [3:0] pio_tag; // from *_rcdbldr.v |
| 89 | input data_start; |
| 90 | input data_done; // from *_datafsm.v |
| 91 | input [6:2] n_y2k_buf_addr_cl; |
| 92 | input [6:0] y2k_buf_addr; // from *_datafsm.v |
| 93 | |
| 94 | output dou_sbd_vld_datafsm; // dou cl avairable to pull to datafsm |
| 95 | output dou_sbd_vld_rcdbldr; // dou cl avairable to rcdbldr |
| 96 | output dou_sbd_err_rcdbldr; // dou cl error to rcdbldr |
| 97 | |
| 98 | //--------------------------------------------------------------------- |
| 99 | // debug signals |
| 100 | //--------------------------------------------------------------------- |
| 101 | output cpl_cl_done; |
| 102 | |
| 103 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 104 | |
| 105 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 106 | |
| 107 | reg [8:0] y2k_rel_rcd; |
| 108 | reg y2k_rel_enq; |
| 109 | |
| 110 | reg [3:0] pio_tag_reg; |
| 111 | reg rcd_is_pio_mwr_reg; |
| 112 | reg data_done_reg; |
| 113 | |
| 114 | // scoreboard for dou dma rd cpl buffer status |
| 115 | reg [`FIRE_DLC_DOU_DPTR_DPTH-1:0] sbd_vld_array; |
| 116 | reg [`FIRE_DLC_DOU_DPTR_DPTH-1:0] sbd_err_array; |
| 117 | |
| 118 | reg [6:2] adv_y2k_buf_addr_cl; // advanced 1 from cacheline y2k_buf_addr |
| 119 | |
| 120 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 121 | |
| 122 | reg [`FIRE_DLC_DOU_DPTR_DPTH-1:0] sbd_vld_set; |
| 123 | reg [`FIRE_DLC_DOU_DPTR_DPTH-1:0] sbd_vld_clr; |
| 124 | |
| 125 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 126 | |
| 127 | wire [8:0] n_rel_rcd; |
| 128 | wire n_rel_enq; |
| 129 | wire cpl_cl_done; // when DOU read address over a cache line |
| 130 | |
| 131 | wire [`FIRE_DLC_DOU_DPTR_DPTH-1:0] n_sbd_vld_array; |
| 132 | wire [`FIRE_DLC_DOU_DPTR_WDTH-1:0] sbd_rd_entry_datafsm; |
| 133 | wire [`FIRE_DLC_DOU_DPTR_WDTH-1:0] sbd_rd_entry_rcdbldr; |
| 134 | |
| 135 | wire clr_sbd; |
| 136 | |
| 137 | wire [6:2] n_adv_y2k_buf_addr_cl; |
| 138 | |
| 139 | // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 140 | |
| 141 | /* 0in scoreboard -rx_id k2y_dou_dptr -rx k2y_dou_vld |
| 142 | -tx_id y2k_buf_addr[6:2] -tx clr_sbd |
| 143 | -max_ids 32 -max_count_per_id 1 */ |
| 144 | |
| 145 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 146 | |
| 147 | //------------------------------------------------------------------------ |
| 148 | // release records generation - |
| 149 | // need to release a cache line whenever y2k_buf_addr[2] flips when it's in |
| 150 | // the middle of processing a DMA CPL(D) rcd |
| 151 | //------------------------------------------------------------------------ |
| 152 | |
| 153 | assign cpl_cl_done = (y2k_buf_addr[2] ^ n_y2k_buf_addr_cl[2]) & (~data_start); |
| 154 | // N2- AT 12/17/04: assign n_rel_enq = (data_done_reg | cpl_cl_done) & (rcd_is_cpl_reg | rcd_is_pio_mwr_reg); |
| 155 | |
| 156 | // N2+ AT 12/17/04: The rel_enq signal is not generated properly in Fire. This |
| 157 | // was not an issue since in Fire, PIO Wr's are 64B. However, |
| 158 | // in N2, PIO Wr's are 8B only. |
| 159 | // According to Fire MAS (sec. 8.4.8, pg 935), logically, |
| 160 | // rel_enq = rls_pio_mwr | rls_dma_cpl |
| 161 | // = (data_done & rcd_is_pio_mwr) | |
| 162 | // ((data_done | y2k_buf_addr[2]_toggle) & rcd_is_cpl) |
| 163 | // The way it was coded above causes an errorneous assertion |
| 164 | // of rel_enq when (rls_is_pio_mwr & y2k_buf_addr[2]_toggle). |
| 165 | |
| 166 | assign n_rel_enq = ((data_done_reg | cpl_cl_done) & (rcd_is_cpl_reg)) | |
| 167 | (data_done_reg & rcd_is_pio_mwr_reg); |
| 168 | // END N2+ AT 12/17/04 |
| 169 | |
| 170 | assign n_rel_rcd = rcd_is_pio_mwr_reg ? {1'b0, 4'b0, pio_tag_reg[3:0]} : |
| 171 | {1'b1, 3'b0, y2k_buf_addr[6:2]}; |
| 172 | |
| 173 | always @ (posedge clk) |
| 174 | if (!rst_l) begin |
| 175 | y2k_rel_enq <= 1'b0; |
| 176 | end |
| 177 | else begin |
| 178 | y2k_rel_enq <= n_rel_enq; |
| 179 | end |
| 180 | |
| 181 | always @ (posedge clk) |
| 182 | if(~rst_l) begin |
| 183 | y2k_rel_rcd <= {9{1'b0}}; |
| 184 | data_done_reg <= {{1'b0}}; |
| 185 | rcd_is_pio_mwr_reg <= {{1'b0}}; |
| 186 | pio_tag_reg <= {{4'b0}}; |
| 187 | end |
| 188 | else begin |
| 189 | y2k_rel_rcd <= n_rel_rcd; |
| 190 | data_done_reg <= data_done; |
| 191 | rcd_is_pio_mwr_reg <= rcd_is_pio_mwr; |
| 192 | pio_tag_reg <= pio_tag; |
| 193 | end |
| 194 | |
| 195 | //------------------------------------------------------------------------ |
| 196 | // flop for advanced 1 cacheline address of y2k_buf_addr[6:2] |
| 197 | //------------------------------------------------------------------------ |
| 198 | assign n_adv_y2k_buf_addr_cl = n_y2k_buf_addr_cl + 1'b1; |
| 199 | always @ (posedge clk) |
| 200 | if(~rst_l) begin |
| 201 | adv_y2k_buf_addr_cl <= {5{1'b0}}; |
| 202 | end |
| 203 | else begin |
| 204 | adv_y2k_buf_addr_cl <= n_adv_y2k_buf_addr_cl; |
| 205 | end |
| 206 | |
| 207 | //------------------------------------------------------------------------ |
| 208 | // DOU dma rd cpl buffer status |
| 209 | //------------------------------------------------------------------------ |
| 210 | |
| 211 | // sbd err |
| 212 | always @ (posedge clk) |
| 213 | if(~rst_l) begin |
| 214 | sbd_err_array <= {`FIRE_DLC_DOU_DPTR_DPTH{1'b0}}; |
| 215 | end |
| 216 | else begin |
| 217 | if (k2y_dou_vld) sbd_err_array[k2y_dou_dptr] <= k2y_dou_err; |
| 218 | end |
| 219 | |
| 220 | // sbd vld |
| 221 | always @ (posedge clk) |
| 222 | if (!rst_l) begin |
| 223 | sbd_vld_array <= {`FIRE_DLC_DOU_DPTR_DPTH{1'b0}}; |
| 224 | end |
| 225 | else begin |
| 226 | sbd_vld_array <= n_sbd_vld_array; |
| 227 | end |
| 228 | |
| 229 | // sbd vld set array |
| 230 | always @ (k2y_dou_vld or k2y_dou_dptr) |
| 231 | begin |
| 232 | sbd_vld_set = {`FIRE_DLC_DOU_DPTR_DPTH{1'b0}}; |
| 233 | sbd_vld_set[k2y_dou_dptr] = k2y_dou_vld; |
| 234 | end |
| 235 | |
| 236 | // sbd vld clr array |
| 237 | assign clr_sbd = (~rcd_is_pio_mwr_reg) & n_rel_enq; |
| 238 | |
| 239 | always @ (clr_sbd or y2k_buf_addr[6:2]) |
| 240 | begin |
| 241 | sbd_vld_clr = {`FIRE_DLC_DOU_DPTR_DPTH{1'b0}}; |
| 242 | sbd_vld_clr[y2k_buf_addr[6:2]] = clr_sbd; |
| 243 | end |
| 244 | |
| 245 | |
| 246 | assign n_sbd_vld_array = (sbd_vld_array | sbd_vld_set) & (~sbd_vld_clr); |
| 247 | |
| 248 | // outputs |
| 249 | assign sbd_rd_entry_datafsm = (&y2k_buf_addr[1:0]) ? adv_y2k_buf_addr_cl : |
| 250 | y2k_buf_addr[6:2]; |
| 251 | |
| 252 | // for PIO MWr, data is in DOU no later than rcd is in ILU and the max. payld is a cacheline |
| 253 | // thus, mux out 1'b1 of dou_sbd_vld_datafsm for PIO MWr. |
| 254 | assign dou_sbd_vld_datafsm = rcd_is_pio_mwr ? 1'b1 : sbd_vld_array[sbd_rd_entry_datafsm]; |
| 255 | |
| 256 | |
| 257 | assign sbd_rd_entry_rcdbldr = n_y2k_buf_addr_cl[6:2]; |
| 258 | |
| 259 | assign dou_sbd_vld_rcdbldr = sbd_vld_array[sbd_rd_entry_rcdbldr]; |
| 260 | |
| 261 | assign dou_sbd_err_rcdbldr = sbd_err_array[sbd_rd_entry_rcdbldr]; |
| 262 | |
| 263 | endmodule // dmu_ilu_eil_relgen |
| 264 | |