| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_rds_mess_default_grp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_rds_mess_default_grp |
| 36 | ( |
| 37 | clk, |
| 38 | err_cor_mapping_v_hw_read, |
| 39 | err_cor_mapping_eqnum_hw_read, |
| 40 | err_cor_mapping_select_pulse, |
| 41 | err_nonfatal_mapping_v_hw_read, |
| 42 | err_nonfatal_mapping_eqnum_hw_read, |
| 43 | err_nonfatal_mapping_select_pulse, |
| 44 | err_fatal_mapping_v_hw_read, |
| 45 | err_fatal_mapping_eqnum_hw_read, |
| 46 | err_fatal_mapping_select_pulse, |
| 47 | pm_pme_mapping_v_hw_read, |
| 48 | pm_pme_mapping_eqnum_hw_read, |
| 49 | pm_pme_mapping_select_pulse, |
| 50 | pme_to_ack_mapping_v_hw_read, |
| 51 | pme_to_ack_mapping_eqnum_hw_read, |
| 52 | pme_to_ack_mapping_select_pulse, |
| 53 | rst_l, |
| 54 | daemon_csrbus_wr_in, |
| 55 | daemon_csrbus_wr_data_in, |
| 56 | read_data_0_out |
| 57 | ); |
| 58 | |
| 59 | //==================================================== |
| 60 | // Polarity declarations |
| 61 | //==================================================== |
| 62 | input clk; // Clock signal |
| 63 | output err_cor_mapping_v_hw_read; // This signal provides the current value of |
| 64 | // err_cor_mapping_v. |
| 65 | output [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_COR_MAPPING_EQNUM_INT_SLC] err_cor_mapping_eqnum_hw_read; |
| 66 | // This signal provides the current value of err_cor_mapping_eqnum. |
| 67 | input err_cor_mapping_select_pulse; // select |
| 68 | output err_nonfatal_mapping_v_hw_read; // This signal provides the current |
| 69 | // value of err_nonfatal_mapping_v. |
| 70 | output [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_NONFATAL_MAPPING_EQNUM_INT_SLC] err_nonfatal_mapping_eqnum_hw_read; |
| 71 | // This signal provides the current value of err_nonfatal_mapping_eqnum. |
| 72 | input err_nonfatal_mapping_select_pulse; // select |
| 73 | output err_fatal_mapping_v_hw_read; // This signal provides the current value |
| 74 | // of err_fatal_mapping_v. |
| 75 | output [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_FATAL_MAPPING_EQNUM_INT_SLC] err_fatal_mapping_eqnum_hw_read; |
| 76 | // This signal provides the current value of err_fatal_mapping_eqnum. |
| 77 | input err_fatal_mapping_select_pulse; // select |
| 78 | output pm_pme_mapping_v_hw_read; // This signal provides the current value of |
| 79 | // pm_pme_mapping_v. |
| 80 | output [`FIRE_DLC_IMU_RDS_MESS_CSR_PM_PME_MAPPING_EQNUM_INT_SLC] pm_pme_mapping_eqnum_hw_read; |
| 81 | // This signal provides the current value of pm_pme_mapping_eqnum. |
| 82 | input pm_pme_mapping_select_pulse; // select |
| 83 | output pme_to_ack_mapping_v_hw_read; // This signal provides the current value |
| 84 | // of pme_to_ack_mapping_v. |
| 85 | output [`FIRE_DLC_IMU_RDS_MESS_CSR_PME_TO_ACK_MAPPING_EQNUM_INT_SLC] pme_to_ack_mapping_eqnum_hw_read; |
| 86 | // This signal provides the current value of pme_to_ack_mapping_eqnum. |
| 87 | input pme_to_ack_mapping_select_pulse; // select |
| 88 | input rst_l; // HW reset |
| 89 | input daemon_csrbus_wr_in; // csrbus_wr |
| 90 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 91 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 92 | |
| 93 | //==================================================== |
| 94 | // Type declarations |
| 95 | //==================================================== |
| 96 | wire clk; // Clock signal |
| 97 | wire err_cor_mapping_v_hw_read; // This signal provides the current value of |
| 98 | // err_cor_mapping_v. |
| 99 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_COR_MAPPING_EQNUM_INT_SLC] err_cor_mapping_eqnum_hw_read; |
| 100 | // This signal provides the current value of err_cor_mapping_eqnum. |
| 101 | wire err_cor_mapping_select_pulse; // select |
| 102 | wire err_nonfatal_mapping_v_hw_read; // This signal provides the current value |
| 103 | // of err_nonfatal_mapping_v. |
| 104 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_NONFATAL_MAPPING_EQNUM_INT_SLC] err_nonfatal_mapping_eqnum_hw_read; |
| 105 | // This signal provides the current value of err_nonfatal_mapping_eqnum. |
| 106 | wire err_nonfatal_mapping_select_pulse; // select |
| 107 | wire err_fatal_mapping_v_hw_read; // This signal provides the current value of |
| 108 | // err_fatal_mapping_v. |
| 109 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_FATAL_MAPPING_EQNUM_INT_SLC] err_fatal_mapping_eqnum_hw_read; |
| 110 | // This signal provides the current value of err_fatal_mapping_eqnum. |
| 111 | wire err_fatal_mapping_select_pulse; // select |
| 112 | wire pm_pme_mapping_v_hw_read; // This signal provides the current value of |
| 113 | // pm_pme_mapping_v. |
| 114 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_PM_PME_MAPPING_EQNUM_INT_SLC] pm_pme_mapping_eqnum_hw_read; |
| 115 | // This signal provides the current value of pm_pme_mapping_eqnum. |
| 116 | wire pm_pme_mapping_select_pulse; // select |
| 117 | wire pme_to_ack_mapping_v_hw_read; // This signal provides the current value of |
| 118 | // pme_to_ack_mapping_v. |
| 119 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_PME_TO_ACK_MAPPING_EQNUM_INT_SLC] pme_to_ack_mapping_eqnum_hw_read; |
| 120 | // This signal provides the current value of pme_to_ack_mapping_eqnum. |
| 121 | wire pme_to_ack_mapping_select_pulse; // select |
| 122 | wire rst_l; // HW reset |
| 123 | wire daemon_csrbus_wr_in; // csrbus_wr |
| 124 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data |
| 125 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data |
| 126 | |
| 127 | |
| 128 | //==================================================== |
| 129 | // Local signals |
| 130 | //==================================================== |
| 131 | //----- For CSR register: err_cor_mapping |
| 132 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_COR_MAPPING_WIDTH-1:0] err_cor_mapping_csrbus_read_data; |
| 133 | // Entry Based Read Data |
| 134 | |
| 135 | //----- For CSR register: err_nonfatal_mapping |
| 136 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_NONFATAL_MAPPING_WIDTH-1:0] err_nonfatal_mapping_csrbus_read_data; |
| 137 | // Entry Based Read Data |
| 138 | |
| 139 | //----- For CSR register: err_fatal_mapping |
| 140 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_ERR_FATAL_MAPPING_WIDTH-1:0] err_fatal_mapping_csrbus_read_data; |
| 141 | // Entry Based Read Data |
| 142 | |
| 143 | //----- For CSR register: pm_pme_mapping |
| 144 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_PM_PME_MAPPING_WIDTH-1:0] pm_pme_mapping_csrbus_read_data; |
| 145 | // Entry Based Read Data |
| 146 | |
| 147 | //----- For CSR register: pme_to_ack_mapping |
| 148 | wire [`FIRE_DLC_IMU_RDS_MESS_CSR_PME_TO_ACK_MAPPING_WIDTH-1:0] pme_to_ack_mapping_csrbus_read_data; |
| 149 | // Entry Based Read Data |
| 150 | |
| 151 | //==================================================== |
| 152 | // Assignments only (first stage) |
| 153 | //==================================================== |
| 154 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data = daemon_csrbus_wr_data_in; |
| 155 | wire daemon_csrbus_wr = daemon_csrbus_wr_in; |
| 156 | |
| 157 | //==================================================== |
| 158 | // Automatic hw_ld / hw_write |
| 159 | //==================================================== |
| 160 | |
| 161 | //==================================================== |
| 162 | // Extern select |
| 163 | //==================================================== |
| 164 | |
| 165 | //===================================================== |
| 166 | // OUTPUT: read_data_out |
| 167 | //===================================================== |
| 168 | dmu_imu_rds_mess_csrpipe_6 dmu_imu_rds_mess_csrpipe_6_inst_1 |
| 169 | ( |
| 170 | .clk (clk), |
| 171 | .rst_l (rst_l), |
| 172 | .reg_in (1'b1), |
| 173 | .reg_out (1'b1), |
| 174 | .data0 (err_cor_mapping_csrbus_read_data), |
| 175 | .sel0 (err_cor_mapping_select_pulse), |
| 176 | .data1 (err_nonfatal_mapping_csrbus_read_data), |
| 177 | .sel1 (err_nonfatal_mapping_select_pulse), |
| 178 | .data2 (err_fatal_mapping_csrbus_read_data), |
| 179 | .sel2 (err_fatal_mapping_select_pulse), |
| 180 | .data3 (pm_pme_mapping_csrbus_read_data), |
| 181 | .sel3 (pm_pme_mapping_select_pulse), |
| 182 | .data4 (pme_to_ack_mapping_csrbus_read_data), |
| 183 | .sel4 (pme_to_ack_mapping_select_pulse), |
| 184 | .data5 (64'b0), |
| 185 | .sel5 (1'b1), |
| 186 | .out (read_data_0_out) |
| 187 | ); |
| 188 | |
| 189 | |
| 190 | //==================================================== |
| 191 | // Instantiation of registers |
| 192 | //==================================================== |
| 193 | |
| 194 | wire err_cor_mapping_w_ld =err_cor_mapping_select_pulse & daemon_csrbus_wr; |
| 195 | |
| 196 | dmu_imu_rds_mess_csr_err_cor_mapping err_cor_mapping |
| 197 | ( |
| 198 | .clk (clk), |
| 199 | .rst_l (rst_l), |
| 200 | .err_cor_mapping_w_ld (err_cor_mapping_w_ld), |
| 201 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 202 | .err_cor_mapping_csrbus_read_data (err_cor_mapping_csrbus_read_data), |
| 203 | .err_cor_mapping_v_hw_read (err_cor_mapping_v_hw_read), |
| 204 | .err_cor_mapping_eqnum_hw_read (err_cor_mapping_eqnum_hw_read) |
| 205 | ); |
| 206 | |
| 207 | wire err_nonfatal_mapping_w_ld =err_nonfatal_mapping_select_pulse & daemon_csrbus_wr; |
| 208 | |
| 209 | dmu_imu_rds_mess_csr_err_nonfatal_mapping err_nonfatal_mapping |
| 210 | ( |
| 211 | .clk (clk), |
| 212 | .rst_l (rst_l), |
| 213 | .err_nonfatal_mapping_w_ld (err_nonfatal_mapping_w_ld), |
| 214 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 215 | .err_nonfatal_mapping_csrbus_read_data (err_nonfatal_mapping_csrbus_read_data), |
| 216 | .err_nonfatal_mapping_v_hw_read (err_nonfatal_mapping_v_hw_read), |
| 217 | .err_nonfatal_mapping_eqnum_hw_read (err_nonfatal_mapping_eqnum_hw_read) |
| 218 | ); |
| 219 | |
| 220 | wire err_fatal_mapping_w_ld =err_fatal_mapping_select_pulse & daemon_csrbus_wr; |
| 221 | |
| 222 | dmu_imu_rds_mess_csr_err_fatal_mapping err_fatal_mapping |
| 223 | ( |
| 224 | .clk (clk), |
| 225 | .rst_l (rst_l), |
| 226 | .err_fatal_mapping_w_ld (err_fatal_mapping_w_ld), |
| 227 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 228 | .err_fatal_mapping_csrbus_read_data (err_fatal_mapping_csrbus_read_data), |
| 229 | .err_fatal_mapping_v_hw_read (err_fatal_mapping_v_hw_read), |
| 230 | .err_fatal_mapping_eqnum_hw_read (err_fatal_mapping_eqnum_hw_read) |
| 231 | ); |
| 232 | |
| 233 | wire pm_pme_mapping_w_ld =pm_pme_mapping_select_pulse & daemon_csrbus_wr; |
| 234 | |
| 235 | dmu_imu_rds_mess_csr_pm_pme_mapping pm_pme_mapping |
| 236 | ( |
| 237 | .clk (clk), |
| 238 | .rst_l (rst_l), |
| 239 | .pm_pme_mapping_w_ld (pm_pme_mapping_w_ld), |
| 240 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 241 | .pm_pme_mapping_csrbus_read_data (pm_pme_mapping_csrbus_read_data), |
| 242 | .pm_pme_mapping_v_hw_read (pm_pme_mapping_v_hw_read), |
| 243 | .pm_pme_mapping_eqnum_hw_read (pm_pme_mapping_eqnum_hw_read) |
| 244 | ); |
| 245 | |
| 246 | wire pme_to_ack_mapping_w_ld =pme_to_ack_mapping_select_pulse & daemon_csrbus_wr; |
| 247 | |
| 248 | dmu_imu_rds_mess_csr_pme_to_ack_mapping pme_to_ack_mapping |
| 249 | ( |
| 250 | .clk (clk), |
| 251 | .rst_l (rst_l), |
| 252 | .pme_to_ack_mapping_w_ld (pme_to_ack_mapping_w_ld), |
| 253 | .csrbus_wr_data (daemon_csrbus_wr_data), |
| 254 | .pme_to_ack_mapping_csrbus_read_data (pme_to_ack_mapping_csrbus_read_data), |
| 255 | .pme_to_ack_mapping_v_hw_read (pme_to_ack_mapping_v_hw_read), |
| 256 | .pme_to_ack_mapping_eqnum_hw_read (pme_to_ack_mapping_eqnum_hw_read) |
| 257 | ); |
| 258 | |
| 259 | endmodule // dmu_imu_rds_mess_default_grp |