| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_srq.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_srq |
| 36 | ( |
| 37 | clk, // clock |
| 38 | rst_l, // rst_l |
| 39 | ld, // load |
| 40 | ds, // data select |
| 41 | di, // data in |
| 42 | do // data out |
| 43 | ); |
| 44 | |
| 45 | // ---------------------------------------------------------------------------- |
| 46 | // Parameters |
| 47 | // ---------------------------------------------------------------------------- |
| 48 | parameter QD = 4, // queue depth |
| 49 | QW = 2; // queue width |
| 50 | |
| 51 | // ---------------------------------------------------------------------------- |
| 52 | // Ports |
| 53 | // ---------------------------------------------------------------------------- |
| 54 | input clk; |
| 55 | input rst_l; |
| 56 | |
| 57 | input [QD-1:0] ld; |
| 58 | input [QD-2:0] ds; |
| 59 | |
| 60 | input [QW-1:0] di; |
| 61 | output [QW-1:0] do; |
| 62 | |
| 63 | // ---------------------------------------------------------------------------- |
| 64 | // Variables |
| 65 | // ---------------------------------------------------------------------------- |
| 66 | wire [QW-1:0] do; |
| 67 | reg [QW-1:0] que [0:QD-1]; |
| 68 | |
| 69 | integer i; |
| 70 | |
| 71 | // ---------------------------------------------------------------------------- |
| 72 | // Combinational |
| 73 | // ---------------------------------------------------------------------------- |
| 74 | assign do = que[0]; |
| 75 | |
| 76 | // ---------------------------------------------------------------------------- |
| 77 | // Sequential |
| 78 | // ---------------------------------------------------------------------------- |
| 79 | always @ (posedge clk) |
| 80 | if(~rst_l) begin : que_rst |
| 81 | integer j; |
| 82 | for (j = 0; j < QD; j = j + 1) begin |
| 83 | que[j] <= {QW{1'b0}}; |
| 84 | end |
| 85 | end |
| 86 | else begin |
| 87 | for (i = 0; i < QD-1; i = i + 1) begin |
| 88 | if (ld[i]) que[i] <= ds[i] ? que[i+1] : di; |
| 89 | end |
| 90 | if (ld[QD-1]) que[QD-1] <= di; |
| 91 | end |
| 92 | |
| 93 | endmodule // dmu_mmu_srq |