| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_tmu.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_tmu ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | // tmu -> peu rams |
| 39 | d2p_idb_rd, |
| 40 | |
| 41 | // ilu <-> dmu-tmu |
| 42 | y2k_rcd, |
| 43 | y2k_rcd_enq, |
| 44 | k2y_rcd_deq, |
| 45 | k2y_rel_rcd, |
| 46 | k2y_rel_enq, |
| 47 | |
| 48 | // data path |
| 49 | y2k_buf_addr_vld_monitor, |
| 50 | k2y_buf_addr_vld_monitor, |
| 51 | k2y_buf_addr, |
| 52 | y2k_buf_data, |
| 53 | y2k_buf_dpar, |
| 54 | |
| 55 | // DIU interface |
| 56 | tm2di_wr, |
| 57 | tm2di_addr, |
| 58 | tm2di_data, |
| 59 | tm2di_bmask, |
| 60 | tm2di_dpar, |
| 61 | |
| 62 | // CLU buf rel interface |
| 63 | cl2tm_dma_rptr, |
| 64 | cl2tm_int_rptr, |
| 65 | tm2cl_dma_wptr, |
| 66 | tm2cl_pio_wptr, |
| 67 | |
| 68 | // RMU interface |
| 69 | tm2rm_rcd, |
| 70 | tm2rm_rcd_enq, |
| 71 | rm2tm_rcd_full, |
| 72 | |
| 73 | // IMU interface |
| 74 | tm2im_data_enq, |
| 75 | tm2im_data, |
| 76 | im2tm_msi32_addr_reg, |
| 77 | im2tm_msi64_addr_reg, |
| 78 | |
| 79 | // CRU (debug) interface |
| 80 | cr2tm_dbg_sel_a, |
| 81 | cr2tm_dbg_sel_b, |
| 82 | tm2cr_dbg_a, |
| 83 | tm2cr_dbg_b, |
| 84 | csr_sun4v_en, |
| 85 | im2tm_eqs_adr_63, |
| 86 | |
| 87 | ); |
| 88 | |
| 89 | //synopsys sync_set_reset "rst_l" |
| 90 | |
| 91 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 92 | |
| 93 | //------------------------------------------------------------------------ |
| 94 | // Clock and Reset Signals |
| 95 | //------------------------------------------------------------------------ |
| 96 | input clk; |
| 97 | input rst_l; |
| 98 | |
| 99 | //------------------------------------------------------------------------ |
| 100 | // rd enable to idb ram for circuit issues |
| 101 | //------------------------------------------------------------------------ |
| 102 | output d2p_idb_rd; |
| 103 | //------------------------------------------------------------------------ |
| 104 | // data path to ILU |
| 105 | //------------------------------------------------------------------------ |
| 106 | input y2k_buf_addr_vld_monitor; |
| 107 | output k2y_buf_addr_vld_monitor; |
| 108 | output [`FIRE_DLC_ITI_ADDR_WDTH-1:0] k2y_buf_addr; // read pointer to IDB |
| 109 | input [`FIRE_DLC_ITI_DATA_WDTH-1:0] y2k_buf_data; // 16-byte data |
| 110 | input [`FIRE_DLC_ITI_DPAR_WDTH-1:0] y2k_buf_dpar; // data parity |
| 111 | |
| 112 | //------------------------------------------------------------------------ |
| 113 | // record interface to ILU |
| 114 | //------------------------------------------------------------------------ |
| 115 | output k2y_rcd_deq; // ingress record fifo full |
| 116 | input [`FIRE_DLC_IPE_REC_WDTH-1:0] y2k_rcd; // ingress PEC record |
| 117 | input y2k_rcd_enq; // ingress PEC record enqueue |
| 118 | |
| 119 | //------------------------------------------------------------------------ |
| 120 | // release interface with ILU |
| 121 | //------------------------------------------------------------------------ |
| 122 | output [`FIRE_DLC_URR_REC_WDTH-1:0] k2y_rel_rcd; // ingress release rcd |
| 123 | output k2y_rel_enq; // ingress enqueue |
| 124 | |
| 125 | //------------------------------------------------------------------------ |
| 126 | // DIU interface |
| 127 | //------------------------------------------------------------------------ |
| 128 | output tm2di_wr; // write |
| 129 | output [`FIRE_DLC_TRD_ADDR_WDTH-1:0] tm2di_addr; // DIU address |
| 130 | output [`FIRE_DLC_TRD_DATA_WDTH-1:0] tm2di_data; // data to DIU |
| 131 | output [`FIRE_DLC_TRD_BMASK_WDTH-1:0] tm2di_bmask; // byte mask |
| 132 | output [`FIRE_DLC_TRD_DPAR_WDTH-1:0] tm2di_dpar; // data parity |
| 133 | |
| 134 | //------------------------------------------------------------------------ |
| 135 | // CLU buf rel interface |
| 136 | //------------------------------------------------------------------------ |
| 137 | input [`FIRE_DLC_DMA_RPTR_WDTH-1:0] cl2tm_dma_rptr; |
| 138 | input [`FIRE_DLC_INT_RPTR_WDTH-1:0] cl2tm_int_rptr; |
| 139 | output [`FIRE_DLC_DMA_WPTR_WDTH-1:0] tm2cl_dma_wptr; |
| 140 | output [`FIRE_DLC_PIO_WPTR_WDTH-1:0] tm2cl_pio_wptr; |
| 141 | |
| 142 | //------------------------------------------------------------------------ |
| 143 | // RMU interface |
| 144 | //------------------------------------------------------------------------ |
| 145 | output [`FIRE_DLC_DIM_REC_WDTH-1:0] tm2rm_rcd; // ingress |
| 146 | output tm2rm_rcd_enq; // ingress |
| 147 | input rm2tm_rcd_full; // ingress |
| 148 | |
| 149 | //------------------------------------------------------------------------ |
| 150 | // IMU interface |
| 151 | //------------------------------------------------------------------------ |
| 152 | output tm2im_data_enq; // ingress |
| 153 | output [`FIRE_DLC_MDF_REC_WDTH-1:0] tm2im_data; // ingress |
| 154 | input [`FIRE_DLC_SCW_MSI32_WDTH-1:0] im2tm_msi32_addr_reg; |
| 155 | input [`FIRE_DLC_SCW_MSI64_WDTH-1:0] im2tm_msi64_addr_reg; |
| 156 | |
| 157 | //------------------------------------------------------------------------ |
| 158 | // CRU (debug) interface |
| 159 | //------------------------------------------------------------------------ |
| 160 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2tm_dbg_sel_a; |
| 161 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2tm_dbg_sel_b; |
| 162 | output [`FIRE_DBG_DATA_BITS] tm2cr_dbg_a; |
| 163 | output [`FIRE_DBG_DATA_BITS] tm2cr_dbg_b; |
| 164 | |
| 165 | // use these 2 signals to disable bit addr 63 compare if sun4v and eq bit 63 is 1 |
| 166 | //------------------------------------------------------------------------ |
| 167 | input csr_sun4v_en; // for msi64 compare |
| 168 | input im2tm_eqs_adr_63; // for msi64 compare |
| 169 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 170 | |
| 171 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 172 | reg tmu_is_idle; |
| 173 | |
| 174 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 175 | wire dim_is_idle; |
| 176 | |
| 177 | // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 178 | |
| 179 | // 0in known_driven -var y2k_rcd_enq |
| 180 | // 0in known_driven -var k2y_rcd_deq |
| 181 | // 0in known_driven -var k2y_rel_enq |
| 182 | // 0in known_driven -var tm2rm_rcd_enq |
| 183 | // 0in known_driven -var rm2tm_rcd_full |
| 184 | // 0in known -var k2y_buf_addr |
| 185 | // 0in known_driven -var tm2di_wr |
| 186 | // 0in known_driven -var tm2im_data_enq |
| 187 | // 0in known -var im2tm_msi32_addr_reg |
| 188 | // 0in known -var im2tm_msi64_addr_reg |
| 189 | |
| 190 | |
| 191 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 192 | |
| 193 | //--------------------------------------------------------------------- |
| 194 | // idle check |
| 195 | //--------------------------------------------------------------------- |
| 196 | //BP N2 no reset, should be 1 at rst_l, ie idle |
| 197 | always @ (posedge clk) begin |
| 198 | tmu_is_idle <= dim_is_idle; |
| 199 | end |
| 200 | //BP temp 4-1-05 |
| 201 | //assign d2p_idb_rd = 1'b1; |
| 202 | |
| 203 | // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 204 | |
| 205 | // DIM sub-block |
| 206 | dmu_tmu_dim dim ( |
| 207 | .clk (clk), |
| 208 | .rst_l (rst_l), |
| 209 | |
| 210 | // ilu -> peu-idb BP n2 5-06-05 rd enable to peu idb ram |
| 211 | .d2p_idb_rd (d2p_idb_rd), |
| 212 | // ilu <-> dmu-tmu |
| 213 | .y2k_rcd (y2k_rcd), |
| 214 | .y2k_rcd_enq (y2k_rcd_enq), |
| 215 | .k2y_rcd_deq (k2y_rcd_deq), |
| 216 | .k2y_rel_rcd (k2y_rel_rcd), |
| 217 | .k2y_rel_enq (k2y_rel_enq), |
| 218 | |
| 219 | // data path |
| 220 | .y2k_buf_addr_vld_monitor (y2k_buf_addr_vld_monitor), |
| 221 | .k2y_buf_addr_vld_monitor (k2y_buf_addr_vld_monitor), |
| 222 | .k2y_buf_addr (k2y_buf_addr), |
| 223 | .y2k_buf_data (y2k_buf_data), |
| 224 | .y2k_buf_dpar (y2k_buf_dpar), |
| 225 | |
| 226 | // DIU interface |
| 227 | .tm2di_wr (tm2di_wr), |
| 228 | .tm2di_addr (tm2di_addr), |
| 229 | .tm2di_data (tm2di_data), |
| 230 | .tm2di_bmask (tm2di_bmask), |
| 231 | .tm2di_dpar (tm2di_dpar), |
| 232 | |
| 233 | // CLU buf rel interface |
| 234 | .cl2tm_dma_rptr (cl2tm_dma_rptr), |
| 235 | .cl2tm_int_rptr (cl2tm_int_rptr), |
| 236 | .tm2cl_dma_wptr (tm2cl_dma_wptr), |
| 237 | .tm2cl_pio_wptr (tm2cl_pio_wptr), |
| 238 | |
| 239 | // RMU interface |
| 240 | .tm2rm_rcd (tm2rm_rcd), |
| 241 | .tm2rm_rcd_enq (tm2rm_rcd_enq), |
| 242 | .rm2tm_rcd_full (rm2tm_rcd_full), |
| 243 | |
| 244 | // IMU interface |
| 245 | .tm2im_data_enq (tm2im_data_enq), |
| 246 | .tm2im_data (tm2im_data), |
| 247 | |
| 248 | // static CSR interface from IMU |
| 249 | .im2tm_msi32_addr_reg (im2tm_msi32_addr_reg), |
| 250 | .im2tm_msi64_addr_reg (im2tm_msi64_addr_reg), |
| 251 | |
| 252 | .cr2tm_dbg_sel_a (cr2tm_dbg_sel_a), |
| 253 | .cr2tm_dbg_sel_b (cr2tm_dbg_sel_b), |
| 254 | .tm2cr_dbg_a (tm2cr_dbg_a), |
| 255 | .tm2cr_dbg_b (tm2cr_dbg_b), |
| 256 | .dim_is_idle (dim_is_idle), |
| 257 | .tmu_is_idle (tmu_is_idle), |
| 258 | .csr_sun4v_en (csr_sun4v_en), |
| 259 | .im2tm_eqs_adr_63 (im2tm_eqs_adr_63) |
| 260 | ); |
| 261 | |
| 262 | |
| 263 | endmodule // dmu_tmu |
| 264 | |
| 265 | |
| 266 | |
| 267 | |