| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: efu_fct_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define RD_CNT_START 9'd20 |
| 36 | `define ASHIFT_CNT_START {(7'd09),2'b11} |
| 37 | `define DSHIFT_CNT_START {(7'd12),2'b11} |
| 38 | `define RSLTSHIFT_CNT_START {(7'd63),2'b11} |
| 39 | `define RECOVER_CNT_START 9'd10 |
| 40 | |
| 41 | `define MSEQ_IDLE 4'b0000 // 4'h0 |
| 42 | `define MSEQ_DUMP 4'b1001 // 4'h9 |
| 43 | `define MSEQ_RSLTSHFT 4'b1011 // 4'ha |
| 44 | `define MSEQ_SGLRD 4'b1010 // 4'hb |
| 45 | `define MSEQ_BYPASS 4'b1100 // 4'hc |
| 46 | `define MSEQ_DEST_SMPL 4'b1101 // 4'hd |
| 47 | `define MSEQ_L2RR_SMPL 4'b1110 // 4'he |
| 48 | `define MSEQ_SHIFT 4'b1111 // 4'hf |
| 49 | `define MRD_IDLE 3'b000 // 3'b0 |
| 50 | `define MRD_RD_ARRAY 3'b100 // 3'b4 |
| 51 | //`define MRD_ASHIFT 3'b001 // 3'b1 |
| 52 | `define MRD_XFER 3'b001 // 3'b1 |
| 53 | `define MRD_DSHIFT 3'b011 // 3'b3 |
| 54 | `define MRD_RECOVER 3'b010 // 3'b2 |
| 55 | |
| 56 | |
| 57 | |
| 58 | module efu_fct_ctl ( |
| 59 | tcu_efu_updatedr, |
| 60 | tcu_efu_read_en, |
| 61 | tcu_efu_read_start, |
| 62 | tcu_efu_fuse_bypass, |
| 63 | tcu_efu_dest_sample, |
| 64 | tcu_efu_coladdr, |
| 65 | tcu_efu_read_mode, |
| 66 | tcu_efu_rowaddr, |
| 67 | tcu_efu_capturedr, |
| 68 | tcu_efu_data_in, |
| 69 | tcu_efu_shiftdr, |
| 70 | efa_sbc_data, |
| 71 | tck, |
| 72 | cmp_io_sync_en, |
| 73 | sbc_efa_power_down, |
| 74 | efu_tcu_data_out, |
| 75 | sync1_rowaddress, |
| 76 | sbc_efa_bit_addr, |
| 77 | sbc_efa_sup_det_rd, |
| 78 | sbc_efa_margin0_rd, |
| 79 | sbc_efa_margin1_rd, |
| 80 | sbc_efa_read_en, |
| 81 | sbc_efa_word_addr, |
| 82 | shift_data_ff_out, |
| 83 | load_l2_read_data, |
| 84 | read_data_ff, |
| 85 | read_data_ff_vld, |
| 86 | update_dr_jbus, |
| 87 | local_read_en, |
| 88 | local_efu_read_start, |
| 89 | local_fuse_bypass, |
| 90 | local_dest_sample, |
| 91 | cmp_mrd_cnt_done, |
| 92 | decode_enable_vld, |
| 93 | iol2clk, |
| 94 | l2clk, |
| 95 | jbus_arst_l, |
| 96 | por_l, |
| 97 | snc1_rowaddr, |
| 98 | efu_ncu_fuse_data, |
| 99 | efu_ncu_srlnum0_xfer_en, |
| 100 | efu_ncu_srlnum1_xfer_en, |
| 101 | efu_ncu_srlnum2_xfer_en, |
| 102 | efu_ncu_fusestat_xfer_en, |
| 103 | efu_ncu_coreavl_xfer_en, |
| 104 | efu_ncu_bankavl_xfer_en, |
| 105 | niu_read_data_shift, |
| 106 | load_niu_read_data, |
| 107 | pwr_ok, |
| 108 | por_n, |
| 109 | tcu_pce_ov, |
| 110 | tcu_aclk, |
| 111 | tcu_bclk, |
| 112 | tcu_scan_en, |
| 113 | scan_in, |
| 114 | scan_out); |
| 115 | wire pce_ov; |
| 116 | wire siclk; |
| 117 | wire soclk; |
| 118 | wire stop; |
| 119 | wire se; |
| 120 | wire read_data_ff_vld_d; |
| 121 | wire seq_state_bypass; |
| 122 | wire mrd_state_xfer; |
| 123 | wire read_data_ff_vld_r1; |
| 124 | wire l1clk; |
| 125 | wire l1clk_cmp; |
| 126 | wire tckl1clk; |
| 127 | wire ff_pulse_read_data_ff_vld_scanin; |
| 128 | wire ff_pulse_read_data_ff_vld_scanout; |
| 129 | wire enable_efa_por_reg_scanin; |
| 130 | wire enable_efa_por_reg_scanout; |
| 131 | wire efa_array_power_down_reg_scanin; |
| 132 | wire efa_array_power_down_reg_scanout; |
| 133 | wire seq_state_reg_scanin; |
| 134 | wire seq_state_reg_scanout; |
| 135 | wire [6:0] addr_cnt_ff; |
| 136 | wire addr_cnt_reg_scanin; |
| 137 | wire addr_cnt_reg_scanout; |
| 138 | wire mrd_state_ashift; |
| 139 | wire mrd_state_dshift; |
| 140 | wire mrd_state_shift; |
| 141 | wire mrd_state_reg_scanin; |
| 142 | wire mrd_state_reg_scanout; |
| 143 | wire mrd_cnt_dec1_true_value; |
| 144 | wire serdes; |
| 145 | wire mrd_cnt_63; |
| 146 | wire ff_mrd_zero_scanin; |
| 147 | wire ff_mrd_zero_scanout; |
| 148 | wire mrd_63_to_0_ff_scanin; |
| 149 | wire mrd_63_to_0_ff_scanout; |
| 150 | wire mrd_63_to_0; |
| 151 | wire mrd_cnt_reg_scanin; |
| 152 | wire mrd_cnt_reg_scanout; |
| 153 | wire [31:0] efa_out_data; |
| 154 | wire [31:0] tck_shft_data_ff; |
| 155 | wire read_data_reg_scanin; |
| 156 | wire read_data_reg_scanout; |
| 157 | wire l2rd_id_reg_scanin; |
| 158 | wire l2rd_id_reg_scanout; |
| 159 | wire rslt_status_reg_scanin; |
| 160 | wire rslt_status_reg_scanout; |
| 161 | wire local_fuse_data_reg_scanin; |
| 162 | wire local_fuse_data_reg_scanout; |
| 163 | wire ncu_bankavail_dec; |
| 164 | wire l2d_fuse_dec; |
| 165 | wire ncu_coreavail_dshift_reg_scanin; |
| 166 | wire ncu_coreavail_dshift_reg_scanout; |
| 167 | wire ncu_bankavail_dshift_reg_scanin; |
| 168 | wire ncu_bankavail_dshift_reg_scanout; |
| 169 | wire ncu_sernum0_dshift_reg_scanin; |
| 170 | wire ncu_sernum0_dshift_reg_scanout; |
| 171 | wire ncu_sernum1_dshift_reg_scanin; |
| 172 | wire ncu_sernum1_dshift_reg_scanout; |
| 173 | wire ncu_sernum2_dshift_reg_scanin; |
| 174 | wire ncu_sernum2_dshift_reg_scanout; |
| 175 | wire ncu_fusestat_dshift_reg_scanin; |
| 176 | wire ncu_fusestat_dshift_reg_scanout; |
| 177 | wire ff_updtdr_slice_scanin; |
| 178 | wire ff_updtdr_slice_scanout; |
| 179 | wire updtdr_sync1; |
| 180 | wire ff_updtdr_slice1_scanin; |
| 181 | wire ff_updtdr_slice1_scanout; |
| 182 | wire updtdr_sync2; |
| 183 | wire ff_updtdr_slice2_scanin; |
| 184 | wire ff_updtdr_slice2_scanout; |
| 185 | wire ff_read_en_slice_scanin; |
| 186 | wire ff_read_en_slice_scanout; |
| 187 | wire read_en_sync1; |
| 188 | wire ff_read_en_slice1_scanin; |
| 189 | wire ff_read_en_slice1_scanout; |
| 190 | wire read_en_sync2; |
| 191 | wire ff_read_en_slice2_scanin; |
| 192 | wire ff_read_en_slice2_scanout; |
| 193 | wire read_en_hist_ff; |
| 194 | wire ff_read_start_0_slice_scanin; |
| 195 | wire ff_read_start_0_slice_scanout; |
| 196 | wire read_start_hist_ff; |
| 197 | wire read_start_sync2; |
| 198 | wire ff_read_start_1_slice_scanin; |
| 199 | wire ff_read_start_1_slice_scanout; |
| 200 | wire cmp_io_sync_en_r1; |
| 201 | wire ff_cmp_io_sync_en_scanin; |
| 202 | wire ff_cmp_io_sync_en_scanout; |
| 203 | wire ff_fuse_bypass_slice_scanin; |
| 204 | wire ff_fuse_bypass_slice_scanout; |
| 205 | wire fuse_bypass_sync1; |
| 206 | wire ff_fuse_bypass_slice_1_scanin; |
| 207 | wire ff_fuse_bypass_slice_1_scanout; |
| 208 | wire fuse_bypass_sync2; |
| 209 | wire ff_fuse_bypass_slice_2_scanin; |
| 210 | wire ff_fuse_bypass_slice_2_scanout; |
| 211 | wire fuse_bypass_hist_ff; |
| 212 | wire ff_dest_sample_slice_scanin; |
| 213 | wire ff_dest_sample_slice_scanout; |
| 214 | wire dest_sample_sync1; |
| 215 | wire ff_dest_sample_slice_1_scanin; |
| 216 | wire ff_dest_sample_slice_1_scanout; |
| 217 | wire dest_sample_sync2; |
| 218 | wire ff_dest_sample_slice_2_scanin; |
| 219 | wire ff_dest_sample_slice_2_scanout; |
| 220 | wire dest_sample_hist_ff; |
| 221 | wire [31:0] w_mux_shift_retain; |
| 222 | wire ff_tck_shift_data_nxt_scanin; |
| 223 | wire ff_tck_shift_data_nxt_scanout; |
| 224 | wire ff_sync1_rowaddr_6_1_scanin; |
| 225 | wire ff_sync1_rowaddr_6_1_scanout; |
| 226 | wire sync_tcu_efu_rowaddr6; |
| 227 | wire tcu_efu_rowaddr6_1; |
| 228 | wire ff_sync1_rowaddr_5_1_scanin; |
| 229 | wire ff_sync1_rowaddr_5_1_scanout; |
| 230 | wire sync_tcu_efu_rowaddr5; |
| 231 | wire tcu_efu_rowaddr5_1; |
| 232 | wire ff_sync1_rowaddr_4_1_scanin; |
| 233 | wire ff_sync1_rowaddr_4_1_scanout; |
| 234 | wire sync_tcu_efu_rowaddr4; |
| 235 | wire tcu_efu_rowaddr4_1; |
| 236 | wire ff_sync1_rowaddr_3_1_scanin; |
| 237 | wire ff_sync1_rowaddr_3_1_scanout; |
| 238 | wire sync_tcu_efu_rowaddr3; |
| 239 | wire tcu_efu_rowaddr3_1; |
| 240 | wire ff_sync1_rowaddr_2_1_scanin; |
| 241 | wire ff_sync1_rowaddr_2_1_scanout; |
| 242 | wire sync_tcu_efu_rowaddr2; |
| 243 | wire tcu_efu_rowaddr2_1; |
| 244 | wire ff_sync1_rowaddr_1_1_scanin; |
| 245 | wire ff_sync1_rowaddr_1_1_scanout; |
| 246 | wire sync_tcu_efu_rowaddr1; |
| 247 | wire tcu_efu_rowaddr1_1; |
| 248 | wire ff_sync1_rowaddr_0_1_scanin; |
| 249 | wire ff_sync1_rowaddr_0_1_scanout; |
| 250 | wire sync_tcu_efu_rowaddr0; |
| 251 | wire tcu_efu_rowaddr0_1; |
| 252 | wire ff_sync1_rowaddr_6_scanin; |
| 253 | wire ff_sync1_rowaddr_6_scanout; |
| 254 | wire ff_sync1_rowaddr_5_scanin; |
| 255 | wire ff_sync1_rowaddr_5_scanout; |
| 256 | wire ff_sync1_rowaddr_4_scanin; |
| 257 | wire ff_sync1_rowaddr_4_scanout; |
| 258 | wire ff_sync1_rowaddr_3_scanin; |
| 259 | wire ff_sync1_rowaddr_3_scanout; |
| 260 | wire ff_sync1_rowaddr_2_scanin; |
| 261 | wire ff_sync1_rowaddr_2_scanout; |
| 262 | wire ff_sync1_rowaddr_1_scanin; |
| 263 | wire ff_sync1_rowaddr_1_scanout; |
| 264 | wire ff_sync1_rowaddr_scanin; |
| 265 | wire ff_sync1_rowaddr_scanout; |
| 266 | wire ff_sync1_coladdr_4_1_scanin; |
| 267 | wire ff_sync1_coladdr_4_1_scanout; |
| 268 | wire sync_tcu_efu_coladdr4; |
| 269 | wire tcu_efu_coladdr4_1; |
| 270 | wire ff_sync1_coladdr_3_1_scanin; |
| 271 | wire ff_sync1_coladdr_3_1_scanout; |
| 272 | wire sync_tcu_efu_coladdr3; |
| 273 | wire tcu_efu_coladdr3_1; |
| 274 | wire ff_sync1_coladdr_2_1_scanin; |
| 275 | wire ff_sync1_coladdr_2_1_scanout; |
| 276 | wire sync_tcu_efu_coladdr2; |
| 277 | wire tcu_efu_coladdr2_1; |
| 278 | wire ff_sync1_coladdr_1_1_scanin; |
| 279 | wire ff_sync1_coladdr_1_1_scanout; |
| 280 | wire sync_tcu_efu_coladdr1; |
| 281 | wire tcu_efu_coladdr1_1; |
| 282 | wire ff_sync1_coladdr_0_1_scanin; |
| 283 | wire ff_sync1_coladdr_0_1_scanout; |
| 284 | wire sync_tcu_efu_coladdr0; |
| 285 | wire tcu_efu_coladdr0_1; |
| 286 | wire ff_sync1_coladdr_4_scanin; |
| 287 | wire ff_sync1_coladdr_4_scanout; |
| 288 | wire ff_sync1_coladdr_3_scanin; |
| 289 | wire ff_sync1_coladdr_3_scanout; |
| 290 | wire ff_sync1_coladdr_2_scanin; |
| 291 | wire ff_sync1_coladdr_2_scanout; |
| 292 | wire ff_sync1_coladdr_1_scanin; |
| 293 | wire ff_sync1_coladdr_1_scanout; |
| 294 | wire ff_sync1_coladdr_scanin; |
| 295 | wire ff_sync1_coladdr_scanout; |
| 296 | wire [4:0] sync_tcu_efu_coladdr; |
| 297 | wire ff_tcu_efu_read_mode_bit1_scanin; |
| 298 | wire ff_tcu_efu_read_mode_bit1_scanout; |
| 299 | wire tcu_efu_read_mode1_1; |
| 300 | wire ff_tcu_efu_read_mode_bit1_1_scanin; |
| 301 | wire ff_tcu_efu_read_mode_bit1_1_scanout; |
| 302 | wire sync_tcu_efu_read_mode1; |
| 303 | wire ff_tcu_efu_read_mode_bit0_scanin; |
| 304 | wire ff_tcu_efu_read_mode_bit0_scanout; |
| 305 | wire tcu_efu_read_mode0_1; |
| 306 | wire ff_tcu_efu_read_mode_bit0_1_scanin; |
| 307 | wire ff_tcu_efu_read_mode_bit0_1_scanout; |
| 308 | wire sync_tcu_efu_read_mode0; |
| 309 | wire [1:0] sync_tcu_efu_read_mode; |
| 310 | wire ff_power_down_sync_slice_scanin; |
| 311 | wire ff_power_down_sync_slice_scanout; |
| 312 | wire inhibit_power_down_sync_l; |
| 313 | wire ff_power_down_sync_slice_1_scanin; |
| 314 | wire ff_power_down_sync_slice_1_scanout; |
| 315 | wire spares_scanin; |
| 316 | wire spares_scanout; |
| 317 | |
| 318 | |
| 319 | //----------------------------------------------------------------------------- |
| 320 | // I/O declarations |
| 321 | //----------------------------------------------------------------------------- |
| 322 | |
| 323 | input tcu_efu_updatedr; |
| 324 | input tcu_efu_read_en; |
| 325 | input tcu_efu_read_start; |
| 326 | input tcu_efu_fuse_bypass; |
| 327 | input tcu_efu_dest_sample; |
| 328 | input [4:0] tcu_efu_coladdr; |
| 329 | input [2:0] tcu_efu_read_mode; |
| 330 | input [6:0] tcu_efu_rowaddr; |
| 331 | input tcu_efu_capturedr; |
| 332 | input tcu_efu_data_in; |
| 333 | input tcu_efu_shiftdr; |
| 334 | input [31:0] efa_sbc_data; |
| 335 | input tck; |
| 336 | input cmp_io_sync_en; |
| 337 | output sbc_efa_power_down; |
| 338 | output efu_tcu_data_out; |
| 339 | output [6:0] sync1_rowaddress; |
| 340 | output [4:0] sbc_efa_bit_addr; |
| 341 | output sbc_efa_sup_det_rd; |
| 342 | output sbc_efa_margin0_rd; |
| 343 | output sbc_efa_margin1_rd; |
| 344 | output sbc_efa_read_en; |
| 345 | output [5:0] sbc_efa_word_addr; |
| 346 | |
| 347 | // l2 and spc read data |
| 348 | input [31:0] shift_data_ff_out; |
| 349 | input load_l2_read_data; |
| 350 | |
| 351 | //output mrd_state_rd_array; |
| 352 | output [31:0] read_data_ff; |
| 353 | output read_data_ff_vld; |
| 354 | //output [6:0] addr_cnt_ff; |
| 355 | //output efa_array_power_down_ff; |
| 356 | |
| 357 | output update_dr_jbus; |
| 358 | output local_read_en; |
| 359 | output local_efu_read_start; |
| 360 | output local_fuse_bypass; |
| 361 | output local_dest_sample; |
| 362 | input cmp_mrd_cnt_done; |
| 363 | |
| 364 | output decode_enable_vld; |
| 365 | // Chip Primary Inputs/Globals |
| 366 | |
| 367 | input iol2clk; |
| 368 | input l2clk; |
| 369 | input jbus_arst_l; // JBus clock domain async reset. |
| 370 | input por_l; |
| 371 | //input testmode_l; |
| 372 | |
| 373 | // CTU/JTAG Interface |
| 374 | |
| 375 | input [6:0] snc1_rowaddr; |
| 376 | //input inhibit_power_down_l; |
| 377 | |
| 378 | // Destination Register Interface |
| 379 | |
| 380 | // Interface with NCU for data array repair |
| 381 | output efu_ncu_fuse_data; |
| 382 | output efu_ncu_srlnum0_xfer_en; |
| 383 | output efu_ncu_srlnum1_xfer_en; |
| 384 | output efu_ncu_srlnum2_xfer_en; |
| 385 | output efu_ncu_fusestat_xfer_en; |
| 386 | output efu_ncu_coreavl_xfer_en; |
| 387 | output efu_ncu_bankavl_xfer_en; |
| 388 | |
| 389 | // with niu |
| 390 | input [31:0] niu_read_data_shift; |
| 391 | input load_niu_read_data; |
| 392 | |
| 393 | // EFA interface |
| 394 | |
| 395 | //input [31:0] efa_out_data; |
| 396 | output pwr_ok; |
| 397 | output por_n; |
| 398 | input tcu_pce_ov; |
| 399 | input tcu_aclk; |
| 400 | input tcu_bclk; |
| 401 | input tcu_scan_en; |
| 402 | input scan_in; |
| 403 | output scan_out; |
| 404 | |
| 405 | |
| 406 | |
| 407 | assign pce_ov = tcu_pce_ov; |
| 408 | assign siclk = tcu_aclk; |
| 409 | assign soclk = tcu_bclk; |
| 410 | assign stop = 1'b0; |
| 411 | assign se = tcu_scan_en; |
| 412 | |
| 413 | |
| 414 | |
| 415 | //----------------------------------------------------------------------------- |
| 416 | // Wire/reg declarations |
| 417 | //----------------------------------------------------------------------------- |
| 418 | |
| 419 | wire efu_ncu_fuse_clk1; |
| 420 | wire efu_ncu_fuse_data; |
| 421 | |
| 422 | wire efu_ncu_sernum0_dshift; |
| 423 | wire efu_ncu_sernum1_dshift; |
| 424 | wire efu_ncu_sernum2_dshift; |
| 425 | wire efu_ncu_fusestat_dshift; |
| 426 | wire efu_ncu_coreavail_dshift; |
| 427 | |
| 428 | wire local_efu_read_start; |
| 429 | wire [6:0] addr_cnt_nxt; |
| 430 | wire addr_cnt_en; |
| 431 | //wire [6:0] addr_cnt_ff; |
| 432 | wire [5:0] addr_cnt_inc1; |
| 433 | wire addr_cnt_max; |
| 434 | wire shift_done; |
| 435 | wire mrd_cnt_done; |
| 436 | wire rd_array_done; |
| 437 | wire recover_done; |
| 438 | wire local_fuse_bypass; //tcu_efu_fuse_bypass |
| 439 | wire local_dest_sample; //tcu_efu_fuse_bypass |
| 440 | wire local_read_en; //tcu_efu_fuse_bypass |
| 441 | wire read_data_en; |
| 442 | wire [31:0] read_data_nxt; |
| 443 | wire [31:0] read_data_ff; |
| 444 | reg [3:0] seq_state_nxt; |
| 445 | reg enter_rsltshft; |
| 446 | wire [3:0] seq_state_ff; |
| 447 | wire seq_state_idle; |
| 448 | wire seq_state_dump; |
| 449 | wire seq_state_sglrd; |
| 450 | //wire seq_state_bypass; |
| 451 | wire seq_state_dest_smpl; |
| 452 | wire seq_state_l2rr_smpl; |
| 453 | wire seq_state_rsltshft; |
| 454 | wire ncu_coreavail_dec; |
| 455 | wire ncu_sernum0_dec; |
| 456 | wire ncu_sernum1_dec; |
| 457 | wire ncu_sernum2_dec; |
| 458 | wire ncu_fusestat_dec; |
| 459 | |
| 460 | wire inhibit_power_down_snc_l; |
| 461 | wire inhibit_power_down_l; |
| 462 | wire efa_read_en_lt; |
| 463 | wire enable_efa_por_nxt_l; |
| 464 | wire enable_efa_por_ff_l; |
| 465 | wire efa_array_power_down_ff; |
| 466 | wire efa_array_power_down_nxt; |
| 467 | |
| 468 | reg valid; |
| 469 | reg val_err; |
| 470 | |
| 471 | //----------------------------------------------------------------------------- |
| 472 | // Misc signals |
| 473 | //----------------------------------------------------------------------------- |
| 474 | assign pwr_ok = jbus_arst_l; |
| 475 | assign por_n = jbus_arst_l & por_l; |
| 476 | assign read_data_ff_vld_d = seq_state_rsltshft | seq_state_bypass | seq_state_dump & mrd_state_xfer ; |
| 477 | assign read_data_ff_vld = read_data_ff_vld_d & ~read_data_ff_vld_r1; |
| 478 | assign decode_enable_vld=1'b0; |
| 479 | |
| 480 | //----------------------------------------------------------------------------- |
| 481 | // Power down control |
| 482 | //----------------------------------------------------------------------------- |
| 483 | |
| 484 | efu_fct_ctl_l1clkhdr_ctl_macro ioclkgen ( |
| 485 | .l2clk(iol2clk), |
| 486 | .l1en (1'b1 ), |
| 487 | .l1clk(l1clk), |
| 488 | .pce_ov(pce_ov), |
| 489 | .stop(stop), |
| 490 | .se(se)); |
| 491 | |
| 492 | efu_fct_ctl_l1clkhdr_ctl_macro l2clkgen ( |
| 493 | .l2clk(l2clk), |
| 494 | .l1en (1'b1 ), |
| 495 | .l1clk(l1clk_cmp), |
| 496 | .pce_ov(pce_ov), |
| 497 | .stop(stop), |
| 498 | .se(se)); |
| 499 | |
| 500 | efu_fct_ctl_l1clkhdr_ctl_macro tckclkgen ( |
| 501 | .l2clk(tck), |
| 502 | .l1en (1'b1 ), |
| 503 | .l1clk(tckl1clk), |
| 504 | .pce_ov(pce_ov), |
| 505 | .stop(stop), |
| 506 | .se(se)); |
| 507 | |
| 508 | assign enable_efa_por_nxt_l = seq_state_rsltshft | enable_efa_por_ff_l; |
| 509 | |
| 510 | efu_fct_ctl_msff_ctl_macro__width_1 ff_pulse_read_data_ff_vld |
| 511 | ( |
| 512 | .scan_in(ff_pulse_read_data_ff_vld_scanin), |
| 513 | .scan_out(ff_pulse_read_data_ff_vld_scanout), |
| 514 | .dout (read_data_ff_vld_r1), |
| 515 | .din (read_data_ff_vld_d), |
| 516 | .l1clk (l1clk), |
| 517 | .siclk(siclk), |
| 518 | .soclk(soclk) |
| 519 | ); |
| 520 | |
| 521 | efu_fct_ctl_msff_ctl_macro__width_1 enable_efa_por_reg |
| 522 | ( |
| 523 | .scan_in(enable_efa_por_reg_scanin), |
| 524 | .scan_out(enable_efa_por_reg_scanout), |
| 525 | .dout (enable_efa_por_ff_l), |
| 526 | .din (enable_efa_por_nxt_l), |
| 527 | .l1clk (l1clk), |
| 528 | .siclk(siclk), |
| 529 | .soclk(soclk) |
| 530 | ); |
| 531 | |
| 532 | |
| 533 | assign efa_array_power_down_nxt |
| 534 | = seq_state_idle & !(local_efu_read_start | local_fuse_bypass |
| 535 | | local_read_en | local_dest_sample) |
| 536 | & enable_efa_por_ff_l & inhibit_power_down_l; |
| 537 | |
| 538 | efu_fct_ctl_msff_ctl_macro__width_1 efa_array_power_down_reg |
| 539 | ( |
| 540 | .scan_in(efa_array_power_down_reg_scanin), |
| 541 | .scan_out(efa_array_power_down_reg_scanout), |
| 542 | .dout (efa_array_power_down_ff), |
| 543 | .din (efa_array_power_down_nxt), |
| 544 | .l1clk (l1clk), |
| 545 | .siclk(siclk), |
| 546 | .soclk(soclk) |
| 547 | ); |
| 548 | |
| 549 | |
| 550 | //----------------------------------------------------------------------------- |
| 551 | // Read whole array sequencer |
| 552 | //----------------------------------------------------------------------------- |
| 553 | // Note| State encodings are chosen so the outputs are equal to signle |
| 554 | // state bits. Changing state encodings will change outputs! |
| 555 | // Bit[3] is used to indicate idle/not idle. |
| 556 | // |
| 557 | |
| 558 | always @(addr_cnt_max or local_dest_sample or local_efu_read_start or local_fuse_bypass or local_read_en or mrd_cnt_done or recover_done or seq_state_ff or shift_done) |
| 559 | begin |
| 560 | enter_rsltshft = 1'b0; |
| 561 | case (seq_state_ff) //synopsys parallel_case full_case |
| 562 | `MSEQ_IDLE: |
| 563 | if (local_efu_read_start) |
| 564 | seq_state_nxt = `MSEQ_DUMP; |
| 565 | else if (local_read_en) |
| 566 | seq_state_nxt = `MSEQ_SGLRD; |
| 567 | else if (local_fuse_bypass | local_dest_sample) |
| 568 | seq_state_nxt = `MSEQ_SHIFT; |
| 569 | else |
| 570 | seq_state_nxt = `MSEQ_IDLE; |
| 571 | `MSEQ_DUMP: |
| 572 | if (addr_cnt_max && shift_done) |
| 573 | begin |
| 574 | seq_state_nxt = `MSEQ_RSLTSHFT; |
| 575 | enter_rsltshft = 1'b1; |
| 576 | end |
| 577 | else |
| 578 | seq_state_nxt = `MSEQ_DUMP; |
| 579 | `MSEQ_RSLTSHFT: |
| 580 | if (mrd_cnt_done) |
| 581 | seq_state_nxt = `MSEQ_IDLE; |
| 582 | else |
| 583 | seq_state_nxt = `MSEQ_RSLTSHFT; |
| 584 | `MSEQ_SGLRD: |
| 585 | if (recover_done) |
| 586 | seq_state_nxt = `MSEQ_IDLE; |
| 587 | else |
| 588 | seq_state_nxt = `MSEQ_SGLRD; |
| 589 | `MSEQ_SHIFT: |
| 590 | if (shift_done) |
| 591 | seq_state_nxt = `MSEQ_IDLE; |
| 592 | else |
| 593 | seq_state_nxt = `MSEQ_SHIFT; |
| 594 | `MSEQ_DEST_SMPL: |
| 595 | if (shift_done) |
| 596 | seq_state_nxt = `MSEQ_IDLE; |
| 597 | else |
| 598 | seq_state_nxt = `MSEQ_DEST_SMPL; |
| 599 | `MSEQ_L2RR_SMPL: |
| 600 | if (shift_done) |
| 601 | seq_state_nxt = `MSEQ_IDLE; |
| 602 | else |
| 603 | seq_state_nxt = `MSEQ_L2RR_SMPL; |
| 604 | `MSEQ_BYPASS: |
| 605 | if (shift_done) |
| 606 | seq_state_nxt = `MSEQ_IDLE; |
| 607 | else |
| 608 | seq_state_nxt = `MSEQ_BYPASS; |
| 609 | default: |
| 610 | seq_state_nxt = `MSEQ_IDLE; |
| 611 | endcase |
| 612 | end |
| 613 | assign seq_state_idle = (!seq_state_ff[3]); |
| 614 | assign seq_state_dump = (seq_state_ff == `MSEQ_DUMP); |
| 615 | assign seq_state_sglrd = (seq_state_ff == `MSEQ_SGLRD); |
| 616 | //assign seq_state_bypass = (seq_state_ff == `MSEQ_BYPASS); |
| 617 | assign seq_state_bypass = (seq_state_ff == `MSEQ_SHIFT); |
| 618 | assign seq_state_rsltshft = (seq_state_ff == `MSEQ_RSLTSHFT); |
| 619 | assign seq_state_dest_smpl = (seq_state_ff == `MSEQ_DEST_SMPL); |
| 620 | assign seq_state_l2rr_smpl = (seq_state_ff == `MSEQ_L2RR_SMPL); |
| 621 | |
| 622 | efu_fct_ctl_msff_ctl_macro__width_4 seq_state_reg |
| 623 | ( |
| 624 | .scan_in(seq_state_reg_scanin), |
| 625 | .scan_out(seq_state_reg_scanout), |
| 626 | .dout (seq_state_ff[3:0]), |
| 627 | .din (seq_state_nxt[3:0]), |
| 628 | .l1clk (l1clk), |
| 629 | .siclk(siclk), |
| 630 | .soclk(soclk) |
| 631 | ); |
| 632 | |
| 633 | //----------------------------------------------------------------------------- |
| 634 | // Address Counter |
| 635 | //----------------------------------------------------------------------------- |
| 636 | assign addr_cnt_inc1[5:0] = addr_cnt_ff[5:0] + 6'b000001; |
| 637 | |
| 638 | assign addr_cnt_nxt [6:0] = local_efu_read_start ? 7'b0000000 |
| 639 | : !seq_state_dump ? snc1_rowaddr[6:0] |
| 640 | : {1'b0,addr_cnt_inc1}; |
| 641 | |
| 642 | assign addr_cnt_max = &addr_cnt_ff[5:0]; |
| 643 | |
| 644 | assign addr_cnt_en = local_efu_read_start |
| 645 | | shift_done & !addr_cnt_max & seq_state_dump |
| 646 | | !seq_state_dump; |
| 647 | |
| 648 | efu_fct_ctl_msff_ctl_macro__en_1__width_7 addr_cnt_reg |
| 649 | ( |
| 650 | .scan_in(addr_cnt_reg_scanin), |
| 651 | .scan_out(addr_cnt_reg_scanout), |
| 652 | .dout (addr_cnt_ff[6:0]), |
| 653 | .din (addr_cnt_nxt[6:0]), |
| 654 | .en (addr_cnt_en), |
| 655 | .l1clk (l1clk), |
| 656 | .siclk(siclk), |
| 657 | .soclk(soclk) |
| 658 | ); |
| 659 | |
| 660 | |
| 661 | |
| 662 | |
| 663 | //----------------------------------------------------------------------------- |
| 664 | // Read and process one entry sequencer |
| 665 | //----------------------------------------------------------------------------- |
| 666 | // Note!! MRD_RD_ARRAY encoding was chosen so that mrd_state_ff[2] uniquely |
| 667 | // defines being in that state. (like one hot, but only for that state) |
| 668 | |
| 669 | reg [2:0] mrd_state_nxt; |
| 670 | reg enter_rd_array; |
| 671 | reg enter_xfer; |
| 672 | //wire enter_ashift; |
| 673 | //wire enter_dshift; |
| 674 | reg enter_recover; |
| 675 | wire [2:0] mrd_state_ff; |
| 676 | wire mrd_state_rd_array; |
| 677 | //wire mrd_state_ashift; |
| 678 | //wire mrd_state_dshift; |
| 679 | //wire mrd_state_shift; |
| 680 | wire mrd_state_recover; |
| 681 | |
| 682 | always @(local_dest_sample or local_fuse_bypass or mrd_cnt_done or mrd_state_ff or seq_state_dump or seq_state_sglrd) |
| 683 | begin |
| 684 | enter_rd_array = 1'b0; |
| 685 | // enter_ashift = 1'b0; |
| 686 | enter_xfer = 1'b0; |
| 687 | enter_recover = 1'b0; |
| 688 | // enter_dshift = 1'b0; |
| 689 | case (mrd_state_ff) //synopsys parallel_case full_case |
| 690 | `MRD_IDLE: |
| 691 | if (seq_state_sglrd || seq_state_dump) |
| 692 | begin |
| 693 | mrd_state_nxt = `MRD_RD_ARRAY; |
| 694 | enter_rd_array = 1'b1; |
| 695 | end |
| 696 | else if (local_fuse_bypass || local_dest_sample) |
| 697 | begin |
| 698 | // mrd_state_nxt = `MRD_ASHIFT; |
| 699 | mrd_state_nxt = `MRD_XFER; |
| 700 | //enter_ashift = 1'b1; |
| 701 | enter_xfer = 1'b1; |
| 702 | end |
| 703 | else |
| 704 | mrd_state_nxt = `MRD_IDLE; |
| 705 | //////////////////////////////////////////// |
| 706 | `MRD_RD_ARRAY: |
| 707 | if (mrd_cnt_done && seq_state_dump) |
| 708 | begin |
| 709 | mrd_state_nxt = `MRD_XFER; |
| 710 | enter_xfer = 1'b1; |
| 711 | end |
| 712 | else if (mrd_cnt_done) |
| 713 | begin |
| 714 | mrd_state_nxt = `MRD_RECOVER; |
| 715 | enter_recover = 1'b1; |
| 716 | end |
| 717 | else |
| 718 | mrd_state_nxt = `MRD_RD_ARRAY; |
| 719 | //////////////////////////////////////////// |
| 720 | `MRD_XFER : |
| 721 | |
| 722 | if( mrd_cnt_done) |
| 723 | mrd_state_nxt = `MRD_IDLE; |
| 724 | else |
| 725 | mrd_state_nxt = `MRD_XFER; |
| 726 | |
| 727 | //////////////////////////////////////////// |
| 728 | |
| 729 | `MRD_RECOVER: |
| 730 | if (mrd_cnt_done) |
| 731 | mrd_state_nxt = `MRD_IDLE; |
| 732 | else |
| 733 | mrd_state_nxt = `MRD_RECOVER; |
| 734 | default: |
| 735 | mrd_state_nxt = `MRD_IDLE; |
| 736 | endcase |
| 737 | end |
| 738 | |
| 739 | //assign mrd_state_idle = (mrd_state_ff == `MRD_IDLE); |
| 740 | assign mrd_state_rd_array = mrd_state_ff[2]; |
| 741 | //assign mrd_state_ashift = (mrd_state_ff == `MRD_ASHIFT); |
| 742 | //assign mrd_state_dshift = (mrd_state_ff == `MRD_DSHIFT); |
| 743 | |
| 744 | assign mrd_state_xfer = (mrd_state_ff == `MRD_XFER); |
| 745 | //assign mrd_state_shift = mrd_state_ashift | mrd_state_dshift; |
| 746 | assign mrd_state_recover = (mrd_state_ff == `MRD_RECOVER); |
| 747 | assign shift_done = mrd_state_xfer & mrd_cnt_done; |
| 748 | assign rd_array_done = mrd_state_rd_array & mrd_cnt_done; |
| 749 | assign recover_done = mrd_state_recover & mrd_cnt_done; |
| 750 | |
| 751 | assign mrd_state_ashift = mrd_state_xfer; |
| 752 | assign mrd_state_dshift = mrd_state_xfer; |
| 753 | assign mrd_state_shift = mrd_state_xfer; |
| 754 | |
| 755 | efu_fct_ctl_msff_ctl_macro__width_3 mrd_state_reg |
| 756 | ( |
| 757 | .scan_in(mrd_state_reg_scanin), |
| 758 | .scan_out(mrd_state_reg_scanout), |
| 759 | .dout (mrd_state_ff[2:0]), |
| 760 | .din (mrd_state_nxt[2:0]), |
| 761 | .l1clk (l1clk), |
| 762 | .siclk(siclk), |
| 763 | .soclk(soclk) |
| 764 | ); |
| 765 | |
| 766 | |
| 767 | |
| 768 | //----------------------------------------------------------------------------- |
| 769 | // General purpose timing counter |
| 770 | //----------------------------------------------------------------------------- |
| 771 | |
| 772 | wire [8:0] mrd_cnt_ff; |
| 773 | wire [8:0] mrd_cnt_nxt; |
| 774 | wire [8:0] mrd_cnt_dec1; |
| 775 | wire [5:0] l2rr_read_cnt; |
| 776 | wire [8:0] mrd_cnt_dec1_true_value_9; |
| 777 | wire [8:0] enter_recover_false_value; |
| 778 | |
| 779 | assign l2rr_read_cnt = read_data_ff[17:12]; |
| 780 | |
| 781 | // General purpose CNTer used for timing reads from array and shifting |
| 782 | // to destination registers. Note that CNTdown stops at 0 and won't wrap. |
| 783 | |
| 784 | assign mrd_cnt_dec1[8:0] = mrd_cnt_ff[8:0] - 9'b0_0000_0001; |
| 785 | assign mrd_cnt_dec1_true_value = !mrd_cnt_done; |
| 786 | assign mrd_cnt_dec1_true_value_9 = {9{mrd_cnt_dec1_true_value}}; |
| 787 | |
| 788 | assign enter_recover_false_value = (mrd_cnt_dec1 & mrd_cnt_dec1_true_value_9); |
| 789 | |
| 790 | |
| 791 | //assign mrd_cnt_nxt [8:0] = enter_rd_array ? 9'd20 |
| 792 | // : enter_ashift ? {(7'd09),2'b11} |
| 793 | // : (enter_dshift & seq_state_l2rr_smpl) ? ({1'b0,l2rr_read_cnt,2'b11}) |
| 794 | // : enter_dshift ? {(7'd12),2'b11} |
| 795 | // : enter_rsltshft ? {(7'd63),2'b11} |
| 796 | // : enter_recover ? 9'd10 : enter_recover_false_value; |
| 797 | |
| 798 | |
| 799 | // ### CPS 3/29/2005 |
| 800 | // need to load d21 so that bit 21-0 get shifted out |
| 801 | // : enter_xfer ? 9'd22 |
| 802 | // : enter_recover ? 9'd10 : enter_recover_false_value; |
| 803 | // : enter_rsltshft ? {(7'd63),2'b11} |
| 804 | //need to change 20 to 40 |
| 805 | assign mrd_cnt_nxt [8:0] = enter_rd_array ? 9'd42 |
| 806 | : enter_xfer ? (serdes ? 9'd91 : 9'd21) |
| 807 | : enter_rsltshft ? 9'd63 |
| 808 | : enter_recover ? 9'd10 |
| 809 | : mrd_cnt_ff == 9'd0 ? 9'd0 |
| 810 | : mrd_cnt_dec1[8:0]; |
| 811 | |
| 812 | |
| 813 | //assign mrd_cnt_done = ~|mrd_cnt_ff; |
| 814 | assign mrd_cnt_63 = mrd_cnt_nxt == 9'd63; |
| 815 | |
| 816 | efu_fct_ctl_msff_ctl_macro__width_1 ff_mrd_zero |
| 817 | ( |
| 818 | .scan_in(ff_mrd_zero_scanin), |
| 819 | .scan_out(ff_mrd_zero_scanout), |
| 820 | .dout (mrd_cnt_done), |
| 821 | .din (mrd_cnt_ff == 9'd1), |
| 822 | .l1clk (l1clk), |
| 823 | .siclk(siclk), |
| 824 | .soclk(soclk) |
| 825 | ); |
| 826 | |
| 827 | efu_fct_ctl_msff_ctl_macro__width_1 mrd_63_to_0_ff |
| 828 | ( |
| 829 | .scan_in(mrd_63_to_0_ff_scanin), |
| 830 | .scan_out(mrd_63_to_0_ff_scanout), |
| 831 | .dout (mrd_63_to_0), |
| 832 | .din ((~mrd_cnt_done & mrd_63_to_0) | mrd_cnt_63), |
| 833 | .l1clk (l1clk), |
| 834 | .siclk(siclk), |
| 835 | .soclk(soclk) |
| 836 | ); |
| 837 | |
| 838 | efu_fct_ctl_msff_ctl_macro__width_9 mrd_cnt_reg |
| 839 | ( |
| 840 | .scan_in(mrd_cnt_reg_scanin), |
| 841 | .scan_out(mrd_cnt_reg_scanout), |
| 842 | .dout (mrd_cnt_ff[8:0]), |
| 843 | .din (mrd_cnt_nxt[8:0]), |
| 844 | .l1clk (l1clk), |
| 845 | .siclk(siclk), |
| 846 | .soclk(soclk) |
| 847 | ); |
| 848 | |
| 849 | |
| 850 | //----------------------------------------------------------------------------- |
| 851 | // Read array data register |
| 852 | //----------------------------------------------------------------------------- |
| 853 | wire [2:0] valid_bits; |
| 854 | //wire parity_bit; |
| 855 | wire [5:0] block_id; |
| 856 | //wire [21:0] payload_data; |
| 857 | wire computed_parity; |
| 858 | wire good_parity; |
| 859 | wire valid_row; |
| 860 | wire row_error; |
| 861 | wire [31:0] read_data_shift; |
| 862 | wire [31:0] read_data_l2shift; |
| 863 | wire read_data_shift_en; |
| 864 | wire shift_in; |
| 865 | wire [2:0] l2rd_id_ff; |
| 866 | wire l2rd_id_en; |
| 867 | |
| 868 | assign serdes = enter_xfer & ((efa_out_data[27:22] == 6'b101010) | (efa_out_data[27:22] == 6'b101001) |
| 869 | | (efa_out_data[27:22] == 6'b101011)); |
| 870 | |
| 871 | assign shift_in = 1'b0; |
| 872 | |
| 873 | assign read_data_shift_en = (seq_state_dest_smpl |
| 874 | | seq_state_l2rr_smpl & mrd_state_xfer) |
| 875 | & (mrd_cnt_ff[1:0]==2'b00); |
| 876 | assign read_data_en = rd_array_done | update_dr_jbus | read_data_shift_en | load_l2_read_data | load_niu_read_data; |
| 877 | assign read_data_shift = {read_data_ff[31:12], read_data_ff[10:0], shift_in}; |
| 878 | assign read_data_l2shift = {read_data_ff[30:0], shift_in}; |
| 879 | assign read_data_nxt = update_dr_jbus ? tck_shft_data_ff |
| 880 | : seq_state_dest_smpl ? read_data_shift |
| 881 | : seq_state_l2rr_smpl ? read_data_l2shift |
| 882 | : load_l2_read_data ? shift_data_ff_out |
| 883 | : load_niu_read_data ? niu_read_data_shift |
| 884 | : efa_out_data; |
| 885 | |
| 886 | //assign l2rd_id_en = enter_ashift; |
| 887 | assign l2rd_id_en = enter_xfer; |
| 888 | |
| 889 | efu_fct_ctl_msff_ctl_macro__en_1__width_32 read_data_reg |
| 890 | ( |
| 891 | .scan_in(read_data_reg_scanin), |
| 892 | .scan_out(read_data_reg_scanout), |
| 893 | .din (read_data_nxt), |
| 894 | .dout (read_data_ff), |
| 895 | .en (read_data_en), |
| 896 | .l1clk (l1clk), |
| 897 | .siclk(siclk), |
| 898 | .soclk(soclk) |
| 899 | ); |
| 900 | |
| 901 | efu_fct_ctl_msff_ctl_macro__en_1__width_3 l2rd_id_reg |
| 902 | ( |
| 903 | .scan_in(l2rd_id_reg_scanin), |
| 904 | .scan_out(l2rd_id_reg_scanout), |
| 905 | .din (block_id[2:0]), |
| 906 | .dout (l2rd_id_ff[2:0]), |
| 907 | .en (l2rd_id_en), |
| 908 | .l1clk (l1clk), |
| 909 | .siclk(siclk), |
| 910 | .soclk(soclk) |
| 911 | ); |
| 912 | |
| 913 | |
| 914 | //assign parity_bit = read_data_ff[28]; |
| 915 | //assign payload_data = read_data_ff[21:0]; |
| 916 | |
| 917 | assign valid_bits = read_data_ff[31:29]; |
| 918 | assign block_id = read_data_ff[27:22]; |
| 919 | assign computed_parity = ^read_data_ff[28:0]; |
| 920 | |
| 921 | assign good_parity = !computed_parity; |
| 922 | //### CPS |
| 923 | //assign good_parity = computed_parity; |
| 924 | |
| 925 | always @(valid_bits) |
| 926 | case (valid_bits) //synopsys parallel_case full_case |
| 927 | 3'b000: {valid, val_err} = 2'b00; |
| 928 | 3'b001: {valid, val_err} = 2'b01; |
| 929 | 3'b010: {valid, val_err} = 2'b01; |
| 930 | 3'b100: {valid, val_err} = 2'b01; |
| 931 | 3'b011: {valid, val_err} = 2'b10; |
| 932 | 3'b101: {valid, val_err} = 2'b10; |
| 933 | 3'b110: {valid, val_err} = 2'b10; |
| 934 | 3'b111: {valid, val_err} = 2'b10; |
| 935 | endcase |
| 936 | |
| 937 | assign valid_row = good_parity & valid; |
| 938 | |
| 939 | wire [63:0] rslt_status_nxt; |
| 940 | wire [63:0] rslt_status_ff; |
| 941 | wire rslt_status_en; |
| 942 | wire [63:0] rslt_status_set; |
| 943 | wire [63:0] rslt_status_clr; |
| 944 | wire [63:0] rslt_status_vect; |
| 945 | |
| 946 | //###CPS parity is 1 == row error ?????? |
| 947 | // parity is 0 == no row error ?????? |
| 948 | // assign row_error = val_err | (valid & ~good_parity); |
| 949 | |
| 950 | //assign invalid_blk_id = (block_id[5] == 1'b1 & block_id[4] == 1'b1) | (block_id == 6'b101101) | (block_id == 6'b101110) | (block_id == 6'b101111); |
| 951 | //assign row_error = (val_err | (valid & ~good_parity)) & ~invalid_blk_id; |
| 952 | assign row_error = val_err | (valid & ~good_parity); |
| 953 | |
| 954 | assign rslt_status_en = seq_state_dump & shift_done; |
| 955 | assign rslt_status_vect = ({{63{1'b0}},rslt_status_en} << addr_cnt_ff[5:0]); |
| 956 | assign rslt_status_set = rslt_status_vect & {64{row_error}}; |
| 957 | assign rslt_status_clr = rslt_status_vect & {64{!row_error}}; |
| 958 | assign rslt_status_nxt = rslt_status_set | ~rslt_status_clr & rslt_status_ff; |
| 959 | |
| 960 | |
| 961 | efu_fct_ctl_msff_ctl_macro__width_64 rslt_status_reg |
| 962 | ( |
| 963 | .scan_in(rslt_status_reg_scanin), |
| 964 | .scan_out(rslt_status_reg_scanout), |
| 965 | .dout (rslt_status_ff[63:0]), |
| 966 | .din (rslt_status_nxt[63:0]), |
| 967 | .l1clk (l1clk), |
| 968 | .siclk(siclk), |
| 969 | .soclk(soclk) |
| 970 | ); |
| 971 | |
| 972 | |
| 973 | |
| 974 | |
| 975 | |
| 976 | //----------------------------------------------------------------------------- |
| 977 | // Shift control |
| 978 | //----------------------------------------------------------------------------- |
| 979 | wire mrd_cnt_ge_12; |
| 980 | wire mrd_cnt_ge_2; |
| 981 | wire mrd_cnt_ge_1; |
| 982 | //wire local_fuse_clk1_nxt; |
| 983 | wire local_fuse_ashift_nxt; |
| 984 | wire local_fuse_dshift_nxt; |
| 985 | wire fuse_data_bit_mux; |
| 986 | wire fuse_rid_bit_mux; |
| 987 | wire rslt_data_bit_mux; |
| 988 | wire local_fuse_data_nxt; |
| 989 | wire decode_enable; |
| 990 | //wire decode_enable_l2rr; |
| 991 | //wire local_fuse_clk1_ff; |
| 992 | //wire local_fuse_clk1_dly_ff; |
| 993 | //wire local_fuse_clk2_ff; |
| 994 | wire local_fuse_data_ff; |
| 995 | wire [15:0] rid_data; |
| 996 | wire [31:0] write_dest_data; |
| 997 | wire write_en; |
| 998 | wire dest_ncu; |
| 999 | |
| 1000 | assign dest_ncu = ncu_coreavail_dec | ncu_sernum0_dec |
| 1001 | | ncu_sernum1_dec | ncu_sernum2_dec; |
| 1002 | assign rid_data = dest_ncu |
| 1003 | ? {{6{1'b0}}, |
| 1004 | read_data_ff[21:12]} |
| 1005 | : {{5{1'b0}}, |
| 1006 | read_data_ff[21:12], write_en}; |
| 1007 | assign write_en = !(seq_state_dest_smpl | seq_state_l2rr_smpl); |
| 1008 | assign write_dest_data = {{8{1'b0}}, |
| 1009 | read_data_ff[21:12], write_en, |
| 1010 | read_data_ff[11:0], |
| 1011 | 1'b0}; |
| 1012 | |
| 1013 | // |
| 1014 | // assign local_fuse_clk1_nxt = |
| 1015 | // (mrd_state_shift | seq_state_rsltshft) & (mrd_cnt_ff[1:0]==2'b10) & efu_rst_l; |
| 1016 | // |
| 1017 | |
| 1018 | //assign local_fuse_clk1_nxt = |
| 1019 | // (mrd_state_shift | seq_state_rsltshft) & (mrd_cnt_ff[1:0]==2'b10); |
| 1020 | |
| 1021 | assign mrd_cnt_ge_12 = (mrd_cnt_ff[6:0] >= {5'd12,2'b00}); |
| 1022 | assign mrd_cnt_ge_2 = (mrd_cnt_ff[6:0] >= { 5'd2,2'b00}); |
| 1023 | assign mrd_cnt_ge_1 = (mrd_cnt_ff[8:0] >= { 7'd1,2'b00}); |
| 1024 | |
| 1025 | //assign local_fuse_ashift_nxt = mrd_state_ashift & efu_rst_l; |
| 1026 | |
| 1027 | assign local_fuse_ashift_nxt = mrd_state_ashift; |
| 1028 | |
| 1029 | // |
| 1030 | //assign local_fuse_dshift_nxt = efu_rst_l & (seq_state_rsltshft |
| 1031 | // | (mrd_state_dshift & (seq_state_dest_smpl ? (!mrd_cnt_ge_12 & mrd_cnt_ge_1) |
| 1032 | // : seq_state_l2rr_smpl ? (mrd_cnt_ge_1) |
| 1033 | // : mrd_cnt_ge_2 | dest_ncu & mrd_cnt_ge_1)) ); |
| 1034 | // |
| 1035 | |
| 1036 | |
| 1037 | assign local_fuse_dshift_nxt = (seq_state_rsltshft & mrd_63_to_0 |
| 1038 | | (mrd_state_dshift & (seq_state_dest_smpl ? (!mrd_cnt_ge_12 & mrd_cnt_ge_1) |
| 1039 | : seq_state_l2rr_smpl ? (mrd_cnt_ge_1) |
| 1040 | : mrd_cnt_ge_2 | dest_ncu & mrd_cnt_ge_1)) ); |
| 1041 | |
| 1042 | assign fuse_data_bit_mux = write_dest_data[mrd_cnt_ff[6:2]]; |
| 1043 | assign fuse_rid_bit_mux = rid_data[mrd_cnt_ff[5:2]]; |
| 1044 | //assign rslt_data_bit_mux = rslt_status_ff[mrd_cnt_ff[7:2]]; |
| 1045 | assign rslt_data_bit_mux = rslt_status_ff[mrd_cnt_ff[5:0]]; |
| 1046 | |
| 1047 | //##### change back if necessary CPS |
| 1048 | // need to include the rsltshft terms |
| 1049 | // need to find something to inhibit the read_data_ff term |
| 1050 | //assign local_fuse_data_nxt = (mrd_state_ashift & fuse_rid_bit_mux) |
| 1051 | // | (mrd_state_dshift & fuse_data_bit_mux) |
| 1052 | // | (seq_state_rsltshft & rslt_data_bit_mux); |
| 1053 | // added mrd_state_shift to qualify the shift out data |
| 1054 | assign local_fuse_data_nxt = (mrd_state_shift & read_data_ff[mrd_cnt_ff]) | (seq_state_rsltshft & rslt_data_bit_mux); |
| 1055 | |
| 1056 | efu_fct_ctl_msff_ctl_macro__width_1 local_fuse_data_reg |
| 1057 | ( |
| 1058 | .scan_in(local_fuse_data_reg_scanin), |
| 1059 | .scan_out(local_fuse_data_reg_scanout), |
| 1060 | .dout (local_fuse_data_ff), |
| 1061 | .din (local_fuse_data_nxt), |
| 1062 | .l1clk (l1clk), |
| 1063 | .siclk(siclk), |
| 1064 | .soclk(soclk) |
| 1065 | ); |
| 1066 | |
| 1067 | // ### CPS |
| 1068 | //assign decode_enable = mrd_state_shift & (valid_row | seq_state_dest_smpl | seq_state_bypass); |
| 1069 | assign decode_enable = mrd_state_shift & (valid_row & (seq_state_dump | seq_state_dest_smpl | seq_state_bypass)); |
| 1070 | //assign decode_enable_l2rr = mrd_state_shift & seq_state_l2rr_smpl; |
| 1071 | |
| 1072 | //----------------------------------------------------------------------------- |
| 1073 | // destination decoder |
| 1074 | //----------------------------------------------------------------------------- |
| 1075 | |
| 1076 | assign ncu_coreavail_dec= (block_id[5:0] == 6'b100000) & decode_enable; |
| 1077 | assign ncu_bankavail_dec= (block_id[5:0] == 6'b100001) & decode_enable; |
| 1078 | assign ncu_sernum0_dec = (block_id[5:0] == 6'b100010) & decode_enable; |
| 1079 | assign ncu_sernum1_dec = (block_id[5:0] == 6'b100011) & decode_enable; |
| 1080 | assign ncu_sernum2_dec = (block_id[5:0] == 6'b100100) & decode_enable; |
| 1081 | assign ncu_fusestat_dec = seq_state_rsltshft; |
| 1082 | |
| 1083 | assign l2d_fuse_dec = (block_id[5:3] == 3'b011); |
| 1084 | //assign l2d0_read_dec = (l2rd_id_ff[2:0] == 3'b000) & decode_enable_l2rr; |
| 1085 | //assign l2d1_read_dec = (l2rd_id_ff[2:0] == 3'b001) & decode_enable_l2rr; |
| 1086 | //assign l2d2_read_dec = (l2rd_id_ff[2:0] == 3'b010) & decode_enable_l2rr; |
| 1087 | //assign l2d3_read_dec = (l2rd_id_ff[2:0] == 3'b011) & decode_enable_l2rr; |
| 1088 | //assign l2d4_read_dec = (l2rd_id_ff[2:0] == 3'b100) & decode_enable_l2rr; |
| 1089 | //assign l2d5_read_dec = (l2rd_id_ff[2:0] == 3'b101) & decode_enable_l2rr; |
| 1090 | //assign l2d6_read_dec = (l2rd_id_ff[2:0] == 3'b110) & decode_enable_l2rr; |
| 1091 | //assign l2d7_read_dec = (l2rd_id_ff[2:0] == 3'b111) & decode_enable_l2rr; |
| 1092 | |
| 1093 | //----------------------------------------------------------------------------- |
| 1094 | // destination demux |
| 1095 | //----------------------------------------------------------------------------- |
| 1096 | |
| 1097 | assign efu_ncu_fuse_data = local_fuse_data_ff; |
| 1098 | |
| 1099 | |
| 1100 | //----------------------------------------------------------------------------- |
| 1101 | // Shift Control Output flops |
| 1102 | //----------------------------------------------------------------------------- |
| 1103 | efu_fct_ctl_msff_ctl_macro__width_1 ncu_coreavail_dshift_reg |
| 1104 | ( |
| 1105 | .scan_in(ncu_coreavail_dshift_reg_scanin), |
| 1106 | .scan_out(ncu_coreavail_dshift_reg_scanout), |
| 1107 | .din (ncu_coreavail_dec & (local_fuse_ashift_nxt | local_fuse_dshift_nxt)), |
| 1108 | .dout (efu_ncu_coreavl_xfer_en), |
| 1109 | .l1clk (l1clk), |
| 1110 | .siclk(siclk), |
| 1111 | .soclk(soclk) |
| 1112 | ); |
| 1113 | |
| 1114 | |
| 1115 | efu_fct_ctl_msff_ctl_macro__width_1 ncu_bankavail_dshift_reg |
| 1116 | ( |
| 1117 | .scan_in(ncu_bankavail_dshift_reg_scanin), |
| 1118 | .scan_out(ncu_bankavail_dshift_reg_scanout), |
| 1119 | .din (ncu_bankavail_dec & (local_fuse_ashift_nxt | local_fuse_dshift_nxt)), |
| 1120 | .dout (efu_ncu_bankavl_xfer_en), |
| 1121 | .l1clk (l1clk), |
| 1122 | .siclk(siclk), |
| 1123 | .soclk(soclk) |
| 1124 | ); |
| 1125 | |
| 1126 | |
| 1127 | efu_fct_ctl_msff_ctl_macro__width_1 ncu_sernum0_dshift_reg |
| 1128 | ( |
| 1129 | .scan_in(ncu_sernum0_dshift_reg_scanin), |
| 1130 | .scan_out(ncu_sernum0_dshift_reg_scanout), |
| 1131 | .din (ncu_sernum0_dec & (local_fuse_ashift_nxt | local_fuse_dshift_nxt)), |
| 1132 | .dout (efu_ncu_srlnum0_xfer_en), |
| 1133 | .l1clk (l1clk), |
| 1134 | .siclk(siclk), |
| 1135 | .soclk(soclk) |
| 1136 | ); |
| 1137 | efu_fct_ctl_msff_ctl_macro__width_1 ncu_sernum1_dshift_reg |
| 1138 | ( |
| 1139 | .scan_in(ncu_sernum1_dshift_reg_scanin), |
| 1140 | .scan_out(ncu_sernum1_dshift_reg_scanout), |
| 1141 | .din (ncu_sernum1_dec & (local_fuse_ashift_nxt | local_fuse_dshift_nxt)), |
| 1142 | .dout (efu_ncu_srlnum1_xfer_en), |
| 1143 | .l1clk (l1clk), |
| 1144 | .siclk(siclk), |
| 1145 | .soclk(soclk) |
| 1146 | ); |
| 1147 | efu_fct_ctl_msff_ctl_macro__width_1 ncu_sernum2_dshift_reg |
| 1148 | ( |
| 1149 | .scan_in(ncu_sernum2_dshift_reg_scanin), |
| 1150 | .scan_out(ncu_sernum2_dshift_reg_scanout), |
| 1151 | .din (ncu_sernum2_dec & (local_fuse_ashift_nxt | local_fuse_dshift_nxt)), |
| 1152 | .dout (efu_ncu_srlnum2_xfer_en), |
| 1153 | .l1clk (l1clk), |
| 1154 | .siclk(siclk), |
| 1155 | .soclk(soclk) |
| 1156 | ); |
| 1157 | |
| 1158 | efu_fct_ctl_msff_ctl_macro__width_1 ncu_fusestat_dshift_reg |
| 1159 | ( |
| 1160 | .scan_in(ncu_fusestat_dshift_reg_scanin), |
| 1161 | .scan_out(ncu_fusestat_dshift_reg_scanout), |
| 1162 | .din (ncu_fusestat_dec & (local_fuse_ashift_nxt | local_fuse_dshift_nxt)), |
| 1163 | .dout (efu_ncu_fusestat_xfer_en), |
| 1164 | .l1clk (l1clk), |
| 1165 | .siclk(siclk), |
| 1166 | .soclk(soclk) |
| 1167 | ); |
| 1168 | |
| 1169 | |
| 1170 | // efu_tcu_dp merge |
| 1171 | wire [31:0] tck_shft_data_nxt; |
| 1172 | wire updtdr_snc1_ff,updtdr_snc2_ff,updtdr_hist_ff; |
| 1173 | |
| 1174 | cl_sc1_clksyncff_4x ff_updtdr_slice |
| 1175 | ( |
| 1176 | .si(ff_updtdr_slice_scanin), |
| 1177 | .so(ff_updtdr_slice_scanout), |
| 1178 | .q (updtdr_sync1), |
| 1179 | .d (tcu_efu_updatedr), |
| 1180 | .l1clk (l1clk), |
| 1181 | .siclk(siclk), |
| 1182 | .soclk(soclk) |
| 1183 | ); |
| 1184 | |
| 1185 | cl_sc1_clksyncff_4x ff_updtdr_slice1 |
| 1186 | ( |
| 1187 | .si(ff_updtdr_slice1_scanin), |
| 1188 | .so(ff_updtdr_slice1_scanout), |
| 1189 | .q (updtdr_sync2), |
| 1190 | .d (updtdr_sync1), |
| 1191 | .l1clk (l1clk), |
| 1192 | .siclk(siclk), |
| 1193 | .soclk(soclk) |
| 1194 | ); |
| 1195 | |
| 1196 | cl_sc1_clksyncff_4x ff_updtdr_slice2 |
| 1197 | ( |
| 1198 | .si(ff_updtdr_slice2_scanin), |
| 1199 | .so(ff_updtdr_slice2_scanout), |
| 1200 | .q (updtdr_hist_ff), |
| 1201 | .d (updtdr_sync2), |
| 1202 | .l1clk (l1clk), |
| 1203 | .siclk(siclk), |
| 1204 | .soclk(soclk) |
| 1205 | ); |
| 1206 | |
| 1207 | //cl_sc1_clksyncff_4x ff_updtdr_slice (width=3) |
| 1208 | // ( |
| 1209 | // .si(ff_updtdr_slice_scanin), |
| 1210 | // .so(ff_updtdr_slice_scanout), |
| 1211 | // .q ({updtdr_sync1,updtdr_sync2,updtdr_hist_ff}), |
| 1212 | // .d ({tcu_efu_updatedr,updtdr_sync1,updtdr_sync2}), |
| 1213 | // .l1clk (l1clk), |
| 1214 | // ); |
| 1215 | |
| 1216 | assign update_dr_jbus = updtdr_sync2 & ~updtdr_hist_ff ; |
| 1217 | |
| 1218 | /////////////////////////////////////////////////////////////////// |
| 1219 | |
| 1220 | cl_sc1_clksyncff_4x ff_read_en_slice |
| 1221 | ( |
| 1222 | .si ( ff_read_en_slice_scanin ), |
| 1223 | .so ( ff_read_en_slice_scanout ), |
| 1224 | .l1clk ( l1clk ), |
| 1225 | .d ( tcu_efu_read_en ), |
| 1226 | .q ( read_en_sync1 ), |
| 1227 | .siclk(siclk), |
| 1228 | .soclk(soclk) |
| 1229 | ); |
| 1230 | |
| 1231 | cl_sc1_clksyncff_4x ff_read_en_slice1 |
| 1232 | ( |
| 1233 | .si ( ff_read_en_slice1_scanin ), |
| 1234 | .so ( ff_read_en_slice1_scanout ), |
| 1235 | .l1clk ( l1clk ), |
| 1236 | .d ( read_en_sync1 ), |
| 1237 | .q ( read_en_sync2 ), |
| 1238 | .siclk(siclk), |
| 1239 | .soclk(soclk) |
| 1240 | ); |
| 1241 | |
| 1242 | cl_sc1_clksyncff_4x ff_read_en_slice2 |
| 1243 | ( |
| 1244 | .si ( ff_read_en_slice2_scanin ), |
| 1245 | .so ( ff_read_en_slice2_scanout ), |
| 1246 | .l1clk ( l1clk ), |
| 1247 | .d ( read_en_sync2 ), |
| 1248 | .q ( read_en_hist_ff ), |
| 1249 | .siclk(siclk), |
| 1250 | .soclk(soclk) |
| 1251 | ); |
| 1252 | |
| 1253 | //msff_ctl_macro ff_read_en_slice (width=3) |
| 1254 | // ( |
| 1255 | // .scan_in(ff_read_en_slice_scanin), |
| 1256 | // .scan_out(ff_read_en_slice_scanout), |
| 1257 | // .dout ({read_en_sync1,read_en_sync2,read_en_hist_ff}), |
| 1258 | // .din ({tcu_efu_read_en,read_en_sync1,read_en_sync2}), |
| 1259 | // .l1clk (l1clk), |
| 1260 | // ); |
| 1261 | |
| 1262 | assign local_read_en = read_en_sync2 & ~read_en_hist_ff ; |
| 1263 | |
| 1264 | /////////////////////////////////////////////////////////////////// |
| 1265 | |
| 1266 | //msff_ctl_macro ff_read_start_slice (width=3) |
| 1267 | // ( |
| 1268 | // .scan_in(ff_read_start_slice_scanin), |
| 1269 | // .scan_out(ff_read_start_slice_scanout), |
| 1270 | // .dout ({read_start_sync1,read_start_sync2,read_start_hist_ff}), |
| 1271 | // .din ({tcu_efu_read_start,read_start_sync1,read_start_sync2}), |
| 1272 | // .l1clk (l1clk), |
| 1273 | // ); |
| 1274 | |
| 1275 | //msff_ctl_macro ff_read_start_2_slice (width=1) |
| 1276 | // ( |
| 1277 | // .scan_in(ff_read_start_2_slice_scanin), |
| 1278 | // .scan_out(ff_read_start_2_slice_scanout), |
| 1279 | // .dout (read_start_sync1), |
| 1280 | // .din (tcu_efu_read_start), |
| 1281 | // .l1clk (l1clk), |
| 1282 | // ); |
| 1283 | |
| 1284 | efu_fct_ctl_msff_ctl_macro__width_1 ff_read_start_0_slice |
| 1285 | ( |
| 1286 | .scan_in(ff_read_start_0_slice_scanin), |
| 1287 | .scan_out(ff_read_start_0_slice_scanout), |
| 1288 | .dout (read_start_hist_ff), |
| 1289 | .din (read_start_sync2), |
| 1290 | .l1clk (l1clk), |
| 1291 | .siclk(siclk), |
| 1292 | .soclk(soclk) |
| 1293 | ); |
| 1294 | |
| 1295 | efu_fct_ctl_msff_ctl_macro__en_1__width_1 ff_read_start_1_slice |
| 1296 | ( |
| 1297 | .scan_in(ff_read_start_1_slice_scanin), |
| 1298 | .scan_out(ff_read_start_1_slice_scanout), |
| 1299 | .dout (read_start_sync2), |
| 1300 | // .din (read_start_sync1), |
| 1301 | .din (tcu_efu_read_start), |
| 1302 | // .en (cmp_io_sync_en_r2), |
| 1303 | .en (cmp_io_sync_en_r1), |
| 1304 | .l1clk (l1clk_cmp), |
| 1305 | .siclk(siclk), |
| 1306 | .soclk(soclk) |
| 1307 | ); |
| 1308 | |
| 1309 | efu_fct_ctl_msff_ctl_macro__width_1 ff_cmp_io_sync_en |
| 1310 | ( |
| 1311 | .scan_in(ff_cmp_io_sync_en_scanin), |
| 1312 | .scan_out(ff_cmp_io_sync_en_scanout), |
| 1313 | .dout (cmp_io_sync_en_r1), |
| 1314 | .din (cmp_io_sync_en), |
| 1315 | .l1clk (l1clk_cmp), |
| 1316 | .siclk(siclk), |
| 1317 | .soclk(soclk) |
| 1318 | ); |
| 1319 | |
| 1320 | //msff_ctl_macro ff_cmp_io_sync_en_r1 (width=1) |
| 1321 | // ( |
| 1322 | // .scan_in(ff_cmp_io_sync_en_r1_scanin), |
| 1323 | // .scan_out(ff_cmp_io_sync_en_r1_scanout), |
| 1324 | // .dout (cmp_io_sync_en_r2), |
| 1325 | // .din (cmp_io_sync_en_r1), |
| 1326 | // .l1clk (l1clk_cmp), |
| 1327 | // ); |
| 1328 | |
| 1329 | |
| 1330 | assign local_efu_read_start = read_start_sync2 & ~read_start_hist_ff ; |
| 1331 | |
| 1332 | /////////////////////////////////////////////////////////////////// |
| 1333 | |
| 1334 | cl_sc1_clksyncff_4x ff_fuse_bypass_slice |
| 1335 | ( |
| 1336 | .si ( ff_fuse_bypass_slice_scanin ), |
| 1337 | .so ( ff_fuse_bypass_slice_scanout ), |
| 1338 | .l1clk ( l1clk ), |
| 1339 | .d ( tcu_efu_fuse_bypass ), |
| 1340 | .q ( fuse_bypass_sync1 ), |
| 1341 | .siclk(siclk), |
| 1342 | .soclk(soclk) |
| 1343 | ); |
| 1344 | |
| 1345 | cl_sc1_clksyncff_4x ff_fuse_bypass_slice1 |
| 1346 | ( |
| 1347 | .si ( ff_fuse_bypass_slice_1_scanin ), |
| 1348 | .so ( ff_fuse_bypass_slice_1_scanout ), |
| 1349 | .l1clk ( l1clk ), |
| 1350 | .d ( fuse_bypass_sync1 ), |
| 1351 | .q ( fuse_bypass_sync2 ), |
| 1352 | .siclk(siclk), |
| 1353 | .soclk(soclk) |
| 1354 | ); |
| 1355 | |
| 1356 | cl_sc1_clksyncff_4x ff_fuse_bypass_slice2 |
| 1357 | ( |
| 1358 | .si ( ff_fuse_bypass_slice_2_scanin ), |
| 1359 | .so ( ff_fuse_bypass_slice_2_scanout ), |
| 1360 | .l1clk ( l1clk ), |
| 1361 | .d ( fuse_bypass_sync2 ), |
| 1362 | .q ( fuse_bypass_hist_ff ), |
| 1363 | .siclk(siclk), |
| 1364 | .soclk(soclk) |
| 1365 | ); |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | //msff_ctl_macro ff_fuse_bypass_slice (width=3) |
| 1371 | // ( |
| 1372 | // .scan_in(ff_fuse_bypass_slice_scanin), |
| 1373 | // .scan_out(ff_fuse_bypass_slice_scanout), |
| 1374 | // .dout ({fuse_bypass_sync1,fuse_bypass_sync2,fuse_bypass_hist_ff}), |
| 1375 | // .din ({tcu_efu_fuse_bypass,fuse_bypass_sync1,fuse_bypass_sync2}), |
| 1376 | // .l1clk (l1clk), |
| 1377 | // ); |
| 1378 | |
| 1379 | assign local_fuse_bypass = fuse_bypass_sync2 & ~fuse_bypass_hist_ff ; |
| 1380 | |
| 1381 | /////////////////////////////////////////////////////////////////// |
| 1382 | |
| 1383 | cl_sc1_clksyncff_4x ff_dest_sample_slice |
| 1384 | ( |
| 1385 | .si ( ff_dest_sample_slice_scanin ), |
| 1386 | .so ( ff_dest_sample_slice_scanout ), |
| 1387 | .l1clk ( l1clk ), |
| 1388 | .d ( tcu_efu_dest_sample ), |
| 1389 | .q ( dest_sample_sync1 ), |
| 1390 | .siclk(siclk), |
| 1391 | .soclk(soclk) |
| 1392 | ); |
| 1393 | |
| 1394 | cl_sc1_clksyncff_4x ff_dest_sample_slice1 |
| 1395 | ( |
| 1396 | .si ( ff_dest_sample_slice_1_scanin ), |
| 1397 | .so ( ff_dest_sample_slice_1_scanout ), |
| 1398 | .l1clk ( l1clk ), |
| 1399 | .d ( dest_sample_sync1 ), |
| 1400 | .q ( dest_sample_sync2 ), |
| 1401 | .siclk(siclk), |
| 1402 | .soclk(soclk) |
| 1403 | ); |
| 1404 | |
| 1405 | cl_sc1_clksyncff_4x ff_dest_sample_slice2 |
| 1406 | ( |
| 1407 | .si ( ff_dest_sample_slice_2_scanin ), |
| 1408 | .so ( ff_dest_sample_slice_2_scanout ), |
| 1409 | .l1clk ( l1clk ), |
| 1410 | .d ( dest_sample_sync2 ), |
| 1411 | .q ( dest_sample_hist_ff ), |
| 1412 | .siclk(siclk), |
| 1413 | .soclk(soclk) |
| 1414 | ); |
| 1415 | |
| 1416 | |
| 1417 | //msff_ctl_macro ff_dest_sample_slice (width=3) |
| 1418 | // ( |
| 1419 | // .scan_in(ff_dest_sample_slice_scanin), |
| 1420 | // .scan_out(ff_dest_sample_slice_scanout), |
| 1421 | // .dout ({dest_sample_sync1,dest_sample_sync2,dest_sample_hist_ff}), |
| 1422 | // .din ({tcu_efu_dest_sample,dest_sample_sync1,dest_sample_sync2}), |
| 1423 | // .l1clk (l1clk), |
| 1424 | // ); |
| 1425 | |
| 1426 | assign local_dest_sample = dest_sample_sync2 & ~dest_sample_hist_ff ; |
| 1427 | |
| 1428 | /////////////////////////////////////////////////////////////////// |
| 1429 | |
| 1430 | assign w_mux_shift_retain[31:0] = tcu_efu_shiftdr ? {tck_shft_data_ff[30:0], tcu_efu_data_in} : tck_shft_data_ff[31:0] ; |
| 1431 | |
| 1432 | assign tck_shft_data_nxt[31:0] = tcu_efu_capturedr ? read_data_ff[31:0] : w_mux_shift_retain[31:0] ; |
| 1433 | |
| 1434 | efu_fct_ctl_msff_ctl_macro__width_32 ff_tck_shift_data_nxt |
| 1435 | ( |
| 1436 | .scan_in(ff_tck_shift_data_nxt_scanin), |
| 1437 | .scan_out(ff_tck_shift_data_nxt_scanout), |
| 1438 | .dout (tck_shft_data_ff[31:0]), |
| 1439 | .din (tck_shft_data_nxt[31:0]), |
| 1440 | .l1clk (tckl1clk), |
| 1441 | .siclk(siclk), |
| 1442 | .soclk(soclk) |
| 1443 | ); |
| 1444 | |
| 1445 | assign efu_tcu_data_out = tck_shft_data_ff[31] ; |
| 1446 | |
| 1447 | /////////////////////////////////////////////////////////////////// |
| 1448 | |
| 1449 | cl_sc1_clksyncff_4x ff_sync1_rowaddr6_1 |
| 1450 | ( |
| 1451 | .si(ff_sync1_rowaddr_6_1_scanin), |
| 1452 | .so(ff_sync1_rowaddr_6_1_scanout), |
| 1453 | .q (sync_tcu_efu_rowaddr6), |
| 1454 | .d (tcu_efu_rowaddr6_1), |
| 1455 | .l1clk (l1clk), |
| 1456 | .siclk(siclk), |
| 1457 | .soclk(soclk) |
| 1458 | ); |
| 1459 | |
| 1460 | cl_sc1_clksyncff_4x ff_sync1_rowaddr5_1 |
| 1461 | ( |
| 1462 | .si(ff_sync1_rowaddr_5_1_scanin), |
| 1463 | .so(ff_sync1_rowaddr_5_1_scanout), |
| 1464 | .q (sync_tcu_efu_rowaddr5), |
| 1465 | .d (tcu_efu_rowaddr5_1), |
| 1466 | .l1clk (l1clk), |
| 1467 | .siclk(siclk), |
| 1468 | .soclk(soclk) |
| 1469 | ); |
| 1470 | |
| 1471 | cl_sc1_clksyncff_4x ff_sync1_rowaddr4_1 |
| 1472 | ( |
| 1473 | .si(ff_sync1_rowaddr_4_1_scanin), |
| 1474 | .so(ff_sync1_rowaddr_4_1_scanout), |
| 1475 | .q (sync_tcu_efu_rowaddr4), |
| 1476 | .d (tcu_efu_rowaddr4_1), |
| 1477 | .l1clk (l1clk), |
| 1478 | .siclk(siclk), |
| 1479 | .soclk(soclk) |
| 1480 | ); |
| 1481 | |
| 1482 | cl_sc1_clksyncff_4x ff_sync1_rowaddr3_1 |
| 1483 | ( |
| 1484 | .si(ff_sync1_rowaddr_3_1_scanin), |
| 1485 | .so(ff_sync1_rowaddr_3_1_scanout), |
| 1486 | .q (sync_tcu_efu_rowaddr3), |
| 1487 | .d (tcu_efu_rowaddr3_1), |
| 1488 | .l1clk (l1clk), |
| 1489 | .siclk(siclk), |
| 1490 | .soclk(soclk) |
| 1491 | ); |
| 1492 | |
| 1493 | cl_sc1_clksyncff_4x ff_sync1_rowaddr2_1 |
| 1494 | ( |
| 1495 | .si(ff_sync1_rowaddr_2_1_scanin), |
| 1496 | .so(ff_sync1_rowaddr_2_1_scanout), |
| 1497 | .q (sync_tcu_efu_rowaddr2), |
| 1498 | .d (tcu_efu_rowaddr2_1), |
| 1499 | .l1clk (l1clk), |
| 1500 | .siclk(siclk), |
| 1501 | .soclk(soclk) |
| 1502 | ); |
| 1503 | |
| 1504 | cl_sc1_clksyncff_4x ff_sync1_rowaddr1_1 |
| 1505 | ( |
| 1506 | .si(ff_sync1_rowaddr_1_1_scanin), |
| 1507 | .so(ff_sync1_rowaddr_1_1_scanout), |
| 1508 | .q (sync_tcu_efu_rowaddr1), |
| 1509 | .d (tcu_efu_rowaddr1_1), |
| 1510 | .l1clk (l1clk), |
| 1511 | .siclk(siclk), |
| 1512 | .soclk(soclk) |
| 1513 | ); |
| 1514 | |
| 1515 | cl_sc1_clksyncff_4x ff_sync1_rowaddr_1 |
| 1516 | ( |
| 1517 | .si(ff_sync1_rowaddr_0_1_scanin), |
| 1518 | .so(ff_sync1_rowaddr_0_1_scanout), |
| 1519 | .q (sync_tcu_efu_rowaddr0), |
| 1520 | .d (tcu_efu_rowaddr0_1), |
| 1521 | .l1clk (l1clk), |
| 1522 | .siclk(siclk), |
| 1523 | .soclk(soclk) |
| 1524 | ); |
| 1525 | |
| 1526 | cl_sc1_clksyncff_4x ff_sync1_rowaddr6 |
| 1527 | ( |
| 1528 | .si(ff_sync1_rowaddr_6_scanin), |
| 1529 | .so(ff_sync1_rowaddr_6_scanout), |
| 1530 | .q (tcu_efu_rowaddr6_1), |
| 1531 | .d (tcu_efu_rowaddr[6]), |
| 1532 | .l1clk (l1clk), |
| 1533 | .siclk(siclk), |
| 1534 | .soclk(soclk) |
| 1535 | ); |
| 1536 | |
| 1537 | cl_sc1_clksyncff_4x ff_sync1_rowaddr5 |
| 1538 | ( |
| 1539 | .si(ff_sync1_rowaddr_5_scanin), |
| 1540 | .so(ff_sync1_rowaddr_5_scanout), |
| 1541 | .q (tcu_efu_rowaddr5_1), |
| 1542 | .d (tcu_efu_rowaddr[5]), |
| 1543 | .l1clk (l1clk), |
| 1544 | .siclk(siclk), |
| 1545 | .soclk(soclk) |
| 1546 | ); |
| 1547 | |
| 1548 | cl_sc1_clksyncff_4x ff_sync1_rowaddr4 |
| 1549 | ( |
| 1550 | .si(ff_sync1_rowaddr_4_scanin), |
| 1551 | .so(ff_sync1_rowaddr_4_scanout), |
| 1552 | .q (tcu_efu_rowaddr4_1), |
| 1553 | .d (tcu_efu_rowaddr[4]), |
| 1554 | .l1clk (l1clk), |
| 1555 | .siclk(siclk), |
| 1556 | .soclk(soclk) |
| 1557 | ); |
| 1558 | |
| 1559 | cl_sc1_clksyncff_4x ff_sync1_rowaddr3 |
| 1560 | ( |
| 1561 | .si(ff_sync1_rowaddr_3_scanin), |
| 1562 | .so(ff_sync1_rowaddr_3_scanout), |
| 1563 | .q (tcu_efu_rowaddr3_1), |
| 1564 | .d (tcu_efu_rowaddr[3]), |
| 1565 | .l1clk (l1clk), |
| 1566 | .siclk(siclk), |
| 1567 | .soclk(soclk) |
| 1568 | ); |
| 1569 | |
| 1570 | cl_sc1_clksyncff_4x ff_sync1_rowaddr2 |
| 1571 | ( |
| 1572 | .si(ff_sync1_rowaddr_2_scanin), |
| 1573 | .so(ff_sync1_rowaddr_2_scanout), |
| 1574 | .q (tcu_efu_rowaddr2_1), |
| 1575 | .d (tcu_efu_rowaddr[2]), |
| 1576 | .l1clk (l1clk), |
| 1577 | .siclk(siclk), |
| 1578 | .soclk(soclk) |
| 1579 | ); |
| 1580 | |
| 1581 | cl_sc1_clksyncff_4x ff_sync1_rowaddr1 |
| 1582 | ( |
| 1583 | .si(ff_sync1_rowaddr_1_scanin), |
| 1584 | .so(ff_sync1_rowaddr_1_scanout), |
| 1585 | .q (tcu_efu_rowaddr1_1), |
| 1586 | .d (tcu_efu_rowaddr[1]), |
| 1587 | .l1clk (l1clk), |
| 1588 | .siclk(siclk), |
| 1589 | .soclk(soclk) |
| 1590 | ); |
| 1591 | |
| 1592 | cl_sc1_clksyncff_4x ff_sync1_rowaddr |
| 1593 | ( |
| 1594 | .si(ff_sync1_rowaddr_scanin), |
| 1595 | .so(ff_sync1_rowaddr_scanout), |
| 1596 | .q (tcu_efu_rowaddr0_1), |
| 1597 | .d (tcu_efu_rowaddr[0]), |
| 1598 | .l1clk (l1clk), |
| 1599 | .siclk(siclk), |
| 1600 | .soclk(soclk) |
| 1601 | ); |
| 1602 | |
| 1603 | //msff_ctl_macro ff_sync1_rowaddr (width=7) |
| 1604 | // ( |
| 1605 | // .scan_in(ff_sync1_rowaddr_scanin), |
| 1606 | // .scan_out(ff_sync1_rowaddr_scanout), |
| 1607 | // .dout (sync1_rowaddress[6:0]), |
| 1608 | // .din (tcu_efu_rowaddr[6:0]), |
| 1609 | // .l1clk (l1clk), |
| 1610 | // ); |
| 1611 | assign sync1_rowaddress[6:0] = {sync_tcu_efu_rowaddr6, sync_tcu_efu_rowaddr5, sync_tcu_efu_rowaddr4, sync_tcu_efu_rowaddr3, sync_tcu_efu_rowaddr2, sync_tcu_efu_rowaddr1, sync_tcu_efu_rowaddr0}; |
| 1612 | |
| 1613 | /////////////////////////////////////////////////////////////////// |
| 1614 | |
| 1615 | cl_sc1_clksyncff_4x ff_sync1_coladdr4_1 |
| 1616 | ( |
| 1617 | .si(ff_sync1_coladdr_4_1_scanin), |
| 1618 | .so(ff_sync1_coladdr_4_1_scanout), |
| 1619 | .q (sync_tcu_efu_coladdr4), |
| 1620 | .d (tcu_efu_coladdr4_1), |
| 1621 | .l1clk (l1clk), |
| 1622 | .siclk(siclk), |
| 1623 | .soclk(soclk) |
| 1624 | ); |
| 1625 | |
| 1626 | cl_sc1_clksyncff_4x ff_sync1_coladdr3_1 |
| 1627 | ( |
| 1628 | .si(ff_sync1_coladdr_3_1_scanin), |
| 1629 | .so(ff_sync1_coladdr_3_1_scanout), |
| 1630 | .q (sync_tcu_efu_coladdr3), |
| 1631 | .d (tcu_efu_coladdr3_1), |
| 1632 | .l1clk (l1clk), |
| 1633 | .siclk(siclk), |
| 1634 | .soclk(soclk) |
| 1635 | ); |
| 1636 | |
| 1637 | cl_sc1_clksyncff_4x ff_sync1_coladdr2_1 |
| 1638 | ( |
| 1639 | .si(ff_sync1_coladdr_2_1_scanin), |
| 1640 | .so(ff_sync1_coladdr_2_1_scanout), |
| 1641 | .q (sync_tcu_efu_coladdr2), |
| 1642 | .d (tcu_efu_coladdr2_1), |
| 1643 | .l1clk (l1clk), |
| 1644 | .siclk(siclk), |
| 1645 | .soclk(soclk) |
| 1646 | ); |
| 1647 | |
| 1648 | cl_sc1_clksyncff_4x ff_sync1_coladdr1_1 |
| 1649 | ( |
| 1650 | .si(ff_sync1_coladdr_1_1_scanin), |
| 1651 | .so(ff_sync1_coladdr_1_1_scanout), |
| 1652 | .q (sync_tcu_efu_coladdr1), |
| 1653 | .d (tcu_efu_coladdr1_1), |
| 1654 | .l1clk (l1clk), |
| 1655 | .siclk(siclk), |
| 1656 | .soclk(soclk) |
| 1657 | ); |
| 1658 | |
| 1659 | cl_sc1_clksyncff_4x ff_sync1_coladdr_1 |
| 1660 | ( |
| 1661 | .si(ff_sync1_coladdr_0_1_scanin), |
| 1662 | .so(ff_sync1_coladdr_0_1_scanout), |
| 1663 | .q (sync_tcu_efu_coladdr0), |
| 1664 | .d (tcu_efu_coladdr0_1), |
| 1665 | .l1clk (l1clk), |
| 1666 | .siclk(siclk), |
| 1667 | .soclk(soclk) |
| 1668 | ); |
| 1669 | |
| 1670 | cl_sc1_clksyncff_4x ff_sync1_coladdr4 |
| 1671 | ( |
| 1672 | .si(ff_sync1_coladdr_4_scanin), |
| 1673 | .so(ff_sync1_coladdr_4_scanout), |
| 1674 | .q (tcu_efu_coladdr4_1), |
| 1675 | .d (tcu_efu_coladdr[4]), |
| 1676 | .l1clk (l1clk), |
| 1677 | .siclk(siclk), |
| 1678 | .soclk(soclk) |
| 1679 | ); |
| 1680 | |
| 1681 | cl_sc1_clksyncff_4x ff_sync1_coladdr3 |
| 1682 | ( |
| 1683 | .si(ff_sync1_coladdr_3_scanin), |
| 1684 | .so(ff_sync1_coladdr_3_scanout), |
| 1685 | .q (tcu_efu_coladdr3_1), |
| 1686 | .d (tcu_efu_coladdr[3]), |
| 1687 | .l1clk (l1clk), |
| 1688 | .siclk(siclk), |
| 1689 | .soclk(soclk) |
| 1690 | ); |
| 1691 | |
| 1692 | cl_sc1_clksyncff_4x ff_sync1_coladdr2 |
| 1693 | ( |
| 1694 | .si(ff_sync1_coladdr_2_scanin), |
| 1695 | .so(ff_sync1_coladdr_2_scanout), |
| 1696 | .q (tcu_efu_coladdr2_1), |
| 1697 | .d (tcu_efu_coladdr[2]), |
| 1698 | .l1clk (l1clk), |
| 1699 | .siclk(siclk), |
| 1700 | .soclk(soclk) |
| 1701 | ); |
| 1702 | |
| 1703 | cl_sc1_clksyncff_4x ff_sync1_coladdr1 |
| 1704 | ( |
| 1705 | .si(ff_sync1_coladdr_1_scanin), |
| 1706 | .so(ff_sync1_coladdr_1_scanout), |
| 1707 | .q (tcu_efu_coladdr1_1), |
| 1708 | .d (tcu_efu_coladdr[1]), |
| 1709 | .l1clk (l1clk), |
| 1710 | .siclk(siclk), |
| 1711 | .soclk(soclk) |
| 1712 | ); |
| 1713 | |
| 1714 | cl_sc1_clksyncff_4x ff_sync1_coladdr |
| 1715 | ( |
| 1716 | .si(ff_sync1_coladdr_scanin), |
| 1717 | .so(ff_sync1_coladdr_scanout), |
| 1718 | .q (tcu_efu_coladdr0_1), |
| 1719 | .d (tcu_efu_coladdr[0]), |
| 1720 | .l1clk (l1clk), |
| 1721 | .siclk(siclk), |
| 1722 | .soclk(soclk) |
| 1723 | ); |
| 1724 | |
| 1725 | assign sync_tcu_efu_coladdr[4:0] = {sync_tcu_efu_coladdr4, sync_tcu_efu_coladdr3, sync_tcu_efu_coladdr2, sync_tcu_efu_coladdr1, sync_tcu_efu_coladdr0}; |
| 1726 | |
| 1727 | |
| 1728 | |
| 1729 | |
| 1730 | /////////////////////////////////////////////////////////////////// |
| 1731 | |
| 1732 | cl_sc1_clksyncff_4x ff_tcu_efu_read_mode_bit1 |
| 1733 | ( |
| 1734 | .si(ff_tcu_efu_read_mode_bit1_scanin), |
| 1735 | .so(ff_tcu_efu_read_mode_bit1_scanout), |
| 1736 | .q (tcu_efu_read_mode1_1), |
| 1737 | .d (tcu_efu_read_mode[1]), |
| 1738 | .l1clk (l1clk), |
| 1739 | .siclk(siclk), |
| 1740 | .soclk(soclk) |
| 1741 | ); |
| 1742 | |
| 1743 | cl_sc1_clksyncff_4x ff_tcu_efu_read_mode_bit1_1 |
| 1744 | ( |
| 1745 | .si(ff_tcu_efu_read_mode_bit1_1_scanin), |
| 1746 | .so(ff_tcu_efu_read_mode_bit1_1_scanout), |
| 1747 | .q (sync_tcu_efu_read_mode1), |
| 1748 | .d (tcu_efu_read_mode1_1), |
| 1749 | .l1clk (l1clk), |
| 1750 | .siclk(siclk), |
| 1751 | .soclk(soclk) |
| 1752 | ); |
| 1753 | |
| 1754 | cl_sc1_clksyncff_4x ff_tcu_efu_read_mode_bit0 |
| 1755 | ( |
| 1756 | .si(ff_tcu_efu_read_mode_bit0_scanin), |
| 1757 | .so(ff_tcu_efu_read_mode_bit0_scanout), |
| 1758 | .q (tcu_efu_read_mode0_1), |
| 1759 | .d (tcu_efu_read_mode[0]), |
| 1760 | .l1clk (l1clk), |
| 1761 | .siclk(siclk), |
| 1762 | .soclk(soclk) |
| 1763 | ); |
| 1764 | |
| 1765 | cl_sc1_clksyncff_4x ff_tcu_efu_read_mode_bit0_1 |
| 1766 | ( |
| 1767 | .si(ff_tcu_efu_read_mode_bit0_1_scanin), |
| 1768 | .so(ff_tcu_efu_read_mode_bit0_1_scanout), |
| 1769 | .q (sync_tcu_efu_read_mode0), |
| 1770 | .d (tcu_efu_read_mode0_1), |
| 1771 | .l1clk (l1clk), |
| 1772 | .siclk(siclk), |
| 1773 | .soclk(soclk) |
| 1774 | ); |
| 1775 | |
| 1776 | assign sync_tcu_efu_read_mode[1:0] = {sync_tcu_efu_read_mode1, sync_tcu_efu_read_mode0}; |
| 1777 | |
| 1778 | /////////////////////////////////////////////////////////////////// |
| 1779 | |
| 1780 | cl_sc1_clksyncff_4x ff_power_down_sync_slice |
| 1781 | ( |
| 1782 | .si(ff_power_down_sync_slice_scanin), |
| 1783 | .so(ff_power_down_sync_slice_scanout), |
| 1784 | .q (inhibit_power_down_sync_l), |
| 1785 | .d (tcu_efu_read_mode[2]), |
| 1786 | .l1clk (l1clk), |
| 1787 | .siclk(siclk), |
| 1788 | .soclk(soclk) |
| 1789 | ); |
| 1790 | |
| 1791 | cl_sc1_clksyncff_4x ff_power_down_sync_slice1 |
| 1792 | ( |
| 1793 | .si(ff_power_down_sync_slice_1_scanin), |
| 1794 | .so(ff_power_down_sync_slice_1_scanout), |
| 1795 | .q (inhibit_power_down_l), |
| 1796 | .d (inhibit_power_down_sync_l), |
| 1797 | .l1clk (l1clk), |
| 1798 | .siclk(siclk), |
| 1799 | .soclk(soclk) |
| 1800 | ); |
| 1801 | |
| 1802 | //msff_ctl_macro ff_power_down_sync_slice (width=2) |
| 1803 | // ( |
| 1804 | // .scan_in(ff_power_down_sync_slice_scanin), |
| 1805 | // .scan_out(ff_power_down_sync_slice_scanout), |
| 1806 | // .dout ({inhibit_power_down_sync_l,inhibit_power_down_l}), |
| 1807 | // .din ({tcu_efu_read_mode[2],inhibit_power_down_sync_l}), |
| 1808 | // .l1clk (l1clk), |
| 1809 | // ); |
| 1810 | |
| 1811 | /////////////////////////////////////////////////////////////////// |
| 1812 | |
| 1813 | efu_fct_ctl_spare_ctl_macro__num_4 spares ( |
| 1814 | .scan_in(spares_scanin), |
| 1815 | .scan_out(spares_scanout), |
| 1816 | .l1clk (l1clk), |
| 1817 | .siclk(siclk), |
| 1818 | .soclk(soclk) |
| 1819 | ); |
| 1820 | |
| 1821 | // ioclk |
| 1822 | assign {sbc_efa_margin1_rd, sbc_efa_margin0_rd} = sync_tcu_efu_read_mode[1:0]; |
| 1823 | // ioclk |
| 1824 | assign sbc_efa_sup_det_rd = addr_cnt_ff[6]; |
| 1825 | // ioclk |
| 1826 | assign sbc_efa_word_addr[5:0] = addr_cnt_ff[5:0]; |
| 1827 | // ioclk |
| 1828 | assign sbc_efa_bit_addr[4:0] = sync_tcu_efu_coladdr[4:0]; |
| 1829 | // ioclk |
| 1830 | assign sbc_efa_power_down = efa_array_power_down_ff; |
| 1831 | // ioclk |
| 1832 | assign efa_out_data[31:0] = efa_sbc_data[31:0]; |
| 1833 | // ioclk |
| 1834 | assign sbc_efa_read_en = mrd_state_rd_array; // & testmode_l; |
| 1835 | |
| 1836 | assign ff_pulse_read_data_ff_vld_scanin = scan_in; |
| 1837 | assign mrd_63_to_0_ff_scanin = ff_pulse_read_data_ff_vld_scanout; |
| 1838 | assign ff_mrd_zero_scanin = mrd_63_to_0_ff_scanout; |
| 1839 | assign enable_efa_por_reg_scanin = ff_mrd_zero_scanout ; |
| 1840 | assign efa_array_power_down_reg_scanin = enable_efa_por_reg_scanout; |
| 1841 | assign seq_state_reg_scanin = efa_array_power_down_reg_scanout; |
| 1842 | assign addr_cnt_reg_scanin = seq_state_reg_scanout ; |
| 1843 | assign mrd_state_reg_scanin = addr_cnt_reg_scanout ; |
| 1844 | assign mrd_cnt_reg_scanin = mrd_state_reg_scanout ; |
| 1845 | assign read_data_reg_scanin = mrd_cnt_reg_scanout ; |
| 1846 | assign l2rd_id_reg_scanin = read_data_reg_scanout ; |
| 1847 | assign rslt_status_reg_scanin = l2rd_id_reg_scanout ; |
| 1848 | assign local_fuse_data_reg_scanin = rslt_status_reg_scanout ; |
| 1849 | assign ncu_coreavail_dshift_reg_scanin = local_fuse_data_reg_scanout; |
| 1850 | assign ncu_bankavail_dshift_reg_scanin = ncu_coreavail_dshift_reg_scanout; |
| 1851 | assign ncu_sernum0_dshift_reg_scanin = ncu_bankavail_dshift_reg_scanout; |
| 1852 | assign ncu_sernum1_dshift_reg_scanin = ncu_sernum0_dshift_reg_scanout; |
| 1853 | assign ncu_sernum2_dshift_reg_scanin = ncu_sernum1_dshift_reg_scanout; |
| 1854 | assign ncu_fusestat_dshift_reg_scanin = ncu_sernum2_dshift_reg_scanout; |
| 1855 | assign ff_updtdr_slice_scanin = ncu_fusestat_dshift_reg_scanout; |
| 1856 | assign ff_updtdr_slice1_scanin = ff_updtdr_slice_scanout; |
| 1857 | assign ff_updtdr_slice2_scanin = ff_updtdr_slice1_scanout; |
| 1858 | assign ff_read_en_slice_scanin = ff_updtdr_slice2_scanout; |
| 1859 | assign ff_read_en_slice1_scanin = ff_read_en_slice_scanout; |
| 1860 | assign ff_read_en_slice2_scanin = ff_read_en_slice1_scanout; |
| 1861 | |
| 1862 | //assign ff_fuse_bypass_slice_scanin = ff_read_start_slice_scanout ; |
| 1863 | //assign ff_read_start_2_slice_scanin = ff_read_en_slice_scanout; |
| 1864 | |
| 1865 | assign ff_read_start_1_slice_scanin = ff_read_en_slice2_scanout; |
| 1866 | assign ff_read_start_0_slice_scanin = ff_read_start_1_slice_scanout; |
| 1867 | |
| 1868 | assign ff_fuse_bypass_slice_scanin = ff_read_start_0_slice_scanout ; |
| 1869 | assign ff_fuse_bypass_slice_1_scanin = ff_fuse_bypass_slice_scanout; |
| 1870 | assign ff_fuse_bypass_slice_2_scanin = ff_fuse_bypass_slice_1_scanout; |
| 1871 | assign ff_dest_sample_slice_scanin = ff_fuse_bypass_slice_2_scanout; |
| 1872 | assign ff_dest_sample_slice_1_scanin = ff_dest_sample_slice_scanout; |
| 1873 | assign ff_dest_sample_slice_2_scanin = ff_dest_sample_slice_1_scanout; |
| 1874 | assign ff_tck_shift_data_nxt_scanin = ff_dest_sample_slice_2_scanout; |
| 1875 | assign ff_sync1_coladdr_4_1_scanin = ff_tck_shift_data_nxt_scanout; |
| 1876 | assign ff_sync1_coladdr_3_1_scanin = ff_sync1_coladdr_4_1_scanout; |
| 1877 | assign ff_sync1_coladdr_2_1_scanin = ff_sync1_coladdr_3_1_scanout; |
| 1878 | assign ff_sync1_coladdr_1_1_scanin = ff_sync1_coladdr_2_1_scanout; |
| 1879 | assign ff_sync1_coladdr_0_1_scanin = ff_sync1_coladdr_1_1_scanout; |
| 1880 | assign ff_sync1_coladdr_4_scanin = ff_sync1_coladdr_0_1_scanout; |
| 1881 | assign ff_sync1_coladdr_3_scanin = ff_sync1_coladdr_4_scanout; |
| 1882 | assign ff_sync1_coladdr_2_scanin = ff_sync1_coladdr_3_scanout; |
| 1883 | assign ff_sync1_coladdr_1_scanin = ff_sync1_coladdr_2_scanout; |
| 1884 | assign ff_sync1_coladdr_scanin = ff_sync1_coladdr_1_scanout; |
| 1885 | assign ff_sync1_rowaddr_scanin = ff_sync1_coladdr_scanout; |
| 1886 | assign ff_sync1_rowaddr_6_scanin = ff_sync1_rowaddr_scanout; |
| 1887 | assign ff_sync1_rowaddr_5_scanin = ff_sync1_rowaddr_6_scanout; |
| 1888 | assign ff_sync1_rowaddr_4_scanin = ff_sync1_rowaddr_5_scanout; |
| 1889 | assign ff_sync1_rowaddr_3_scanin = ff_sync1_rowaddr_4_scanout; |
| 1890 | assign ff_sync1_rowaddr_2_scanin = ff_sync1_rowaddr_3_scanout; |
| 1891 | assign ff_sync1_rowaddr_1_scanin = ff_sync1_rowaddr_2_scanout; |
| 1892 | assign ff_sync1_rowaddr_6_1_scanin = ff_sync1_rowaddr_1_scanout; |
| 1893 | assign ff_sync1_rowaddr_5_1_scanin = ff_sync1_rowaddr_6_1_scanout; |
| 1894 | assign ff_sync1_rowaddr_4_1_scanin = ff_sync1_rowaddr_5_1_scanout; |
| 1895 | assign ff_sync1_rowaddr_3_1_scanin = ff_sync1_rowaddr_4_1_scanout; |
| 1896 | assign ff_sync1_rowaddr_2_1_scanin = ff_sync1_rowaddr_3_1_scanout; |
| 1897 | assign ff_sync1_rowaddr_1_1_scanin = ff_sync1_rowaddr_2_1_scanout; |
| 1898 | assign ff_sync1_rowaddr_0_1_scanin = ff_sync1_rowaddr_1_1_scanout; |
| 1899 | assign ff_power_down_sync_slice_scanin = ff_sync1_rowaddr_0_1_scanout; |
| 1900 | assign ff_power_down_sync_slice_1_scanin = ff_power_down_sync_slice_scanout; |
| 1901 | assign ff_cmp_io_sync_en_scanin = ff_power_down_sync_slice_1_scanout; |
| 1902 | assign ff_tcu_efu_read_mode_bit1_scanin = ff_cmp_io_sync_en_scanout; |
| 1903 | assign ff_tcu_efu_read_mode_bit1_1_scanin = ff_tcu_efu_read_mode_bit1_scanout; |
| 1904 | assign ff_tcu_efu_read_mode_bit0_scanin = ff_tcu_efu_read_mode_bit1_1_scanout; |
| 1905 | assign ff_tcu_efu_read_mode_bit0_1_scanin = ff_tcu_efu_read_mode_bit0_scanout; |
| 1906 | assign spares_scanin = ff_tcu_efu_read_mode_bit0_1_scanout; |
| 1907 | |
| 1908 | //assign ff_cmp_io_sync_en_r1_scanin = ff_cmp_io_sync_en_scanout; |
| 1909 | //assign spares_scanin = ff_cmp_io_sync_en_r1_scanout; |
| 1910 | |
| 1911 | assign scan_out = spares_scanout; |
| 1912 | endmodule |
| 1913 | |
| 1914 | |
| 1915 | |
| 1916 | |
| 1917 | |
| 1918 | |
| 1919 | // any PARAMS parms go into naming of macro |
| 1920 | |
| 1921 | module efu_fct_ctl_l1clkhdr_ctl_macro ( |
| 1922 | l2clk, |
| 1923 | l1en, |
| 1924 | pce_ov, |
| 1925 | stop, |
| 1926 | se, |
| 1927 | l1clk); |
| 1928 | |
| 1929 | |
| 1930 | input l2clk; |
| 1931 | input l1en; |
| 1932 | input pce_ov; |
| 1933 | input stop; |
| 1934 | input se; |
| 1935 | output l1clk; |
| 1936 | |
| 1937 | |
| 1938 | |
| 1939 | |
| 1940 | |
| 1941 | cl_sc1_l1hdr_8x c_0 ( |
| 1942 | |
| 1943 | |
| 1944 | .l2clk(l2clk), |
| 1945 | .pce(l1en), |
| 1946 | .l1clk(l1clk), |
| 1947 | .se(se), |
| 1948 | .pce_ov(pce_ov), |
| 1949 | .stop(stop) |
| 1950 | ); |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | endmodule |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | // any PARAMS parms go into naming of macro |
| 1969 | |
| 1970 | module efu_fct_ctl_msff_ctl_macro__width_1 ( |
| 1971 | din, |
| 1972 | l1clk, |
| 1973 | scan_in, |
| 1974 | siclk, |
| 1975 | soclk, |
| 1976 | dout, |
| 1977 | scan_out); |
| 1978 | wire [0:0] fdin; |
| 1979 | |
| 1980 | input [0:0] din; |
| 1981 | input l1clk; |
| 1982 | input scan_in; |
| 1983 | |
| 1984 | |
| 1985 | input siclk; |
| 1986 | input soclk; |
| 1987 | |
| 1988 | output [0:0] dout; |
| 1989 | output scan_out; |
| 1990 | assign fdin[0:0] = din[0:0]; |
| 1991 | |
| 1992 | |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | dff #(1) d0_0 ( |
| 1998 | .l1clk(l1clk), |
| 1999 | .siclk(siclk), |
| 2000 | .soclk(soclk), |
| 2001 | .d(fdin[0:0]), |
| 2002 | .si(scan_in), |
| 2003 | .so(scan_out), |
| 2004 | .q(dout[0:0]) |
| 2005 | ); |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | endmodule |
| 2019 | |
| 2020 | |
| 2021 | |
| 2022 | |
| 2023 | |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | |
| 2031 | |
| 2032 | // any PARAMS parms go into naming of macro |
| 2033 | |
| 2034 | module efu_fct_ctl_msff_ctl_macro__width_4 ( |
| 2035 | din, |
| 2036 | l1clk, |
| 2037 | scan_in, |
| 2038 | siclk, |
| 2039 | soclk, |
| 2040 | dout, |
| 2041 | scan_out); |
| 2042 | wire [3:0] fdin; |
| 2043 | wire [2:0] so; |
| 2044 | |
| 2045 | input [3:0] din; |
| 2046 | input l1clk; |
| 2047 | input scan_in; |
| 2048 | |
| 2049 | |
| 2050 | input siclk; |
| 2051 | input soclk; |
| 2052 | |
| 2053 | output [3:0] dout; |
| 2054 | output scan_out; |
| 2055 | assign fdin[3:0] = din[3:0]; |
| 2056 | |
| 2057 | |
| 2058 | |
| 2059 | |
| 2060 | |
| 2061 | |
| 2062 | dff #(4) d0_0 ( |
| 2063 | .l1clk(l1clk), |
| 2064 | .siclk(siclk), |
| 2065 | .soclk(soclk), |
| 2066 | .d(fdin[3:0]), |
| 2067 | .si({scan_in,so[2:0]}), |
| 2068 | .so({so[2:0],scan_out}), |
| 2069 | .q(dout[3:0]) |
| 2070 | ); |
| 2071 | |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | endmodule |
| 2084 | |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | // any PARAMS parms go into naming of macro |
| 2098 | |
| 2099 | module efu_fct_ctl_msff_ctl_macro__en_1__width_7 ( |
| 2100 | din, |
| 2101 | en, |
| 2102 | l1clk, |
| 2103 | scan_in, |
| 2104 | siclk, |
| 2105 | soclk, |
| 2106 | dout, |
| 2107 | scan_out); |
| 2108 | wire [6:0] fdin; |
| 2109 | wire [5:0] so; |
| 2110 | |
| 2111 | input [6:0] din; |
| 2112 | input en; |
| 2113 | input l1clk; |
| 2114 | input scan_in; |
| 2115 | |
| 2116 | |
| 2117 | input siclk; |
| 2118 | input soclk; |
| 2119 | |
| 2120 | output [6:0] dout; |
| 2121 | output scan_out; |
| 2122 | assign fdin[6:0] = (din[6:0] & {7{en}}) | (dout[6:0] & ~{7{en}}); |
| 2123 | |
| 2124 | |
| 2125 | |
| 2126 | |
| 2127 | |
| 2128 | |
| 2129 | dff #(7) d0_0 ( |
| 2130 | .l1clk(l1clk), |
| 2131 | .siclk(siclk), |
| 2132 | .soclk(soclk), |
| 2133 | .d(fdin[6:0]), |
| 2134 | .si({scan_in,so[5:0]}), |
| 2135 | .so({so[5:0],scan_out}), |
| 2136 | .q(dout[6:0]) |
| 2137 | ); |
| 2138 | |
| 2139 | |
| 2140 | |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | |
| 2146 | |
| 2147 | |
| 2148 | |
| 2149 | |
| 2150 | endmodule |
| 2151 | |
| 2152 | |
| 2153 | |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | |
| 2163 | |
| 2164 | // any PARAMS parms go into naming of macro |
| 2165 | |
| 2166 | module efu_fct_ctl_msff_ctl_macro__width_3 ( |
| 2167 | din, |
| 2168 | l1clk, |
| 2169 | scan_in, |
| 2170 | siclk, |
| 2171 | soclk, |
| 2172 | dout, |
| 2173 | scan_out); |
| 2174 | wire [2:0] fdin; |
| 2175 | wire [1:0] so; |
| 2176 | |
| 2177 | input [2:0] din; |
| 2178 | input l1clk; |
| 2179 | input scan_in; |
| 2180 | |
| 2181 | |
| 2182 | input siclk; |
| 2183 | input soclk; |
| 2184 | |
| 2185 | output [2:0] dout; |
| 2186 | output scan_out; |
| 2187 | assign fdin[2:0] = din[2:0]; |
| 2188 | |
| 2189 | |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | |
| 2194 | dff #(3) d0_0 ( |
| 2195 | .l1clk(l1clk), |
| 2196 | .siclk(siclk), |
| 2197 | .soclk(soclk), |
| 2198 | .d(fdin[2:0]), |
| 2199 | .si({scan_in,so[1:0]}), |
| 2200 | .so({so[1:0],scan_out}), |
| 2201 | .q(dout[2:0]) |
| 2202 | ); |
| 2203 | |
| 2204 | |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | |
| 2212 | |
| 2213 | |
| 2214 | |
| 2215 | endmodule |
| 2216 | |
| 2217 | |
| 2218 | |
| 2219 | |
| 2220 | |
| 2221 | |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | |
| 2226 | |
| 2227 | |
| 2228 | |
| 2229 | // any PARAMS parms go into naming of macro |
| 2230 | |
| 2231 | module efu_fct_ctl_msff_ctl_macro__width_9 ( |
| 2232 | din, |
| 2233 | l1clk, |
| 2234 | scan_in, |
| 2235 | siclk, |
| 2236 | soclk, |
| 2237 | dout, |
| 2238 | scan_out); |
| 2239 | wire [8:0] fdin; |
| 2240 | wire [7:0] so; |
| 2241 | |
| 2242 | input [8:0] din; |
| 2243 | input l1clk; |
| 2244 | input scan_in; |
| 2245 | |
| 2246 | |
| 2247 | input siclk; |
| 2248 | input soclk; |
| 2249 | |
| 2250 | output [8:0] dout; |
| 2251 | output scan_out; |
| 2252 | assign fdin[8:0] = din[8:0]; |
| 2253 | |
| 2254 | |
| 2255 | |
| 2256 | |
| 2257 | |
| 2258 | |
| 2259 | dff #(9) d0_0 ( |
| 2260 | .l1clk(l1clk), |
| 2261 | .siclk(siclk), |
| 2262 | .soclk(soclk), |
| 2263 | .d(fdin[8:0]), |
| 2264 | .si({scan_in,so[7:0]}), |
| 2265 | .so({so[7:0],scan_out}), |
| 2266 | .q(dout[8:0]) |
| 2267 | ); |
| 2268 | |
| 2269 | |
| 2270 | |
| 2271 | |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | |
| 2277 | |
| 2278 | |
| 2279 | |
| 2280 | endmodule |
| 2281 | |
| 2282 | |
| 2283 | |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | |
| 2289 | |
| 2290 | |
| 2291 | |
| 2292 | |
| 2293 | |
| 2294 | // any PARAMS parms go into naming of macro |
| 2295 | |
| 2296 | module efu_fct_ctl_msff_ctl_macro__en_1__width_32 ( |
| 2297 | din, |
| 2298 | en, |
| 2299 | l1clk, |
| 2300 | scan_in, |
| 2301 | siclk, |
| 2302 | soclk, |
| 2303 | dout, |
| 2304 | scan_out); |
| 2305 | wire [31:0] fdin; |
| 2306 | wire [30:0] so; |
| 2307 | |
| 2308 | input [31:0] din; |
| 2309 | input en; |
| 2310 | input l1clk; |
| 2311 | input scan_in; |
| 2312 | |
| 2313 | |
| 2314 | input siclk; |
| 2315 | input soclk; |
| 2316 | |
| 2317 | output [31:0] dout; |
| 2318 | output scan_out; |
| 2319 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); |
| 2320 | |
| 2321 | |
| 2322 | |
| 2323 | |
| 2324 | |
| 2325 | |
| 2326 | dff #(32) d0_0 ( |
| 2327 | .l1clk(l1clk), |
| 2328 | .siclk(siclk), |
| 2329 | .soclk(soclk), |
| 2330 | .d(fdin[31:0]), |
| 2331 | .si({scan_in,so[30:0]}), |
| 2332 | .so({so[30:0],scan_out}), |
| 2333 | .q(dout[31:0]) |
| 2334 | ); |
| 2335 | |
| 2336 | |
| 2337 | |
| 2338 | |
| 2339 | |
| 2340 | |
| 2341 | |
| 2342 | |
| 2343 | |
| 2344 | |
| 2345 | |
| 2346 | |
| 2347 | endmodule |
| 2348 | |
| 2349 | |
| 2350 | |
| 2351 | |
| 2352 | |
| 2353 | |
| 2354 | |
| 2355 | |
| 2356 | |
| 2357 | |
| 2358 | |
| 2359 | |
| 2360 | |
| 2361 | // any PARAMS parms go into naming of macro |
| 2362 | |
| 2363 | module efu_fct_ctl_msff_ctl_macro__en_1__width_3 ( |
| 2364 | din, |
| 2365 | en, |
| 2366 | l1clk, |
| 2367 | scan_in, |
| 2368 | siclk, |
| 2369 | soclk, |
| 2370 | dout, |
| 2371 | scan_out); |
| 2372 | wire [2:0] fdin; |
| 2373 | wire [1:0] so; |
| 2374 | |
| 2375 | input [2:0] din; |
| 2376 | input en; |
| 2377 | input l1clk; |
| 2378 | input scan_in; |
| 2379 | |
| 2380 | |
| 2381 | input siclk; |
| 2382 | input soclk; |
| 2383 | |
| 2384 | output [2:0] dout; |
| 2385 | output scan_out; |
| 2386 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | |
| 2391 | |
| 2392 | |
| 2393 | dff #(3) d0_0 ( |
| 2394 | .l1clk(l1clk), |
| 2395 | .siclk(siclk), |
| 2396 | .soclk(soclk), |
| 2397 | .d(fdin[2:0]), |
| 2398 | .si({scan_in,so[1:0]}), |
| 2399 | .so({so[1:0],scan_out}), |
| 2400 | .q(dout[2:0]) |
| 2401 | ); |
| 2402 | |
| 2403 | |
| 2404 | |
| 2405 | |
| 2406 | |
| 2407 | |
| 2408 | |
| 2409 | |
| 2410 | |
| 2411 | |
| 2412 | |
| 2413 | |
| 2414 | endmodule |
| 2415 | |
| 2416 | |
| 2417 | |
| 2418 | |
| 2419 | |
| 2420 | |
| 2421 | |
| 2422 | |
| 2423 | |
| 2424 | |
| 2425 | |
| 2426 | |
| 2427 | |
| 2428 | // any PARAMS parms go into naming of macro |
| 2429 | |
| 2430 | module efu_fct_ctl_msff_ctl_macro__width_64 ( |
| 2431 | din, |
| 2432 | l1clk, |
| 2433 | scan_in, |
| 2434 | siclk, |
| 2435 | soclk, |
| 2436 | dout, |
| 2437 | scan_out); |
| 2438 | wire [63:0] fdin; |
| 2439 | wire [62:0] so; |
| 2440 | |
| 2441 | input [63:0] din; |
| 2442 | input l1clk; |
| 2443 | input scan_in; |
| 2444 | |
| 2445 | |
| 2446 | input siclk; |
| 2447 | input soclk; |
| 2448 | |
| 2449 | output [63:0] dout; |
| 2450 | output scan_out; |
| 2451 | assign fdin[63:0] = din[63:0]; |
| 2452 | |
| 2453 | |
| 2454 | |
| 2455 | |
| 2456 | |
| 2457 | |
| 2458 | dff #(64) d0_0 ( |
| 2459 | .l1clk(l1clk), |
| 2460 | .siclk(siclk), |
| 2461 | .soclk(soclk), |
| 2462 | .d(fdin[63:0]), |
| 2463 | .si({scan_in,so[62:0]}), |
| 2464 | .so({so[62:0],scan_out}), |
| 2465 | .q(dout[63:0]) |
| 2466 | ); |
| 2467 | |
| 2468 | |
| 2469 | |
| 2470 | |
| 2471 | |
| 2472 | |
| 2473 | |
| 2474 | |
| 2475 | |
| 2476 | |
| 2477 | |
| 2478 | |
| 2479 | endmodule |
| 2480 | |
| 2481 | |
| 2482 | |
| 2483 | |
| 2484 | |
| 2485 | |
| 2486 | |
| 2487 | |
| 2488 | |
| 2489 | |
| 2490 | |
| 2491 | |
| 2492 | |
| 2493 | // any PARAMS parms go into naming of macro |
| 2494 | |
| 2495 | module efu_fct_ctl_msff_ctl_macro__en_1__width_1 ( |
| 2496 | din, |
| 2497 | en, |
| 2498 | l1clk, |
| 2499 | scan_in, |
| 2500 | siclk, |
| 2501 | soclk, |
| 2502 | dout, |
| 2503 | scan_out); |
| 2504 | wire [0:0] fdin; |
| 2505 | |
| 2506 | input [0:0] din; |
| 2507 | input en; |
| 2508 | input l1clk; |
| 2509 | input scan_in; |
| 2510 | |
| 2511 | |
| 2512 | input siclk; |
| 2513 | input soclk; |
| 2514 | |
| 2515 | output [0:0] dout; |
| 2516 | output scan_out; |
| 2517 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 2518 | |
| 2519 | |
| 2520 | |
| 2521 | |
| 2522 | |
| 2523 | |
| 2524 | dff #(1) d0_0 ( |
| 2525 | .l1clk(l1clk), |
| 2526 | .siclk(siclk), |
| 2527 | .soclk(soclk), |
| 2528 | .d(fdin[0:0]), |
| 2529 | .si(scan_in), |
| 2530 | .so(scan_out), |
| 2531 | .q(dout[0:0]) |
| 2532 | ); |
| 2533 | |
| 2534 | |
| 2535 | |
| 2536 | |
| 2537 | |
| 2538 | |
| 2539 | |
| 2540 | |
| 2541 | |
| 2542 | |
| 2543 | |
| 2544 | |
| 2545 | endmodule |
| 2546 | |
| 2547 | |
| 2548 | |
| 2549 | |
| 2550 | |
| 2551 | |
| 2552 | |
| 2553 | |
| 2554 | |
| 2555 | |
| 2556 | |
| 2557 | |
| 2558 | |
| 2559 | // any PARAMS parms go into naming of macro |
| 2560 | |
| 2561 | module efu_fct_ctl_msff_ctl_macro__width_32 ( |
| 2562 | din, |
| 2563 | l1clk, |
| 2564 | scan_in, |
| 2565 | siclk, |
| 2566 | soclk, |
| 2567 | dout, |
| 2568 | scan_out); |
| 2569 | wire [31:0] fdin; |
| 2570 | wire [30:0] so; |
| 2571 | |
| 2572 | input [31:0] din; |
| 2573 | input l1clk; |
| 2574 | input scan_in; |
| 2575 | |
| 2576 | |
| 2577 | input siclk; |
| 2578 | input soclk; |
| 2579 | |
| 2580 | output [31:0] dout; |
| 2581 | output scan_out; |
| 2582 | assign fdin[31:0] = din[31:0]; |
| 2583 | |
| 2584 | |
| 2585 | |
| 2586 | |
| 2587 | |
| 2588 | |
| 2589 | dff #(32) d0_0 ( |
| 2590 | .l1clk(l1clk), |
| 2591 | .siclk(siclk), |
| 2592 | .soclk(soclk), |
| 2593 | .d(fdin[31:0]), |
| 2594 | .si({scan_in,so[30:0]}), |
| 2595 | .so({so[30:0],scan_out}), |
| 2596 | .q(dout[31:0]) |
| 2597 | ); |
| 2598 | |
| 2599 | |
| 2600 | |
| 2601 | |
| 2602 | |
| 2603 | |
| 2604 | |
| 2605 | |
| 2606 | |
| 2607 | |
| 2608 | |
| 2609 | |
| 2610 | endmodule |
| 2611 | |
| 2612 | |
| 2613 | |
| 2614 | |
| 2615 | |
| 2616 | |
| 2617 | |
| 2618 | |
| 2619 | |
| 2620 | // Description: Spare gate macro for control blocks |
| 2621 | // |
| 2622 | // Param num controls the number of times the macro is added |
| 2623 | // flops=0 can be used to use only combination spare logic |
| 2624 | |
| 2625 | |
| 2626 | module efu_fct_ctl_spare_ctl_macro__num_4 ( |
| 2627 | l1clk, |
| 2628 | scan_in, |
| 2629 | siclk, |
| 2630 | soclk, |
| 2631 | scan_out); |
| 2632 | wire si_0; |
| 2633 | wire so_0; |
| 2634 | wire spare0_flop_unused; |
| 2635 | wire spare0_buf_32x_unused; |
| 2636 | wire spare0_nand3_8x_unused; |
| 2637 | wire spare0_inv_8x_unused; |
| 2638 | wire spare0_aoi22_4x_unused; |
| 2639 | wire spare0_buf_8x_unused; |
| 2640 | wire spare0_oai22_4x_unused; |
| 2641 | wire spare0_inv_16x_unused; |
| 2642 | wire spare0_nand2_16x_unused; |
| 2643 | wire spare0_nor3_4x_unused; |
| 2644 | wire spare0_nand2_8x_unused; |
| 2645 | wire spare0_buf_16x_unused; |
| 2646 | wire spare0_nor2_16x_unused; |
| 2647 | wire spare0_inv_32x_unused; |
| 2648 | wire si_1; |
| 2649 | wire so_1; |
| 2650 | wire spare1_flop_unused; |
| 2651 | wire spare1_buf_32x_unused; |
| 2652 | wire spare1_nand3_8x_unused; |
| 2653 | wire spare1_inv_8x_unused; |
| 2654 | wire spare1_aoi22_4x_unused; |
| 2655 | wire spare1_buf_8x_unused; |
| 2656 | wire spare1_oai22_4x_unused; |
| 2657 | wire spare1_inv_16x_unused; |
| 2658 | wire spare1_nand2_16x_unused; |
| 2659 | wire spare1_nor3_4x_unused; |
| 2660 | wire spare1_nand2_8x_unused; |
| 2661 | wire spare1_buf_16x_unused; |
| 2662 | wire spare1_nor2_16x_unused; |
| 2663 | wire spare1_inv_32x_unused; |
| 2664 | wire si_2; |
| 2665 | wire so_2; |
| 2666 | wire spare2_flop_unused; |
| 2667 | wire spare2_buf_32x_unused; |
| 2668 | wire spare2_nand3_8x_unused; |
| 2669 | wire spare2_inv_8x_unused; |
| 2670 | wire spare2_aoi22_4x_unused; |
| 2671 | wire spare2_buf_8x_unused; |
| 2672 | wire spare2_oai22_4x_unused; |
| 2673 | wire spare2_inv_16x_unused; |
| 2674 | wire spare2_nand2_16x_unused; |
| 2675 | wire spare2_nor3_4x_unused; |
| 2676 | wire spare2_nand2_8x_unused; |
| 2677 | wire spare2_buf_16x_unused; |
| 2678 | wire spare2_nor2_16x_unused; |
| 2679 | wire spare2_inv_32x_unused; |
| 2680 | wire si_3; |
| 2681 | wire so_3; |
| 2682 | wire spare3_flop_unused; |
| 2683 | wire spare3_buf_32x_unused; |
| 2684 | wire spare3_nand3_8x_unused; |
| 2685 | wire spare3_inv_8x_unused; |
| 2686 | wire spare3_aoi22_4x_unused; |
| 2687 | wire spare3_buf_8x_unused; |
| 2688 | wire spare3_oai22_4x_unused; |
| 2689 | wire spare3_inv_16x_unused; |
| 2690 | wire spare3_nand2_16x_unused; |
| 2691 | wire spare3_nor3_4x_unused; |
| 2692 | wire spare3_nand2_8x_unused; |
| 2693 | wire spare3_buf_16x_unused; |
| 2694 | wire spare3_nor2_16x_unused; |
| 2695 | wire spare3_inv_32x_unused; |
| 2696 | |
| 2697 | |
| 2698 | input l1clk; |
| 2699 | input scan_in; |
| 2700 | input siclk; |
| 2701 | input soclk; |
| 2702 | output scan_out; |
| 2703 | |
| 2704 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 2705 | .siclk(siclk), |
| 2706 | .soclk(soclk), |
| 2707 | .si(si_0), |
| 2708 | .so(so_0), |
| 2709 | .d(1'b0), |
| 2710 | .q(spare0_flop_unused)); |
| 2711 | assign si_0 = scan_in; |
| 2712 | |
| 2713 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 2714 | .out(spare0_buf_32x_unused)); |
| 2715 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 2716 | .in1(1'b1), |
| 2717 | .in2(1'b1), |
| 2718 | .out(spare0_nand3_8x_unused)); |
| 2719 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 2720 | .out(spare0_inv_8x_unused)); |
| 2721 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 2722 | .in01(1'b1), |
| 2723 | .in10(1'b1), |
| 2724 | .in11(1'b1), |
| 2725 | .out(spare0_aoi22_4x_unused)); |
| 2726 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 2727 | .out(spare0_buf_8x_unused)); |
| 2728 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 2729 | .in01(1'b1), |
| 2730 | .in10(1'b1), |
| 2731 | .in11(1'b1), |
| 2732 | .out(spare0_oai22_4x_unused)); |
| 2733 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 2734 | .out(spare0_inv_16x_unused)); |
| 2735 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 2736 | .in1(1'b1), |
| 2737 | .out(spare0_nand2_16x_unused)); |
| 2738 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 2739 | .in1(1'b0), |
| 2740 | .in2(1'b0), |
| 2741 | .out(spare0_nor3_4x_unused)); |
| 2742 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 2743 | .in1(1'b1), |
| 2744 | .out(spare0_nand2_8x_unused)); |
| 2745 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 2746 | .out(spare0_buf_16x_unused)); |
| 2747 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 2748 | .in1(1'b0), |
| 2749 | .out(spare0_nor2_16x_unused)); |
| 2750 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 2751 | .out(spare0_inv_32x_unused)); |
| 2752 | |
| 2753 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 2754 | .siclk(siclk), |
| 2755 | .soclk(soclk), |
| 2756 | .si(si_1), |
| 2757 | .so(so_1), |
| 2758 | .d(1'b0), |
| 2759 | .q(spare1_flop_unused)); |
| 2760 | assign si_1 = so_0; |
| 2761 | |
| 2762 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 2763 | .out(spare1_buf_32x_unused)); |
| 2764 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 2765 | .in1(1'b1), |
| 2766 | .in2(1'b1), |
| 2767 | .out(spare1_nand3_8x_unused)); |
| 2768 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 2769 | .out(spare1_inv_8x_unused)); |
| 2770 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 2771 | .in01(1'b1), |
| 2772 | .in10(1'b1), |
| 2773 | .in11(1'b1), |
| 2774 | .out(spare1_aoi22_4x_unused)); |
| 2775 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 2776 | .out(spare1_buf_8x_unused)); |
| 2777 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 2778 | .in01(1'b1), |
| 2779 | .in10(1'b1), |
| 2780 | .in11(1'b1), |
| 2781 | .out(spare1_oai22_4x_unused)); |
| 2782 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 2783 | .out(spare1_inv_16x_unused)); |
| 2784 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 2785 | .in1(1'b1), |
| 2786 | .out(spare1_nand2_16x_unused)); |
| 2787 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 2788 | .in1(1'b0), |
| 2789 | .in2(1'b0), |
| 2790 | .out(spare1_nor3_4x_unused)); |
| 2791 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 2792 | .in1(1'b1), |
| 2793 | .out(spare1_nand2_8x_unused)); |
| 2794 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 2795 | .out(spare1_buf_16x_unused)); |
| 2796 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 2797 | .in1(1'b0), |
| 2798 | .out(spare1_nor2_16x_unused)); |
| 2799 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 2800 | .out(spare1_inv_32x_unused)); |
| 2801 | |
| 2802 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 2803 | .siclk(siclk), |
| 2804 | .soclk(soclk), |
| 2805 | .si(si_2), |
| 2806 | .so(so_2), |
| 2807 | .d(1'b0), |
| 2808 | .q(spare2_flop_unused)); |
| 2809 | assign si_2 = so_1; |
| 2810 | |
| 2811 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 2812 | .out(spare2_buf_32x_unused)); |
| 2813 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 2814 | .in1(1'b1), |
| 2815 | .in2(1'b1), |
| 2816 | .out(spare2_nand3_8x_unused)); |
| 2817 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 2818 | .out(spare2_inv_8x_unused)); |
| 2819 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 2820 | .in01(1'b1), |
| 2821 | .in10(1'b1), |
| 2822 | .in11(1'b1), |
| 2823 | .out(spare2_aoi22_4x_unused)); |
| 2824 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 2825 | .out(spare2_buf_8x_unused)); |
| 2826 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 2827 | .in01(1'b1), |
| 2828 | .in10(1'b1), |
| 2829 | .in11(1'b1), |
| 2830 | .out(spare2_oai22_4x_unused)); |
| 2831 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 2832 | .out(spare2_inv_16x_unused)); |
| 2833 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 2834 | .in1(1'b1), |
| 2835 | .out(spare2_nand2_16x_unused)); |
| 2836 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 2837 | .in1(1'b0), |
| 2838 | .in2(1'b0), |
| 2839 | .out(spare2_nor3_4x_unused)); |
| 2840 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 2841 | .in1(1'b1), |
| 2842 | .out(spare2_nand2_8x_unused)); |
| 2843 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 2844 | .out(spare2_buf_16x_unused)); |
| 2845 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 2846 | .in1(1'b0), |
| 2847 | .out(spare2_nor2_16x_unused)); |
| 2848 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 2849 | .out(spare2_inv_32x_unused)); |
| 2850 | |
| 2851 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 2852 | .siclk(siclk), |
| 2853 | .soclk(soclk), |
| 2854 | .si(si_3), |
| 2855 | .so(so_3), |
| 2856 | .d(1'b0), |
| 2857 | .q(spare3_flop_unused)); |
| 2858 | assign si_3 = so_2; |
| 2859 | |
| 2860 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 2861 | .out(spare3_buf_32x_unused)); |
| 2862 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 2863 | .in1(1'b1), |
| 2864 | .in2(1'b1), |
| 2865 | .out(spare3_nand3_8x_unused)); |
| 2866 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 2867 | .out(spare3_inv_8x_unused)); |
| 2868 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 2869 | .in01(1'b1), |
| 2870 | .in10(1'b1), |
| 2871 | .in11(1'b1), |
| 2872 | .out(spare3_aoi22_4x_unused)); |
| 2873 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 2874 | .out(spare3_buf_8x_unused)); |
| 2875 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 2876 | .in01(1'b1), |
| 2877 | .in10(1'b1), |
| 2878 | .in11(1'b1), |
| 2879 | .out(spare3_oai22_4x_unused)); |
| 2880 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 2881 | .out(spare3_inv_16x_unused)); |
| 2882 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 2883 | .in1(1'b1), |
| 2884 | .out(spare3_nand2_16x_unused)); |
| 2885 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 2886 | .in1(1'b0), |
| 2887 | .in2(1'b0), |
| 2888 | .out(spare3_nor3_4x_unused)); |
| 2889 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 2890 | .in1(1'b1), |
| 2891 | .out(spare3_nand2_8x_unused)); |
| 2892 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 2893 | .out(spare3_buf_16x_unused)); |
| 2894 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 2895 | .in1(1'b0), |
| 2896 | .out(spare3_nor2_16x_unused)); |
| 2897 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 2898 | .out(spare3_inv_32x_unused)); |
| 2899 | assign scan_out = so_3; |
| 2900 | |
| 2901 | |
| 2902 | |
| 2903 | endmodule |
| 2904 | |