| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fsr_bottom.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module fsr_bottom |
| 36 | (fsr7_mcu3_rd0, |
| 37 | fsr7_mcu3_rd1, |
| 38 | fsr7_mcu3_rd2, |
| 39 | fsr7_mcu3_rd3, |
| 40 | fsr7_mcu3_rd4, |
| 41 | fsr7_mcu3_rd5, |
| 42 | fsr7_mcu3_rd6, |
| 43 | fsr7_mcu3_rd7, |
| 44 | fsr7_mcu3_rd8, |
| 45 | fsr7_mcu3_rd9, |
| 46 | fsr7_mcu3_rd10, |
| 47 | fsr7_mcu3_rd11, |
| 48 | fsr7_mcu3_rd12, |
| 49 | fsr7_mcu3_rd13, |
| 50 | fsr7_mcu3_ststx_testfail, |
| 51 | fsr7_mcu3_stspll_lock, |
| 52 | fsr7_mcu3_stsrx_testfail, |
| 53 | fsr7_mcu3_stsrx_sync, |
| 54 | fsr7_mcu3_stsrx_losdtct, |
| 55 | fsr7_mcu3_stsrx_bsrxp, |
| 56 | fsr7_mcu3_stsrx_bsrxn, |
| 57 | fsr7_mcu3_rxbclk, |
| 58 | FBDIMM3B_TX_N, |
| 59 | FBDIMM3B_TX_P, |
| 60 | FBDIMM3B_AMUX, |
| 61 | fsr7_fdo, |
| 62 | fsr7_stciq, |
| 63 | mcu3_fsr7_cfgpll0, |
| 64 | mcu3_fsr7_cfgpll1, |
| 65 | mcu3_fsr7_cfgpll2, |
| 66 | mcu3_fsr7_cfgrx0, |
| 67 | mcu3_fsr7_cfgrx1, |
| 68 | mcu3_fsr7_cfgrx2, |
| 69 | mcu3_fsr7_cfgrx3, |
| 70 | mcu3_fsr7_cfgrx4, |
| 71 | mcu3_fsr7_cfgrx5, |
| 72 | mcu3_fsr7_cfgrx6, |
| 73 | mcu3_fsr7_cfgrx7, |
| 74 | mcu3_fsr7_cfgrx8, |
| 75 | mcu3_fsr7_cfgrx9, |
| 76 | mcu3_fsr7_cfgrx10, |
| 77 | mcu3_fsr7_cfgrx11, |
| 78 | mcu3_fsr7_cfgrx12, |
| 79 | mcu3_fsr7_cfgrx13, |
| 80 | mcu3_fsr7_cfgtx0, |
| 81 | mcu3_fsr7_cfgtx1, |
| 82 | mcu3_fsr7_cfgtx2, |
| 83 | mcu3_fsr7_cfgtx3, |
| 84 | mcu3_fsr7_cfgtx4, |
| 85 | mcu3_fsr7_cfgtx5, |
| 86 | mcu3_fsr7_cfgtx6, |
| 87 | mcu3_fsr7_cfgtx7, |
| 88 | mcu3_fsr7_cfgtx8, |
| 89 | mcu3_fsr7_cfgtx9, |
| 90 | mcu3_fsr7_testcfg0, |
| 91 | mcu3_fsr7_testcfg1, |
| 92 | mcu3_fsr7_testcfg2, |
| 93 | mcu3_fsr7_td0, |
| 94 | mcu3_fsr7_td1, |
| 95 | mcu3_fsr7_td2, |
| 96 | mcu3_fsr7_td3, |
| 97 | mcu3_fsr7_td4, |
| 98 | mcu3_fsr7_td5, |
| 99 | mcu3_fsr7_td6, |
| 100 | mcu3_fsr7_td7, |
| 101 | mcu3_fsr7_td8, |
| 102 | mcu3_fsr7_td9, |
| 103 | fsr7_stcicfg, |
| 104 | fsr7_txbclkin, |
| 105 | fsr7_rxbclkin, |
| 106 | fsr7_bsinitclk, |
| 107 | fsr7_fclk, |
| 108 | fsr7_fclrz, |
| 109 | fsr7_fdi, |
| 110 | FBDIMM3B_RX_N, |
| 111 | FBDIMM3B_RX_P, |
| 112 | fsr7_stciclk, |
| 113 | fsr7_stcid, |
| 114 | fsr7_testclkr, |
| 115 | fsr7_testclkt, |
| 116 | fsr_bottom_atpgd, |
| 117 | fsr_bottom_atpgq, |
| 118 | FBDIMM3_REFCLK_N, |
| 119 | FBDIMM3_REFCLK_P, |
| 120 | VDDA, |
| 121 | VDDD, |
| 122 | VDDR, |
| 123 | VDDT, |
| 124 | VSSA); |
| 125 | |
| 126 | output [11:0] fsr7_mcu3_rd0; |
| 127 | output [11:0] fsr7_mcu3_rd1; |
| 128 | output [11:0] fsr7_mcu3_rd2; |
| 129 | output [11:0] fsr7_mcu3_rd3; |
| 130 | output [11:0] fsr7_mcu3_rd4; |
| 131 | output [11:0] fsr7_mcu3_rd5; |
| 132 | output [11:0] fsr7_mcu3_rd6; |
| 133 | output [11:0] fsr7_mcu3_rd7; |
| 134 | output [11:0] fsr7_mcu3_rd8; |
| 135 | output [11:0] fsr7_mcu3_rd9; |
| 136 | output [11:0] fsr7_mcu3_rd10; |
| 137 | output [11:0] fsr7_mcu3_rd11; |
| 138 | output [11:0] fsr7_mcu3_rd12; |
| 139 | output [11:0] fsr7_mcu3_rd13; |
| 140 | output [9:0] fsr7_mcu3_ststx_testfail; |
| 141 | output [2:0] fsr7_mcu3_stspll_lock; |
| 142 | output [13:0] fsr7_mcu3_stsrx_testfail; |
| 143 | output [13:0] fsr7_mcu3_stsrx_sync; |
| 144 | output [13:0] fsr7_mcu3_stsrx_losdtct; |
| 145 | output [13:0] fsr7_mcu3_stsrx_bsrxp; |
| 146 | output [13:0] fsr7_mcu3_stsrx_bsrxn; |
| 147 | output [13:0] fsr7_mcu3_rxbclk; |
| 148 | output [9:0] FBDIMM3B_TX_N; |
| 149 | output [9:0] FBDIMM3B_TX_P; |
| 150 | output [2:0] FBDIMM3B_AMUX; |
| 151 | output [2:0] fsr7_fdo; |
| 152 | output [2:0] fsr7_stciq; |
| 153 | |
| 154 | |
| 155 | input [6:0] mcu3_fsr7_cfgpll0; |
| 156 | input [6:0] mcu3_fsr7_cfgpll1; |
| 157 | input [6:0] mcu3_fsr7_cfgpll2; |
| 158 | input [19:0] mcu3_fsr7_cfgrx0; |
| 159 | input [19:0] mcu3_fsr7_cfgrx1; |
| 160 | input [19:0] mcu3_fsr7_cfgrx2; |
| 161 | input [19:0] mcu3_fsr7_cfgrx3; |
| 162 | input [19:0] mcu3_fsr7_cfgrx4; |
| 163 | input [19:0] mcu3_fsr7_cfgrx5; |
| 164 | input [19:0] mcu3_fsr7_cfgrx6; |
| 165 | input [19:0] mcu3_fsr7_cfgrx7; |
| 166 | input [19:0] mcu3_fsr7_cfgrx8; |
| 167 | input [19:0] mcu3_fsr7_cfgrx9; |
| 168 | input [19:0] mcu3_fsr7_cfgrx10; |
| 169 | input [19:0] mcu3_fsr7_cfgrx11; |
| 170 | input [19:0] mcu3_fsr7_cfgrx12; |
| 171 | input [19:0] mcu3_fsr7_cfgrx13; |
| 172 | input [15:0] mcu3_fsr7_cfgtx0; |
| 173 | input [15:0] mcu3_fsr7_cfgtx1; |
| 174 | input [15:0] mcu3_fsr7_cfgtx2; |
| 175 | input [15:0] mcu3_fsr7_cfgtx3; |
| 176 | input [15:0] mcu3_fsr7_cfgtx4; |
| 177 | input [15:0] mcu3_fsr7_cfgtx5; |
| 178 | input [15:0] mcu3_fsr7_cfgtx6; |
| 179 | input [15:0] mcu3_fsr7_cfgtx7; |
| 180 | input [15:0] mcu3_fsr7_cfgtx8; |
| 181 | input [15:0] mcu3_fsr7_cfgtx9; |
| 182 | input [17:0] mcu3_fsr7_testcfg0; |
| 183 | input [17:0] mcu3_fsr7_testcfg1; |
| 184 | input [17:0] mcu3_fsr7_testcfg2; |
| 185 | input [11:0] mcu3_fsr7_td0; |
| 186 | input [11:0] mcu3_fsr7_td1; |
| 187 | input [11:0] mcu3_fsr7_td2; |
| 188 | input [11:0] mcu3_fsr7_td3; |
| 189 | input [11:0] mcu3_fsr7_td4; |
| 190 | input [11:0] mcu3_fsr7_td5; |
| 191 | input [11:0] mcu3_fsr7_td6; |
| 192 | input [11:0] mcu3_fsr7_td7; |
| 193 | input [11:0] mcu3_fsr7_td8; |
| 194 | input [11:0] mcu3_fsr7_td9; |
| 195 | input [5:0] fsr7_stcicfg; |
| 196 | input [2:0] fsr7_txbclkin; |
| 197 | input [13:0] fsr7_rxbclkin; |
| 198 | input [2:0] fsr7_bsinitclk; |
| 199 | input [2:0] fsr7_fclk; |
| 200 | input [2:0] fsr7_fclrz; |
| 201 | input [2:0] fsr7_fdi; |
| 202 | input [13:0] FBDIMM3B_RX_N; |
| 203 | input [13:0] FBDIMM3B_RX_P; |
| 204 | input [2:0] fsr7_stciclk; |
| 205 | input [2:0] fsr7_stcid; |
| 206 | input [2:0] fsr7_testclkr; |
| 207 | input [2:0] fsr7_testclkt; |
| 208 | |
| 209 | input fsr_bottom_atpgd; |
| 210 | output fsr_bottom_atpgq; |
| 211 | |
| 212 | input FBDIMM3_REFCLK_N; |
| 213 | input FBDIMM3_REFCLK_P; |
| 214 | |
| 215 | input VDDA; |
| 216 | input VDDD; |
| 217 | input VDDR; |
| 218 | input VDDT; |
| 219 | input VSSA; |
| 220 | |
| 221 | assign clk622b_b_27 = FBDIMM3_REFCLK_P; |
| 222 | assign clk622b_b_27x = FBDIMM3_REFCLK_N; |
| 223 | assign clk622b_b_26 = FBDIMM3_REFCLK_P; |
| 224 | assign clk622b_b_26x = FBDIMM3_REFCLK_N; |
| 225 | assign clk622b_b_25 = FBDIMM3_REFCLK_P; |
| 226 | assign clk622b_b_25x = FBDIMM3_REFCLK_N; |
| 227 | |
| 228 | wire [9:0] fsr7_txbclk_unused; |
| 229 | wire [13:0] fsr7_rxbclklln_unused; |
| 230 | wire [13:0] fsr7_rxbclkllp_unused; |
| 231 | wire [3:0] fsr7_mcu3_stspll_b80; |
| 232 | wire [3:0] fsr7_mcu3_stspll_b81; |
| 233 | wire [3:0] fsr7_mcu3_stspll_b62; |
| 234 | wire [3:0] fsr7_mcu3_stsrx0_unused; |
| 235 | wire [3:0] fsr7_mcu3_stsrx1_unused; |
| 236 | wire [3:0] fsr7_mcu3_stsrx2_unused; |
| 237 | wire [3:0] fsr7_mcu3_stsrx3_unused; |
| 238 | wire [3:0] fsr7_mcu3_stsrx4_unused; |
| 239 | wire [3:0] fsr7_mcu3_stsrx5_unused; |
| 240 | wire [3:0] fsr7_mcu3_stsrx6_unused; |
| 241 | wire [3:0] fsr7_mcu3_stsrx7_unused; |
| 242 | wire [3:0] fsr7_mcu3_stsrx8_unused; |
| 243 | wire [3:0] fsr7_mcu3_stsrx9_unused; |
| 244 | wire [3:0] fsr7_mcu3_stsrx10_unused; |
| 245 | wire [3:0] fsr7_mcu3_stsrx11_unused; |
| 246 | wire [3:0] fsr7_mcu3_stsrx12_unused; |
| 247 | wire [3:0] fsr7_mcu3_stsrx13_unused; |
| 248 | wire [2:0] fsr7_mcu3_ststx0_unused; |
| 249 | wire [2:0] fsr7_mcu3_ststx1_unused; |
| 250 | wire [2:0] fsr7_mcu3_ststx2_unused; |
| 251 | wire [2:0] fsr7_mcu3_ststx3_unused; |
| 252 | wire [2:0] fsr7_mcu3_ststx4_unused; |
| 253 | wire [2:0] fsr7_mcu3_ststx5_unused; |
| 254 | wire [2:0] fsr7_mcu3_ststx6_unused; |
| 255 | wire [2:0] fsr7_mcu3_ststx7_unused; |
| 256 | wire [2:0] fsr7_mcu3_ststx8_unused; |
| 257 | wire [2:0] fsr7_mcu3_ststx9_unused; |
| 258 | wire [1:0] fsr7_rdll0_b80; |
| 259 | wire [1:0] fsr7_rdll1_b80; |
| 260 | wire [1:0] fsr7_rdll2_b80; |
| 261 | wire [1:0] fsr7_rdll3_b80; |
| 262 | wire [1:0] fsr7_rdll0_b81; |
| 263 | wire [1:0] fsr7_rdll1_b81; |
| 264 | wire [1:0] fsr7_rdll2_b81; |
| 265 | wire [1:0] fsr7_rdll3_b81; |
| 266 | wire [1:0] fsr7_rdll0_b62; |
| 267 | wire [1:0] fsr7_rdll1_b62; |
| 268 | wire [1:0] fsr7_rdll2_b62; |
| 269 | wire [1:0] fsr7_rdll3_b62; |
| 270 | |
| 271 | wire fsr7_atpgmq_b80; |
| 272 | wire fsr7_atpgmq_a8; |
| 273 | wire fsr7_atpgmq_b81; |
| 274 | wire [3:0] fsr7_atpgrq_b80; |
| 275 | wire [5:0] fsr7_atpgrq_a8; |
| 276 | wire [3:0] fsr7_atpgrq_b81; |
| 277 | wire [3:0] fsr7_atpgtq_b80; |
| 278 | wire [1:0] fsr7_atpgtq_a8; |
| 279 | wire [3:0] fsr7_atpgtq_b81; |
| 280 | |
| 281 | // first serdes macro: rx ports 0-3, tx ports 0-3 |
| 282 | |
| 283 | wiz6c2b8n6d2t fsr7_b8_0 ( |
| 284 | .bsinitclk ( fsr7_bsinitclk[0]), |
| 285 | .cfgpll ({2'b0, mcu3_fsr7_cfgpll0[6:5], 3'b0, mcu3_fsr7_cfgpll0[4:0]}), |
| 286 | .cfgrx0 ({2'b0, mcu3_fsr7_cfgrx0[19:18], 1'b0, mcu3_fsr7_cfgrx0[17:9], 1'b0, mcu3_fsr7_cfgrx0[8], |
| 287 | 1'b0, mcu3_fsr7_cfgrx0[7:2], 3'b0, mcu3_fsr7_cfgrx0[1:0]}), |
| 288 | .cfgrx1 ({2'b0, mcu3_fsr7_cfgrx1[19:18], 1'b0, mcu3_fsr7_cfgrx1[17:9], 1'b0, mcu3_fsr7_cfgrx1[8], |
| 289 | 1'b0, mcu3_fsr7_cfgrx1[7:2], 3'b0, mcu3_fsr7_cfgrx1[1:0]}), |
| 290 | .cfgrx2 ({2'b0, mcu3_fsr7_cfgrx2[19:18], 1'b0, mcu3_fsr7_cfgrx2[17:9], 1'b0, mcu3_fsr7_cfgrx2[8], |
| 291 | 1'b0, mcu3_fsr7_cfgrx2[7:2], 3'b0, mcu3_fsr7_cfgrx2[1:0]}), |
| 292 | .cfgrx3 ({2'b0, mcu3_fsr7_cfgrx3[19:18], 1'b0, mcu3_fsr7_cfgrx3[17:9], 1'b0, mcu3_fsr7_cfgrx3[8], |
| 293 | 1'b0, mcu3_fsr7_cfgrx3[7:2], 3'b0, mcu3_fsr7_cfgrx3[1:0]}), |
| 294 | .cfgtx0 ({1'b0, mcu3_fsr7_cfgtx0[15:2], 3'b0, mcu3_fsr7_cfgtx0[1:0]}), |
| 295 | .cfgtx1 ({1'b0, mcu3_fsr7_cfgtx1[15:2], 3'b0, mcu3_fsr7_cfgtx1[1:0]}), |
| 296 | .cfgtx2 ({1'b0, mcu3_fsr7_cfgtx2[15:2], 3'b0, mcu3_fsr7_cfgtx2[1:0]}), |
| 297 | .cfgtx3 ({1'b0, mcu3_fsr7_cfgtx3[15:2], 3'b0, mcu3_fsr7_cfgtx3[1:0]}), |
| 298 | .fclk ( fsr7_fclk[0] ), |
| 299 | .fclrz ( fsr7_fclrz[0] ), |
| 300 | .fdi ( fsr7_fdi[0] ), |
| 301 | .refclkn ( clk622b_b_27x ), |
| 302 | .refclkp ( clk622b_b_27 ), |
| 303 | .rxbclkin ( fsr7_rxbclkin[3:0] ), |
| 304 | .rxn0 ( FBDIMM3B_RX_N[0] ), |
| 305 | .rxn1 ( FBDIMM3B_RX_N[1] ), |
| 306 | .rxn2 ( FBDIMM3B_RX_N[2] ), |
| 307 | .rxn3 ( FBDIMM3B_RX_N[3] ), |
| 308 | .rxp0 ( FBDIMM3B_RX_P[0] ), |
| 309 | .rxp1 ( FBDIMM3B_RX_P[1] ), |
| 310 | .rxp2 ( FBDIMM3B_RX_P[2] ), |
| 311 | .rxp3 ( FBDIMM3B_RX_P[3] ), |
| 312 | .stcicfg ( fsr7_stcicfg[1:0] ), |
| 313 | .stciclk ( fsr7_stciclk[0] ), |
| 314 | .stcid ( fsr7_stcid[0] ), |
| 315 | .td0 ( {mcu3_fsr7_td0[0], mcu3_fsr7_td0[1], mcu3_fsr7_td0[2], mcu3_fsr7_td0[3], |
| 316 | mcu3_fsr7_td0[4], mcu3_fsr7_td0[5], mcu3_fsr7_td0[6], mcu3_fsr7_td0[7], |
| 317 | mcu3_fsr7_td0[8], mcu3_fsr7_td0[9], mcu3_fsr7_td0[10], mcu3_fsr7_td0[11]} ), |
| 318 | .td1 ( {mcu3_fsr7_td1[0], mcu3_fsr7_td1[1], mcu3_fsr7_td1[2], mcu3_fsr7_td1[3], |
| 319 | mcu3_fsr7_td1[4], mcu3_fsr7_td1[5], mcu3_fsr7_td1[6], mcu3_fsr7_td1[7], |
| 320 | mcu3_fsr7_td1[8], mcu3_fsr7_td1[9], mcu3_fsr7_td1[10], mcu3_fsr7_td1[11]} ), |
| 321 | .td2 ( {mcu3_fsr7_td2[0], mcu3_fsr7_td2[1], mcu3_fsr7_td2[2], mcu3_fsr7_td2[3], |
| 322 | mcu3_fsr7_td2[4], mcu3_fsr7_td2[5], mcu3_fsr7_td2[6], mcu3_fsr7_td2[7], |
| 323 | mcu3_fsr7_td2[8], mcu3_fsr7_td2[9], mcu3_fsr7_td2[10], mcu3_fsr7_td2[11]} ), |
| 324 | .td3 ( {mcu3_fsr7_td3[0], mcu3_fsr7_td3[1], mcu3_fsr7_td3[2], mcu3_fsr7_td3[3], |
| 325 | mcu3_fsr7_td3[4], mcu3_fsr7_td3[5], mcu3_fsr7_td3[6], mcu3_fsr7_td3[7], |
| 326 | mcu3_fsr7_td3[8], mcu3_fsr7_td3[9], mcu3_fsr7_td3[10], mcu3_fsr7_td3[11]} ), |
| 327 | .testcfg ( {mcu3_fsr7_testcfg0[17:14], 1'b0, mcu3_fsr7_testcfg0[13:11], 1'b0, mcu3_fsr7_testcfg0[10:0]} ), |
| 328 | .testclkr ( fsr7_testclkr[0] ), |
| 329 | .testclkt ( fsr7_testclkt[0] ), |
| 330 | .txbclkin ( {4{fsr7_txbclkin[0]}} ), |
| 331 | .amux ( FBDIMM3B_AMUX[0] ), |
| 332 | .fdo ( fsr7_fdo[0] ), |
| 333 | .rd0 ( {fsr7_mcu3_rd0[0], fsr7_mcu3_rd0[1], fsr7_mcu3_rd0[2], fsr7_mcu3_rd0[3], |
| 334 | fsr7_mcu3_rd0[4], fsr7_mcu3_rd0[5], fsr7_mcu3_rd0[6], fsr7_mcu3_rd0[7], |
| 335 | fsr7_mcu3_rd0[8], fsr7_mcu3_rd0[9], fsr7_mcu3_rd0[10], fsr7_mcu3_rd0[11]} ), |
| 336 | .rd1 ( {fsr7_mcu3_rd1[0], fsr7_mcu3_rd1[1], fsr7_mcu3_rd1[2], fsr7_mcu3_rd1[3], |
| 337 | fsr7_mcu3_rd1[4], fsr7_mcu3_rd1[5], fsr7_mcu3_rd1[6], fsr7_mcu3_rd1[7], |
| 338 | fsr7_mcu3_rd1[8], fsr7_mcu3_rd1[9], fsr7_mcu3_rd1[10], fsr7_mcu3_rd1[11]} ), |
| 339 | .rd2 ( {fsr7_mcu3_rd2[0], fsr7_mcu3_rd2[1], fsr7_mcu3_rd2[2], fsr7_mcu3_rd2[3], |
| 340 | fsr7_mcu3_rd2[4], fsr7_mcu3_rd2[5], fsr7_mcu3_rd2[6], fsr7_mcu3_rd2[7], |
| 341 | fsr7_mcu3_rd2[8], fsr7_mcu3_rd2[9], fsr7_mcu3_rd2[10], fsr7_mcu3_rd2[11]} ), |
| 342 | .rd3 ( {fsr7_mcu3_rd3[0], fsr7_mcu3_rd3[1], fsr7_mcu3_rd3[2], fsr7_mcu3_rd3[3], |
| 343 | fsr7_mcu3_rd3[4], fsr7_mcu3_rd3[5], fsr7_mcu3_rd3[6], fsr7_mcu3_rd3[7], |
| 344 | fsr7_mcu3_rd3[8], fsr7_mcu3_rd3[9], fsr7_mcu3_rd3[10], fsr7_mcu3_rd3[11]} ), |
| 345 | .rdll0 ( fsr7_rdll0_b80[1:0] ), |
| 346 | .rdll1 ( fsr7_rdll1_b80[1:0] ), |
| 347 | .rdll2 ( fsr7_rdll2_b80[1:0] ), |
| 348 | .rdll3 ( fsr7_rdll3_b80[1:0] ), |
| 349 | .rxbclk ( fsr7_mcu3_rxbclk[3:0] ), |
| 350 | .rxbclklln ( fsr7_rxbclklln_unused[3:0] ), |
| 351 | .rxbclkllp ( fsr7_rxbclkllp_unused[3:0] ), |
| 352 | .stciq ( fsr7_stciq[0] ), |
| 353 | .stspll ( {fsr7_mcu3_stspll_b80[2:0], fsr7_mcu3_stspll_lock[0]} ), |
| 354 | .stsrx0 ( {fsr7_mcu3_stsrx0_unused[2:1], fsr7_mcu3_stsrx_bsrxn[0], fsr7_mcu3_stsrx_bsrxp[0], |
| 355 | fsr7_mcu3_stsrx_losdtct[0], fsr7_mcu3_stsrx0_unused[0], fsr7_mcu3_stsrx_sync[0], |
| 356 | fsr7_mcu3_stsrx_testfail[0]} ), |
| 357 | .stsrx1 ( {fsr7_mcu3_stsrx1_unused[2:1], fsr7_mcu3_stsrx_bsrxn[1], fsr7_mcu3_stsrx_bsrxp[1], |
| 358 | fsr7_mcu3_stsrx_losdtct[1], fsr7_mcu3_stsrx1_unused[0], fsr7_mcu3_stsrx_sync[1], |
| 359 | fsr7_mcu3_stsrx_testfail[1]} ), |
| 360 | .stsrx2 ( {fsr7_mcu3_stsrx2_unused[2:1], fsr7_mcu3_stsrx_bsrxn[2], fsr7_mcu3_stsrx_bsrxp[2], |
| 361 | fsr7_mcu3_stsrx_losdtct[2], fsr7_mcu3_stsrx2_unused[0], fsr7_mcu3_stsrx_sync[2], |
| 362 | fsr7_mcu3_stsrx_testfail[2]} ), |
| 363 | .stsrx3 ( {fsr7_mcu3_stsrx3_unused[2:1], fsr7_mcu3_stsrx_bsrxn[3], fsr7_mcu3_stsrx_bsrxp[3], |
| 364 | fsr7_mcu3_stsrx_losdtct[3], fsr7_mcu3_stsrx3_unused[0], fsr7_mcu3_stsrx_sync[3], |
| 365 | fsr7_mcu3_stsrx_testfail[3]} ), |
| 366 | .ststx0 ( {fsr7_mcu3_ststx0_unused[2:0], fsr7_mcu3_ststx_testfail[0]} ), |
| 367 | .ststx1 ( {fsr7_mcu3_ststx1_unused[2:0], fsr7_mcu3_ststx_testfail[1]} ), |
| 368 | .ststx2 ( {fsr7_mcu3_ststx2_unused[2:0], fsr7_mcu3_ststx_testfail[2]} ), |
| 369 | .ststx3 ( {fsr7_mcu3_ststx3_unused[2:0], fsr7_mcu3_ststx_testfail[3]} ), |
| 370 | .txbclk ( fsr7_txbclk_unused[3:0] ), |
| 371 | .txn0 ( FBDIMM3B_TX_N[0] ), |
| 372 | .txn1 ( FBDIMM3B_TX_N[1] ), |
| 373 | .txn2 ( FBDIMM3B_TX_N[2] ), |
| 374 | .txn3 ( FBDIMM3B_TX_N[3] ), |
| 375 | .txp0 ( FBDIMM3B_TX_P[0] ), |
| 376 | .txp1 ( FBDIMM3B_TX_P[1] ), |
| 377 | .txp2 ( FBDIMM3B_TX_P[2] ), |
| 378 | .txp3 ( FBDIMM3B_TX_P[3] ), |
| 379 | .atpgmd ( fsr7_atpgtq_b80[1] ), |
| 380 | .atpgmq ( fsr7_atpgmq_b80 ), |
| 381 | .atpgrd ( {fsr7_atpgrq_b80[2],fsr7_atpgtq_b80[2],fsr7_atpgrq_b80[0],fsr7_atpgtq_b80[0]} ), |
| 382 | .atpgrq ( fsr7_atpgrq_b80[3:0] ), |
| 383 | .atpgtd ( {fsr7_atpgrq_b80[3],fsr7_atpgmq_b80,fsr7_atpgrq_b80[1],fsr_bottom_atpgd} ), |
| 384 | .atpgtq ( fsr7_atpgtq_b80[3:0] ), |
| 385 | .vdda ( VDDA ), |
| 386 | .vddd ( VDDD ), |
| 387 | .vddr ( VDDR ), |
| 388 | .vddt ( VDDT ), |
| 389 | .vssa ( VSSA ) |
| 390 | ); |
| 391 | |
| 392 | |
| 393 | // second serdes macro: RX ports 4-9, TX ports 4-5 |
| 394 | |
| 395 | wiz6c2a8n6d2t fsr7_a8 ( |
| 396 | .bsinitclk ( fsr7_bsinitclk[1]), |
| 397 | .cfgpll ({2'b0, mcu3_fsr7_cfgpll1[6:5], 3'b0, mcu3_fsr7_cfgpll1[4:0]}), |
| 398 | .cfgrx0 ({2'b0, mcu3_fsr7_cfgrx4[19:18], 1'b0, mcu3_fsr7_cfgrx4[17:9], 1'b0, mcu3_fsr7_cfgrx4[8], |
| 399 | 1'b0, mcu3_fsr7_cfgrx4[7:2], 3'b0, mcu3_fsr7_cfgrx4[1:0]}), |
| 400 | .cfgrx1 ({2'b0, mcu3_fsr7_cfgrx5[19:18], 1'b0, mcu3_fsr7_cfgrx5[17:9], 1'b0, mcu3_fsr7_cfgrx5[8], |
| 401 | 1'b0, mcu3_fsr7_cfgrx5[7:2], 3'b0, mcu3_fsr7_cfgrx5[1:0]}), |
| 402 | .cfgrx2 ({2'b0, mcu3_fsr7_cfgrx6[19:18], 1'b0, mcu3_fsr7_cfgrx6[17:9], 1'b0, mcu3_fsr7_cfgrx6[8], |
| 403 | 1'b0, mcu3_fsr7_cfgrx6[7:2], 3'b0, mcu3_fsr7_cfgrx6[1:0]}), |
| 404 | .cfgrx3 ({2'b0, mcu3_fsr7_cfgrx7[19:18], 1'b0, mcu3_fsr7_cfgrx7[17:9], 1'b0, mcu3_fsr7_cfgrx7[8], |
| 405 | 1'b0, mcu3_fsr7_cfgrx7[7:2], 3'b0, mcu3_fsr7_cfgrx7[1:0]}), |
| 406 | .cfgrx4 ({2'b0, mcu3_fsr7_cfgrx8[19:18], 1'b0, mcu3_fsr7_cfgrx8[17:9], 1'b0, mcu3_fsr7_cfgrx8[8], |
| 407 | 1'b0, mcu3_fsr7_cfgrx8[7:2], 3'b0, mcu3_fsr7_cfgrx8[1:0]}), |
| 408 | .cfgrx5 ({2'b0, mcu3_fsr7_cfgrx9[19:18], 1'b0, mcu3_fsr7_cfgrx9[17:9], 1'b0, mcu3_fsr7_cfgrx9[8], |
| 409 | 1'b0, mcu3_fsr7_cfgrx9[7:2], 3'b0, mcu3_fsr7_cfgrx9[1:0]}), |
| 410 | .cfgtx0 ({1'b0, mcu3_fsr7_cfgtx4[15:2], 3'b0, mcu3_fsr7_cfgtx4[1:0]}), |
| 411 | .cfgtx1 ({1'b0, mcu3_fsr7_cfgtx5[15:2], 3'b0, mcu3_fsr7_cfgtx5[1:0]}), |
| 412 | .fclk ( fsr7_fclk[1] ), |
| 413 | .fclrz ( fsr7_fclrz[1] ), |
| 414 | .fdi ( fsr7_fdi[1] ), |
| 415 | .refclkn ( clk622b_b_26x ), |
| 416 | .refclkp ( clk622b_b_26 ), |
| 417 | .rxbclkin ( fsr7_rxbclkin[9:4] ), |
| 418 | .rxn0 ( FBDIMM3B_RX_N[4] ), |
| 419 | .rxn1 ( FBDIMM3B_RX_N[5] ), |
| 420 | .rxn2 ( FBDIMM3B_RX_N[6] ), |
| 421 | .rxn3 ( FBDIMM3B_RX_N[7] ), |
| 422 | .rxn4 ( FBDIMM3B_RX_N[8] ), |
| 423 | .rxn5 ( FBDIMM3B_RX_N[9] ), |
| 424 | .rxp0 ( FBDIMM3B_RX_P[4] ), |
| 425 | .rxp1 ( FBDIMM3B_RX_P[5] ), |
| 426 | .rxp2 ( FBDIMM3B_RX_P[6] ), |
| 427 | .rxp3 ( FBDIMM3B_RX_P[7] ), |
| 428 | .rxp4 ( FBDIMM3B_RX_P[8] ), |
| 429 | .rxp5 ( FBDIMM3B_RX_P[9] ), |
| 430 | .stcicfg ( fsr7_stcicfg[3:2] ), |
| 431 | .stciclk ( fsr7_stciclk[1] ), |
| 432 | .stcid ( fsr7_stcid[1] ), |
| 433 | .td0 ( {mcu3_fsr7_td4[0], mcu3_fsr7_td4[1], mcu3_fsr7_td4[2], mcu3_fsr7_td4[3], |
| 434 | mcu3_fsr7_td4[4], mcu3_fsr7_td4[5], mcu3_fsr7_td4[6], mcu3_fsr7_td4[7], |
| 435 | mcu3_fsr7_td4[8], mcu3_fsr7_td4[9], mcu3_fsr7_td4[10], mcu3_fsr7_td4[11]} ), |
| 436 | .td1 ( {mcu3_fsr7_td5[0], mcu3_fsr7_td5[1], mcu3_fsr7_td5[2], mcu3_fsr7_td5[3], |
| 437 | mcu3_fsr7_td5[4], mcu3_fsr7_td5[5], mcu3_fsr7_td5[6], mcu3_fsr7_td5[7], |
| 438 | mcu3_fsr7_td5[8], mcu3_fsr7_td5[9], mcu3_fsr7_td5[10], mcu3_fsr7_td5[11]} ), |
| 439 | .testcfg ( {mcu3_fsr7_testcfg1[17:14], 1'b0, mcu3_fsr7_testcfg1[13:11], 1'b0, mcu3_fsr7_testcfg1[10:0]} ), |
| 440 | .testclkr ( fsr7_testclkr[1] ), |
| 441 | .testclkt ( fsr7_testclkt[1] ), |
| 442 | .txbclkin ( {2{fsr7_txbclkin[1]}} ), |
| 443 | .amux ( FBDIMM3B_AMUX[1] ), |
| 444 | .fdo ( fsr7_fdo[1] ), |
| 445 | .rd0 ( {fsr7_mcu3_rd4[0], fsr7_mcu3_rd4[1], fsr7_mcu3_rd4[2], fsr7_mcu3_rd4[3], |
| 446 | fsr7_mcu3_rd4[4], fsr7_mcu3_rd4[5], fsr7_mcu3_rd4[6], fsr7_mcu3_rd4[7], |
| 447 | fsr7_mcu3_rd4[8], fsr7_mcu3_rd4[9], fsr7_mcu3_rd4[10], fsr7_mcu3_rd4[11]} ), |
| 448 | .rd1 ( {fsr7_mcu3_rd5[0], fsr7_mcu3_rd5[1], fsr7_mcu3_rd5[2], fsr7_mcu3_rd5[3], |
| 449 | fsr7_mcu3_rd5[4], fsr7_mcu3_rd5[5], fsr7_mcu3_rd5[6], fsr7_mcu3_rd5[7], |
| 450 | fsr7_mcu3_rd5[8], fsr7_mcu3_rd5[9], fsr7_mcu3_rd5[10], fsr7_mcu3_rd5[11]} ), |
| 451 | .rd2 ( {fsr7_mcu3_rd6[0], fsr7_mcu3_rd6[1], fsr7_mcu3_rd6[2], fsr7_mcu3_rd6[3], |
| 452 | fsr7_mcu3_rd6[4], fsr7_mcu3_rd6[5], fsr7_mcu3_rd6[6], fsr7_mcu3_rd6[7], |
| 453 | fsr7_mcu3_rd6[8], fsr7_mcu3_rd6[9], fsr7_mcu3_rd6[10], fsr7_mcu3_rd6[11]} ), |
| 454 | .rd3 ( {fsr7_mcu3_rd7[0], fsr7_mcu3_rd7[1], fsr7_mcu3_rd7[2], fsr7_mcu3_rd7[3], |
| 455 | fsr7_mcu3_rd7[4], fsr7_mcu3_rd7[5], fsr7_mcu3_rd7[6], fsr7_mcu3_rd7[7], |
| 456 | fsr7_mcu3_rd7[8], fsr7_mcu3_rd7[9], fsr7_mcu3_rd7[10], fsr7_mcu3_rd7[11]} ), |
| 457 | .rd4 ( {fsr7_mcu3_rd8[0], fsr7_mcu3_rd8[1], fsr7_mcu3_rd8[2], fsr7_mcu3_rd8[3], |
| 458 | fsr7_mcu3_rd8[4], fsr7_mcu3_rd8[5], fsr7_mcu3_rd8[6], fsr7_mcu3_rd8[7], |
| 459 | fsr7_mcu3_rd8[8], fsr7_mcu3_rd8[9], fsr7_mcu3_rd8[10], fsr7_mcu3_rd8[11]} ), |
| 460 | .rd5 ( {fsr7_mcu3_rd9[0], fsr7_mcu3_rd9[1], fsr7_mcu3_rd9[2], fsr7_mcu3_rd9[3], |
| 461 | fsr7_mcu3_rd9[4], fsr7_mcu3_rd9[5], fsr7_mcu3_rd9[6], fsr7_mcu3_rd9[7], |
| 462 | fsr7_mcu3_rd9[8], fsr7_mcu3_rd9[9], fsr7_mcu3_rd9[10], fsr7_mcu3_rd9[11]} ), |
| 463 | .rdll0 ( fsr7_rdll0_b62[1:0] ), |
| 464 | .rdll1 ( fsr7_rdll1_b62[1:0] ), |
| 465 | .rdll2 ( fsr7_rdll2_b62[1:0] ), |
| 466 | .rdll3 ( fsr7_rdll3_b62[1:0] ), |
| 467 | .rxbclk ( fsr7_mcu3_rxbclk[9:4] ), |
| 468 | .rxbclklln ( fsr7_rxbclklln_unused[9:4] ), |
| 469 | .rxbclkllp ( fsr7_rxbclkllp_unused[9:4] ), |
| 470 | .stciq ( fsr7_stciq[1] ), |
| 471 | .stspll ( {fsr7_mcu3_stspll_b62[2:0], fsr7_mcu3_stspll_lock[1]} ), |
| 472 | .stsrx0 ( {fsr7_mcu3_stsrx4_unused[2:1], fsr7_mcu3_stsrx_bsrxn[4], fsr7_mcu3_stsrx_bsrxp[4], |
| 473 | fsr7_mcu3_stsrx_losdtct[4], fsr7_mcu3_stsrx4_unused[0], fsr7_mcu3_stsrx_sync[4], |
| 474 | fsr7_mcu3_stsrx_testfail[4]} ), |
| 475 | .stsrx1 ( {fsr7_mcu3_stsrx5_unused[2:1], fsr7_mcu3_stsrx_bsrxn[5], fsr7_mcu3_stsrx_bsrxp[5], |
| 476 | fsr7_mcu3_stsrx_losdtct[5], fsr7_mcu3_stsrx5_unused[0], fsr7_mcu3_stsrx_sync[5], |
| 477 | fsr7_mcu3_stsrx_testfail[5]} ), |
| 478 | .stsrx2 ( {fsr7_mcu3_stsrx6_unused[2:1], fsr7_mcu3_stsrx_bsrxn[6], fsr7_mcu3_stsrx_bsrxp[6], |
| 479 | fsr7_mcu3_stsrx_losdtct[6], fsr7_mcu3_stsrx6_unused[0], fsr7_mcu3_stsrx_sync[6], |
| 480 | fsr7_mcu3_stsrx_testfail[6]} ), |
| 481 | .stsrx3 ( {fsr7_mcu3_stsrx7_unused[2:1], fsr7_mcu3_stsrx_bsrxn[7], fsr7_mcu3_stsrx_bsrxp[7], |
| 482 | fsr7_mcu3_stsrx_losdtct[7], fsr7_mcu3_stsrx7_unused[0], fsr7_mcu3_stsrx_sync[7], |
| 483 | fsr7_mcu3_stsrx_testfail[7]} ), |
| 484 | .stsrx4 ( {fsr7_mcu3_stsrx8_unused[2:1], fsr7_mcu3_stsrx_bsrxn[8], fsr7_mcu3_stsrx_bsrxp[8], |
| 485 | fsr7_mcu3_stsrx_losdtct[8], fsr7_mcu3_stsrx8_unused[0], fsr7_mcu3_stsrx_sync[8], |
| 486 | fsr7_mcu3_stsrx_testfail[8]} ), |
| 487 | .stsrx5 ( {fsr7_mcu3_stsrx9_unused[2:1], fsr7_mcu3_stsrx_bsrxn[9], fsr7_mcu3_stsrx_bsrxp[9], |
| 488 | fsr7_mcu3_stsrx_losdtct[9], fsr7_mcu3_stsrx9_unused[0], fsr7_mcu3_stsrx_sync[9], |
| 489 | fsr7_mcu3_stsrx_testfail[9]} ), |
| 490 | .ststx0 ( {fsr7_mcu3_ststx4_unused[2:0], fsr7_mcu3_ststx_testfail[4]} ), |
| 491 | .ststx1 ( {fsr7_mcu3_ststx5_unused[2:0], fsr7_mcu3_ststx_testfail[5]} ), |
| 492 | .txbclk ( fsr7_txbclk_unused[5:4] ), |
| 493 | .txn0 ( FBDIMM3B_TX_N[4] ), |
| 494 | .txn1 ( FBDIMM3B_TX_N[5] ), |
| 495 | .txp0 ( FBDIMM3B_TX_P[4] ), |
| 496 | .txp1 ( FBDIMM3B_TX_P[5] ), |
| 497 | .atpgmd ( fsr7_atpgrq_a8[4] ), |
| 498 | .atpgmq ( fsr7_atpgmq_a8 ), |
| 499 | .atpgrd ( {fsr7_atpgmq_a8,fsr7_atpgrq_a8[1],fsr7_atpgrq_a8[2],fsr7_atpgrq_a8[5],fsr7_atpgrq_a8[0], |
| 500 | fsr7_atpgtq_a8[0]} ), |
| 501 | .atpgrq ( fsr7_atpgrq_a8[5:0] ), |
| 502 | .atpgtd ( {fsr7_atpgrq_a8[3],fsr7_atpgtq_b80[3]} ), |
| 503 | .atpgtq ( fsr7_atpgtq_a8[1:0] ), |
| 504 | .vdda ( VDDA ), |
| 505 | .vddd ( VDDD ), |
| 506 | .vddr ( VDDR ), |
| 507 | .vddt ( VDDT ), |
| 508 | .vssa ( VSSA ) |
| 509 | ); |
| 510 | |
| 511 | // third serdes macro: RX ports 10-13, TX ports 6-9 |
| 512 | |
| 513 | wiz6c2b8n6d2t fsr7_b8_1 ( |
| 514 | .bsinitclk ( fsr7_bsinitclk[2]), |
| 515 | .cfgpll ({2'b0, mcu3_fsr7_cfgpll2[6:5], 3'b0, mcu3_fsr7_cfgpll2[4:0]}), |
| 516 | .cfgrx0 ({2'b0, mcu3_fsr7_cfgrx10[19:18], 1'b0, mcu3_fsr7_cfgrx10[17:9], 1'b0, mcu3_fsr7_cfgrx10[8], |
| 517 | 1'b0, mcu3_fsr7_cfgrx10[7:2], 3'b0, mcu3_fsr7_cfgrx10[1:0]}), |
| 518 | .cfgrx1 ({2'b0, mcu3_fsr7_cfgrx11[19:18], 1'b0, mcu3_fsr7_cfgrx11[17:9], 1'b0, mcu3_fsr7_cfgrx11[8], |
| 519 | 1'b0, mcu3_fsr7_cfgrx11[7:2], 3'b0, mcu3_fsr7_cfgrx11[1:0]}), |
| 520 | .cfgrx2 ({2'b0, mcu3_fsr7_cfgrx12[19:18], 1'b0, mcu3_fsr7_cfgrx12[17:9], 1'b0, mcu3_fsr7_cfgrx12[8], |
| 521 | 1'b0, mcu3_fsr7_cfgrx12[7:2], 3'b0, mcu3_fsr7_cfgrx12[1:0]}), |
| 522 | .cfgrx3 ({2'b0, mcu3_fsr7_cfgrx13[19:18], 1'b0, mcu3_fsr7_cfgrx13[17:9], 1'b0, mcu3_fsr7_cfgrx13[8], |
| 523 | 1'b0, mcu3_fsr7_cfgrx13[7:2], 3'b0, mcu3_fsr7_cfgrx13[1:0]}), |
| 524 | .cfgtx0 ({1'b0, mcu3_fsr7_cfgtx6[15:2], 3'b0, mcu3_fsr7_cfgtx6[1:0]}), |
| 525 | .cfgtx1 ({1'b0, mcu3_fsr7_cfgtx7[15:2], 3'b0, mcu3_fsr7_cfgtx7[1:0]}), |
| 526 | .cfgtx2 ({1'b0, mcu3_fsr7_cfgtx8[15:2], 3'b0, mcu3_fsr7_cfgtx8[1:0]}), |
| 527 | .cfgtx3 ({1'b0, mcu3_fsr7_cfgtx9[15:2], 3'b0, mcu3_fsr7_cfgtx9[1:0]}), |
| 528 | .fclk ( fsr7_fclk[2] ), |
| 529 | .fclrz ( fsr7_fclrz[2] ), |
| 530 | .fdi ( fsr7_fdi[2] ), |
| 531 | .refclkn ( clk622b_b_25x ), |
| 532 | .refclkp ( clk622b_b_25 ), |
| 533 | .rxbclkin ( fsr7_rxbclkin[13:10] ), |
| 534 | .rxn0 ( FBDIMM3B_RX_N[10] ), |
| 535 | .rxn1 ( FBDIMM3B_RX_N[11] ), |
| 536 | .rxn2 ( FBDIMM3B_RX_N[12] ), |
| 537 | .rxn3 ( FBDIMM3B_RX_N[13] ), |
| 538 | .rxp0 ( FBDIMM3B_RX_P[10] ), |
| 539 | .rxp1 ( FBDIMM3B_RX_P[11] ), |
| 540 | .rxp2 ( FBDIMM3B_RX_P[12] ), |
| 541 | .rxp3 ( FBDIMM3B_RX_P[13] ), |
| 542 | .stcicfg ( fsr7_stcicfg[5:4] ), |
| 543 | .stciclk ( fsr7_stciclk[2] ), |
| 544 | .stcid ( fsr7_stcid[2] ), |
| 545 | .td0 ( {mcu3_fsr7_td6[0], mcu3_fsr7_td6[1], mcu3_fsr7_td6[2], mcu3_fsr7_td6[3], |
| 546 | mcu3_fsr7_td6[4], mcu3_fsr7_td6[5], mcu3_fsr7_td6[6], mcu3_fsr7_td6[7], |
| 547 | mcu3_fsr7_td6[8], mcu3_fsr7_td6[9], mcu3_fsr7_td6[10], mcu3_fsr7_td6[11]} ), |
| 548 | .td1 ( {mcu3_fsr7_td7[0], mcu3_fsr7_td7[1], mcu3_fsr7_td7[2], mcu3_fsr7_td7[3], |
| 549 | mcu3_fsr7_td7[4], mcu3_fsr7_td7[5], mcu3_fsr7_td7[6], mcu3_fsr7_td7[7], |
| 550 | mcu3_fsr7_td7[8], mcu3_fsr7_td7[9], mcu3_fsr7_td7[10], mcu3_fsr7_td7[11]} ), |
| 551 | .td2 ( {mcu3_fsr7_td8[0], mcu3_fsr7_td8[1], mcu3_fsr7_td8[2], mcu3_fsr7_td8[3], |
| 552 | mcu3_fsr7_td8[4], mcu3_fsr7_td8[5], mcu3_fsr7_td8[6], mcu3_fsr7_td8[7], |
| 553 | mcu3_fsr7_td8[8], mcu3_fsr7_td8[9], mcu3_fsr7_td8[10], mcu3_fsr7_td8[11]} ), |
| 554 | .td3 ( {mcu3_fsr7_td9[0], mcu3_fsr7_td9[1], mcu3_fsr7_td9[2], mcu3_fsr7_td9[3], |
| 555 | mcu3_fsr7_td9[4], mcu3_fsr7_td9[5], mcu3_fsr7_td9[6], mcu3_fsr7_td9[7], |
| 556 | mcu3_fsr7_td9[8], mcu3_fsr7_td9[9], mcu3_fsr7_td9[10], mcu3_fsr7_td9[11]} ), |
| 557 | .testcfg ( {mcu3_fsr7_testcfg2[17:14], 1'b0, mcu3_fsr7_testcfg2[13:11], 1'b0, mcu3_fsr7_testcfg2[10:0]} ), |
| 558 | .testclkr ( fsr7_testclkr[2] ), |
| 559 | .testclkt ( fsr7_testclkt[2] ), |
| 560 | .txbclkin ( {4{fsr7_txbclkin[2]}} ), |
| 561 | .amux ( FBDIMM3B_AMUX[2] ), |
| 562 | .fdo ( fsr7_fdo[2] ), |
| 563 | .rd0 ( {fsr7_mcu3_rd10[0], fsr7_mcu3_rd10[1], fsr7_mcu3_rd10[2], fsr7_mcu3_rd10[3], |
| 564 | fsr7_mcu3_rd10[4], fsr7_mcu3_rd10[5], fsr7_mcu3_rd10[6], fsr7_mcu3_rd10[7], |
| 565 | fsr7_mcu3_rd10[8], fsr7_mcu3_rd10[9], fsr7_mcu3_rd10[10], fsr7_mcu3_rd10[11]} ), |
| 566 | .rd1 ( {fsr7_mcu3_rd11[0], fsr7_mcu3_rd11[1], fsr7_mcu3_rd11[2], fsr7_mcu3_rd11[3], |
| 567 | fsr7_mcu3_rd11[4], fsr7_mcu3_rd11[5], fsr7_mcu3_rd11[6], fsr7_mcu3_rd11[7], |
| 568 | fsr7_mcu3_rd11[8], fsr7_mcu3_rd11[9], fsr7_mcu3_rd11[10], fsr7_mcu3_rd11[11]} ), |
| 569 | .rd2 ( {fsr7_mcu3_rd12[0], fsr7_mcu3_rd12[1], fsr7_mcu3_rd12[2], fsr7_mcu3_rd12[3], |
| 570 | fsr7_mcu3_rd12[4], fsr7_mcu3_rd12[5], fsr7_mcu3_rd12[6], fsr7_mcu3_rd12[7], |
| 571 | fsr7_mcu3_rd12[8], fsr7_mcu3_rd12[9], fsr7_mcu3_rd12[10], fsr7_mcu3_rd12[11]} ), |
| 572 | .rd3 ( {fsr7_mcu3_rd13[0], fsr7_mcu3_rd13[1], fsr7_mcu3_rd13[2], fsr7_mcu3_rd13[3], |
| 573 | fsr7_mcu3_rd13[4], fsr7_mcu3_rd13[5], fsr7_mcu3_rd13[6], fsr7_mcu3_rd13[7], |
| 574 | fsr7_mcu3_rd13[8], fsr7_mcu3_rd13[9], fsr7_mcu3_rd13[10], fsr7_mcu3_rd13[11]} ), |
| 575 | .rdll0 ( fsr7_rdll0_b81[1:0] ), |
| 576 | .rdll1 ( fsr7_rdll1_b81[1:0] ), |
| 577 | .rdll2 ( fsr7_rdll2_b81[1:0] ), |
| 578 | .rdll3 ( fsr7_rdll3_b81[1:0] ), |
| 579 | .rxbclk ( fsr7_mcu3_rxbclk[13:10] ), |
| 580 | .rxbclklln ( fsr7_rxbclklln_unused[13:10] ), |
| 581 | .rxbclkllp ( fsr7_rxbclkllp_unused[13:10] ), |
| 582 | .stciq ( fsr7_stciq[2] ), |
| 583 | .stspll ( {fsr7_mcu3_stspll_b81[2:0], fsr7_mcu3_stspll_lock[2]} ), |
| 584 | .stsrx0 ( {fsr7_mcu3_stsrx10_unused[2:1], fsr7_mcu3_stsrx_bsrxn[10], fsr7_mcu3_stsrx_bsrxp[10], |
| 585 | fsr7_mcu3_stsrx_losdtct[10], fsr7_mcu3_stsrx10_unused[0], fsr7_mcu3_stsrx_sync[10], |
| 586 | fsr7_mcu3_stsrx_testfail[10]} ), |
| 587 | .stsrx1 ( {fsr7_mcu3_stsrx11_unused[2:1], fsr7_mcu3_stsrx_bsrxn[11], fsr7_mcu3_stsrx_bsrxp[11], |
| 588 | fsr7_mcu3_stsrx_losdtct[11], fsr7_mcu3_stsrx11_unused[0], fsr7_mcu3_stsrx_sync[11], |
| 589 | fsr7_mcu3_stsrx_testfail[11]} ), |
| 590 | .stsrx2 ( {fsr7_mcu3_stsrx12_unused[2:1], fsr7_mcu3_stsrx_bsrxn[12], fsr7_mcu3_stsrx_bsrxp[12], |
| 591 | fsr7_mcu3_stsrx_losdtct[12], fsr7_mcu3_stsrx12_unused[0], fsr7_mcu3_stsrx_sync[12], |
| 592 | fsr7_mcu3_stsrx_testfail[12]} ), |
| 593 | .stsrx3 ( {fsr7_mcu3_stsrx13_unused[2:1], fsr7_mcu3_stsrx_bsrxn[13], fsr7_mcu3_stsrx_bsrxp[13], |
| 594 | fsr7_mcu3_stsrx_losdtct[13], fsr7_mcu3_stsrx13_unused[0], fsr7_mcu3_stsrx_sync[13], |
| 595 | fsr7_mcu3_stsrx_testfail[13]} ), |
| 596 | .ststx0 ( {fsr7_mcu3_ststx6_unused[2:0], fsr7_mcu3_ststx_testfail[6]} ), |
| 597 | .ststx1 ( {fsr7_mcu3_ststx7_unused[2:0], fsr7_mcu3_ststx_testfail[7]} ), |
| 598 | .ststx2 ( {fsr7_mcu3_ststx8_unused[2:0], fsr7_mcu3_ststx_testfail[8]} ), |
| 599 | .ststx3 ( {fsr7_mcu3_ststx9_unused[2:0], fsr7_mcu3_ststx_testfail[9]} ), |
| 600 | .txbclk ( fsr7_txbclk_unused[9:6] ), |
| 601 | .txn0 ( FBDIMM3B_TX_N[6] ), |
| 602 | .txn1 ( FBDIMM3B_TX_N[7] ), |
| 603 | .txn2 ( FBDIMM3B_TX_N[8] ), |
| 604 | .txn3 ( FBDIMM3B_TX_N[9] ), |
| 605 | .txp0 ( FBDIMM3B_TX_P[6] ), |
| 606 | .txp1 ( FBDIMM3B_TX_P[7] ), |
| 607 | .txp2 ( FBDIMM3B_TX_P[8] ), |
| 608 | .txp3 ( FBDIMM3B_TX_P[9] ), |
| 609 | .atpgmd ( fsr7_atpgtq_b81[1] ), |
| 610 | .atpgmq ( fsr7_atpgmq_b81 ), |
| 611 | .atpgrd ( {fsr7_atpgrq_b81[2],fsr7_atpgtq_b81[2],fsr7_atpgrq_b81[0],fsr7_atpgtq_b81[0]} ), |
| 612 | .atpgrq ( fsr7_atpgrq_b81[3:0] ), |
| 613 | .atpgtd ( {fsr7_atpgrq_b81[3],fsr7_atpgmq_b81,fsr7_atpgrq_b81[1],fsr7_atpgtq_a8[1]} ), |
| 614 | .atpgtq ( {fsr_bottom_atpgq,fsr7_atpgtq_b81[2:0]} ), |
| 615 | .vdda ( VDDA ), |
| 616 | .vddd ( VDDD ), |
| 617 | .vddr ( VDDR ), |
| 618 | .vddt ( VDDT ), |
| 619 | .vssa ( VSSA ) |
| 620 | ); |
| 621 | |
| 622 | endmodule |
| 623 | |