| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcu_frdbuf_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mcu_frdbuf_dp ( |
| 36 | frdbuf_data, |
| 37 | frdbuf_elect_idle_sync, |
| 38 | frdbuf_frame_lock, |
| 39 | frdbuf_testfail_sync, |
| 40 | fsr_data, |
| 41 | fsr_stsrx_sync, |
| 42 | fsr_stsrx_losdtct, |
| 43 | fsr_stsrx_testfail, |
| 44 | fdout_rptr, |
| 45 | fdout_frame_lock, |
| 46 | fbdic_enable_sync_count, |
| 47 | rxbclk, |
| 48 | drl2clk, |
| 49 | tcu_pce_ov, |
| 50 | tcu_aclk, |
| 51 | tcu_bclk, |
| 52 | tcu_scan_en, |
| 53 | tcu_mcu_fbd_clk_stop, |
| 54 | tcu_mcu_testmode, |
| 55 | tcu_atpg_mode, |
| 56 | scan_in, |
| 57 | scan_out); |
| 58 | wire pce_ov; |
| 59 | wire stop; |
| 60 | wire siclk; |
| 61 | wire soclk; |
| 62 | wire se; |
| 63 | wire fbd_siclk; |
| 64 | wire fbd_soclk; |
| 65 | wire fbd_se; |
| 66 | wire ff_clk_stop_sync_scanin; |
| 67 | wire ff_clk_stop_sync_scanout; |
| 68 | wire clk_stop_d1; |
| 69 | wire tcu_pce_ov_d1; |
| 70 | wire rxbclk_stop; |
| 71 | wire fbd_pce_ov; |
| 72 | wire rxbclk_stop_l; |
| 73 | wire rxbclk_stop_atpg; |
| 74 | wire rxb_l1clk; |
| 75 | wire rxb_siclk; |
| 76 | wire rxb_soclk; |
| 77 | wire alat10_so; |
| 78 | wire alat11_so; |
| 79 | wire [11:0] latout; |
| 80 | wire alat9_so; |
| 81 | wire alat8_so; |
| 82 | wire alat7_so; |
| 83 | wire alat6_so; |
| 84 | wire alat5_so; |
| 85 | wire alat4_so; |
| 86 | wire alat3_so; |
| 87 | wire alat2_so; |
| 88 | wire alat1_so; |
| 89 | wire alat0_so; |
| 90 | wire alat0_si; |
| 91 | wire [11:0] latout_buf; |
| 92 | wire [3:0] frdbuf_cnt; |
| 93 | wire fsr_stsrx_sync_lat; |
| 94 | wire [3:0] frdbuf_cnt_next; |
| 95 | wire frdbuf_cnt_cout_unused; |
| 96 | wire fsr_stsrx_losdtct_sync_l; |
| 97 | wire frdbuf_enable_sync_count; |
| 98 | wire [3:0] frdbuf_cnt_in; |
| 99 | wire fbd_siclk_out; |
| 100 | wire fbd_soclk_out; |
| 101 | wire l1clk_cnt; |
| 102 | wire [10:0] sout; |
| 103 | wire ff_cnt_scanout; |
| 104 | wire frdbuf_frame_lock_in; |
| 105 | wire [1:0] frdbuf_wptr_in; |
| 106 | wire [1:0] frdbuf_wptr; |
| 107 | wire fsr_stsrx_losdtct_d1; |
| 108 | wire fsr_stsrx_losdtct_sync; |
| 109 | wire frdbuf_enable_sync_count_in; |
| 110 | wire ff_cnt_scanin; |
| 111 | wire t2; |
| 112 | wire frdbuf_frame_lock_l; |
| 113 | wire [1:0] frdbuf_wptr_l; |
| 114 | wire frdbuf_buffer0_en; |
| 115 | wire ff_buffer0_scanin; |
| 116 | wire ff_buffer0_scanout; |
| 117 | wire [11:0] frdbuf_buffer0; |
| 118 | wire frdbuf_buffer1_en; |
| 119 | wire ff_buffer1_scanin; |
| 120 | wire ff_buffer1_scanout; |
| 121 | wire [11:0] frdbuf_buffer1; |
| 122 | wire frdbuf_buffer2_en; |
| 123 | wire ff_buffer2_scanin; |
| 124 | wire ff_buffer2_scanout; |
| 125 | wire [11:0] frdbuf_buffer2; |
| 126 | wire frdbuf_buffer3_en; |
| 127 | wire ff_buffer3_scanin; |
| 128 | wire ff_buffer3_scanout; |
| 129 | wire [11:0] frdbuf_buffer3; |
| 130 | wire ff_sync_scanin; |
| 131 | wire ff_sync_scanout; |
| 132 | wire frdbuf_testfail_d1; |
| 133 | wire frdbuf_elect_idle_d1; |
| 134 | wire [1:0] fdout_rptr_l; |
| 135 | wire sl0; |
| 136 | wire sl1; |
| 137 | wire sl2; |
| 138 | wire sl3; |
| 139 | wire ff_data_sync_scanin; |
| 140 | wire ff_data_sync_scanout; |
| 141 | wire tcu_mcu_testmode_l; |
| 142 | wire m_scan_mux_scanout; |
| 143 | |
| 144 | |
| 145 | output [11:0] frdbuf_data; |
| 146 | output frdbuf_elect_idle_sync; |
| 147 | output frdbuf_frame_lock; |
| 148 | output frdbuf_testfail_sync; |
| 149 | |
| 150 | input [11:0] fsr_data; |
| 151 | input fsr_stsrx_sync; |
| 152 | input fsr_stsrx_losdtct; |
| 153 | input fsr_stsrx_testfail; |
| 154 | input [1:0] fdout_rptr; |
| 155 | input fdout_frame_lock; |
| 156 | input fbdic_enable_sync_count; |
| 157 | |
| 158 | input rxbclk; |
| 159 | input drl2clk; |
| 160 | |
| 161 | input tcu_pce_ov; |
| 162 | input tcu_aclk; |
| 163 | input tcu_bclk; |
| 164 | input tcu_scan_en; |
| 165 | input tcu_mcu_fbd_clk_stop; |
| 166 | input tcu_mcu_testmode; |
| 167 | input tcu_atpg_mode; |
| 168 | |
| 169 | input scan_in; |
| 170 | output scan_out; |
| 171 | |
| 172 | assign pce_ov = tcu_pce_ov; |
| 173 | assign stop = 1'b0; |
| 174 | assign siclk = tcu_aclk; |
| 175 | assign soclk = tcu_bclk; |
| 176 | assign se = tcu_scan_en; |
| 177 | |
| 178 | // |
| 179 | mcu_frdbuf_dp_and_macro m_fbd_siclk ( |
| 180 | .din0(tcu_aclk), |
| 181 | .din1(tcu_mcu_testmode), |
| 182 | .dout(fbd_siclk)); |
| 183 | |
| 184 | mcu_frdbuf_dp_and_macro m_fbd_soclk ( |
| 185 | .din0(tcu_bclk), |
| 186 | .din1(tcu_mcu_testmode), |
| 187 | .dout(fbd_soclk)); |
| 188 | |
| 189 | mcu_frdbuf_dp_and_macro m_fbd_se ( |
| 190 | .din0(tcu_scan_en), |
| 191 | .din1(tcu_mcu_testmode), |
| 192 | .dout(fbd_se)); |
| 193 | |
| 194 | assign ff_clk_stop_sync_scanin = 1'b0; |
| 195 | mcu_frdbuf_dp_msff_macro__stack_11r__width_4 ff_clk_stop_sync ( |
| 196 | .scan_in(ff_clk_stop_sync_scanin), |
| 197 | .scan_out(ff_clk_stop_sync_scanout), |
| 198 | .din({tcu_mcu_fbd_clk_stop, clk_stop_d1, tcu_pce_ov, tcu_pce_ov_d1}), |
| 199 | .dout({clk_stop_d1, rxbclk_stop, tcu_pce_ov_d1, fbd_pce_ov}), |
| 200 | .en(1'b1), |
| 201 | .se(1'b0), |
| 202 | .siclk(1'b0), |
| 203 | .soclk(1'b0), |
| 204 | .pce_ov(1'b0), |
| 205 | .clk(rxbclk), |
| 206 | .stop(stop)); |
| 207 | |
| 208 | // want to turn off clk_stop in atpg_mode |
| 209 | mcu_frdbuf_dp_inv_macro m_inv_rxbclk_stop ( |
| 210 | .din(rxbclk_stop), |
| 211 | .dout(rxbclk_stop_l)); |
| 212 | |
| 213 | mcu_frdbuf_dp_nor_macro m_rxbclk_stop_atpg ( |
| 214 | .din0(rxbclk_stop_l), |
| 215 | .din1(tcu_atpg_mode), |
| 216 | .dout(rxbclk_stop_atpg)); |
| 217 | |
| 218 | //////////////////////////// |
| 219 | // SERDES Clock Domain |
| 220 | //////////////////////////// |
| 221 | |
| 222 | cl_dp1_l1hdr_8x alat_hdr ( |
| 223 | .l2clk(rxbclk), |
| 224 | .pce(1'b1), |
| 225 | .aclk(fbd_siclk), |
| 226 | .bclk(fbd_soclk), |
| 227 | .l1clk(rxb_l1clk), |
| 228 | .se(fbd_se), |
| 229 | .pce_ov(fbd_pce_ov), |
| 230 | .stop(rxbclk_stop_atpg), |
| 231 | .siclk_out(rxb_siclk), |
| 232 | .soclk_out(rxb_soclk)); |
| 233 | |
| 234 | cl_dp1_alatch_4x alat11 ( |
| 235 | .si(alat10_so), |
| 236 | .so(alat11_so), |
| 237 | .q(latout[11]), |
| 238 | .d(fsr_data[11]), |
| 239 | .se(fbd_se), |
| 240 | .siclk(rxb_siclk), |
| 241 | .soclk(rxb_soclk), |
| 242 | .l1clk(rxb_l1clk)); |
| 243 | |
| 244 | cl_dp1_alatch_4x alat10 ( |
| 245 | .si(alat9_so), |
| 246 | .so(alat10_so), |
| 247 | .q(latout[10]), |
| 248 | .d(fsr_data[10]), |
| 249 | .se(fbd_se), |
| 250 | .siclk(rxb_siclk), |
| 251 | .soclk(rxb_soclk), |
| 252 | .l1clk(rxb_l1clk)); |
| 253 | |
| 254 | cl_dp1_alatch_4x alat9 ( |
| 255 | .si(alat8_so), |
| 256 | .so(alat9_so), |
| 257 | .q(latout[9]), |
| 258 | .d(fsr_data[9]), |
| 259 | .se(fbd_se), |
| 260 | .siclk(rxb_siclk), |
| 261 | .soclk(rxb_soclk), |
| 262 | .l1clk(rxb_l1clk)); |
| 263 | |
| 264 | cl_dp1_alatch_4x alat8 ( |
| 265 | .si(alat7_so), |
| 266 | .so(alat8_so), |
| 267 | .q(latout[8]), |
| 268 | .d(fsr_data[8]), |
| 269 | .se(fbd_se), |
| 270 | .siclk(rxb_siclk), |
| 271 | .soclk(rxb_soclk), |
| 272 | .l1clk(rxb_l1clk)); |
| 273 | |
| 274 | cl_dp1_alatch_4x alat7 ( |
| 275 | .si(alat6_so), |
| 276 | .so(alat7_so), |
| 277 | .q(latout[7]), |
| 278 | .d(fsr_data[7]), |
| 279 | .se(fbd_se), |
| 280 | .siclk(rxb_siclk), |
| 281 | .soclk(rxb_soclk), |
| 282 | .l1clk(rxb_l1clk)); |
| 283 | |
| 284 | cl_dp1_alatch_4x alat6 ( |
| 285 | .si(alat5_so), |
| 286 | .so(alat6_so), |
| 287 | .q(latout[6]), |
| 288 | .d(fsr_data[6]), |
| 289 | .se(fbd_se), |
| 290 | .siclk(rxb_siclk), |
| 291 | .soclk(rxb_soclk), |
| 292 | .l1clk(rxb_l1clk)); |
| 293 | |
| 294 | cl_dp1_alatch_4x alat5 ( |
| 295 | .si(alat4_so), |
| 296 | .so(alat5_so), |
| 297 | .q(latout[5]), |
| 298 | .d(fsr_data[5]), |
| 299 | .se(fbd_se), |
| 300 | .siclk(rxb_siclk), |
| 301 | .soclk(rxb_soclk), |
| 302 | .l1clk(rxb_l1clk)); |
| 303 | |
| 304 | cl_dp1_alatch_4x alat4 ( |
| 305 | .si(alat3_so), |
| 306 | .so(alat4_so), |
| 307 | .q(latout[4]), |
| 308 | .d(fsr_data[4]), |
| 309 | .se(fbd_se), |
| 310 | .siclk(rxb_siclk), |
| 311 | .soclk(rxb_soclk), |
| 312 | .l1clk(rxb_l1clk)); |
| 313 | |
| 314 | cl_dp1_alatch_4x alat3 ( |
| 315 | .si(alat2_so), |
| 316 | .so(alat3_so), |
| 317 | .q(latout[3]), |
| 318 | .d(fsr_data[3]), |
| 319 | .se(fbd_se), |
| 320 | .siclk(rxb_siclk), |
| 321 | .soclk(rxb_soclk), |
| 322 | .l1clk(rxb_l1clk)); |
| 323 | |
| 324 | cl_dp1_alatch_4x alat2 ( |
| 325 | .si(alat1_so), |
| 326 | .so(alat2_so), |
| 327 | .q(latout[2]), |
| 328 | .d(fsr_data[2]), |
| 329 | .se(fbd_se), |
| 330 | .siclk(rxb_siclk), |
| 331 | .soclk(rxb_soclk), |
| 332 | .l1clk(rxb_l1clk)); |
| 333 | |
| 334 | cl_dp1_alatch_4x alat1 ( |
| 335 | .si(alat0_so), |
| 336 | .so(alat1_so), |
| 337 | .q(latout[1]), |
| 338 | .d(fsr_data[1]), |
| 339 | .se(fbd_se), |
| 340 | .siclk(rxb_siclk), |
| 341 | .soclk(rxb_soclk), |
| 342 | .l1clk(rxb_l1clk)); |
| 343 | |
| 344 | cl_dp1_alatch_4x alat0 ( |
| 345 | .si(alat0_si), |
| 346 | .so(alat0_so), |
| 347 | .q(latout[0]), |
| 348 | .d(fsr_data[0]), |
| 349 | .se(fbd_se), |
| 350 | .siclk(rxb_siclk), |
| 351 | .soclk(rxb_soclk), |
| 352 | .l1clk(rxb_l1clk)); |
| 353 | |
| 354 | mcu_frdbuf_dp_buff_macro__minbuff_1__stack_12r__width_12 m_alat_buf ( |
| 355 | .din(latout[11:0]), |
| 356 | .dout(latout_buf[11:0])); |
| 357 | |
| 358 | // Count 4 frame sync signals from SERDES before determining frame lock |
| 359 | // Reset on electrical idle |
| 360 | |
| 361 | mcu_frdbuf_dp_increment_macro__width_4 m_frdbuf_cnt_inc ( |
| 362 | .din ( frdbuf_cnt[3:0] ), |
| 363 | .cin ( fsr_stsrx_sync_lat ), |
| 364 | .dout ( frdbuf_cnt_next[3:0] ), |
| 365 | .cout ( frdbuf_cnt_cout_unused ) ); |
| 366 | |
| 367 | mcu_frdbuf_dp_and_macro__ports_3__width_4 m_frdbuf_cnt_clr ( |
| 368 | .din0(frdbuf_cnt_next[3:0]), |
| 369 | .din1({4{fsr_stsrx_losdtct_sync_l}}), |
| 370 | .din2({4{frdbuf_enable_sync_count}}), |
| 371 | .dout(frdbuf_cnt_in[3:0])); |
| 372 | |
| 373 | // ff_cnt[11:0] |
| 374 | cl_dp1_l1hdr_8x ff_cnt_hdr ( |
| 375 | .l2clk(rxbclk), |
| 376 | .pce(1'b1), |
| 377 | .aclk(fbd_siclk), |
| 378 | .bclk(fbd_soclk), |
| 379 | .siclk_out(fbd_siclk_out), |
| 380 | .soclk_out(fbd_soclk_out), |
| 381 | .l1clk(l1clk_cnt), |
| 382 | .se(fbd_se), |
| 383 | .pce_ov(fbd_pce_ov), |
| 384 | .stop(rxbclk_stop_atpg)); |
| 385 | |
| 386 | cl_dp1_alatch_4x ff_cnt_d11 ( |
| 387 | .si(sout[10]), |
| 388 | .so(ff_cnt_scanout), |
| 389 | .q(fsr_stsrx_sync_lat), |
| 390 | .d(fsr_stsrx_sync), |
| 391 | .se(fbd_se), |
| 392 | .siclk(fbd_siclk_out), |
| 393 | .soclk(fbd_soclk_out), |
| 394 | .l1clk(l1clk_cnt)); |
| 395 | |
| 396 | cl_dp1_msff_4x ff_cnt_d10 ( |
| 397 | .l1clk(l1clk_cnt), |
| 398 | .d(frdbuf_frame_lock_in), |
| 399 | .siclk(fbd_siclk_out), |
| 400 | .soclk(fbd_soclk_out), |
| 401 | .si(sout[9]), |
| 402 | .so(sout[10]), |
| 403 | .q(frdbuf_frame_lock)); |
| 404 | |
| 405 | cl_dp1_msff_4x ff_cnt_d9 ( |
| 406 | .l1clk(l1clk_cnt), |
| 407 | .d(frdbuf_wptr_in[1]), |
| 408 | .siclk(fbd_siclk_out), |
| 409 | .soclk(fbd_soclk_out), |
| 410 | .si(sout[8]), |
| 411 | .so(sout[9]), |
| 412 | .q(frdbuf_wptr[1])); |
| 413 | |
| 414 | cl_dp1_msff_4x ff_cnt_d8 ( |
| 415 | .l1clk(l1clk_cnt), |
| 416 | .d(frdbuf_wptr_in[0]), |
| 417 | .siclk(fbd_siclk_out), |
| 418 | .soclk(fbd_soclk_out), |
| 419 | .si(sout[7]), |
| 420 | .so(sout[8]), |
| 421 | .q(frdbuf_wptr[0])); |
| 422 | |
| 423 | cl_dp1_msff_4x ff_cnt_d7 ( |
| 424 | .l1clk(l1clk_cnt), |
| 425 | .d(frdbuf_cnt_in[3]), |
| 426 | .siclk(fbd_siclk_out), |
| 427 | .soclk(fbd_soclk_out), |
| 428 | .si(sout[6]), |
| 429 | .so(sout[7]), |
| 430 | .q(frdbuf_cnt[3])); |
| 431 | |
| 432 | cl_dp1_msff_4x ff_cnt_d6 ( |
| 433 | .l1clk(l1clk_cnt), |
| 434 | .d(frdbuf_cnt_in[2]), |
| 435 | .siclk(fbd_siclk_out), |
| 436 | .soclk(fbd_soclk_out), |
| 437 | .si(sout[5]), |
| 438 | .so(sout[6]), |
| 439 | .q(frdbuf_cnt[2])); |
| 440 | |
| 441 | cl_dp1_msff_4x ff_cnt_d5 ( |
| 442 | .l1clk(l1clk_cnt), |
| 443 | .d(frdbuf_cnt_in[1]), |
| 444 | .siclk(fbd_siclk_out), |
| 445 | .soclk(fbd_soclk_out), |
| 446 | .si(sout[4]), |
| 447 | .so(sout[5]), |
| 448 | .q(frdbuf_cnt[1])); |
| 449 | |
| 450 | cl_dp1_msff_4x ff_cnt_d4 ( |
| 451 | .l1clk(l1clk_cnt), |
| 452 | .d(frdbuf_cnt_in[0]), |
| 453 | .siclk(fbd_siclk_out), |
| 454 | .soclk(fbd_soclk_out), |
| 455 | .si(sout[3]), |
| 456 | .so(sout[4]), |
| 457 | .q(frdbuf_cnt[0])); |
| 458 | |
| 459 | cl_dp1_msff_4x ff_cnt_d3 ( |
| 460 | .l1clk(l1clk_cnt), |
| 461 | .d(fsr_stsrx_losdtct), |
| 462 | .siclk(fbd_siclk_out), |
| 463 | .soclk(fbd_soclk_out), |
| 464 | .si(sout[2]), |
| 465 | .so(sout[3]), |
| 466 | .q(fsr_stsrx_losdtct_d1)); |
| 467 | |
| 468 | cl_dp1_msff_4x ff_cnt_d2 ( |
| 469 | .l1clk(l1clk_cnt), |
| 470 | .d(fsr_stsrx_losdtct_d1), |
| 471 | .siclk(fbd_siclk_out), |
| 472 | .soclk(fbd_soclk_out), |
| 473 | .si(sout[1]), |
| 474 | .so(sout[2]), |
| 475 | .q(fsr_stsrx_losdtct_sync)); |
| 476 | |
| 477 | cl_dp1_msff_4x ff_cnt_d1 ( |
| 478 | .l1clk(l1clk_cnt), |
| 479 | .d(fbdic_enable_sync_count), |
| 480 | .siclk(fbd_siclk_out), |
| 481 | .soclk(fbd_soclk_out), |
| 482 | .si(sout[0]), |
| 483 | .so(sout[1]), |
| 484 | .q(frdbuf_enable_sync_count_in)); |
| 485 | |
| 486 | cl_dp1_msff_4x ff_cnt_d0 ( |
| 487 | .l1clk(l1clk_cnt), |
| 488 | .d(frdbuf_enable_sync_count_in), |
| 489 | .siclk(fbd_siclk_out), |
| 490 | .soclk(fbd_soclk_out), |
| 491 | .si(ff_cnt_scanin), |
| 492 | .so(sout[0]), |
| 493 | .q(frdbuf_enable_sync_count)); |
| 494 | |
| 495 | ////csret 11/12/2004 |
| 496 | //assign frdbuf_frame_lock_in = ~fsr_fbd_elect_idle & (frdbuf_cnt[2] | frdbuf_frame_lock); |
| 497 | |
| 498 | mcu_frdbuf_dp_or_macro__ports_2__width_1 m_or_0_0 ( |
| 499 | .din0 ( frdbuf_cnt[2] ), |
| 500 | .din1 ( frdbuf_frame_lock ), |
| 501 | .dout ( t2 ) ); |
| 502 | |
| 503 | mcu_frdbuf_dp_inv_macro__width_1 m_fsr_fbd_elect_idle_not ( |
| 504 | .din ( fsr_stsrx_losdtct_sync ), |
| 505 | .dout ( fsr_stsrx_losdtct_sync_l ) ); |
| 506 | |
| 507 | mcu_frdbuf_dp_and_macro__ports_2__width_1 m_frdbuf_frame_lock_in ( |
| 508 | .din0 ( fsr_stsrx_losdtct_sync_l ), |
| 509 | .din1 ( t2 ), |
| 510 | .dout ( frdbuf_frame_lock_in ) ); |
| 511 | |
| 512 | mcu_frdbuf_dp_inv_macro__width_1 m_frdbuf_frame_lock_inv ( |
| 513 | .din ( frdbuf_frame_lock ), |
| 514 | .dout ( frdbuf_frame_lock_l ) ); |
| 515 | |
| 516 | ////csret 11/12/2004 |
| 517 | // write pointer for asynchronous buffer, enabled by frame lock in SERDES clock domain |
| 518 | //assign frdbuf_wptr_in[1:0] = {2{frdbuf_frame_lock}} & {frdbuf_wptr[0],~frdbuf_wptr[1]}; |
| 519 | |
| 520 | mcu_frdbuf_dp_inv_macro__width_2 m_frdbuf_wptr_inv ( |
| 521 | .din ( frdbuf_wptr[1:0] ), |
| 522 | .dout ( frdbuf_wptr_l[1:0] ) ); |
| 523 | |
| 524 | mcu_frdbuf_dp_and_macro__width_2 m_frdbuf_wptr_in ( |
| 525 | .din0({frdbuf_wptr[0],frdbuf_wptr_l[1]}), |
| 526 | .din1({2{frdbuf_frame_lock}}), |
| 527 | .dout(frdbuf_wptr_in[1:0])); |
| 528 | |
| 529 | ////csret 11/12/2004 |
| 530 | // Four deep buffer for asynchronous clock domain crossing |
| 531 | //assign frdbuf_buffer0_en = frdbuf_frame_lock & ~frdbuf_wptr[1] & ~frdbuf_wptr[0]; |
| 532 | mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer0_en ( |
| 533 | .din0 ( frdbuf_wptr[0] ), |
| 534 | .din1 ( frdbuf_wptr[1] ), |
| 535 | .din2 ( frdbuf_frame_lock_l ), |
| 536 | .dout ( frdbuf_buffer0_en ) ); |
| 537 | |
| 538 | mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer0 ( |
| 539 | .scan_in(ff_buffer0_scanin), |
| 540 | .scan_out(ff_buffer0_scanout), |
| 541 | .din(latout_buf[11:0]), |
| 542 | .dout(frdbuf_buffer0[11:0]), |
| 543 | .en(frdbuf_buffer0_en), |
| 544 | .se(fbd_se), |
| 545 | .siclk(fbd_siclk), |
| 546 | .soclk(fbd_soclk), |
| 547 | .stop(rxbclk_stop_atpg), |
| 548 | .pce_ov(fbd_pce_ov), |
| 549 | .clk(rxbclk)); |
| 550 | |
| 551 | ////csret 11/12/2004 |
| 552 | //assign frdbuf_buffer1_en = frdbuf_frame_lock & ~frdbuf_wptr[1] & frdbuf_wptr[0]; |
| 553 | mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer1_en ( |
| 554 | .din0 ( frdbuf_wptr[1] ), |
| 555 | .din1 ( frdbuf_wptr_l[0] ), |
| 556 | .din2 ( frdbuf_frame_lock_l ), |
| 557 | .dout ( frdbuf_buffer1_en ) ); |
| 558 | |
| 559 | mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer1 ( |
| 560 | .scan_in(ff_buffer1_scanin), |
| 561 | .scan_out(ff_buffer1_scanout), |
| 562 | .din(latout_buf[11:0]), |
| 563 | .dout(frdbuf_buffer1[11:0]), |
| 564 | .en(frdbuf_buffer1_en), |
| 565 | .se(fbd_se), |
| 566 | .siclk(fbd_siclk), |
| 567 | .soclk(fbd_soclk), |
| 568 | .stop(rxbclk_stop_atpg), |
| 569 | .pce_ov(fbd_pce_ov), |
| 570 | .clk(rxbclk)); |
| 571 | |
| 572 | ////csret 11/12/2004 |
| 573 | //assign frdbuf_buffer2_en = frdbuf_frame_lock & frdbuf_wptr[1] & ~frdbuf_wptr[0]; |
| 574 | mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer2_en ( |
| 575 | .din0 ( frdbuf_wptr[0] ), |
| 576 | .din1 ( frdbuf_wptr_l[1] ), |
| 577 | .din2 ( frdbuf_frame_lock_l ), |
| 578 | .dout ( frdbuf_buffer2_en ) ); |
| 579 | |
| 580 | mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer2 ( |
| 581 | .scan_in(ff_buffer2_scanin), |
| 582 | .scan_out(ff_buffer2_scanout), |
| 583 | .din(latout_buf[11:0]), |
| 584 | .dout(frdbuf_buffer2[11:0]), |
| 585 | .en(frdbuf_buffer2_en), |
| 586 | .se(fbd_se), |
| 587 | .siclk(fbd_siclk), |
| 588 | .soclk(fbd_soclk), |
| 589 | .stop(rxbclk_stop_atpg), |
| 590 | .pce_ov(fbd_pce_ov), |
| 591 | .clk(rxbclk)); |
| 592 | |
| 593 | ////csret 11/12/2004 |
| 594 | //assign frdbuf_buffer3_en = frdbuf_frame_lock & frdbuf_wptr[1] & frdbuf_wptr[0]; |
| 595 | mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer3_en ( |
| 596 | .din0 ( frdbuf_wptr_l[0] ), |
| 597 | .din1 ( frdbuf_wptr_l[1] ), |
| 598 | .din2 ( frdbuf_frame_lock_l ), |
| 599 | .dout ( frdbuf_buffer3_en ) ); |
| 600 | |
| 601 | mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer3 ( |
| 602 | .scan_in(ff_buffer3_scanin), |
| 603 | .scan_out(ff_buffer3_scanout), |
| 604 | .din(latout_buf[11:0]), |
| 605 | .dout(frdbuf_buffer3[11:0]), |
| 606 | .en(frdbuf_buffer3_en), |
| 607 | .se(fbd_se), |
| 608 | .siclk(fbd_siclk), |
| 609 | .soclk(fbd_soclk), |
| 610 | .stop(rxbclk_stop_atpg), |
| 611 | .pce_ov(fbd_pce_ov), |
| 612 | .clk(rxbclk)); |
| 613 | |
| 614 | //////////////////////////// |
| 615 | // MCU Clock Domain |
| 616 | //////////////////////////// |
| 617 | |
| 618 | // Synchronize electrical idle and frame lock signals for MCU |
| 619 | mcu_frdbuf_dp_msff_macro__stack_12r__width_4 ff_sync ( |
| 620 | .scan_in(ff_sync_scanin), |
| 621 | .scan_out(ff_sync_scanout), |
| 622 | .din({fsr_stsrx_testfail,frdbuf_testfail_d1,fsr_stsrx_losdtct,frdbuf_elect_idle_d1}), |
| 623 | .dout({frdbuf_testfail_d1,frdbuf_testfail_sync,frdbuf_elect_idle_d1,frdbuf_elect_idle_sync}), |
| 624 | .en(1'b1), |
| 625 | .clk(drl2clk), |
| 626 | .se(se), |
| 627 | .siclk(siclk), |
| 628 | .soclk(soclk), |
| 629 | .pce_ov(pce_ov), |
| 630 | .stop(stop)); |
| 631 | |
| 632 | mcu_frdbuf_dp_inv_macro__width_2 m_frdbuf_rptr_inv ( |
| 633 | .din ( fdout_rptr[1:0] ), |
| 634 | .dout ( fdout_rptr_l[1:0] ) ); |
| 635 | |
| 636 | // Selection of async buffer output |
| 637 | |
| 638 | mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl0 ( |
| 639 | .dout ( sl0 ), |
| 640 | .din0 ( fdout_rptr[0] ), |
| 641 | .din1 ( fdout_rptr[1] ) ); |
| 642 | |
| 643 | mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl1 ( |
| 644 | .dout ( sl1 ), |
| 645 | .din0 ( fdout_rptr_l[0] ), |
| 646 | .din1 ( fdout_rptr[1] ) ); |
| 647 | |
| 648 | mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl2 ( |
| 649 | .dout ( sl2 ), |
| 650 | .din0 ( fdout_rptr[0] ), |
| 651 | .din1 ( fdout_rptr_l[1] ) ); |
| 652 | |
| 653 | mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl3 ( |
| 654 | .dout ( sl3 ), |
| 655 | .din0 ( fdout_rptr_l[0] ), |
| 656 | .din1 ( fdout_rptr_l[1] ) ); |
| 657 | |
| 658 | mcu_frdbuf_dp_msff_macro__mux_aonpe__ports_4__stack_12r__width_12 ff_data_sync ( |
| 659 | .scan_in(ff_data_sync_scanin), |
| 660 | .scan_out(ff_data_sync_scanout), |
| 661 | .din0 ( frdbuf_buffer0[11:0] ), |
| 662 | .din1 ( frdbuf_buffer1[11:0] ), |
| 663 | .din2 ( frdbuf_buffer2[11:0] ), |
| 664 | .din3 ( frdbuf_buffer3[11:0] ), |
| 665 | .dout ( frdbuf_data[11:0] ), |
| 666 | .sel0 ( sl0 ), |
| 667 | .sel1 ( sl1 ), |
| 668 | .sel2 ( sl2 ), |
| 669 | .sel3 ( sl3 ), |
| 670 | .en (fdout_frame_lock), |
| 671 | .clk (drl2clk), |
| 672 | .se(se), |
| 673 | .siclk(siclk), |
| 674 | .soclk(soclk), |
| 675 | .pce_ov(pce_ov), |
| 676 | .stop(stop)); |
| 677 | |
| 678 | mcu_frdbuf_dp_inv_macro m_inv_testmode ( |
| 679 | .din(tcu_mcu_testmode), |
| 680 | .dout(tcu_mcu_testmode_l)); |
| 681 | |
| 682 | mcu_frdbuf_dp_mux_macro__buffsel_none__mux_aonpe m_scan_mux ( |
| 683 | .din0(ff_buffer3_scanout), |
| 684 | .din1(scan_in), |
| 685 | .sel0(tcu_mcu_testmode), |
| 686 | .sel1(tcu_mcu_testmode_l), |
| 687 | .dout(m_scan_mux_scanout)); |
| 688 | |
| 689 | assign alat0_si = scan_in ; |
| 690 | assign ff_cnt_scanin = alat11_so ; |
| 691 | assign ff_buffer0_scanin = ff_cnt_scanout ; |
| 692 | assign ff_buffer1_scanin = ff_buffer0_scanout ; |
| 693 | assign ff_buffer2_scanin = ff_buffer1_scanout ; |
| 694 | assign ff_buffer3_scanin = ff_buffer2_scanout ; |
| 695 | assign ff_sync_scanin = m_scan_mux_scanout ; |
| 696 | assign ff_data_sync_scanin = ff_sync_scanout ; |
| 697 | assign scan_out = ff_data_sync_scanout ; |
| 698 | |
| 699 | endmodule |
| 700 | |
| 701 | |
| 702 | // |
| 703 | // and macro for ports = 2,3,4 |
| 704 | // |
| 705 | // |
| 706 | |
| 707 | |
| 708 | |
| 709 | |
| 710 | |
| 711 | module mcu_frdbuf_dp_and_macro ( |
| 712 | din0, |
| 713 | din1, |
| 714 | dout); |
| 715 | input [0:0] din0; |
| 716 | input [0:0] din1; |
| 717 | output [0:0] dout; |
| 718 | |
| 719 | |
| 720 | |
| 721 | |
| 722 | |
| 723 | |
| 724 | and2 #(1) d0_0 ( |
| 725 | .in0(din0[0:0]), |
| 726 | .in1(din1[0:0]), |
| 727 | .out(dout[0:0]) |
| 728 | ); |
| 729 | |
| 730 | |
| 731 | |
| 732 | |
| 733 | |
| 734 | |
| 735 | |
| 736 | |
| 737 | |
| 738 | endmodule |
| 739 | |
| 740 | |
| 741 | |
| 742 | |
| 743 | |
| 744 | |
| 745 | |
| 746 | |
| 747 | |
| 748 | // any PARAMS parms go into naming of macro |
| 749 | |
| 750 | module mcu_frdbuf_dp_msff_macro__stack_11r__width_4 ( |
| 751 | din, |
| 752 | clk, |
| 753 | en, |
| 754 | se, |
| 755 | scan_in, |
| 756 | siclk, |
| 757 | soclk, |
| 758 | pce_ov, |
| 759 | stop, |
| 760 | dout, |
| 761 | scan_out); |
| 762 | wire l1clk; |
| 763 | wire siclk_out; |
| 764 | wire soclk_out; |
| 765 | wire [2:0] so; |
| 766 | |
| 767 | input [3:0] din; |
| 768 | |
| 769 | |
| 770 | input clk; |
| 771 | input en; |
| 772 | input se; |
| 773 | input scan_in; |
| 774 | input siclk; |
| 775 | input soclk; |
| 776 | input pce_ov; |
| 777 | input stop; |
| 778 | |
| 779 | |
| 780 | |
| 781 | output [3:0] dout; |
| 782 | |
| 783 | |
| 784 | output scan_out; |
| 785 | |
| 786 | |
| 787 | |
| 788 | |
| 789 | cl_dp1_l1hdr_8x c0_0 ( |
| 790 | .l2clk(clk), |
| 791 | .pce(en), |
| 792 | .aclk(siclk), |
| 793 | .bclk(soclk), |
| 794 | .l1clk(l1clk), |
| 795 | .se(se), |
| 796 | .pce_ov(pce_ov), |
| 797 | .stop(stop), |
| 798 | .siclk_out(siclk_out), |
| 799 | .soclk_out(soclk_out) |
| 800 | ); |
| 801 | dff #(4) d0_0 ( |
| 802 | .l1clk(l1clk), |
| 803 | .siclk(siclk_out), |
| 804 | .soclk(soclk_out), |
| 805 | .d(din[3:0]), |
| 806 | .si({scan_in,so[2:0]}), |
| 807 | .so({so[2:0],scan_out}), |
| 808 | .q(dout[3:0]) |
| 809 | ); |
| 810 | |
| 811 | |
| 812 | |
| 813 | |
| 814 | |
| 815 | |
| 816 | |
| 817 | |
| 818 | |
| 819 | |
| 820 | |
| 821 | |
| 822 | |
| 823 | |
| 824 | |
| 825 | |
| 826 | |
| 827 | |
| 828 | |
| 829 | |
| 830 | endmodule |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | |
| 836 | |
| 837 | |
| 838 | |
| 839 | |
| 840 | // |
| 841 | // invert macro |
| 842 | // |
| 843 | // |
| 844 | |
| 845 | |
| 846 | |
| 847 | |
| 848 | |
| 849 | module mcu_frdbuf_dp_inv_macro ( |
| 850 | din, |
| 851 | dout); |
| 852 | input [0:0] din; |
| 853 | output [0:0] dout; |
| 854 | |
| 855 | |
| 856 | |
| 857 | |
| 858 | |
| 859 | |
| 860 | inv #(1) d0_0 ( |
| 861 | .in(din[0:0]), |
| 862 | .out(dout[0:0]) |
| 863 | ); |
| 864 | |
| 865 | |
| 866 | |
| 867 | |
| 868 | |
| 869 | |
| 870 | |
| 871 | |
| 872 | |
| 873 | endmodule |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | // |
| 880 | // nor macro for ports = 2,3 |
| 881 | // |
| 882 | // |
| 883 | |
| 884 | |
| 885 | |
| 886 | |
| 887 | |
| 888 | module mcu_frdbuf_dp_nor_macro ( |
| 889 | din0, |
| 890 | din1, |
| 891 | dout); |
| 892 | input [0:0] din0; |
| 893 | input [0:0] din1; |
| 894 | output [0:0] dout; |
| 895 | |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | nor2 #(1) d0_0 ( |
| 902 | .in0(din0[0:0]), |
| 903 | .in1(din1[0:0]), |
| 904 | .out(dout[0:0]) |
| 905 | ); |
| 906 | |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | endmodule |
| 914 | |
| 915 | |
| 916 | |
| 917 | |
| 918 | |
| 919 | // |
| 920 | // buff macro |
| 921 | // |
| 922 | // |
| 923 | |
| 924 | |
| 925 | |
| 926 | |
| 927 | |
| 928 | module mcu_frdbuf_dp_buff_macro__minbuff_1__stack_12r__width_12 ( |
| 929 | din, |
| 930 | dout); |
| 931 | input [11:0] din; |
| 932 | output [11:0] dout; |
| 933 | |
| 934 | |
| 935 | |
| 936 | |
| 937 | |
| 938 | |
| 939 | buff #(12) d0_0 ( |
| 940 | .in(din[11:0]), |
| 941 | .out(dout[11:0]) |
| 942 | ); |
| 943 | |
| 944 | |
| 945 | |
| 946 | |
| 947 | |
| 948 | |
| 949 | |
| 950 | |
| 951 | endmodule |
| 952 | |
| 953 | |
| 954 | |
| 955 | |
| 956 | |
| 957 | // |
| 958 | // increment macro |
| 959 | // |
| 960 | // |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | |
| 966 | module mcu_frdbuf_dp_increment_macro__width_4 ( |
| 967 | din, |
| 968 | cin, |
| 969 | dout, |
| 970 | cout); |
| 971 | input [3:0] din; |
| 972 | input cin; |
| 973 | output [3:0] dout; |
| 974 | output cout; |
| 975 | |
| 976 | |
| 977 | |
| 978 | |
| 979 | |
| 980 | |
| 981 | incr #(4) m0_0 ( |
| 982 | .cin(cin), |
| 983 | .in(din[3:0]), |
| 984 | .out(dout[3:0]), |
| 985 | .cout(cout) |
| 986 | ); |
| 987 | |
| 988 | |
| 989 | |
| 990 | |
| 991 | |
| 992 | |
| 993 | |
| 994 | |
| 995 | |
| 996 | |
| 997 | |
| 998 | endmodule |
| 999 | |
| 1000 | |
| 1001 | |
| 1002 | |
| 1003 | |
| 1004 | // |
| 1005 | // and macro for ports = 2,3,4 |
| 1006 | // |
| 1007 | // |
| 1008 | |
| 1009 | |
| 1010 | |
| 1011 | |
| 1012 | |
| 1013 | module mcu_frdbuf_dp_and_macro__ports_3__width_4 ( |
| 1014 | din0, |
| 1015 | din1, |
| 1016 | din2, |
| 1017 | dout); |
| 1018 | input [3:0] din0; |
| 1019 | input [3:0] din1; |
| 1020 | input [3:0] din2; |
| 1021 | output [3:0] dout; |
| 1022 | |
| 1023 | |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | |
| 1028 | and3 #(4) d0_0 ( |
| 1029 | .in0(din0[3:0]), |
| 1030 | .in1(din1[3:0]), |
| 1031 | .in2(din2[3:0]), |
| 1032 | .out(dout[3:0]) |
| 1033 | ); |
| 1034 | |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | |
| 1041 | |
| 1042 | |
| 1043 | endmodule |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | |
| 1049 | // |
| 1050 | // or macro for ports = 2,3 |
| 1051 | // |
| 1052 | // |
| 1053 | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | |
| 1058 | module mcu_frdbuf_dp_or_macro__ports_2__width_1 ( |
| 1059 | din0, |
| 1060 | din1, |
| 1061 | dout); |
| 1062 | input [0:0] din0; |
| 1063 | input [0:0] din1; |
| 1064 | output [0:0] dout; |
| 1065 | |
| 1066 | |
| 1067 | |
| 1068 | |
| 1069 | |
| 1070 | |
| 1071 | or2 #(1) d0_0 ( |
| 1072 | .in0(din0[0:0]), |
| 1073 | .in1(din1[0:0]), |
| 1074 | .out(dout[0:0]) |
| 1075 | ); |
| 1076 | |
| 1077 | |
| 1078 | |
| 1079 | |
| 1080 | |
| 1081 | |
| 1082 | |
| 1083 | |
| 1084 | |
| 1085 | endmodule |
| 1086 | |
| 1087 | |
| 1088 | |
| 1089 | |
| 1090 | |
| 1091 | // |
| 1092 | // invert macro |
| 1093 | // |
| 1094 | // |
| 1095 | |
| 1096 | |
| 1097 | |
| 1098 | |
| 1099 | |
| 1100 | module mcu_frdbuf_dp_inv_macro__width_1 ( |
| 1101 | din, |
| 1102 | dout); |
| 1103 | input [0:0] din; |
| 1104 | output [0:0] dout; |
| 1105 | |
| 1106 | |
| 1107 | |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | inv #(1) d0_0 ( |
| 1112 | .in(din[0:0]), |
| 1113 | .out(dout[0:0]) |
| 1114 | ); |
| 1115 | |
| 1116 | |
| 1117 | |
| 1118 | |
| 1119 | |
| 1120 | |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | endmodule |
| 1125 | |
| 1126 | |
| 1127 | |
| 1128 | |
| 1129 | |
| 1130 | // |
| 1131 | // and macro for ports = 2,3,4 |
| 1132 | // |
| 1133 | // |
| 1134 | |
| 1135 | |
| 1136 | |
| 1137 | |
| 1138 | |
| 1139 | module mcu_frdbuf_dp_and_macro__ports_2__width_1 ( |
| 1140 | din0, |
| 1141 | din1, |
| 1142 | dout); |
| 1143 | input [0:0] din0; |
| 1144 | input [0:0] din1; |
| 1145 | output [0:0] dout; |
| 1146 | |
| 1147 | |
| 1148 | |
| 1149 | |
| 1150 | |
| 1151 | |
| 1152 | and2 #(1) d0_0 ( |
| 1153 | .in0(din0[0:0]), |
| 1154 | .in1(din1[0:0]), |
| 1155 | .out(dout[0:0]) |
| 1156 | ); |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | |
| 1161 | |
| 1162 | |
| 1163 | |
| 1164 | |
| 1165 | |
| 1166 | endmodule |
| 1167 | |
| 1168 | |
| 1169 | |
| 1170 | |
| 1171 | |
| 1172 | // |
| 1173 | // invert macro |
| 1174 | // |
| 1175 | // |
| 1176 | |
| 1177 | |
| 1178 | |
| 1179 | |
| 1180 | |
| 1181 | module mcu_frdbuf_dp_inv_macro__width_2 ( |
| 1182 | din, |
| 1183 | dout); |
| 1184 | input [1:0] din; |
| 1185 | output [1:0] dout; |
| 1186 | |
| 1187 | |
| 1188 | |
| 1189 | |
| 1190 | |
| 1191 | |
| 1192 | inv #(2) d0_0 ( |
| 1193 | .in(din[1:0]), |
| 1194 | .out(dout[1:0]) |
| 1195 | ); |
| 1196 | |
| 1197 | |
| 1198 | |
| 1199 | |
| 1200 | |
| 1201 | |
| 1202 | |
| 1203 | |
| 1204 | |
| 1205 | endmodule |
| 1206 | |
| 1207 | |
| 1208 | |
| 1209 | |
| 1210 | |
| 1211 | // |
| 1212 | // and macro for ports = 2,3,4 |
| 1213 | // |
| 1214 | // |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | module mcu_frdbuf_dp_and_macro__width_2 ( |
| 1221 | din0, |
| 1222 | din1, |
| 1223 | dout); |
| 1224 | input [1:0] din0; |
| 1225 | input [1:0] din1; |
| 1226 | output [1:0] dout; |
| 1227 | |
| 1228 | |
| 1229 | |
| 1230 | |
| 1231 | |
| 1232 | |
| 1233 | and2 #(2) d0_0 ( |
| 1234 | .in0(din0[1:0]), |
| 1235 | .in1(din1[1:0]), |
| 1236 | .out(dout[1:0]) |
| 1237 | ); |
| 1238 | |
| 1239 | |
| 1240 | |
| 1241 | |
| 1242 | |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | endmodule |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | |
| 1253 | // |
| 1254 | // nor macro for ports = 2,3 |
| 1255 | // |
| 1256 | // |
| 1257 | |
| 1258 | |
| 1259 | |
| 1260 | |
| 1261 | |
| 1262 | module mcu_frdbuf_dp_nor_macro__ports_3__width_1 ( |
| 1263 | din0, |
| 1264 | din1, |
| 1265 | din2, |
| 1266 | dout); |
| 1267 | input [0:0] din0; |
| 1268 | input [0:0] din1; |
| 1269 | input [0:0] din2; |
| 1270 | output [0:0] dout; |
| 1271 | |
| 1272 | |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | |
| 1277 | nor3 #(1) d0_0 ( |
| 1278 | .in0(din0[0:0]), |
| 1279 | .in1(din1[0:0]), |
| 1280 | .in2(din2[0:0]), |
| 1281 | .out(dout[0:0]) |
| 1282 | ); |
| 1283 | |
| 1284 | |
| 1285 | |
| 1286 | |
| 1287 | |
| 1288 | |
| 1289 | |
| 1290 | endmodule |
| 1291 | |
| 1292 | |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | |
| 1297 | |
| 1298 | |
| 1299 | |
| 1300 | // any PARAMS parms go into naming of macro |
| 1301 | |
| 1302 | module mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ( |
| 1303 | din, |
| 1304 | clk, |
| 1305 | en, |
| 1306 | se, |
| 1307 | scan_in, |
| 1308 | siclk, |
| 1309 | soclk, |
| 1310 | pce_ov, |
| 1311 | stop, |
| 1312 | dout, |
| 1313 | scan_out); |
| 1314 | wire l1clk; |
| 1315 | wire siclk_out; |
| 1316 | wire soclk_out; |
| 1317 | wire [10:0] so; |
| 1318 | |
| 1319 | input [11:0] din; |
| 1320 | |
| 1321 | |
| 1322 | input clk; |
| 1323 | input en; |
| 1324 | input se; |
| 1325 | input scan_in; |
| 1326 | input siclk; |
| 1327 | input soclk; |
| 1328 | input pce_ov; |
| 1329 | input stop; |
| 1330 | |
| 1331 | |
| 1332 | |
| 1333 | output [11:0] dout; |
| 1334 | |
| 1335 | |
| 1336 | output scan_out; |
| 1337 | |
| 1338 | |
| 1339 | |
| 1340 | |
| 1341 | cl_dp1_l1hdr_8x c0_0 ( |
| 1342 | .l2clk(clk), |
| 1343 | .pce(en), |
| 1344 | .aclk(siclk), |
| 1345 | .bclk(soclk), |
| 1346 | .l1clk(l1clk), |
| 1347 | .se(se), |
| 1348 | .pce_ov(pce_ov), |
| 1349 | .stop(stop), |
| 1350 | .siclk_out(siclk_out), |
| 1351 | .soclk_out(soclk_out) |
| 1352 | ); |
| 1353 | dff #(12) d0_0 ( |
| 1354 | .l1clk(l1clk), |
| 1355 | .siclk(siclk_out), |
| 1356 | .soclk(soclk_out), |
| 1357 | .d(din[11:0]), |
| 1358 | .si({scan_in,so[10:0]}), |
| 1359 | .so({so[10:0],scan_out}), |
| 1360 | .q(dout[11:0]) |
| 1361 | ); |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | |
| 1375 | |
| 1376 | |
| 1377 | |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | endmodule |
| 1383 | |
| 1384 | |
| 1385 | |
| 1386 | |
| 1387 | |
| 1388 | |
| 1389 | |
| 1390 | |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | |
| 1395 | |
| 1396 | // any PARAMS parms go into naming of macro |
| 1397 | |
| 1398 | module mcu_frdbuf_dp_msff_macro__stack_12r__width_4 ( |
| 1399 | din, |
| 1400 | clk, |
| 1401 | en, |
| 1402 | se, |
| 1403 | scan_in, |
| 1404 | siclk, |
| 1405 | soclk, |
| 1406 | pce_ov, |
| 1407 | stop, |
| 1408 | dout, |
| 1409 | scan_out); |
| 1410 | wire l1clk; |
| 1411 | wire siclk_out; |
| 1412 | wire soclk_out; |
| 1413 | wire [2:0] so; |
| 1414 | |
| 1415 | input [3:0] din; |
| 1416 | |
| 1417 | |
| 1418 | input clk; |
| 1419 | input en; |
| 1420 | input se; |
| 1421 | input scan_in; |
| 1422 | input siclk; |
| 1423 | input soclk; |
| 1424 | input pce_ov; |
| 1425 | input stop; |
| 1426 | |
| 1427 | |
| 1428 | |
| 1429 | output [3:0] dout; |
| 1430 | |
| 1431 | |
| 1432 | output scan_out; |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | |
| 1437 | cl_dp1_l1hdr_8x c0_0 ( |
| 1438 | .l2clk(clk), |
| 1439 | .pce(en), |
| 1440 | .aclk(siclk), |
| 1441 | .bclk(soclk), |
| 1442 | .l1clk(l1clk), |
| 1443 | .se(se), |
| 1444 | .pce_ov(pce_ov), |
| 1445 | .stop(stop), |
| 1446 | .siclk_out(siclk_out), |
| 1447 | .soclk_out(soclk_out) |
| 1448 | ); |
| 1449 | dff #(4) d0_0 ( |
| 1450 | .l1clk(l1clk), |
| 1451 | .siclk(siclk_out), |
| 1452 | .soclk(soclk_out), |
| 1453 | .d(din[3:0]), |
| 1454 | .si({scan_in,so[2:0]}), |
| 1455 | .so({so[2:0],scan_out}), |
| 1456 | .q(dout[3:0]) |
| 1457 | ); |
| 1458 | |
| 1459 | |
| 1460 | |
| 1461 | |
| 1462 | |
| 1463 | |
| 1464 | |
| 1465 | |
| 1466 | |
| 1467 | |
| 1468 | |
| 1469 | |
| 1470 | |
| 1471 | |
| 1472 | |
| 1473 | |
| 1474 | |
| 1475 | |
| 1476 | |
| 1477 | |
| 1478 | endmodule |
| 1479 | |
| 1480 | |
| 1481 | |
| 1482 | |
| 1483 | |
| 1484 | |
| 1485 | |
| 1486 | |
| 1487 | |
| 1488 | // |
| 1489 | // nor macro for ports = 2,3 |
| 1490 | // |
| 1491 | // |
| 1492 | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | module mcu_frdbuf_dp_nor_macro__ports_2__width_1 ( |
| 1498 | din0, |
| 1499 | din1, |
| 1500 | dout); |
| 1501 | input [0:0] din0; |
| 1502 | input [0:0] din1; |
| 1503 | output [0:0] dout; |
| 1504 | |
| 1505 | |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | |
| 1510 | nor2 #(1) d0_0 ( |
| 1511 | .in0(din0[0:0]), |
| 1512 | .in1(din1[0:0]), |
| 1513 | .out(dout[0:0]) |
| 1514 | ); |
| 1515 | |
| 1516 | |
| 1517 | |
| 1518 | |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | endmodule |
| 1523 | |
| 1524 | |
| 1525 | |
| 1526 | |
| 1527 | |
| 1528 | |
| 1529 | |
| 1530 | |
| 1531 | |
| 1532 | // any PARAMS parms go into naming of macro |
| 1533 | |
| 1534 | module mcu_frdbuf_dp_msff_macro__mux_aonpe__ports_4__stack_12r__width_12 ( |
| 1535 | din0, |
| 1536 | sel0, |
| 1537 | din1, |
| 1538 | sel1, |
| 1539 | din2, |
| 1540 | sel2, |
| 1541 | din3, |
| 1542 | sel3, |
| 1543 | clk, |
| 1544 | en, |
| 1545 | se, |
| 1546 | scan_in, |
| 1547 | siclk, |
| 1548 | soclk, |
| 1549 | pce_ov, |
| 1550 | stop, |
| 1551 | dout, |
| 1552 | scan_out); |
| 1553 | wire buffout0; |
| 1554 | wire buffout1; |
| 1555 | wire buffout2; |
| 1556 | wire buffout3; |
| 1557 | wire [11:0] muxout; |
| 1558 | wire l1clk; |
| 1559 | wire siclk_out; |
| 1560 | wire soclk_out; |
| 1561 | wire [10:0] so; |
| 1562 | |
| 1563 | input [11:0] din0; |
| 1564 | input sel0; |
| 1565 | input [11:0] din1; |
| 1566 | input sel1; |
| 1567 | input [11:0] din2; |
| 1568 | input sel2; |
| 1569 | input [11:0] din3; |
| 1570 | input sel3; |
| 1571 | |
| 1572 | |
| 1573 | input clk; |
| 1574 | input en; |
| 1575 | input se; |
| 1576 | input scan_in; |
| 1577 | input siclk; |
| 1578 | input soclk; |
| 1579 | input pce_ov; |
| 1580 | input stop; |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | output [11:0] dout; |
| 1585 | |
| 1586 | |
| 1587 | output scan_out; |
| 1588 | |
| 1589 | |
| 1590 | |
| 1591 | |
| 1592 | cl_dp1_muxbuff4_8x c1_0 ( |
| 1593 | .in0(sel0), |
| 1594 | .in1(sel1), |
| 1595 | .in2(sel2), |
| 1596 | .in3(sel3), |
| 1597 | .out0(buffout0), |
| 1598 | .out1(buffout1), |
| 1599 | .out2(buffout2), |
| 1600 | .out3(buffout3) |
| 1601 | ); |
| 1602 | mux4s #(12) d1_0 ( |
| 1603 | .sel0(buffout0), |
| 1604 | .sel1(buffout1), |
| 1605 | .sel2(buffout2), |
| 1606 | .sel3(buffout3), |
| 1607 | .in0(din0[11:0]), |
| 1608 | .in1(din1[11:0]), |
| 1609 | .in2(din2[11:0]), |
| 1610 | .in3(din3[11:0]), |
| 1611 | .dout(muxout[11:0]) |
| 1612 | ); |
| 1613 | cl_dp1_l1hdr_8x c0_0 ( |
| 1614 | .l2clk(clk), |
| 1615 | .pce(en), |
| 1616 | .aclk(siclk), |
| 1617 | .bclk(soclk), |
| 1618 | .l1clk(l1clk), |
| 1619 | .se(se), |
| 1620 | .pce_ov(pce_ov), |
| 1621 | .stop(stop), |
| 1622 | .siclk_out(siclk_out), |
| 1623 | .soclk_out(soclk_out) |
| 1624 | ); |
| 1625 | dff #(12) d0_0 ( |
| 1626 | .l1clk(l1clk), |
| 1627 | .siclk(siclk_out), |
| 1628 | .soclk(soclk_out), |
| 1629 | .d(muxout[11:0]), |
| 1630 | .si({scan_in,so[10:0]}), |
| 1631 | .so({so[10:0],scan_out}), |
| 1632 | .q(dout[11:0]) |
| 1633 | ); |
| 1634 | |
| 1635 | |
| 1636 | |
| 1637 | |
| 1638 | |
| 1639 | |
| 1640 | |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | |
| 1650 | |
| 1651 | |
| 1652 | |
| 1653 | |
| 1654 | endmodule |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | |
| 1661 | |
| 1662 | |
| 1663 | |
| 1664 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1665 | // also for pass-gate with decoder |
| 1666 | |
| 1667 | |
| 1668 | |
| 1669 | |
| 1670 | |
| 1671 | // any PARAMS parms go into naming of macro |
| 1672 | |
| 1673 | module mcu_frdbuf_dp_mux_macro__buffsel_none__mux_aonpe ( |
| 1674 | din0, |
| 1675 | sel0, |
| 1676 | din1, |
| 1677 | sel1, |
| 1678 | dout); |
| 1679 | input [0:0] din0; |
| 1680 | input sel0; |
| 1681 | input [0:0] din1; |
| 1682 | input sel1; |
| 1683 | output [0:0] dout; |
| 1684 | |
| 1685 | |
| 1686 | |
| 1687 | |
| 1688 | |
| 1689 | mux2s #(1) d0_0 ( |
| 1690 | .sel0(sel0), |
| 1691 | .sel1(sel1), |
| 1692 | .in0(din0[0:0]), |
| 1693 | .in1(din1[0:0]), |
| 1694 | .dout(dout[0:0]) |
| 1695 | ); |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | |
| 1709 | endmodule |
| 1710 | |