| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcu_pdmc_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mcu_pdmc_ctl ( |
| 36 | pdmc_pde_pending, |
| 37 | pdmc_pdx_pending, |
| 38 | pdmc_rank_avail, |
| 39 | drq0_pd_mode_rd_incr, |
| 40 | drq1_pd_mode_rd_incr, |
| 41 | drq0_pd_mode_wr_incr, |
| 42 | drq1_pd_mode_wr_incr, |
| 43 | drif_pd_mode_scrub_incr, |
| 44 | drif_pd_mode_err_incr, |
| 45 | woq_pd_mode_wr_err_incr, |
| 46 | drq0_pd_mode_rd_decr, |
| 47 | drq1_pd_mode_rd_decr, |
| 48 | woq_pd_mode_wr_decr, |
| 49 | drif_pd_mode_scrub_decr, |
| 50 | drif_pd_mode_err_decr, |
| 51 | woq_pd_mode_wr_err_decr, |
| 52 | drif_pdx_issued, |
| 53 | drif_pde_issued, |
| 54 | fbdic_l0_state, |
| 55 | drif_pdmc_enable, |
| 56 | drif_refresh_mode, |
| 57 | fbdic_scr_frame_req_d4, |
| 58 | drif_pdmc_idle, |
| 59 | dal_reg, |
| 60 | ral_reg, |
| 61 | l1clk, |
| 62 | scan_in, |
| 63 | scan_out, |
| 64 | tcu_aclk, |
| 65 | tcu_bclk, |
| 66 | tcu_scan_en); |
| 67 | wire siclk; |
| 68 | wire soclk; |
| 69 | wire se; |
| 70 | wire [2:0] pdmc_pd_cnt_incr; |
| 71 | wire [5:0] pdmc_pd_cnt_decr; |
| 72 | wire [5:0] pdmc_pd_cnt_in; |
| 73 | wire [5:0] pdmc_pd_cnt; |
| 74 | wire ff_pd_cnt_scanin; |
| 75 | wire ff_pd_cnt_scanout; |
| 76 | wire pdmc_pd_cnt_is_zero; |
| 77 | wire [3:0] pdmc_state; |
| 78 | wire inv_pdmc_state_in_0; |
| 79 | wire inv_pdmc_state_0; |
| 80 | wire ff_pdmc_state_scanin; |
| 81 | wire ff_pdmc_state_scanout; |
| 82 | wire pdmc_cke_cnt_is_zero; |
| 83 | wire pdmc_precharge_cnt_is_zero; |
| 84 | wire pdmc_xp_cnt_is_zero; |
| 85 | wire pdmc_cke_reset; |
| 86 | wire [1:0] pdmc_cke_cnt_in; |
| 87 | wire [1:0] pdmc_cke_cnt; |
| 88 | wire ff_cke_cnt_scanin; |
| 89 | wire ff_cke_cnt_scanout; |
| 90 | wire pdmc_xp_reset; |
| 91 | wire [1:0] pdmc_xp_cnt_in; |
| 92 | wire [1:0] pdmc_xp_cnt; |
| 93 | wire ff_xp_cnt_scanin; |
| 94 | wire ff_xp_cnt_scanout; |
| 95 | wire pdmc_precharge_rd_reset; |
| 96 | wire pdmc_precharge_wr_reset; |
| 97 | wire [4:0] pdmc_precharge_cnt_in; |
| 98 | wire [4:0] pdmc_precharge_cnt; |
| 99 | wire ff_precharge_cnt_scanin; |
| 100 | wire ff_precharge_cnt_scanout; |
| 101 | |
| 102 | |
| 103 | output pdmc_pde_pending; |
| 104 | output pdmc_pdx_pending; |
| 105 | |
| 106 | output pdmc_rank_avail; |
| 107 | |
| 108 | input drq0_pd_mode_rd_incr; |
| 109 | input drq1_pd_mode_rd_incr; |
| 110 | input drq0_pd_mode_wr_incr; |
| 111 | input drq1_pd_mode_wr_incr; |
| 112 | input drif_pd_mode_scrub_incr; |
| 113 | input drif_pd_mode_err_incr; |
| 114 | input woq_pd_mode_wr_err_incr; |
| 115 | |
| 116 | input drq0_pd_mode_rd_decr; |
| 117 | input drq1_pd_mode_rd_decr; |
| 118 | input woq_pd_mode_wr_decr; |
| 119 | input drif_pd_mode_scrub_decr; |
| 120 | input drif_pd_mode_err_decr; |
| 121 | input woq_pd_mode_wr_err_decr; |
| 122 | |
| 123 | input drif_pdx_issued; |
| 124 | input drif_pde_issued; |
| 125 | |
| 126 | input fbdic_l0_state; |
| 127 | input drif_pdmc_enable; |
| 128 | input drif_refresh_mode; |
| 129 | input fbdic_scr_frame_req_d4; |
| 130 | input drif_pdmc_idle; |
| 131 | |
| 132 | input [4:0] dal_reg; |
| 133 | input [4:0] ral_reg; |
| 134 | |
| 135 | input l1clk; |
| 136 | input scan_in; |
| 137 | output scan_out; |
| 138 | input tcu_aclk; |
| 139 | input tcu_bclk; |
| 140 | input tcu_scan_en; |
| 141 | |
| 142 | // Clock header connections |
| 143 | assign siclk = tcu_aclk; |
| 144 | assign soclk = tcu_bclk; |
| 145 | assign se = tcu_scan_en; |
| 146 | |
| 147 | // Count the number of pending transactions |
| 148 | assign pdmc_pd_cnt_incr[2:0] = {2'h0, drq0_pd_mode_rd_incr} + {2'h0, drq0_pd_mode_wr_incr} + |
| 149 | {2'h0, drq1_pd_mode_rd_incr} + {2'h0, drq1_pd_mode_wr_incr} + |
| 150 | {2'h0, drif_pd_mode_err_incr} + {2'h0, drif_pd_mode_scrub_incr} + |
| 151 | {2'h0, woq_pd_mode_wr_err_incr}; |
| 152 | assign pdmc_pd_cnt_decr[5:0] = {5'h0, drq0_pd_mode_rd_decr | drq1_pd_mode_rd_decr | |
| 153 | woq_pd_mode_wr_decr | drif_pd_mode_scrub_decr | |
| 154 | drif_pd_mode_err_decr | woq_pd_mode_wr_err_decr}; |
| 155 | |
| 156 | assign pdmc_pd_cnt_in[5:0] = {6{~drif_pdmc_idle}} & |
| 157 | (pdmc_pd_cnt[5:0] + {3'h0, pdmc_pd_cnt_incr[2:0]} - pdmc_pd_cnt_decr[5:0]); |
| 158 | |
| 159 | // 0in overflow -var pdmc_pd_cnt[5:0] |
| 160 | // 0in underflow -var pdmc_pd_cnt[5:0] |
| 161 | mcu_pdmc_ctl_msff_ctl_macro__width_6 ff_pd_cnt ( |
| 162 | .scan_in(ff_pd_cnt_scanin), |
| 163 | .scan_out(ff_pd_cnt_scanout), |
| 164 | .din(pdmc_pd_cnt_in[5:0]), |
| 165 | .dout(pdmc_pd_cnt[5:0]), |
| 166 | .l1clk(l1clk), |
| 167 | .siclk(siclk), |
| 168 | .soclk(soclk)); |
| 169 | |
| 170 | assign pdmc_pd_cnt_is_zero = pdmc_pd_cnt[5:0] == 6'h0 & ~drif_refresh_mode; |
| 171 | |
| 172 | reg [3:0] pdmc_state_in; |
| 173 | |
| 174 | // 0in one_hot -var pdmc_state[3:0] |
| 175 | always @(pdmc_pd_cnt_is_zero or fbdic_l0_state or drif_pdmc_enable or drif_pde_issued or |
| 176 | drif_pdx_issued or pdmc_state or fbdic_scr_frame_req_d4) |
| 177 | begin |
| 178 | pdmc_state_in[3:0] = 4'h0; |
| 179 | |
| 180 | case (1'b1) |
| 181 | |
| 182 | // State 0: In active mode |
| 183 | pdmc_state[0] : begin |
| 184 | if (pdmc_pd_cnt_is_zero & fbdic_l0_state & drif_pdmc_enable) |
| 185 | pdmc_state_in[1] = 1'b1; |
| 186 | else |
| 187 | pdmc_state_in[0] = 1'b1; |
| 188 | end |
| 189 | |
| 190 | // State 1: Entering power down mode |
| 191 | pdmc_state[1] : begin |
| 192 | if (~fbdic_l0_state | ~drif_pdmc_enable | ~pdmc_pd_cnt_is_zero & ~drif_pde_issued | fbdic_scr_frame_req_d4) |
| 193 | pdmc_state_in[0] = 1'b1; |
| 194 | else if (drif_pde_issued) |
| 195 | pdmc_state_in[2] = 1'b1; |
| 196 | else |
| 197 | pdmc_state_in[1] = 1'b1; |
| 198 | end |
| 199 | |
| 200 | // State 2: In power down mode |
| 201 | pdmc_state[2] : begin |
| 202 | if (~fbdic_l0_state | fbdic_scr_frame_req_d4) |
| 203 | pdmc_state_in[0] = 1'b1; |
| 204 | else if (~pdmc_pd_cnt_is_zero | ~drif_pdmc_enable) |
| 205 | pdmc_state_in[3] = 1'b1; |
| 206 | else |
| 207 | pdmc_state_in[2] = 1'b1; |
| 208 | end |
| 209 | |
| 210 | // State 3: Exiting power down mode |
| 211 | pdmc_state[3] : begin |
| 212 | if (~fbdic_l0_state | drif_pdx_issued | fbdic_scr_frame_req_d4) |
| 213 | pdmc_state_in[0] = 1'b1; |
| 214 | else |
| 215 | pdmc_state_in[3] = 1'b1; |
| 216 | end |
| 217 | |
| 218 | default: ; |
| 219 | |
| 220 | endcase |
| 221 | |
| 222 | end |
| 223 | |
| 224 | assign inv_pdmc_state_in_0 = ~pdmc_state_in[0]; |
| 225 | assign pdmc_state[0] = ~inv_pdmc_state_0; |
| 226 | mcu_pdmc_ctl_msff_ctl_macro__width_4 ff_pdmc_state ( |
| 227 | .scan_in(ff_pdmc_state_scanin), |
| 228 | .scan_out(ff_pdmc_state_scanout), |
| 229 | .din({pdmc_state_in[3:1], inv_pdmc_state_in_0}), |
| 230 | .dout({pdmc_state[3:1], inv_pdmc_state_0}), |
| 231 | .l1clk(l1clk), |
| 232 | .siclk(siclk), |
| 233 | .soclk(soclk)); |
| 234 | |
| 235 | assign pdmc_pde_pending = pdmc_state[1] & pdmc_cke_cnt_is_zero & pdmc_precharge_cnt_is_zero; |
| 236 | assign pdmc_pdx_pending = pdmc_state[3] & pdmc_cke_cnt_is_zero; |
| 237 | |
| 238 | assign pdmc_rank_avail = pdmc_state[0] & pdmc_xp_cnt_is_zero; |
| 239 | |
| 240 | // Make sure CKE is asserted or deasserted for tCKE cycles before changing |
| 241 | assign pdmc_cke_reset = pdmc_state[3] & drif_pdx_issued | pdmc_state[1] & drif_pde_issued; |
| 242 | assign pdmc_cke_cnt_in[1:0] = pdmc_cke_reset ? 2'h3 : pdmc_cke_cnt_is_zero ? 2'h0 : pdmc_cke_cnt[1:0] - 2'h1; |
| 243 | mcu_pdmc_ctl_msff_ctl_macro__width_2 ff_cke_cnt ( |
| 244 | .scan_in(ff_cke_cnt_scanin), |
| 245 | .scan_out(ff_cke_cnt_scanout), |
| 246 | .din(pdmc_cke_cnt_in[1:0]), |
| 247 | .dout(pdmc_cke_cnt[1:0]), |
| 248 | .l1clk(l1clk), |
| 249 | .siclk(siclk), |
| 250 | .soclk(soclk)); |
| 251 | |
| 252 | assign pdmc_cke_cnt_is_zero = pdmc_cke_cnt[1:0] == 2'h0; |
| 253 | |
| 254 | // Wait for tXP (precharge power down to any command) before enabling rank |
| 255 | assign pdmc_xp_reset = pdmc_state[3] & drif_pdx_issued; |
| 256 | assign pdmc_xp_cnt_in[1:0] = pdmc_xp_reset ? 2'h2 : pdmc_xp_cnt_is_zero ? 2'h0 : pdmc_xp_cnt[1:0] - 2'h1; |
| 257 | mcu_pdmc_ctl_msff_ctl_macro__width_2 ff_xp_cnt ( |
| 258 | .scan_in(ff_xp_cnt_scanin), |
| 259 | .scan_out(ff_xp_cnt_scanout), |
| 260 | .din(pdmc_xp_cnt_in[1:0]), |
| 261 | .dout(pdmc_xp_cnt[1:0]), |
| 262 | .l1clk(l1clk), |
| 263 | .siclk(siclk), |
| 264 | .soclk(soclk)); |
| 265 | |
| 266 | assign pdmc_xp_cnt_is_zero = pdmc_xp_cnt[1:0] == 2'h0; |
| 267 | |
| 268 | // Wait for precharge time after a command is issued before going back to power down mode |
| 269 | assign pdmc_precharge_rd_reset = drq0_pd_mode_rd_decr | drq1_pd_mode_rd_decr | |
| 270 | drif_pd_mode_scrub_decr | drif_pd_mode_err_decr; |
| 271 | assign pdmc_precharge_wr_reset = woq_pd_mode_wr_decr | woq_pd_mode_wr_err_decr; |
| 272 | assign pdmc_precharge_cnt_in[4:0] = pdmc_precharge_rd_reset ? ral_reg[4:0] : |
| 273 | pdmc_precharge_wr_reset ? dal_reg[4:0] : |
| 274 | pdmc_precharge_cnt_is_zero ? 5'h0 : pdmc_precharge_cnt[4:0] - 5'h1; |
| 275 | mcu_pdmc_ctl_msff_ctl_macro__width_5 ff_precharge_cnt ( |
| 276 | .scan_in(ff_precharge_cnt_scanin), |
| 277 | .scan_out(ff_precharge_cnt_scanout), |
| 278 | .din(pdmc_precharge_cnt_in[4:0]), |
| 279 | .dout(pdmc_precharge_cnt[4:0]), |
| 280 | .l1clk(l1clk), |
| 281 | .siclk(siclk), |
| 282 | .soclk(soclk)); |
| 283 | |
| 284 | assign pdmc_precharge_cnt_is_zero = pdmc_precharge_cnt[4:0] == 5'h0; |
| 285 | |
| 286 | // fixscan start: |
| 287 | assign ff_pd_cnt_scanin = scan_in ; |
| 288 | assign ff_pdmc_state_scanin = ff_pd_cnt_scanout ; |
| 289 | assign ff_cke_cnt_scanin = ff_pdmc_state_scanout ; |
| 290 | assign ff_xp_cnt_scanin = ff_cke_cnt_scanout ; |
| 291 | assign ff_precharge_cnt_scanin = ff_xp_cnt_scanout ; |
| 292 | assign scan_out = ff_precharge_cnt_scanout ; |
| 293 | // fixscan end: |
| 294 | endmodule |
| 295 | |
| 296 | |
| 297 | |
| 298 | |
| 299 | |
| 300 | |
| 301 | // any PARAMS parms go into naming of macro |
| 302 | |
| 303 | module mcu_pdmc_ctl_msff_ctl_macro__width_6 ( |
| 304 | din, |
| 305 | l1clk, |
| 306 | scan_in, |
| 307 | siclk, |
| 308 | soclk, |
| 309 | dout, |
| 310 | scan_out); |
| 311 | wire [5:0] fdin; |
| 312 | wire [4:0] so; |
| 313 | |
| 314 | input [5:0] din; |
| 315 | input l1clk; |
| 316 | input scan_in; |
| 317 | |
| 318 | |
| 319 | input siclk; |
| 320 | input soclk; |
| 321 | |
| 322 | output [5:0] dout; |
| 323 | output scan_out; |
| 324 | assign fdin[5:0] = din[5:0]; |
| 325 | |
| 326 | |
| 327 | |
| 328 | |
| 329 | |
| 330 | |
| 331 | dff #(6) d0_0 ( |
| 332 | .l1clk(l1clk), |
| 333 | .siclk(siclk), |
| 334 | .soclk(soclk), |
| 335 | .d(fdin[5:0]), |
| 336 | .si({scan_in,so[4:0]}), |
| 337 | .so({so[4:0],scan_out}), |
| 338 | .q(dout[5:0]) |
| 339 | ); |
| 340 | |
| 341 | |
| 342 | |
| 343 | |
| 344 | |
| 345 | |
| 346 | |
| 347 | |
| 348 | |
| 349 | |
| 350 | |
| 351 | |
| 352 | endmodule |
| 353 | |
| 354 | |
| 355 | |
| 356 | |
| 357 | |
| 358 | |
| 359 | |
| 360 | |
| 361 | |
| 362 | |
| 363 | |
| 364 | |
| 365 | |
| 366 | // any PARAMS parms go into naming of macro |
| 367 | |
| 368 | module mcu_pdmc_ctl_msff_ctl_macro__width_4 ( |
| 369 | din, |
| 370 | l1clk, |
| 371 | scan_in, |
| 372 | siclk, |
| 373 | soclk, |
| 374 | dout, |
| 375 | scan_out); |
| 376 | wire [3:0] fdin; |
| 377 | wire [2:0] so; |
| 378 | |
| 379 | input [3:0] din; |
| 380 | input l1clk; |
| 381 | input scan_in; |
| 382 | |
| 383 | |
| 384 | input siclk; |
| 385 | input soclk; |
| 386 | |
| 387 | output [3:0] dout; |
| 388 | output scan_out; |
| 389 | assign fdin[3:0] = din[3:0]; |
| 390 | |
| 391 | |
| 392 | |
| 393 | |
| 394 | |
| 395 | |
| 396 | dff #(4) d0_0 ( |
| 397 | .l1clk(l1clk), |
| 398 | .siclk(siclk), |
| 399 | .soclk(soclk), |
| 400 | .d(fdin[3:0]), |
| 401 | .si({scan_in,so[2:0]}), |
| 402 | .so({so[2:0],scan_out}), |
| 403 | .q(dout[3:0]) |
| 404 | ); |
| 405 | |
| 406 | |
| 407 | |
| 408 | |
| 409 | |
| 410 | |
| 411 | |
| 412 | |
| 413 | |
| 414 | |
| 415 | |
| 416 | |
| 417 | endmodule |
| 418 | |
| 419 | |
| 420 | |
| 421 | |
| 422 | |
| 423 | |
| 424 | |
| 425 | |
| 426 | |
| 427 | |
| 428 | |
| 429 | |
| 430 | |
| 431 | // any PARAMS parms go into naming of macro |
| 432 | |
| 433 | module mcu_pdmc_ctl_msff_ctl_macro__width_2 ( |
| 434 | din, |
| 435 | l1clk, |
| 436 | scan_in, |
| 437 | siclk, |
| 438 | soclk, |
| 439 | dout, |
| 440 | scan_out); |
| 441 | wire [1:0] fdin; |
| 442 | wire [0:0] so; |
| 443 | |
| 444 | input [1:0] din; |
| 445 | input l1clk; |
| 446 | input scan_in; |
| 447 | |
| 448 | |
| 449 | input siclk; |
| 450 | input soclk; |
| 451 | |
| 452 | output [1:0] dout; |
| 453 | output scan_out; |
| 454 | assign fdin[1:0] = din[1:0]; |
| 455 | |
| 456 | |
| 457 | |
| 458 | |
| 459 | |
| 460 | |
| 461 | dff #(2) d0_0 ( |
| 462 | .l1clk(l1clk), |
| 463 | .siclk(siclk), |
| 464 | .soclk(soclk), |
| 465 | .d(fdin[1:0]), |
| 466 | .si({scan_in,so[0:0]}), |
| 467 | .so({so[0:0],scan_out}), |
| 468 | .q(dout[1:0]) |
| 469 | ); |
| 470 | |
| 471 | |
| 472 | |
| 473 | |
| 474 | |
| 475 | |
| 476 | |
| 477 | |
| 478 | |
| 479 | |
| 480 | |
| 481 | |
| 482 | endmodule |
| 483 | |
| 484 | |
| 485 | |
| 486 | |
| 487 | |
| 488 | |
| 489 | |
| 490 | |
| 491 | |
| 492 | |
| 493 | |
| 494 | |
| 495 | |
| 496 | // any PARAMS parms go into naming of macro |
| 497 | |
| 498 | module mcu_pdmc_ctl_msff_ctl_macro__width_5 ( |
| 499 | din, |
| 500 | l1clk, |
| 501 | scan_in, |
| 502 | siclk, |
| 503 | soclk, |
| 504 | dout, |
| 505 | scan_out); |
| 506 | wire [4:0] fdin; |
| 507 | wire [3:0] so; |
| 508 | |
| 509 | input [4:0] din; |
| 510 | input l1clk; |
| 511 | input scan_in; |
| 512 | |
| 513 | |
| 514 | input siclk; |
| 515 | input soclk; |
| 516 | |
| 517 | output [4:0] dout; |
| 518 | output scan_out; |
| 519 | assign fdin[4:0] = din[4:0]; |
| 520 | |
| 521 | |
| 522 | |
| 523 | |
| 524 | |
| 525 | |
| 526 | dff #(5) d0_0 ( |
| 527 | .l1clk(l1clk), |
| 528 | .siclk(siclk), |
| 529 | .soclk(soclk), |
| 530 | .d(fdin[4:0]), |
| 531 | .si({scan_in,so[3:0]}), |
| 532 | .so({so[3:0],scan_out}), |
| 533 | .q(dout[4:0]) |
| 534 | ); |
| 535 | |
| 536 | |
| 537 | |
| 538 | |
| 539 | |
| 540 | |
| 541 | |
| 542 | |
| 543 | |
| 544 | |
| 545 | |
| 546 | |
| 547 | endmodule |
| 548 | |
| 549 | |
| 550 | |
| 551 | |
| 552 | |
| 553 | |
| 554 | |
| 555 | |