| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ncu_i2cbuf4_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define RF_RDEN_OFFSTATE 1'b1 |
| 36 | |
| 37 | //==================================== |
| 38 | `define NCU_INTMANRF_DEPTH 128 |
| 39 | `define NCU_INTMANRF_DATAWIDTH 16 |
| 40 | `define NCU_INTMANRF_ADDRWIDTH 7 |
| 41 | //==================================== |
| 42 | |
| 43 | //==================================== |
| 44 | `define NCU_MONDORF_DEPTH 64 |
| 45 | `define NCU_MONDORF_DATAWIDTH 72 |
| 46 | `define NCU_MONDORF_ADDRWIDTH 6 |
| 47 | //==================================== |
| 48 | |
| 49 | //==================================== |
| 50 | `define NCU_CPUBUFRF_DEPTH 32 |
| 51 | `define NCU_CPUBUFRF_DATAWIDTH 144 |
| 52 | `define NCU_CPUBUFRF_ADDRWIDTH 5 |
| 53 | //==================================== |
| 54 | |
| 55 | //==================================== |
| 56 | `define NCU_IOBUFRF_DEPTH 32 |
| 57 | `define NCU_IOBUFRF_DATAWIDTH 144 |
| 58 | `define NCU_IOBUFRF_ADDRWIDTH 5 |
| 59 | //==================================== |
| 60 | |
| 61 | //==================================== |
| 62 | `define NCU_IOBUF1RF_DEPTH 32 |
| 63 | `define NCU_IOBUF1RF_DATAWIDTH 32 |
| 64 | `define NCU_IOBUF1RF_ADDRWIDTH 5 |
| 65 | //==================================== |
| 66 | |
| 67 | //==================================== |
| 68 | `define NCU_INTBUFRF_DEPTH 32 |
| 69 | `define NCU_INTBUFRF_DATAWIDTH 144 |
| 70 | `define NCU_INTBUFRF_ADDRWIDTH 5 |
| 71 | //==================================== |
| 72 | |
| 73 | //== fix me : need to remove when warm // |
| 74 | //== becomes available // |
| 75 | `define WMR_LENGTH 10'd999 |
| 76 | `define WMR_LENGTH_P1 10'd1000 |
| 77 | |
| 78 | //// NCU CSR_MAN address 80_0000_xxxx //// |
| 79 | `define NCU_CSR_MAN 16'h0000 |
| 80 | `define NCU_CREG_INTMAN 16'h0000 |
| 81 | //`define NCU_CREG_INTVECDISP 16'h0800 |
| 82 | `define NCU_CREG_MONDOINVEC 16'h0a00 |
| 83 | `define NCU_CREG_SERNUM 16'h1000 |
| 84 | `define NCU_CREG_FUSESTAT 16'h1008 |
| 85 | `define NCU_CREG_COREAVAIL 16'h1010 |
| 86 | `define NCU_CREG_BANKAVAIL 16'h1018 |
| 87 | `define NCU_CREG_BANK_ENABLE 16'h1020 |
| 88 | `define NCU_CREG_BANK_ENABLE_STATUS 16'h1028 |
| 89 | `define NCU_CREG_L2_HASH_ENABLE 16'h1030 |
| 90 | `define NCU_CREG_L2_HASH_ENABLE_STATUS 16'h1038 |
| 91 | |
| 92 | |
| 93 | `define NCU_CREG_MEM32_BASE 16'h2000 |
| 94 | `define NCU_CREG_MEM32_MASK 16'h2008 |
| 95 | `define NCU_CREG_MEM64_BASE 16'h2010 |
| 96 | `define NCU_CREG_MEM64_MASK 16'h2018 |
| 97 | `define NCU_CREG_IOCON_BASE 16'h2020 |
| 98 | `define NCU_CREG_IOCON_MASK 16'h2028 |
| 99 | `define NCU_CREG_MMUFSH 16'h2030 |
| 100 | |
| 101 | `define NCU_CREG_ESR 16'h3000 |
| 102 | `define NCU_CREG_ELE 16'h3008 |
| 103 | `define NCU_CREG_EIE 16'h3010 |
| 104 | `define NCU_CREG_EJR 16'h3018 |
| 105 | `define NCU_CREG_FEE 16'h3020 |
| 106 | `define NCU_CREG_PER 16'h3028 |
| 107 | `define NCU_CREG_SIISYN 16'h3030 |
| 108 | `define NCU_CREG_NCUSYN 16'h3038 |
| 109 | `define NCU_CREG_SCKSEL 16'h3040 |
| 110 | `define NCU_CREG_DBGTRIG_EN 16'h4000 |
| 111 | |
| 112 | //// NUC CSR_MONDO address 80_0004_xxxx //// |
| 113 | `define NCU_CSR_MONDO 16'h0004 |
| 114 | `define NCU_CREG_MDATA0 16'h0000 |
| 115 | `define NCU_CREG_MDATA1 16'h0200 |
| 116 | `define NCU_CREG_MDATA0_ALIAS 16'h0400 |
| 117 | `define NCU_CREG_MDATA1_ALIAS 16'h0600 |
| 118 | `define NCU_CREG_MBUSY 16'h0800 |
| 119 | `define NCU_CREG_MBUSY_ALIAS 16'h0a00 |
| 120 | |
| 121 | |
| 122 | |
| 123 | // ASI shared reg 90_xxxx_xxxx// |
| 124 | `define NCU_ASI_A_HIT 10'h104 // 6-bits cpuid and thread id are "x" |
| 125 | `define NCU_ASI_B_HIT 10'h1CC // 6-bits cpuid and thread id are "x" |
| 126 | `define NCU_ASI_C_HIT 10'h114 // 6-bits cpuid and thread id are "x" |
| 127 | `define NCU_ASI_COREAVAIL 16'h0000 |
| 128 | `define NCU_ASI_CORE_ENABLE_STATUS 16'h0010 |
| 129 | `define NCU_ASI_CORE_ENABLE 16'h0020 |
| 130 | `define NCU_ASI_XIR_STEERING 16'h0030 |
| 131 | `define NCU_ASI_CORE_RUNNINGRW 16'h0050 |
| 132 | `define NCU_ASI_CORE_RUNNING_STATUS 16'h0058 |
| 133 | `define NCU_ASI_CORE_RUNNING_W1S 16'h0060 |
| 134 | `define NCU_ASI_CORE_RUNNING_W1C 16'h0068 |
| 135 | `define NCU_ASI_INTVECDISP 16'h0000 |
| 136 | `define NCU_ASI_ERR_STR 16'h1000 |
| 137 | `define NCU_ASI_WMR_VEC_MASK 16'h0018 |
| 138 | `define NCU_ASI_CMP_TICK_ENABLE 16'h0038 |
| 139 | |
| 140 | |
| 141 | //// UCB packet type //// |
| 142 | `define UCB_READ_NACK 4'b0000 // ack/nack types |
| 143 | `define UCB_READ_ACK 4'b0001 |
| 144 | `define UCB_WRITE_ACK 4'b0010 |
| 145 | `define UCB_IFILL_ACK 4'b0011 |
| 146 | `define UCB_IFILL_NACK 4'b0111 |
| 147 | |
| 148 | `define UCB_READ_REQ 4'b0100 // req types |
| 149 | `define UCB_WRITE_REQ 4'b0101 |
| 150 | `define UCB_IFILL_REQ 4'b0110 |
| 151 | |
| 152 | `define UCB_INT 4'b1000 // plain interrupt |
| 153 | `define UCB_INT_VEC 4'b1100 // interrupt with vector |
| 154 | `define UCB_INT_SOC_UE 4'b1001 // soc interrup ue |
| 155 | `define UCB_INT_SOC_CE 4'b1010 // soc interrup ce |
| 156 | `define UCB_RESET_VEC 4'b0101 // reset with vector |
| 157 | `define UCB_IDLE_VEC 4'b1110 // idle with vector |
| 158 | `define UCB_RESUME_VEC 4'b1111 // resume with vector |
| 159 | |
| 160 | `define UCB_INT_SOC 4'b1101 // soc interrup ce |
| 161 | |
| 162 | |
| 163 | //// PCX packet type //// |
| 164 | `define PCX_LOAD_RQ 5'b00000 |
| 165 | `define PCX_IMISS_RQ 5'b10000 |
| 166 | `define PCX_STORE_RQ 5'b00001 |
| 167 | `define PCX_FWD_RQs 5'b01101 |
| 168 | `define PCX_FWD_RPYs 5'b01110 |
| 169 | |
| 170 | //// CPX packet type //// |
| 171 | //`define CPX_LOAD_RET 4'b0000 |
| 172 | `define CPX_LOAD_RET 4'b1000 |
| 173 | `define CPX_ST_ACK 4'b0100 |
| 174 | //`define CPX_IFILL_RET 4'b0001 |
| 175 | `define CPX_IFILL_RET 4'b1001 |
| 176 | `define CPX_INT_RET 4'b0111 |
| 177 | `define CPX_INT_SOC 4'b1101 |
| 178 | //`define CPX_FWD_RQ_RET 4'b1010 |
| 179 | //`define CPX_FWD_RPY_RET 4'b1011 |
| 180 | |
| 181 | |
| 182 | |
| 183 | |
| 184 | //// Global CSR decode //// |
| 185 | `define NCU_CSR 8'h80 |
| 186 | `define NIU_CSR 8'h81 |
| 187 | //`define RNG_CSR 8'h82 |
| 188 | `define DBG1_CSR 8'h86 |
| 189 | `define CCU_CSR 8'h83 |
| 190 | `define MCU_CSR 8'h84 |
| 191 | `define TCU_CSR 8'h85 |
| 192 | `define DMU_CSR 8'h88 |
| 193 | `define RCU_CSR 8'h89 |
| 194 | `define NCU_ASI 8'h90 |
| 195 | /////8'h91 ~ 9F reserved |
| 196 | /////8'hA0 ~ BF L2 CSR//// |
| 197 | `define DMU_PIO 4'hC // C0 ~ CF |
| 198 | /////8'hB0 ~ FE reserved |
| 199 | `define SSI_CSR 8'hFF |
| 200 | |
| 201 | |
| 202 | //// NCU_SSI //// |
| 203 | `define SSI_ADDR 12'hFF_F |
| 204 | `define SSI_ADDR_TIMEOUT_REG 40'hFF_0001_0088 |
| 205 | `define SSI_ADDR_LOG_REG 40'hFF_0000_0018 |
| 206 | |
| 207 | `define IF_IDLE 2'b00 |
| 208 | `define IF_ACPT 2'b01 |
| 209 | `define IF_DROP 2'b10 |
| 210 | |
| 211 | `define SSI_IDLE 3'b000 |
| 212 | `define SSI_REQ 3'b001 |
| 213 | `define SSI_WDATA 3'b011 |
| 214 | `define SSI_REQ_PAR 3'b101 |
| 215 | `define SSI_ACK 3'b111 |
| 216 | `define SSI_RDATA 3'b110 |
| 217 | `define SSI_ACK_PAR 3'b010 |
| 218 | |
| 219 | |
| 220 | |
| 221 | |
| 222 | |
| 223 | |
| 224 | |
| 225 | |
| 226 | |
| 227 | |
| 228 | module ncu_i2cbuf4_ctl ( |
| 229 | iol2clk, |
| 230 | scan_in, |
| 231 | scan_out, |
| 232 | tcu_pce_ov, |
| 233 | tcu_clk_stop, |
| 234 | tcu_scan_en, |
| 235 | tcu_aclk, |
| 236 | tcu_bclk, |
| 237 | ucb_iob_vld, |
| 238 | ucb_iob_data, |
| 239 | iob_ucb_stall, |
| 240 | req_ack_obj, |
| 241 | req_ack_vld, |
| 242 | rd_req_ack_dbl_buf, |
| 243 | int_obj, |
| 244 | int_vld, |
| 245 | rd_int_dbl_buf) ; |
| 246 | wire stall_d1_n; |
| 247 | wire stall_d1; |
| 248 | wire vld_d1_ff_scanin; |
| 249 | wire vld_d1_ff_scanout; |
| 250 | wire vld_d1; |
| 251 | wire l1clk; |
| 252 | wire rdy1; |
| 253 | wire data_d1_ff_scanin; |
| 254 | wire data_d1_ff_scanout; |
| 255 | wire [3:0] data_d1; |
| 256 | wire stall_ff_scanin; |
| 257 | wire stall_ff_scanout; |
| 258 | wire iob_ucb_stall_a1; |
| 259 | wire stall_d1_ff_scanin; |
| 260 | wire stall_d1_ff_scanout; |
| 261 | wire rdy0_ff_scanin; |
| 262 | wire rdy0_ff_scanout; |
| 263 | wire rdy0; |
| 264 | wire rdy1_ff_scanin; |
| 265 | wire rdy1_ff_scanout; |
| 266 | wire skid_buf0_en; |
| 267 | wire vld_buf0_ff_scanin; |
| 268 | wire vld_buf0_ff_scanout; |
| 269 | wire vld_buf0; |
| 270 | wire data_buf0_ff_scanin; |
| 271 | wire data_buf0_ff_scanout; |
| 272 | wire [3:0] data_buf0; |
| 273 | wire skid_buf1_en_ff_scanin; |
| 274 | wire skid_buf1_en_ff_scanout; |
| 275 | wire skid_buf1_en; |
| 276 | wire vld_buf1_ff_scanin; |
| 277 | wire vld_buf1_ff_scanout; |
| 278 | wire vld_buf1; |
| 279 | wire data_buf1_ff_scanin; |
| 280 | wire data_buf1_ff_scanout; |
| 281 | wire [3:0] data_buf1; |
| 282 | wire skid_buf0_sel; |
| 283 | wire skid_buf1_sel_ff_scanin; |
| 284 | wire skid_buf1_sel_ff_scanout; |
| 285 | wire skid_buf1_sel; |
| 286 | wire vld_mux; |
| 287 | wire [3:0] data_mux; |
| 288 | wire [31:0] indata_vec_next; |
| 289 | wire [31:0] indata_vec; |
| 290 | wire iob_ucb_stall_a1_n; |
| 291 | wire indata_vec_ff_scanin; |
| 292 | wire indata_vec_ff_scanout; |
| 293 | wire [127:0] indata_buf_next; |
| 294 | wire [127:0] indata_buf; |
| 295 | wire indata_buf_ff_scanin; |
| 296 | wire indata_buf_ff_scanout; |
| 297 | wire indata_vec0_d1_ff_scanin; |
| 298 | wire indata_vec0_d1_ff_scanout; |
| 299 | wire indata_vec0_d1; |
| 300 | wire indata_buf_vld; |
| 301 | wire req_ack_pending; |
| 302 | wire int_type; |
| 303 | wire int_pending; |
| 304 | wire req_ack_dbl_buf_full; |
| 305 | wire int_dbl_buf_full; |
| 306 | wire wr_req_ack_dbl_buf; |
| 307 | wire a_wr_buf0; |
| 308 | wire a_buf1_vld; |
| 309 | wire a_buf0_vld; |
| 310 | wire a_buf1_older; |
| 311 | wire a_wr_buf1; |
| 312 | wire a_rd_buf0; |
| 313 | wire a_rd_buf1; |
| 314 | wire a_rd_buf; |
| 315 | wire a_buf1_older_n; |
| 316 | wire a_buf1_older_ff_scanin; |
| 317 | wire a_buf1_older_ff_scanout; |
| 318 | wire a_en_vld0; |
| 319 | wire a_en_vld1; |
| 320 | wire a_buf0_vld_ff_scanin; |
| 321 | wire a_buf0_vld_ff_scanout; |
| 322 | wire a_buf1_vld_ff_scanin; |
| 323 | wire a_buf1_vld_ff_scanout; |
| 324 | wire a_buf0_obj_ff_scanin; |
| 325 | wire a_buf0_obj_ff_scanout; |
| 326 | wire [127:0] a_buf0_obj; |
| 327 | wire a_buf1_obj_ff_scanin; |
| 328 | wire a_buf1_obj_ff_scanout; |
| 329 | wire [127:0] a_buf1_obj; |
| 330 | wire wr_int_dbl_buf; |
| 331 | wire i_wr_buf0; |
| 332 | wire i_buf1_vld; |
| 333 | wire i_buf0_vld; |
| 334 | wire i_buf1_older; |
| 335 | wire i_wr_buf1; |
| 336 | wire i_rd_buf0; |
| 337 | wire i_rd_buf1; |
| 338 | wire i_rd_buf; |
| 339 | wire i_buf1_older_n; |
| 340 | wire i_buf1_older_ff_scanin; |
| 341 | wire i_buf1_older_ff_scanout; |
| 342 | wire i_en_vld0; |
| 343 | wire i_en_vld1; |
| 344 | wire i_buf0_vld_ff_scanin; |
| 345 | wire i_buf0_vld_ff_scanout; |
| 346 | wire i_buf1_vld_ff_scanin; |
| 347 | wire i_buf1_vld_ff_scanout; |
| 348 | wire i_buf0_obj_ff_scanin; |
| 349 | wire i_buf0_obj_ff_scanout; |
| 350 | wire [24:0] i_buf0_obj; |
| 351 | wire i_buf1_obj_ff_scanin; |
| 352 | wire i_buf1_obj_ff_scanout; |
| 353 | wire [24:0] i_buf1_obj; |
| 354 | wire siclk; |
| 355 | wire soclk; |
| 356 | wire se; |
| 357 | wire pce_ov; |
| 358 | wire stop; |
| 359 | |
| 360 | |
| 361 | // Global interface |
| 362 | input iol2clk; |
| 363 | input scan_in; |
| 364 | output scan_out; |
| 365 | input tcu_pce_ov; |
| 366 | input tcu_clk_stop; |
| 367 | input tcu_scan_en; |
| 368 | input tcu_aclk; |
| 369 | input tcu_bclk; |
| 370 | |
| 371 | // UCB interface |
| 372 | input ucb_iob_vld; |
| 373 | input [3:0] ucb_iob_data; |
| 374 | output iob_ucb_stall; |
| 375 | |
| 376 | // i2c slow control/datapath interface |
| 377 | output [127:0] req_ack_obj; |
| 378 | output req_ack_vld; |
| 379 | input rd_req_ack_dbl_buf; |
| 380 | |
| 381 | output [24:0] int_obj; |
| 382 | output int_vld; |
| 383 | input rd_int_dbl_buf; |
| 384 | |
| 385 | // Internal signals |
| 386 | |
| 387 | /************************************************************ |
| 388 | * Assemble inbound packet |
| 389 | ************************************************************/ |
| 390 | //ucb_bus_in #(UCB_BUS_WIDTH) ucb_bus_in ( |
| 391 | // .clk(iol2clk), |
| 392 | // .vld(ucb_iob_vld), |
| 393 | // .data(ucb_iob_data[UCB_BUS_WIDTH-1:0]), |
| 394 | // .stall(iob_ucb_stall), |
| 395 | // .indata_buf_vld(indata_buf_vld), |
| 396 | // .indata_buf(indata_buf[127:0]), |
| 397 | // .stall_a1(iob_ucb_stall_a1)); |
| 398 | //=============================================================== |
| 399 | //=============================================================== |
| 400 | //==================================== ucb_bus_in =============== |
| 401 | |
| 402 | /************************************************************ |
| 403 | * UCB bus interface flops |
| 404 | * This is to make signals going between IOB and UCB flop-to-flop |
| 405 | * to improve timing. |
| 406 | ************************************************************/ |
| 407 | assign stall_d1_n = ~stall_d1; |
| 408 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 vld_d1_ff |
| 409 | ( |
| 410 | .scan_in(vld_d1_ff_scanin), |
| 411 | .scan_out(vld_d1_ff_scanout), |
| 412 | .dout (vld_d1), |
| 413 | .l1clk (l1clk), |
| 414 | .en (stall_d1_n&rdy1), |
| 415 | .din (ucb_iob_vld), |
| 416 | .siclk(siclk), |
| 417 | .soclk(soclk) |
| 418 | ); |
| 419 | |
| 420 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_4 data_d1_ff |
| 421 | ( |
| 422 | .scan_in(data_d1_ff_scanin), |
| 423 | .scan_out(data_d1_ff_scanout), |
| 424 | .dout (data_d1[3:0]), |
| 425 | .l1clk (l1clk), |
| 426 | .en (stall_d1_n), |
| 427 | .din (ucb_iob_data[3:0]), |
| 428 | .siclk(siclk), |
| 429 | .soclk(soclk) |
| 430 | ); |
| 431 | |
| 432 | ncu_i2cbuf4_ctl_msff_ctl_macro__width_1 stall_ff |
| 433 | ( |
| 434 | .scan_in(stall_ff_scanin), |
| 435 | .scan_out(stall_ff_scanout), |
| 436 | .dout (iob_ucb_stall), |
| 437 | .l1clk (l1clk), |
| 438 | .din (iob_ucb_stall_a1), |
| 439 | .siclk(siclk), |
| 440 | .soclk(soclk) |
| 441 | ); |
| 442 | |
| 443 | ncu_i2cbuf4_ctl_msff_ctl_macro__width_1 stall_d1_ff |
| 444 | ( |
| 445 | .scan_in(stall_d1_ff_scanin), |
| 446 | .scan_out(stall_d1_ff_scanout), |
| 447 | .dout (stall_d1), |
| 448 | .l1clk (l1clk), |
| 449 | .din (iob_ucb_stall), |
| 450 | .siclk(siclk), |
| 451 | .soclk(soclk) |
| 452 | ); |
| 453 | |
| 454 | ncu_i2cbuf4_ctl_msff_ctl_macro__width_1 rdy0_ff |
| 455 | ( |
| 456 | .scan_in(rdy0_ff_scanin), |
| 457 | .scan_out(rdy0_ff_scanout), |
| 458 | .dout (rdy0), |
| 459 | .l1clk (l1clk), |
| 460 | .din (1'b1), |
| 461 | .siclk(siclk), |
| 462 | .soclk(soclk) |
| 463 | ); |
| 464 | |
| 465 | ncu_i2cbuf4_ctl_msff_ctl_macro__width_1 rdy1_ff |
| 466 | ( |
| 467 | .scan_in(rdy1_ff_scanin), |
| 468 | .scan_out(rdy1_ff_scanout), |
| 469 | .dout (rdy1), |
| 470 | .l1clk (l1clk), |
| 471 | .din (rdy0), |
| 472 | .siclk(siclk), |
| 473 | .soclk(soclk) |
| 474 | ); |
| 475 | |
| 476 | /************************************************************ |
| 477 | * Skid buffer |
| 478 | * We need a two deep skid buffer to handle stalling. |
| 479 | ************************************************************/ |
| 480 | // Assertion: stall has to be deasserted for more than 1 cycle |
| 481 | // ie time between two separate stalls has to be |
| 482 | // at least two cycles. Otherwise, contents from |
| 483 | // skid buffer will be lost. |
| 484 | |
| 485 | // Buffer 0 |
| 486 | assign skid_buf0_en = iob_ucb_stall_a1 & ~iob_ucb_stall; |
| 487 | |
| 488 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 vld_buf0_ff |
| 489 | ( |
| 490 | .scan_in(vld_buf0_ff_scanin), |
| 491 | .scan_out(vld_buf0_ff_scanout), |
| 492 | .dout (vld_buf0), |
| 493 | .l1clk (l1clk), |
| 494 | .en (skid_buf0_en), |
| 495 | .din (vld_d1), |
| 496 | .siclk(siclk), |
| 497 | .soclk(soclk) |
| 498 | ); |
| 499 | |
| 500 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_4 data_buf0_ff |
| 501 | ( |
| 502 | .scan_in(data_buf0_ff_scanin), |
| 503 | .scan_out(data_buf0_ff_scanout), |
| 504 | .dout (data_buf0[3:0]), |
| 505 | .l1clk (l1clk), |
| 506 | .en (skid_buf0_en), |
| 507 | .din (data_d1[3:0]), |
| 508 | .siclk(siclk), |
| 509 | .soclk(soclk) |
| 510 | ); |
| 511 | |
| 512 | // Buffer 1 |
| 513 | ncu_i2cbuf4_ctl_msff_ctl_macro__width_1 skid_buf1_en_ff |
| 514 | ( |
| 515 | .scan_in(skid_buf1_en_ff_scanin), |
| 516 | .scan_out(skid_buf1_en_ff_scanout), |
| 517 | .dout (skid_buf1_en), |
| 518 | .l1clk (l1clk), |
| 519 | .din (skid_buf0_en), |
| 520 | .siclk(siclk), |
| 521 | .soclk(soclk) |
| 522 | ); |
| 523 | |
| 524 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 vld_buf1_ff |
| 525 | ( |
| 526 | .scan_in(vld_buf1_ff_scanin), |
| 527 | .scan_out(vld_buf1_ff_scanout), |
| 528 | .dout (vld_buf1), |
| 529 | .l1clk (l1clk), |
| 530 | .en (skid_buf1_en), |
| 531 | .din (vld_d1), |
| 532 | .siclk(siclk), |
| 533 | .soclk(soclk) |
| 534 | ); |
| 535 | |
| 536 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_4 data_buf1_ff |
| 537 | ( |
| 538 | .scan_in(data_buf1_ff_scanin), |
| 539 | .scan_out(data_buf1_ff_scanout), |
| 540 | .dout (data_buf1[3:0]), |
| 541 | .l1clk (l1clk), |
| 542 | .en (skid_buf1_en), |
| 543 | .din (data_d1[3:0]), |
| 544 | .siclk(siclk), |
| 545 | .soclk(soclk) |
| 546 | ); |
| 547 | /************************************************************ |
| 548 | * Mux between skid buffer and interface flop |
| 549 | ************************************************************/ |
| 550 | // Assertion: stall has to be deasserted for more than 1 cycle |
| 551 | // ie time between two separate stalls has to be |
| 552 | // at least two cycles. Otherwise, contents from |
| 553 | // skid buffer will be lost. |
| 554 | |
| 555 | assign skid_buf0_sel = ~iob_ucb_stall_a1 & iob_ucb_stall; |
| 556 | |
| 557 | ncu_i2cbuf4_ctl_msff_ctl_macro__width_1 skid_buf1_sel_ff |
| 558 | ( |
| 559 | .scan_in(skid_buf1_sel_ff_scanin), |
| 560 | .scan_out(skid_buf1_sel_ff_scanout), |
| 561 | .dout (skid_buf1_sel), |
| 562 | .l1clk (l1clk), |
| 563 | .din (skid_buf0_sel), |
| 564 | .siclk(siclk), |
| 565 | .soclk(soclk) |
| 566 | ); |
| 567 | |
| 568 | assign vld_mux = skid_buf0_sel ? vld_buf0 : |
| 569 | skid_buf1_sel ? vld_buf1 : |
| 570 | vld_d1; |
| 571 | |
| 572 | assign data_mux[3:0] = skid_buf0_sel ? data_buf0[3:0] : |
| 573 | skid_buf1_sel ? data_buf1[3:0] : |
| 574 | data_d1[3:0]; |
| 575 | |
| 576 | /************************************************************ |
| 577 | * Assemble inbound data |
| 578 | ************************************************************/ |
| 579 | // valid vector |
| 580 | assign indata_vec_next[31:0] = {vld_mux, |
| 581 | indata_vec[31:1]}; |
| 582 | assign iob_ucb_stall_a1_n = ~iob_ucb_stall_a1; |
| 583 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_32 indata_vec_ff |
| 584 | ( |
| 585 | .scan_in(indata_vec_ff_scanin), |
| 586 | .scan_out(indata_vec_ff_scanout), |
| 587 | .dout (indata_vec[31:0]), |
| 588 | .l1clk (l1clk), |
| 589 | .en (iob_ucb_stall_a1_n), |
| 590 | .din (indata_vec_next[31:0]), |
| 591 | .siclk(siclk), |
| 592 | .soclk(soclk) |
| 593 | ); |
| 594 | |
| 595 | // data buffer |
| 596 | assign indata_buf_next[127:0] = {data_mux[3:0], indata_buf[127:4]}; |
| 597 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_128 indata_buf_ff |
| 598 | ( |
| 599 | .scan_in(indata_buf_ff_scanin), |
| 600 | .scan_out(indata_buf_ff_scanout), |
| 601 | .dout (indata_buf[127:0]), |
| 602 | .l1clk (l1clk), |
| 603 | .en (iob_ucb_stall_a1_n), |
| 604 | .din (indata_buf_next[127:0]), |
| 605 | .siclk(siclk), |
| 606 | .soclk(soclk) |
| 607 | ); |
| 608 | |
| 609 | // detect a new packet |
| 610 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 indata_vec0_d1_ff |
| 611 | ( |
| 612 | .scan_in(indata_vec0_d1_ff_scanin), |
| 613 | .scan_out(indata_vec0_d1_ff_scanout), |
| 614 | .dout (indata_vec0_d1), |
| 615 | .l1clk (l1clk), |
| 616 | .en (iob_ucb_stall_a1_n), |
| 617 | .din (indata_vec[0]), |
| 618 | .siclk(siclk), |
| 619 | .soclk(soclk) |
| 620 | ); |
| 621 | |
| 622 | assign indata_buf_vld = indata_vec[0] & ~indata_vec0_d1; |
| 623 | //================================= ucb_bus_in ================== |
| 624 | //=============================================================== |
| 625 | //=============================================================== |
| 626 | |
| 627 | |
| 628 | |
| 629 | |
| 630 | |
| 631 | |
| 632 | |
| 633 | |
| 634 | /************************************************************ |
| 635 | * Decode inbound packet type |
| 636 | ************************************************************/ |
| 637 | // non-interrupt packet |
| 638 | assign req_ack_pending = ~int_type & indata_buf_vld; |
| 639 | |
| 640 | // interrupt packet |
| 641 | assign int_type = ((indata_buf[3:0] == `UCB_INT) | |
| 642 | (indata_buf[3:0] == `UCB_INT_VEC) | |
| 643 | (indata_buf[3:0] == `UCB_RESET_VEC) | |
| 644 | (indata_buf[3:0] == `UCB_IDLE_VEC) | |
| 645 | (indata_buf[3:0] == `UCB_RESUME_VEC) ); |
| 646 | |
| 647 | assign int_pending = int_type & indata_buf_vld; |
| 648 | |
| 649 | assign iob_ucb_stall_a1 = (req_ack_pending & req_ack_dbl_buf_full) | |
| 650 | (int_pending & int_dbl_buf_full); |
| 651 | |
| 652 | /************************************************************ |
| 653 | * Double buffer to store non-interrupt packets |
| 654 | ************************************************************/ |
| 655 | assign wr_req_ack_dbl_buf = req_ack_pending & ~req_ack_dbl_buf_full; |
| 656 | |
| 657 | //dbl_buf #(128) req_ack_dbl_buf ( |
| 658 | // .clk(iol2clk), |
| 659 | // .wr(wr_req_ack_dbl_buf), |
| 660 | // .din(indata_buf[127:0]), |
| 661 | // .rd(rd_req_ack_dbl_buf), |
| 662 | // .dout(req_ack_obj[127:0]), |
| 663 | // .vld(req_ack_vld), |
| 664 | // .full(req_ack_dbl_buf_full)); |
| 665 | //=============================================================== |
| 666 | //=============================================================== |
| 667 | //======================================= dbl_buf =============== |
| 668 | |
| 669 | |
| 670 | //////////////////////////////////////////////////////////////////////// |
| 671 | // Code starts here |
| 672 | //////////////////////////////////////////////////////////////////////// |
| 673 | // if both entries are empty, write to entry pointed to by the older pointer |
| 674 | assign a_wr_buf0 = wr_req_ack_dbl_buf & (a_buf1_vld | (~a_buf0_vld & ~a_buf1_older)); |
| 675 | assign a_wr_buf1 = wr_req_ack_dbl_buf & (a_buf0_vld | (~a_buf1_vld & a_buf1_older)); |
| 676 | |
| 677 | // read from the older entry |
| 678 | assign a_rd_buf0 = rd_req_ack_dbl_buf & ~a_buf1_older; |
| 679 | assign a_rd_buf1 = rd_req_ack_dbl_buf & a_buf1_older; |
| 680 | |
| 681 | // flip older pointer when an entry is read |
| 682 | assign a_rd_buf = rd_req_ack_dbl_buf & (a_buf0_vld | a_buf1_vld); |
| 683 | assign a_buf1_older_n = ~a_buf1_older; |
| 684 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 a_buf1_older_ff |
| 685 | ( |
| 686 | .scan_in(a_buf1_older_ff_scanin), |
| 687 | .scan_out(a_buf1_older_ff_scanout), |
| 688 | .dout (a_buf1_older), |
| 689 | .l1clk (l1clk), |
| 690 | .en (a_rd_buf), |
| 691 | .din (a_buf1_older_n), |
| 692 | .siclk(siclk), |
| 693 | .soclk(soclk) |
| 694 | ); |
| 695 | |
| 696 | // set valid bit for writes and reset for reads |
| 697 | assign a_en_vld0 = a_wr_buf0 | a_rd_buf0; |
| 698 | assign a_en_vld1 = a_wr_buf1 | a_rd_buf1; |
| 699 | |
| 700 | // the actual buffers |
| 701 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 a_buf0_vld_ff |
| 702 | ( |
| 703 | .scan_in(a_buf0_vld_ff_scanin), |
| 704 | .scan_out(a_buf0_vld_ff_scanout), |
| 705 | .dout (a_buf0_vld), |
| 706 | .l1clk (l1clk), |
| 707 | .en (a_en_vld0), |
| 708 | .din (a_wr_buf0), |
| 709 | .siclk(siclk), |
| 710 | .soclk(soclk) |
| 711 | ); |
| 712 | |
| 713 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 a_buf1_vld_ff |
| 714 | ( |
| 715 | .scan_in(a_buf1_vld_ff_scanin), |
| 716 | .scan_out(a_buf1_vld_ff_scanout), |
| 717 | .dout (a_buf1_vld), |
| 718 | .l1clk (l1clk), |
| 719 | .en (a_en_vld1), |
| 720 | .din (a_wr_buf1), |
| 721 | .siclk(siclk), |
| 722 | .soclk(soclk) |
| 723 | ); |
| 724 | |
| 725 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_128 a_buf0_obj_ff |
| 726 | ( |
| 727 | .scan_in(a_buf0_obj_ff_scanin), |
| 728 | .scan_out(a_buf0_obj_ff_scanout), |
| 729 | .dout (a_buf0_obj[127:0]), |
| 730 | .l1clk (l1clk), |
| 731 | .en (a_wr_buf0), |
| 732 | .din (indata_buf[127:0]), |
| 733 | .siclk(siclk), |
| 734 | .soclk(soclk) |
| 735 | ); |
| 736 | |
| 737 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_128 a_buf1_obj_ff |
| 738 | ( |
| 739 | .scan_in(a_buf1_obj_ff_scanin), |
| 740 | .scan_out(a_buf1_obj_ff_scanout), |
| 741 | .dout (a_buf1_obj[127:0]), |
| 742 | .l1clk (l1clk), |
| 743 | .en (a_wr_buf1), |
| 744 | .din (indata_buf[127:0]), |
| 745 | .siclk(siclk), |
| 746 | .soclk(soclk) |
| 747 | ); |
| 748 | |
| 749 | // mux out the older entry |
| 750 | assign req_ack_obj[127:0] = (a_buf1_older) ? a_buf1_obj[127:0] : a_buf0_obj[127:0] ; |
| 751 | |
| 752 | assign req_ack_vld = a_buf0_vld | a_buf1_vld; |
| 753 | assign req_ack_dbl_buf_full = a_buf0_vld & a_buf1_vld; |
| 754 | //================================ dbl_buf ====================== |
| 755 | //=============================================================== |
| 756 | //=============================================================== |
| 757 | |
| 758 | |
| 759 | |
| 760 | |
| 761 | /************************************************************ |
| 762 | * Double buffer to store interrupt packets |
| 763 | ************************************************************/ |
| 764 | assign wr_int_dbl_buf = int_pending & ~int_dbl_buf_full; |
| 765 | //dbl_buf #(64) int_dbl_buf ( |
| 766 | // .clk(iol2clk), |
| 767 | // .wr(wr_int_dbl_buf), |
| 768 | // .din(indata_buf[63:0]), |
| 769 | // .rd(rd_int_dbl_buf), |
| 770 | // .dout(int_obj[63:0]), |
| 771 | // .vld(int_vld), |
| 772 | // .full(int_dbl_buf_full)); |
| 773 | //=============================================================== |
| 774 | //=============================================================== |
| 775 | //======================================= dbl_buf =============== |
| 776 | |
| 777 | //////////////////////////////////////////////////////////////////////// |
| 778 | // Code starts here |
| 779 | //////////////////////////////////////////////////////////////////////// |
| 780 | // if both entries are empty, write to entry pointed to by the older pointer |
| 781 | assign i_wr_buf0 = wr_int_dbl_buf & (i_buf1_vld | (~i_buf0_vld & ~i_buf1_older)); |
| 782 | assign i_wr_buf1 = wr_int_dbl_buf & (i_buf0_vld | (~i_buf1_vld & i_buf1_older)); |
| 783 | |
| 784 | // read from the older entry |
| 785 | assign i_rd_buf0 = rd_int_dbl_buf & ~i_buf1_older; |
| 786 | assign i_rd_buf1 = rd_int_dbl_buf & i_buf1_older; |
| 787 | |
| 788 | // flip older pointer when an entry is read |
| 789 | assign i_rd_buf = rd_int_dbl_buf & (i_buf0_vld | i_buf1_vld); |
| 790 | assign i_buf1_older_n = ~i_buf1_older; |
| 791 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 i_buf1_older_ff |
| 792 | ( |
| 793 | .scan_in(i_buf1_older_ff_scanin), |
| 794 | .scan_out(i_buf1_older_ff_scanout), |
| 795 | .dout (i_buf1_older), |
| 796 | .l1clk (l1clk), |
| 797 | .en (i_rd_buf), |
| 798 | .din (i_buf1_older_n), |
| 799 | .siclk(siclk), |
| 800 | .soclk(soclk) |
| 801 | ); |
| 802 | |
| 803 | // set valid bit for writes and reset for reads |
| 804 | assign i_en_vld0 = i_wr_buf0 | i_rd_buf0; |
| 805 | assign i_en_vld1 = i_wr_buf1 | i_rd_buf1; |
| 806 | |
| 807 | // the actual buffers |
| 808 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 i_buf0_vld_ff |
| 809 | ( |
| 810 | .scan_in(i_buf0_vld_ff_scanin), |
| 811 | .scan_out(i_buf0_vld_ff_scanout), |
| 812 | .dout (i_buf0_vld), |
| 813 | .l1clk (l1clk), |
| 814 | .en (i_en_vld0), |
| 815 | .din (i_wr_buf0), |
| 816 | .siclk(siclk), |
| 817 | .soclk(soclk) |
| 818 | ); |
| 819 | |
| 820 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 i_buf1_vld_ff |
| 821 | ( |
| 822 | .scan_in(i_buf1_vld_ff_scanin), |
| 823 | .scan_out(i_buf1_vld_ff_scanout), |
| 824 | .dout (i_buf1_vld), |
| 825 | .l1clk (l1clk), |
| 826 | .en (i_en_vld1), |
| 827 | .din (i_wr_buf1), |
| 828 | .siclk(siclk), |
| 829 | .soclk(soclk) |
| 830 | ); |
| 831 | |
| 832 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_25 i_buf0_obj_ff |
| 833 | ( |
| 834 | .scan_in(i_buf0_obj_ff_scanin), |
| 835 | .scan_out(i_buf0_obj_ff_scanout), |
| 836 | .dout (i_buf0_obj[24:0]), |
| 837 | .l1clk (l1clk), |
| 838 | .en (i_wr_buf0), |
| 839 | .din ({indata_buf[56:51],indata_buf[18:0]}), |
| 840 | .siclk(siclk), |
| 841 | .soclk(soclk) |
| 842 | ); |
| 843 | |
| 844 | ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_25 i_buf1_obj_ff |
| 845 | ( |
| 846 | .scan_in(i_buf1_obj_ff_scanin), |
| 847 | .scan_out(i_buf1_obj_ff_scanout), |
| 848 | .dout (i_buf1_obj[24:0]), |
| 849 | .l1clk (l1clk), |
| 850 | .en (i_wr_buf1), |
| 851 | .din ({indata_buf[56:51],indata_buf[18:0]}), |
| 852 | .siclk(siclk), |
| 853 | .soclk(soclk) |
| 854 | ); |
| 855 | |
| 856 | // mux out the older entry |
| 857 | assign int_obj[24:0] = (i_buf1_older) ? i_buf1_obj[24:0] : i_buf0_obj[24:0] ; |
| 858 | |
| 859 | assign int_vld = i_buf0_vld | i_buf1_vld; |
| 860 | assign int_dbl_buf_full = i_buf0_vld & i_buf1_vld; |
| 861 | //========================================== dbl_buf ============ |
| 862 | //=============================================================== |
| 863 | //=============================================================== |
| 864 | |
| 865 | |
| 866 | |
| 867 | |
| 868 | |
| 869 | |
| 870 | /**** adding clock header ****/ |
| 871 | ncu_i2cbuf4_ctl_l1clkhdr_ctl_macro clkgen ( |
| 872 | .l2clk (iol2clk), |
| 873 | .l1en (1'b1), |
| 874 | .l1clk (l1clk), |
| 875 | .pce_ov(pce_ov), |
| 876 | .stop(stop), |
| 877 | .se(se) |
| 878 | ); |
| 879 | |
| 880 | /*** building tcu port ***/ |
| 881 | assign siclk = tcu_aclk; |
| 882 | assign soclk = tcu_bclk; |
| 883 | assign se = tcu_scan_en; |
| 884 | assign pce_ov = tcu_pce_ov; |
| 885 | assign stop = tcu_clk_stop; |
| 886 | |
| 887 | // fixscan start: |
| 888 | assign vld_d1_ff_scanin = scan_in ; |
| 889 | assign data_d1_ff_scanin = vld_d1_ff_scanout ; |
| 890 | assign stall_ff_scanin = data_d1_ff_scanout ; |
| 891 | assign stall_d1_ff_scanin = stall_ff_scanout ; |
| 892 | assign rdy0_ff_scanin = stall_d1_ff_scanout ; |
| 893 | assign rdy1_ff_scanin = rdy0_ff_scanout ; |
| 894 | assign vld_buf0_ff_scanin = rdy1_ff_scanout ; |
| 895 | assign data_buf0_ff_scanin = vld_buf0_ff_scanout ; |
| 896 | assign skid_buf1_en_ff_scanin = data_buf0_ff_scanout ; |
| 897 | assign vld_buf1_ff_scanin = skid_buf1_en_ff_scanout ; |
| 898 | assign data_buf1_ff_scanin = vld_buf1_ff_scanout ; |
| 899 | assign skid_buf1_sel_ff_scanin = data_buf1_ff_scanout ; |
| 900 | assign indata_vec_ff_scanin = skid_buf1_sel_ff_scanout ; |
| 901 | assign indata_buf_ff_scanin = indata_vec_ff_scanout ; |
| 902 | assign indata_vec0_d1_ff_scanin = indata_buf_ff_scanout ; |
| 903 | assign a_buf1_older_ff_scanin = indata_vec0_d1_ff_scanout; |
| 904 | assign a_buf0_vld_ff_scanin = a_buf1_older_ff_scanout ; |
| 905 | assign a_buf1_vld_ff_scanin = a_buf0_vld_ff_scanout ; |
| 906 | assign a_buf0_obj_ff_scanin = a_buf1_vld_ff_scanout ; |
| 907 | assign a_buf1_obj_ff_scanin = a_buf0_obj_ff_scanout ; |
| 908 | assign i_buf1_older_ff_scanin = a_buf1_obj_ff_scanout ; |
| 909 | assign i_buf0_vld_ff_scanin = i_buf1_older_ff_scanout ; |
| 910 | assign i_buf1_vld_ff_scanin = i_buf0_vld_ff_scanout ; |
| 911 | assign i_buf0_obj_ff_scanin = i_buf1_vld_ff_scanout ; |
| 912 | assign i_buf1_obj_ff_scanin = i_buf0_obj_ff_scanout ; |
| 913 | assign scan_out = i_buf1_obj_ff_scanout ; |
| 914 | // fixscan end: |
| 915 | endmodule // i2c_buf |
| 916 | |
| 917 | |
| 918 | |
| 919 | |
| 920 | |
| 921 | |
| 922 | |
| 923 | |
| 924 | // any PARAMS parms go into naming of macro |
| 925 | |
| 926 | module ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_1 ( |
| 927 | din, |
| 928 | en, |
| 929 | l1clk, |
| 930 | scan_in, |
| 931 | siclk, |
| 932 | soclk, |
| 933 | dout, |
| 934 | scan_out); |
| 935 | wire [0:0] fdin; |
| 936 | |
| 937 | input [0:0] din; |
| 938 | input en; |
| 939 | input l1clk; |
| 940 | input scan_in; |
| 941 | |
| 942 | |
| 943 | input siclk; |
| 944 | input soclk; |
| 945 | |
| 946 | output [0:0] dout; |
| 947 | output scan_out; |
| 948 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 949 | |
| 950 | |
| 951 | |
| 952 | |
| 953 | |
| 954 | |
| 955 | dff #(1) d0_0 ( |
| 956 | .l1clk(l1clk), |
| 957 | .siclk(siclk), |
| 958 | .soclk(soclk), |
| 959 | .d(fdin[0:0]), |
| 960 | .si(scan_in), |
| 961 | .so(scan_out), |
| 962 | .q(dout[0:0]) |
| 963 | ); |
| 964 | |
| 965 | |
| 966 | |
| 967 | |
| 968 | |
| 969 | |
| 970 | |
| 971 | |
| 972 | |
| 973 | |
| 974 | |
| 975 | |
| 976 | endmodule |
| 977 | |
| 978 | |
| 979 | |
| 980 | |
| 981 | |
| 982 | |
| 983 | |
| 984 | |
| 985 | |
| 986 | |
| 987 | |
| 988 | |
| 989 | |
| 990 | // any PARAMS parms go into naming of macro |
| 991 | |
| 992 | module ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_4 ( |
| 993 | din, |
| 994 | en, |
| 995 | l1clk, |
| 996 | scan_in, |
| 997 | siclk, |
| 998 | soclk, |
| 999 | dout, |
| 1000 | scan_out); |
| 1001 | wire [3:0] fdin; |
| 1002 | wire [2:0] so; |
| 1003 | |
| 1004 | input [3:0] din; |
| 1005 | input en; |
| 1006 | input l1clk; |
| 1007 | input scan_in; |
| 1008 | |
| 1009 | |
| 1010 | input siclk; |
| 1011 | input soclk; |
| 1012 | |
| 1013 | output [3:0] dout; |
| 1014 | output scan_out; |
| 1015 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); |
| 1016 | |
| 1017 | |
| 1018 | |
| 1019 | |
| 1020 | |
| 1021 | |
| 1022 | dff #(4) d0_0 ( |
| 1023 | .l1clk(l1clk), |
| 1024 | .siclk(siclk), |
| 1025 | .soclk(soclk), |
| 1026 | .d(fdin[3:0]), |
| 1027 | .si({scan_in,so[2:0]}), |
| 1028 | .so({so[2:0],scan_out}), |
| 1029 | .q(dout[3:0]) |
| 1030 | ); |
| 1031 | |
| 1032 | |
| 1033 | |
| 1034 | |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | |
| 1041 | |
| 1042 | |
| 1043 | endmodule |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | |
| 1049 | |
| 1050 | |
| 1051 | |
| 1052 | |
| 1053 | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | // any PARAMS parms go into naming of macro |
| 1058 | |
| 1059 | module ncu_i2cbuf4_ctl_msff_ctl_macro__width_1 ( |
| 1060 | din, |
| 1061 | l1clk, |
| 1062 | scan_in, |
| 1063 | siclk, |
| 1064 | soclk, |
| 1065 | dout, |
| 1066 | scan_out); |
| 1067 | wire [0:0] fdin; |
| 1068 | |
| 1069 | input [0:0] din; |
| 1070 | input l1clk; |
| 1071 | input scan_in; |
| 1072 | |
| 1073 | |
| 1074 | input siclk; |
| 1075 | input soclk; |
| 1076 | |
| 1077 | output [0:0] dout; |
| 1078 | output scan_out; |
| 1079 | assign fdin[0:0] = din[0:0]; |
| 1080 | |
| 1081 | |
| 1082 | |
| 1083 | |
| 1084 | |
| 1085 | |
| 1086 | dff #(1) d0_0 ( |
| 1087 | .l1clk(l1clk), |
| 1088 | .siclk(siclk), |
| 1089 | .soclk(soclk), |
| 1090 | .d(fdin[0:0]), |
| 1091 | .si(scan_in), |
| 1092 | .so(scan_out), |
| 1093 | .q(dout[0:0]) |
| 1094 | ); |
| 1095 | |
| 1096 | |
| 1097 | |
| 1098 | |
| 1099 | |
| 1100 | |
| 1101 | |
| 1102 | |
| 1103 | |
| 1104 | |
| 1105 | |
| 1106 | |
| 1107 | endmodule |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | |
| 1114 | |
| 1115 | |
| 1116 | |
| 1117 | |
| 1118 | |
| 1119 | |
| 1120 | |
| 1121 | // any PARAMS parms go into naming of macro |
| 1122 | |
| 1123 | module ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_32 ( |
| 1124 | din, |
| 1125 | en, |
| 1126 | l1clk, |
| 1127 | scan_in, |
| 1128 | siclk, |
| 1129 | soclk, |
| 1130 | dout, |
| 1131 | scan_out); |
| 1132 | wire [31:0] fdin; |
| 1133 | wire [30:0] so; |
| 1134 | |
| 1135 | input [31:0] din; |
| 1136 | input en; |
| 1137 | input l1clk; |
| 1138 | input scan_in; |
| 1139 | |
| 1140 | |
| 1141 | input siclk; |
| 1142 | input soclk; |
| 1143 | |
| 1144 | output [31:0] dout; |
| 1145 | output scan_out; |
| 1146 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); |
| 1147 | |
| 1148 | |
| 1149 | |
| 1150 | |
| 1151 | |
| 1152 | |
| 1153 | dff #(32) d0_0 ( |
| 1154 | .l1clk(l1clk), |
| 1155 | .siclk(siclk), |
| 1156 | .soclk(soclk), |
| 1157 | .d(fdin[31:0]), |
| 1158 | .si({scan_in,so[30:0]}), |
| 1159 | .so({so[30:0],scan_out}), |
| 1160 | .q(dout[31:0]) |
| 1161 | ); |
| 1162 | |
| 1163 | |
| 1164 | |
| 1165 | |
| 1166 | |
| 1167 | |
| 1168 | |
| 1169 | |
| 1170 | |
| 1171 | |
| 1172 | |
| 1173 | |
| 1174 | endmodule |
| 1175 | |
| 1176 | |
| 1177 | |
| 1178 | |
| 1179 | |
| 1180 | |
| 1181 | |
| 1182 | |
| 1183 | |
| 1184 | |
| 1185 | |
| 1186 | |
| 1187 | |
| 1188 | // any PARAMS parms go into naming of macro |
| 1189 | |
| 1190 | module ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_128 ( |
| 1191 | din, |
| 1192 | en, |
| 1193 | l1clk, |
| 1194 | scan_in, |
| 1195 | siclk, |
| 1196 | soclk, |
| 1197 | dout, |
| 1198 | scan_out); |
| 1199 | wire [127:0] fdin; |
| 1200 | wire [126:0] so; |
| 1201 | |
| 1202 | input [127:0] din; |
| 1203 | input en; |
| 1204 | input l1clk; |
| 1205 | input scan_in; |
| 1206 | |
| 1207 | |
| 1208 | input siclk; |
| 1209 | input soclk; |
| 1210 | |
| 1211 | output [127:0] dout; |
| 1212 | output scan_out; |
| 1213 | assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}}); |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | dff #(128) d0_0 ( |
| 1221 | .l1clk(l1clk), |
| 1222 | .siclk(siclk), |
| 1223 | .soclk(soclk), |
| 1224 | .d(fdin[127:0]), |
| 1225 | .si({scan_in,so[126:0]}), |
| 1226 | .so({so[126:0],scan_out}), |
| 1227 | .q(dout[127:0]) |
| 1228 | ); |
| 1229 | |
| 1230 | |
| 1231 | |
| 1232 | |
| 1233 | |
| 1234 | |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | |
| 1239 | |
| 1240 | |
| 1241 | endmodule |
| 1242 | |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | |
| 1253 | |
| 1254 | |
| 1255 | // any PARAMS parms go into naming of macro |
| 1256 | |
| 1257 | module ncu_i2cbuf4_ctl_msff_ctl_macro__en_1__width_25 ( |
| 1258 | din, |
| 1259 | en, |
| 1260 | l1clk, |
| 1261 | scan_in, |
| 1262 | siclk, |
| 1263 | soclk, |
| 1264 | dout, |
| 1265 | scan_out); |
| 1266 | wire [24:0] fdin; |
| 1267 | wire [23:0] so; |
| 1268 | |
| 1269 | input [24:0] din; |
| 1270 | input en; |
| 1271 | input l1clk; |
| 1272 | input scan_in; |
| 1273 | |
| 1274 | |
| 1275 | input siclk; |
| 1276 | input soclk; |
| 1277 | |
| 1278 | output [24:0] dout; |
| 1279 | output scan_out; |
| 1280 | assign fdin[24:0] = (din[24:0] & {25{en}}) | (dout[24:0] & ~{25{en}}); |
| 1281 | |
| 1282 | |
| 1283 | |
| 1284 | |
| 1285 | |
| 1286 | |
| 1287 | dff #(25) d0_0 ( |
| 1288 | .l1clk(l1clk), |
| 1289 | .siclk(siclk), |
| 1290 | .soclk(soclk), |
| 1291 | .d(fdin[24:0]), |
| 1292 | .si({scan_in,so[23:0]}), |
| 1293 | .so({so[23:0],scan_out}), |
| 1294 | .q(dout[24:0]) |
| 1295 | ); |
| 1296 | |
| 1297 | |
| 1298 | |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | |
| 1303 | |
| 1304 | |
| 1305 | |
| 1306 | |
| 1307 | |
| 1308 | endmodule |
| 1309 | |
| 1310 | |
| 1311 | |
| 1312 | |
| 1313 | |
| 1314 | |
| 1315 | |
| 1316 | |
| 1317 | |
| 1318 | |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | // any PARAMS parms go into naming of macro |
| 1323 | |
| 1324 | module ncu_i2cbuf4_ctl_l1clkhdr_ctl_macro ( |
| 1325 | l2clk, |
| 1326 | l1en, |
| 1327 | pce_ov, |
| 1328 | stop, |
| 1329 | se, |
| 1330 | l1clk); |
| 1331 | |
| 1332 | |
| 1333 | input l2clk; |
| 1334 | input l1en; |
| 1335 | input pce_ov; |
| 1336 | input stop; |
| 1337 | input se; |
| 1338 | output l1clk; |
| 1339 | |
| 1340 | |
| 1341 | |
| 1342 | |
| 1343 | |
| 1344 | cl_sc1_l1hdr_8x c_0 ( |
| 1345 | |
| 1346 | |
| 1347 | .l2clk(l2clk), |
| 1348 | .pce(l1en), |
| 1349 | .l1clk(l1clk), |
| 1350 | .se(se), |
| 1351 | .pce_ov(pce_ov), |
| 1352 | .stop(stop) |
| 1353 | ); |
| 1354 | |
| 1355 | |
| 1356 | |
| 1357 | endmodule |
| 1358 | |
| 1359 | |
| 1360 | |
| 1361 | |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | |