| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ncu_ssisif_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define RF_RDEN_OFFSTATE 1'b1 |
| 36 | |
| 37 | //==================================== |
| 38 | `define NCU_INTMANRF_DEPTH 128 |
| 39 | `define NCU_INTMANRF_DATAWIDTH 16 |
| 40 | `define NCU_INTMANRF_ADDRWIDTH 7 |
| 41 | //==================================== |
| 42 | |
| 43 | //==================================== |
| 44 | `define NCU_MONDORF_DEPTH 64 |
| 45 | `define NCU_MONDORF_DATAWIDTH 72 |
| 46 | `define NCU_MONDORF_ADDRWIDTH 6 |
| 47 | //==================================== |
| 48 | |
| 49 | //==================================== |
| 50 | `define NCU_CPUBUFRF_DEPTH 32 |
| 51 | `define NCU_CPUBUFRF_DATAWIDTH 144 |
| 52 | `define NCU_CPUBUFRF_ADDRWIDTH 5 |
| 53 | //==================================== |
| 54 | |
| 55 | //==================================== |
| 56 | `define NCU_IOBUFRF_DEPTH 32 |
| 57 | `define NCU_IOBUFRF_DATAWIDTH 144 |
| 58 | `define NCU_IOBUFRF_ADDRWIDTH 5 |
| 59 | //==================================== |
| 60 | |
| 61 | //==================================== |
| 62 | `define NCU_IOBUF1RF_DEPTH 32 |
| 63 | `define NCU_IOBUF1RF_DATAWIDTH 32 |
| 64 | `define NCU_IOBUF1RF_ADDRWIDTH 5 |
| 65 | //==================================== |
| 66 | |
| 67 | //==================================== |
| 68 | `define NCU_INTBUFRF_DEPTH 32 |
| 69 | `define NCU_INTBUFRF_DATAWIDTH 144 |
| 70 | `define NCU_INTBUFRF_ADDRWIDTH 5 |
| 71 | //==================================== |
| 72 | |
| 73 | //== fix me : need to remove when warm // |
| 74 | //== becomes available // |
| 75 | `define WMR_LENGTH 10'd999 |
| 76 | `define WMR_LENGTH_P1 10'd1000 |
| 77 | |
| 78 | //// NCU CSR_MAN address 80_0000_xxxx //// |
| 79 | `define NCU_CSR_MAN 16'h0000 |
| 80 | `define NCU_CREG_INTMAN 16'h0000 |
| 81 | //`define NCU_CREG_INTVECDISP 16'h0800 |
| 82 | `define NCU_CREG_MONDOINVEC 16'h0a00 |
| 83 | `define NCU_CREG_SERNUM 16'h1000 |
| 84 | `define NCU_CREG_FUSESTAT 16'h1008 |
| 85 | `define NCU_CREG_COREAVAIL 16'h1010 |
| 86 | `define NCU_CREG_BANKAVAIL 16'h1018 |
| 87 | `define NCU_CREG_BANK_ENABLE 16'h1020 |
| 88 | `define NCU_CREG_BANK_ENABLE_STATUS 16'h1028 |
| 89 | `define NCU_CREG_L2_HASH_ENABLE 16'h1030 |
| 90 | `define NCU_CREG_L2_HASH_ENABLE_STATUS 16'h1038 |
| 91 | |
| 92 | |
| 93 | `define NCU_CREG_MEM32_BASE 16'h2000 |
| 94 | `define NCU_CREG_MEM32_MASK 16'h2008 |
| 95 | `define NCU_CREG_MEM64_BASE 16'h2010 |
| 96 | `define NCU_CREG_MEM64_MASK 16'h2018 |
| 97 | `define NCU_CREG_IOCON_BASE 16'h2020 |
| 98 | `define NCU_CREG_IOCON_MASK 16'h2028 |
| 99 | `define NCU_CREG_MMUFSH 16'h2030 |
| 100 | |
| 101 | `define NCU_CREG_ESR 16'h3000 |
| 102 | `define NCU_CREG_ELE 16'h3008 |
| 103 | `define NCU_CREG_EIE 16'h3010 |
| 104 | `define NCU_CREG_EJR 16'h3018 |
| 105 | `define NCU_CREG_FEE 16'h3020 |
| 106 | `define NCU_CREG_PER 16'h3028 |
| 107 | `define NCU_CREG_SIISYN 16'h3030 |
| 108 | `define NCU_CREG_NCUSYN 16'h3038 |
| 109 | `define NCU_CREG_SCKSEL 16'h3040 |
| 110 | `define NCU_CREG_DBGTRIG_EN 16'h4000 |
| 111 | |
| 112 | //// NUC CSR_MONDO address 80_0004_xxxx //// |
| 113 | `define NCU_CSR_MONDO 16'h0004 |
| 114 | `define NCU_CREG_MDATA0 16'h0000 |
| 115 | `define NCU_CREG_MDATA1 16'h0200 |
| 116 | `define NCU_CREG_MDATA0_ALIAS 16'h0400 |
| 117 | `define NCU_CREG_MDATA1_ALIAS 16'h0600 |
| 118 | `define NCU_CREG_MBUSY 16'h0800 |
| 119 | `define NCU_CREG_MBUSY_ALIAS 16'h0a00 |
| 120 | |
| 121 | |
| 122 | |
| 123 | // ASI shared reg 90_xxxx_xxxx// |
| 124 | `define NCU_ASI_A_HIT 10'h104 // 6-bits cpuid and thread id are "x" |
| 125 | `define NCU_ASI_B_HIT 10'h1CC // 6-bits cpuid and thread id are "x" |
| 126 | `define NCU_ASI_C_HIT 10'h114 // 6-bits cpuid and thread id are "x" |
| 127 | `define NCU_ASI_COREAVAIL 16'h0000 |
| 128 | `define NCU_ASI_CORE_ENABLE_STATUS 16'h0010 |
| 129 | `define NCU_ASI_CORE_ENABLE 16'h0020 |
| 130 | `define NCU_ASI_XIR_STEERING 16'h0030 |
| 131 | `define NCU_ASI_CORE_RUNNINGRW 16'h0050 |
| 132 | `define NCU_ASI_CORE_RUNNING_STATUS 16'h0058 |
| 133 | `define NCU_ASI_CORE_RUNNING_W1S 16'h0060 |
| 134 | `define NCU_ASI_CORE_RUNNING_W1C 16'h0068 |
| 135 | `define NCU_ASI_INTVECDISP 16'h0000 |
| 136 | `define NCU_ASI_ERR_STR 16'h1000 |
| 137 | `define NCU_ASI_WMR_VEC_MASK 16'h0018 |
| 138 | `define NCU_ASI_CMP_TICK_ENABLE 16'h0038 |
| 139 | |
| 140 | |
| 141 | //// UCB packet type //// |
| 142 | `define UCB_READ_NACK 4'b0000 // ack/nack types |
| 143 | `define UCB_READ_ACK 4'b0001 |
| 144 | `define UCB_WRITE_ACK 4'b0010 |
| 145 | `define UCB_IFILL_ACK 4'b0011 |
| 146 | `define UCB_IFILL_NACK 4'b0111 |
| 147 | |
| 148 | `define UCB_READ_REQ 4'b0100 // req types |
| 149 | `define UCB_WRITE_REQ 4'b0101 |
| 150 | `define UCB_IFILL_REQ 4'b0110 |
| 151 | |
| 152 | `define UCB_INT 4'b1000 // plain interrupt |
| 153 | `define UCB_INT_VEC 4'b1100 // interrupt with vector |
| 154 | `define UCB_INT_SOC_UE 4'b1001 // soc interrup ue |
| 155 | `define UCB_INT_SOC_CE 4'b1010 // soc interrup ce |
| 156 | `define UCB_RESET_VEC 4'b0101 // reset with vector |
| 157 | `define UCB_IDLE_VEC 4'b1110 // idle with vector |
| 158 | `define UCB_RESUME_VEC 4'b1111 // resume with vector |
| 159 | |
| 160 | `define UCB_INT_SOC 4'b1101 // soc interrup ce |
| 161 | |
| 162 | |
| 163 | //// PCX packet type //// |
| 164 | `define PCX_LOAD_RQ 5'b00000 |
| 165 | `define PCX_IMISS_RQ 5'b10000 |
| 166 | `define PCX_STORE_RQ 5'b00001 |
| 167 | `define PCX_FWD_RQs 5'b01101 |
| 168 | `define PCX_FWD_RPYs 5'b01110 |
| 169 | |
| 170 | //// CPX packet type //// |
| 171 | //`define CPX_LOAD_RET 4'b0000 |
| 172 | `define CPX_LOAD_RET 4'b1000 |
| 173 | `define CPX_ST_ACK 4'b0100 |
| 174 | //`define CPX_IFILL_RET 4'b0001 |
| 175 | `define CPX_IFILL_RET 4'b1001 |
| 176 | `define CPX_INT_RET 4'b0111 |
| 177 | `define CPX_INT_SOC 4'b1101 |
| 178 | //`define CPX_FWD_RQ_RET 4'b1010 |
| 179 | //`define CPX_FWD_RPY_RET 4'b1011 |
| 180 | |
| 181 | |
| 182 | |
| 183 | |
| 184 | //// Global CSR decode //// |
| 185 | `define NCU_CSR 8'h80 |
| 186 | `define NIU_CSR 8'h81 |
| 187 | //`define RNG_CSR 8'h82 |
| 188 | `define DBG1_CSR 8'h86 |
| 189 | `define CCU_CSR 8'h83 |
| 190 | `define MCU_CSR 8'h84 |
| 191 | `define TCU_CSR 8'h85 |
| 192 | `define DMU_CSR 8'h88 |
| 193 | `define RCU_CSR 8'h89 |
| 194 | `define NCU_ASI 8'h90 |
| 195 | /////8'h91 ~ 9F reserved |
| 196 | /////8'hA0 ~ BF L2 CSR//// |
| 197 | `define DMU_PIO 4'hC // C0 ~ CF |
| 198 | /////8'hB0 ~ FE reserved |
| 199 | `define SSI_CSR 8'hFF |
| 200 | |
| 201 | |
| 202 | //// NCU_SSI //// |
| 203 | `define SSI_ADDR 12'hFF_F |
| 204 | `define SSI_ADDR_TIMEOUT_REG 40'hFF_0001_0088 |
| 205 | `define SSI_ADDR_LOG_REG 40'hFF_0000_0018 |
| 206 | |
| 207 | `define IF_IDLE 2'b00 |
| 208 | `define IF_ACPT 2'b01 |
| 209 | `define IF_DROP 2'b10 |
| 210 | |
| 211 | `define SSI_IDLE 3'b000 |
| 212 | `define SSI_REQ 3'b001 |
| 213 | `define SSI_WDATA 3'b011 |
| 214 | `define SSI_REQ_PAR 3'b101 |
| 215 | `define SSI_ACK 3'b111 |
| 216 | `define SSI_RDATA 3'b110 |
| 217 | `define SSI_ACK_PAR 3'b010 |
| 218 | |
| 219 | |
| 220 | |
| 221 | |
| 222 | |
| 223 | |
| 224 | |
| 225 | |
| 226 | |
| 227 | module ncu_ssisif_ctl ( |
| 228 | iol2clk, |
| 229 | tcu_pce_ov, |
| 230 | tcu_clk_stop, |
| 231 | tcu_scan_en, |
| 232 | tcu_aclk, |
| 233 | tcu_bclk, |
| 234 | scan_in, |
| 235 | scan_out, |
| 236 | ucbif_sif_timeval, |
| 237 | ucbif_sif_timeout_accpt, |
| 238 | ncu_scksel, |
| 239 | sif_ucbif_timeout, |
| 240 | sif_ucbif_timeout_rw, |
| 241 | sif_ucbif_par_err, |
| 242 | sif_ucbif_busy, |
| 243 | ucbif_sif_vld, |
| 244 | ucbif_sif_rw, |
| 245 | ucbif_sif_size, |
| 246 | ucbif_sif_addr, |
| 247 | ucbif_sif_wdata, |
| 248 | ucbif_sif_rdata_accpt, |
| 249 | sif_ucbif_rdata, |
| 250 | sif_ucbif_rdata_vld, |
| 251 | io_jbi_ssi_miso, |
| 252 | jbi_io_ssi_mosi, |
| 253 | jbi_io_ssi_sck, |
| 254 | tcu_sck_bypass, |
| 255 | sck_cntexp) ; |
| 256 | wire [2:0] ssi_sm; |
| 257 | wire sck_posedge_d1; |
| 258 | wire req_info_en; |
| 259 | wire [63:0] next_wdata; |
| 260 | wire wdata_en; |
| 261 | wire [2:0] next_wdata_sel; |
| 262 | wire wdata_sel_en; |
| 263 | wire [1:0] next_size; |
| 264 | wire size_en; |
| 265 | wire next_rw; |
| 266 | wire rw_en; |
| 267 | wire u_dffrle_rw_scanin; |
| 268 | wire u_dffrle_rw_scanout; |
| 269 | wire rw; |
| 270 | wire l1clk; |
| 271 | wire u_dffrle_size_scanin; |
| 272 | wire u_dffrle_size_scanout; |
| 273 | wire [1:0] size; |
| 274 | wire u_dffrle_wdata_scanin; |
| 275 | wire u_dffrle_wdata_scanout; |
| 276 | wire [63:0] wdata; |
| 277 | wire u_dffrle_wdata_sel_scanin; |
| 278 | wire u_dffrle_wdata_sel_scanout; |
| 279 | wire [2:0] wdata_sel; |
| 280 | wire u_dffrle_sif_ucbif_rdata_scanin; |
| 281 | wire u_dffrle_sif_ucbif_rdata_scanout; |
| 282 | wire sif_ucbif_rdata_en; |
| 283 | wire n_par; |
| 284 | wire par_rst_l; |
| 285 | wire u_dffrle_par_scanin; |
| 286 | wire u_dffrle_par_scanout; |
| 287 | wire par; |
| 288 | wire par_en; |
| 289 | wire [23:0] n_timeout_cnt; |
| 290 | wire timeout_cnt_rst_l; |
| 291 | wire [23:0] next_timeout_cnt; |
| 292 | wire u_dffrle_timeout_cnt_scanin; |
| 293 | wire u_dffrle_timeout_cnt_scanout; |
| 294 | wire [23:0] timeout_cnt; |
| 295 | wire sck_posedge; |
| 296 | wire timeout_cnt_en; |
| 297 | wire mosi_shreg0_s_in; |
| 298 | wire mosi_shreg1_s_in; |
| 299 | wire [7:0] mosi_shreg0_p_out; |
| 300 | wire mosi_shreg2_s_in; |
| 301 | wire [7:0] mosi_shreg1_p_out; |
| 302 | wire mosi_shreg3_s_in; |
| 303 | wire [7:0] mosi_shreg2_p_out; |
| 304 | wire mosi_shreg4_s_in; |
| 305 | wire [7:0] mosi_shreg3_p_out; |
| 306 | wire mosi_shreg5_s_in; |
| 307 | wire [7:0] mosi_shreg4_p_out; |
| 308 | wire mosi_shreg6_s_in; |
| 309 | wire [7:0] mosi_shreg5_p_out; |
| 310 | wire mosi_shreg7_s_in; |
| 311 | wire [7:0] mosi_shreg6_p_out; |
| 312 | wire [7:0] mosi_shreg0_p_in; |
| 313 | wire [63:0] mosi_shreg_din; |
| 314 | wire [7:0] mosi_shreg1_p_in; |
| 315 | wire [7:0] mosi_shreg2_p_in; |
| 316 | wire [7:0] mosi_shreg3_p_in; |
| 317 | wire [7:0] mosi_shreg4_p_in; |
| 318 | wire [7:0] mosi_shreg5_p_in; |
| 319 | wire [7:0] mosi_shreg6_p_in; |
| 320 | wire [7:0] mosi_shreg7_p_in; |
| 321 | wire u_mosi_shreg0_scanin; |
| 322 | wire u_mosi_shreg0_scanout; |
| 323 | wire mosi_shift_n; |
| 324 | wire mosi_load_n; |
| 325 | wire u_mosi_shreg1_scanin; |
| 326 | wire u_mosi_shreg1_scanout; |
| 327 | wire u_mosi_shreg2_scanin; |
| 328 | wire u_mosi_shreg2_scanout; |
| 329 | wire u_mosi_shreg3_scanin; |
| 330 | wire u_mosi_shreg3_scanout; |
| 331 | wire u_mosi_shreg4_scanin; |
| 332 | wire u_mosi_shreg4_scanout; |
| 333 | wire u_mosi_shreg5_scanin; |
| 334 | wire u_mosi_shreg5_scanout; |
| 335 | wire u_mosi_shreg6_scanin; |
| 336 | wire u_mosi_shreg6_scanout; |
| 337 | wire [7:0] mosi_shreg7_p_out; |
| 338 | wire u_mosi_shreg7_scanin; |
| 339 | wire u_mosi_shreg7_scanout; |
| 340 | wire sck_cyc_cnt_rst_l; |
| 341 | wire [6:0] next_sck_cyc_cnt; |
| 342 | wire sck_posedge_d4; |
| 343 | wire [6:0] sck_cyc_cnt; |
| 344 | wire [30:0] ssi_req; |
| 345 | wire sck_posedge_d2; |
| 346 | wire io_jbi_ssi_miso_ff; |
| 347 | wire rdata_shift_n; |
| 348 | wire [63:0] srg64p_out_next; |
| 349 | wire [63:0] srg64p_out; |
| 350 | wire [63:0] rdata_shreg; |
| 351 | wire srg64p_out_ff_scanin; |
| 352 | wire srg64p_out_ff_scanout; |
| 353 | wire next_sif_ucbif_rdata_vld; |
| 354 | wire ack_par_rdy; |
| 355 | wire sif_ucbif_timeout_rst_l; |
| 356 | wire next_sif_ucbif_timeout; |
| 357 | wire next_sif_ucbif_par_err; |
| 358 | wire [2:0] cntr_n; |
| 359 | wire [2:0] cntr; |
| 360 | wire cntr_ff_scanin; |
| 361 | wire cntr_ff_scanout; |
| 362 | wire u_dffrl_async_ctu_jbi_ssiclk_ff_scanin; |
| 363 | wire u_dffrl_async_ctu_jbi_ssiclk_ff_scanout; |
| 364 | wire ctu_jbi_ssiclk_ff; |
| 365 | wire next_jbi_io_ssi_sck; |
| 366 | wire u_dffrl_async_jbi_io_ssi_sck_scanin; |
| 367 | wire u_dffrl_async_jbi_io_ssi_sck_scanout; |
| 368 | wire u_dff_io_jbi_ssi_miso_ff_scanin; |
| 369 | wire u_dff_io_jbi_ssi_miso_ff_scanout; |
| 370 | wire sck_posedge_ff_scanin; |
| 371 | wire sck_posedge_ff_scanout; |
| 372 | wire sck_posedge_d1_ff_scanin; |
| 373 | wire sck_posedge_d1_ff_scanout; |
| 374 | wire sck_posedge_d2_ff_scanin; |
| 375 | wire sck_posedge_d2_ff_scanout; |
| 376 | wire sck_posedge_d3_ff_scanin; |
| 377 | wire sck_posedge_d3_ff_scanout; |
| 378 | wire sck_posedge_d3; |
| 379 | wire sck_posedge_d4_ff_scanin; |
| 380 | wire sck_posedge_d4_ff_scanout; |
| 381 | wire [2:0] n_ssi_sm; |
| 382 | wire ssi_sm_rst_l; |
| 383 | wire u_dffrl_ssi_sm_scanin; |
| 384 | wire u_dffrl_ssi_sm_scanout; |
| 385 | wire [6:0] n_sck_cyc_cnt; |
| 386 | wire u_dffrl_sck_cyc_cnt_scanin; |
| 387 | wire u_dffrl_sck_cyc_cnt_scanout; |
| 388 | wire u_dffrl_sif_ucbif_rdata_vld_scanin; |
| 389 | wire u_dffrl_sif_ucbif_rdata_vld_scanout; |
| 390 | wire n_sif_ucbif_timeout; |
| 391 | wire u_dffrl_sif_ucbif_timeout_scanin; |
| 392 | wire u_dffrl_sif_ucbif_timeout_scanout; |
| 393 | wire u_dffrl_sif_ucbif_par_err_scanin; |
| 394 | wire u_dffrl_sif_ucbif_par_err_scanout; |
| 395 | wire u_dffrl_jbi_io_ssi_mosi_scanin; |
| 396 | wire u_dffrl_jbi_io_ssi_mosi_scanout; |
| 397 | wire sck_cnt_ff_scanin; |
| 398 | wire sck_cnt_ff_scanout; |
| 399 | wire [17:0] sck_cnt; |
| 400 | wire [17:0] next_sck_cnt; |
| 401 | wire sck_bypass_ff_scanin; |
| 402 | wire sck_bypass_ff_scanout; |
| 403 | wire sck_bypass; |
| 404 | wire spares_scanin; |
| 405 | wire spares_scanout; |
| 406 | wire siclk; |
| 407 | wire soclk; |
| 408 | wire se; |
| 409 | wire pce_ov; |
| 410 | wire stop; |
| 411 | |
| 412 | //////////////////////////////////////////////////////////////////////// |
| 413 | // Interface signal list declarations |
| 414 | //////////////////////////////////////////////////////////////////////// |
| 415 | input iol2clk; |
| 416 | input tcu_pce_ov; |
| 417 | input tcu_clk_stop; |
| 418 | input tcu_scan_en; |
| 419 | input tcu_aclk; |
| 420 | input tcu_bclk; |
| 421 | input scan_in; |
| 422 | output scan_out; |
| 423 | |
| 424 | // CSR |
| 425 | input [23:0] ucbif_sif_timeval; |
| 426 | input ucbif_sif_timeout_accpt; |
| 427 | input [1:0] ncu_scksel; |
| 428 | output sif_ucbif_timeout; //assert until accepted |
| 429 | output sif_ucbif_timeout_rw; //timeout of a rd or wr |
| 430 | output sif_ucbif_par_err; //for rd par err, assert until accepted |
| 431 | |
| 432 | //issue SSI command |
| 433 | output sif_ucbif_busy; |
| 434 | input ucbif_sif_vld; |
| 435 | input ucbif_sif_rw; //instr w/o data will have no dlen asserted |
| 436 | input [1:0] ucbif_sif_size; |
| 437 | input [27:0] ucbif_sif_addr; |
| 438 | input [63:0] ucbif_sif_wdata; |
| 439 | |
| 440 | //read return data |
| 441 | input ucbif_sif_rdata_accpt; |
| 442 | output [63:0] sif_ucbif_rdata; |
| 443 | output sif_ucbif_rdata_vld; |
| 444 | |
| 445 | // SSI bus signals |
| 446 | input io_jbi_ssi_miso; |
| 447 | output jbi_io_ssi_mosi; |
| 448 | output jbi_io_ssi_sck; |
| 449 | input tcu_sck_bypass; |
| 450 | output sck_cntexp; |
| 451 | |
| 452 | //////////////////////////////////////////////////////////////////////// |
| 453 | // Interface signal type declarations |
| 454 | //////////////////////////////////////////////////////////////////////// |
| 455 | |
| 456 | //////////////////////////////////////////////////////////////////////// |
| 457 | // Local signal declarations |
| 458 | //////////////////////////////////////////////////////////////////////// |
| 459 | // |
| 460 | // Code start here |
| 461 | // |
| 462 | //parameter SSI_IDLE = 3'b000, |
| 463 | //SSI_REQ = 3'b001, |
| 464 | //SSI_WDATA = 3'b011, |
| 465 | //SSI_REQ_PAR = 3'b101, |
| 466 | //SSI_ACK = 3'b111, |
| 467 | //SSI_RDATA = 3'b110, |
| 468 | //SSI_ACK_PAR = 3'b010; |
| 469 | |
| 470 | reg [2:0] next_ssi_sm; |
| 471 | reg next_par; |
| 472 | |
| 473 | |
| 474 | reg [63:0] next_sif_ucbif_rdata; |
| 475 | reg next_jbi_io_ssi_mosi; |
| 476 | |
| 477 | |
| 478 | |
| 479 | |
| 480 | reg mosi_wdata_bit; |
| 481 | |
| 482 | |
| 483 | //******************************************************************************* |
| 484 | // Accept new request |
| 485 | //******************************************************************************* |
| 486 | |
| 487 | assign sif_ucbif_busy = ~sck_cntexp | ((ssi_sm[2:0]!=`SSI_IDLE) | |
| 488 | sif_ucbif_rdata_vld | |
| 489 | sif_ucbif_timeout | |
| 490 | ~sck_posedge_d1) ; |
| 491 | |
| 492 | assign req_info_en = ucbif_sif_vld & ~sif_ucbif_busy; |
| 493 | |
| 494 | |
| 495 | // Store command info |
| 496 | assign next_wdata[63:0] = ucbif_sif_wdata[63:0]; |
| 497 | assign wdata_en = req_info_en; |
| 498 | |
| 499 | assign next_wdata_sel[2:0] = ucbif_sif_addr[2:0]; |
| 500 | assign wdata_sel_en = req_info_en; |
| 501 | |
| 502 | assign next_size[1:0] = ucbif_sif_size[1:0]; |
| 503 | assign size_en = req_info_en; |
| 504 | |
| 505 | assign next_rw = ucbif_sif_rw; |
| 506 | assign rw_en = req_info_en; |
| 507 | |
| 508 | //******************************************************************************* |
| 509 | // DFFRE Instantiations |
| 510 | //******************************************************************************* |
| 511 | |
| 512 | ncu_ssisif_ctl_msff_ctl_macro__en_1__width_1 u_dffrle_rw |
| 513 | ( |
| 514 | .scan_in(u_dffrle_rw_scanin), |
| 515 | .scan_out(u_dffrle_rw_scanout), |
| 516 | .dout (rw), |
| 517 | .l1clk (l1clk), |
| 518 | .en (rw_en), |
| 519 | .din (next_rw), |
| 520 | .siclk(siclk), |
| 521 | .soclk(soclk) |
| 522 | ); |
| 523 | |
| 524 | ncu_ssisif_ctl_msff_ctl_macro__en_1__width_2 u_dffrle_size |
| 525 | ( |
| 526 | .scan_in(u_dffrle_size_scanin), |
| 527 | .scan_out(u_dffrle_size_scanout), |
| 528 | .dout (size[1:0]), |
| 529 | .l1clk (l1clk), |
| 530 | .en (size_en), |
| 531 | .din (next_size[1:0]), |
| 532 | .siclk(siclk), |
| 533 | .soclk(soclk) |
| 534 | ); |
| 535 | |
| 536 | ncu_ssisif_ctl_msff_ctl_macro__en_1__width_64 u_dffrle_wdata |
| 537 | ( |
| 538 | .scan_in(u_dffrle_wdata_scanin), |
| 539 | .scan_out(u_dffrle_wdata_scanout), |
| 540 | .dout (wdata[63:0]), |
| 541 | .l1clk (l1clk), |
| 542 | .en (wdata_en), |
| 543 | .din (next_wdata[63:0]), |
| 544 | .siclk(siclk), |
| 545 | .soclk(soclk) |
| 546 | ); |
| 547 | |
| 548 | ncu_ssisif_ctl_msff_ctl_macro__en_1__width_3 u_dffrle_wdata_sel |
| 549 | ( |
| 550 | .scan_in(u_dffrle_wdata_sel_scanin), |
| 551 | .scan_out(u_dffrle_wdata_sel_scanout), |
| 552 | .dout (wdata_sel[2:0]), |
| 553 | .l1clk (l1clk), |
| 554 | .en (wdata_sel_en), |
| 555 | .din (next_wdata_sel[2:0]), |
| 556 | .siclk(siclk), |
| 557 | .soclk(soclk) |
| 558 | ); |
| 559 | |
| 560 | ncu_ssisif_ctl_msff_ctl_macro__en_1__width_64 u_dffrle_sif_ucbif_rdata |
| 561 | ( |
| 562 | .scan_in(u_dffrle_sif_ucbif_rdata_scanin), |
| 563 | .scan_out(u_dffrle_sif_ucbif_rdata_scanout), |
| 564 | .dout (sif_ucbif_rdata[63:0]), |
| 565 | .l1clk (l1clk), |
| 566 | .en (sif_ucbif_rdata_en), |
| 567 | .din (next_sif_ucbif_rdata[63:0]), |
| 568 | .siclk(siclk), |
| 569 | .soclk(soclk) |
| 570 | ); |
| 571 | |
| 572 | assign n_par = par_rst_l ? next_par : 1'b0 ; |
| 573 | ncu_ssisif_ctl_msff_ctl_macro__en_1__width_1 u_dffrle_par |
| 574 | ( |
| 575 | .scan_in(u_dffrle_par_scanin), |
| 576 | .scan_out(u_dffrle_par_scanout), |
| 577 | .dout (par), |
| 578 | .l1clk (l1clk), |
| 579 | .en (par_en|~par_rst_l), |
| 580 | .din (n_par), |
| 581 | .siclk(siclk), |
| 582 | .soclk(soclk) |
| 583 | ); |
| 584 | |
| 585 | assign n_timeout_cnt[23:0] = timeout_cnt_rst_l ? next_timeout_cnt[23:0] : 24'b0 ; |
| 586 | ncu_ssisif_ctl_msff_ctl_macro__en_1__width_24 u_dffrle_timeout_cnt |
| 587 | ( |
| 588 | .scan_in(u_dffrle_timeout_cnt_scanin), |
| 589 | .scan_out(u_dffrle_timeout_cnt_scanout), |
| 590 | .dout (timeout_cnt[23:0]), |
| 591 | .l1clk (l1clk), |
| 592 | .en ((sck_posedge&timeout_cnt_en)|~timeout_cnt_rst_l), |
| 593 | .din (n_timeout_cnt[23:0]), |
| 594 | .siclk(siclk), |
| 595 | .soclk(soclk) |
| 596 | ); |
| 597 | |
| 598 | //------------------ |
| 599 | // Shift Registers |
| 600 | //------------------ |
| 601 | |
| 602 | assign mosi_shreg0_s_in = 1'b0; |
| 603 | assign mosi_shreg1_s_in = mosi_shreg0_p_out[7]; |
| 604 | assign mosi_shreg2_s_in = mosi_shreg1_p_out[7]; |
| 605 | assign mosi_shreg3_s_in = mosi_shreg2_p_out[7]; |
| 606 | assign mosi_shreg4_s_in = mosi_shreg3_p_out[7]; |
| 607 | assign mosi_shreg5_s_in = mosi_shreg4_p_out[7]; |
| 608 | assign mosi_shreg6_s_in = mosi_shreg5_p_out[7]; |
| 609 | assign mosi_shreg7_s_in = mosi_shreg6_p_out[7]; |
| 610 | |
| 611 | assign mosi_shreg0_p_in[7:0] = mosi_shreg_din[ 7: 0]; |
| 612 | assign mosi_shreg1_p_in[7:0] = mosi_shreg_din[15: 8]; |
| 613 | assign mosi_shreg2_p_in[7:0] = mosi_shreg_din[23:16]; |
| 614 | assign mosi_shreg3_p_in[7:0] = mosi_shreg_din[31:24]; |
| 615 | assign mosi_shreg4_p_in[7:0] = mosi_shreg_din[39:32]; |
| 616 | assign mosi_shreg5_p_in[7:0] = mosi_shreg_din[47:40]; |
| 617 | assign mosi_shreg6_p_in[7:0] = mosi_shreg_din[55:48]; |
| 618 | assign mosi_shreg7_p_in[7:0] = mosi_shreg_din[63:56]; |
| 619 | |
| 620 | |
| 621 | //DW03_shftreg #(8) u_mosi_shreg0 (/*AUTOINST*/ |
| 622 | ncu_ssisrg8_ctl u_mosi_shreg0 (/*AUTOINST*/ |
| 623 | // Outputs |
| 624 | .p_out (mosi_shreg0_p_out[7:0]), // Templated |
| 625 | // Inputs |
| 626 | .scan_in(u_mosi_shreg0_scanin), |
| 627 | .scan_out(u_mosi_shreg0_scanout), |
| 628 | .iol2clk (iol2clk), |
| 629 | .tcu_pce_ov (tcu_pce_ov), |
| 630 | .tcu_clk_stop (tcu_clk_stop), |
| 631 | .tcu_scan_en (tcu_scan_en), |
| 632 | .tcu_aclk (tcu_aclk), |
| 633 | .tcu_bclk (tcu_bclk), |
| 634 | .s_in (mosi_shreg0_s_in), // Templated |
| 635 | .p_in (mosi_shreg0_p_in[7:0]), // Templated |
| 636 | .shift_n(mosi_shift_n), // Templated |
| 637 | .load_n(mosi_load_n)); // Templated |
| 638 | ncu_ssisrg8_ctl u_mosi_shreg1 (/*AUTOINST*/ |
| 639 | // Outputs |
| 640 | .p_out (mosi_shreg1_p_out[7:0]), // Templated |
| 641 | // Inputs |
| 642 | .scan_in(u_mosi_shreg1_scanin), |
| 643 | .scan_out(u_mosi_shreg1_scanout), |
| 644 | .iol2clk (iol2clk), |
| 645 | .tcu_pce_ov (tcu_pce_ov), |
| 646 | .tcu_clk_stop (tcu_clk_stop), |
| 647 | .tcu_scan_en (tcu_scan_en), |
| 648 | .tcu_aclk (tcu_aclk), |
| 649 | .tcu_bclk (tcu_bclk), |
| 650 | .s_in (mosi_shreg1_s_in), // Templated |
| 651 | .p_in (mosi_shreg1_p_in[7:0]), // Templated |
| 652 | .shift_n(mosi_shift_n), // Templated |
| 653 | .load_n(mosi_load_n)); // Templated |
| 654 | ncu_ssisrg8_ctl u_mosi_shreg2 (/*AUTOINST*/ |
| 655 | // Outputs |
| 656 | .p_out (mosi_shreg2_p_out[7:0]), // Templated |
| 657 | // Inputs |
| 658 | .scan_in(u_mosi_shreg2_scanin), |
| 659 | .scan_out(u_mosi_shreg2_scanout), |
| 660 | .iol2clk (iol2clk), |
| 661 | .tcu_pce_ov (tcu_pce_ov), |
| 662 | .tcu_clk_stop (tcu_clk_stop), |
| 663 | .tcu_scan_en (tcu_scan_en), |
| 664 | .tcu_aclk (tcu_aclk), |
| 665 | .tcu_bclk (tcu_bclk), |
| 666 | .s_in (mosi_shreg2_s_in), // Templated |
| 667 | .p_in (mosi_shreg2_p_in[7:0]), // Templated |
| 668 | .shift_n(mosi_shift_n), // Templated |
| 669 | .load_n(mosi_load_n)); // Templated |
| 670 | ncu_ssisrg8_ctl u_mosi_shreg3 (/*AUTOINST*/ |
| 671 | // Outputs |
| 672 | .p_out (mosi_shreg3_p_out[7:0]), // Templated |
| 673 | // Inputs |
| 674 | .scan_in(u_mosi_shreg3_scanin), |
| 675 | .scan_out(u_mosi_shreg3_scanout), |
| 676 | .iol2clk (iol2clk), |
| 677 | .tcu_pce_ov (tcu_pce_ov), |
| 678 | .tcu_clk_stop (tcu_clk_stop), |
| 679 | .tcu_scan_en (tcu_scan_en), |
| 680 | .tcu_aclk (tcu_aclk), |
| 681 | .tcu_bclk (tcu_bclk), |
| 682 | .s_in (mosi_shreg3_s_in), // Templated |
| 683 | .p_in (mosi_shreg3_p_in[7:0]), // Templated |
| 684 | .shift_n(mosi_shift_n), // Templated |
| 685 | .load_n(mosi_load_n)); // Templated |
| 686 | ncu_ssisrg8_ctl u_mosi_shreg4 (/*AUTOINST*/ |
| 687 | // Outputs |
| 688 | .p_out (mosi_shreg4_p_out[7:0]), // Templated |
| 689 | // Inputs |
| 690 | .scan_in(u_mosi_shreg4_scanin), |
| 691 | .scan_out(u_mosi_shreg4_scanout), |
| 692 | .iol2clk (iol2clk), |
| 693 | .tcu_pce_ov (tcu_pce_ov), |
| 694 | .tcu_clk_stop (tcu_clk_stop), |
| 695 | .tcu_scan_en (tcu_scan_en), |
| 696 | .tcu_aclk (tcu_aclk), |
| 697 | .tcu_bclk (tcu_bclk), |
| 698 | .s_in (mosi_shreg4_s_in), // Templated |
| 699 | .p_in (mosi_shreg4_p_in[7:0]), // Templated |
| 700 | .shift_n(mosi_shift_n), // Templated |
| 701 | .load_n(mosi_load_n)); // Templated |
| 702 | ncu_ssisrg8_ctl u_mosi_shreg5 (/*AUTOINST*/ |
| 703 | // Outputs |
| 704 | .p_out (mosi_shreg5_p_out[7:0]), // Templated |
| 705 | // Inputs |
| 706 | .scan_in(u_mosi_shreg5_scanin), |
| 707 | .scan_out(u_mosi_shreg5_scanout), |
| 708 | .iol2clk (iol2clk), |
| 709 | .tcu_pce_ov (tcu_pce_ov), |
| 710 | .tcu_clk_stop (tcu_clk_stop), |
| 711 | .tcu_scan_en (tcu_scan_en), |
| 712 | .tcu_aclk (tcu_aclk), |
| 713 | .tcu_bclk (tcu_bclk), |
| 714 | .s_in (mosi_shreg5_s_in), // Templated |
| 715 | .p_in (mosi_shreg5_p_in[7:0]), // Templated |
| 716 | .shift_n(mosi_shift_n), // Templated |
| 717 | .load_n(mosi_load_n)); // Templated |
| 718 | ncu_ssisrg8_ctl u_mosi_shreg6 (/*AUTOINST*/ |
| 719 | // Outputs |
| 720 | .p_out (mosi_shreg6_p_out[7:0]), // Templated |
| 721 | // Inputs |
| 722 | .scan_in(u_mosi_shreg6_scanin), |
| 723 | .scan_out(u_mosi_shreg6_scanout), |
| 724 | .iol2clk (iol2clk), |
| 725 | .tcu_pce_ov (tcu_pce_ov), |
| 726 | .tcu_clk_stop (tcu_clk_stop), |
| 727 | .tcu_scan_en (tcu_scan_en), |
| 728 | .tcu_aclk (tcu_aclk), |
| 729 | .tcu_bclk (tcu_bclk), |
| 730 | .s_in (mosi_shreg6_s_in), // Templated |
| 731 | .p_in (mosi_shreg6_p_in[7:0]), // Templated |
| 732 | .shift_n(mosi_shift_n), // Templated |
| 733 | .load_n(mosi_load_n)); // Templated |
| 734 | ncu_ssisrg8_ctl u_mosi_shreg7 (/*AUTOINST*/ |
| 735 | // Outputs |
| 736 | .p_out (mosi_shreg7_p_out[7:0]), // Templated |
| 737 | // Inputs |
| 738 | .scan_in(u_mosi_shreg7_scanin), |
| 739 | .scan_out(u_mosi_shreg7_scanout), |
| 740 | .iol2clk (iol2clk), |
| 741 | .tcu_pce_ov (tcu_pce_ov), |
| 742 | .tcu_clk_stop (tcu_clk_stop), |
| 743 | .tcu_scan_en (tcu_scan_en), |
| 744 | .tcu_aclk (tcu_aclk), |
| 745 | .tcu_bclk (tcu_bclk), |
| 746 | .s_in (mosi_shreg7_s_in), // Templated |
| 747 | .p_in (mosi_shreg7_p_in[7:0]), // Templated |
| 748 | .shift_n(mosi_shift_n), // Templated |
| 749 | .load_n(mosi_load_n)); // Templated |
| 750 | |
| 751 | |
| 752 | //******************************************************************************* |
| 753 | // SCK Dependencies |
| 754 | // - ctu_jbi_ssiclk is jbus clk divided by 4 |
| 755 | //******************************************************************************* |
| 756 | |
| 757 | ////assign sck_posedge_d1 = ~ctu_jbi_ssiclk_d1 & ctu_jbi_ssiclk_ff; |
| 758 | ////assign sck_negedge_d1 = ctu_jbi_ssiclk_d1 & ~ctu_jbi_ssiclk_ff; |
| 759 | |
| 760 | //assign sck_negedge = sck_posedge_d2; |
| 761 | //sck cycle count increments at rising edge of sck |
| 762 | assign sck_cyc_cnt_rst_l = ssi_sm[2:0] == next_ssi_sm[2:0]; //clear count when jumping into new state |
| 763 | |
| 764 | assign next_sck_cyc_cnt[6:0] = ( ( (ssi_sm[2:0] == `SSI_RDATA | ssi_sm[2:0] == `SSI_ACK_PAR) & sck_posedge_d4) |
| 765 | | ( ~(ssi_sm[2:0] == `SSI_RDATA | ssi_sm[2:0] == `SSI_ACK_PAR) & sck_posedge) ) ? |
| 766 | sck_cyc_cnt[6:0] + 7'd1 : sck_cyc_cnt[6:0] ; |
| 767 | |
| 768 | |
| 769 | |
| 770 | //*********************************************************************************** |
| 771 | // signal at pin (board level, note, mosi and miso do not active at same time) |
| 772 | //*********************************************************************************** |
| 773 | // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |16 | |
| 774 | // _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |
| 775 | //iol2clk _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
| 776 | // _______________ _______________ _____ |
| 777 | //sck(pin) _|a |_______________|b |_______________| |
| 778 | // _____ _______________________________ _______________ |
| 779 | //mosi(pin) _____X_________data_out______________X_______________ |
| 780 | // __ _________________ _________ |
| 781 | //miso(pin) __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX___data_a________XXXXXXXXXXXXXXX__data_b_ |
| 782 | // ^ ^ |
| 783 | // MIO sample miso @ rising of sck |
| 784 | // |
| 785 | //*********************************************************************************** |
| 786 | // AT NCU port level (note mosi and miso do not active at same time) |
| 787 | //*********************************************************************************** |
| 788 | // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |16 |17 | |
| 789 | // _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |
| 790 | //iol2clk | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
| 791 | // _______________ _______________ _ |
| 792 | //sck(pin) ___|a |_______________|b |_______________| |
| 793 | // _______________ _______________ _____ |
| 794 | //io_ssi_sck _|a |_______________|b |_______________| |
| 795 | // __ _______________________________ _______________________________ __ |
| 796 | //ssi_mosi(ncu) __X_____data______________________X_________data__________________X__ |
| 797 | // _______________________________ ______ |
| 798 | //ssi_miso(ncu) XXXXXXXXXXXXXXXXXXXXXXXXXXXX__data_a_______________________X______ |
| 799 | // ^ncu sample ssi_miso(from mio) ^ |
| 800 | // _______________________________ __ |
| 801 | //ssi_miso_ff(internal) XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX__data_a_______________________X__ |
| 802 | // |
| 803 | // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |16 |17 |18 | |
| 804 | // P2 P3 P4 P5 |
| 805 | // ^Internally processing at P4 |
| 806 | // |
| 807 | |
| 808 | |
| 809 | |
| 810 | |
| 811 | |
| 812 | |
| 813 | |
| 814 | |
| 815 | |
| 816 | |
| 817 | |
| 818 | |
| 819 | |
| 820 | |
| 821 | |
| 822 | // Load miso shift register |
| 823 | assign ssi_req[27:0] = ucbif_sif_addr[27:0]; |
| 824 | assign ssi_req[29:28] = ucbif_sif_size[1:0]; |
| 825 | assign ssi_req[30] = ucbif_sif_rw; |
| 826 | |
| 827 | assign mosi_shreg_din[63:0] = (ssi_sm[2:0] == `SSI_IDLE) ? { {33{1'b1}}, ssi_req[30:0] } : wdata[63:0] ; |
| 828 | |
| 829 | |
| 830 | assign mosi_load_n = ~(ssi_sm[2:0] == `SSI_IDLE | |
| 831 | (ssi_sm[2:0] == `SSI_REQ & sck_cyc_cnt[5] & ~rw)); |
| 832 | |
| 833 | // Advance miso shift register |
| 834 | assign mosi_shift_n = ~(sck_posedge_d1 |
| 835 | & (ssi_sm[2:0] == `SSI_REQ | ssi_sm[2:0] == `SSI_WDATA) & mosi_load_n); |
| 836 | |
| 837 | // Determine where wdata is to be taken |
| 838 | always @ ( /*AUTOSENSE*/mosi_shreg0_p_out or mosi_shreg1_p_out |
| 839 | or mosi_shreg2_p_out or mosi_shreg3_p_out |
| 840 | or mosi_shreg4_p_out or mosi_shreg5_p_out |
| 841 | or mosi_shreg6_p_out or mosi_shreg7_p_out or wdata_sel) begin |
| 842 | case(wdata_sel[2:0]) |
| 843 | 3'd0: mosi_wdata_bit = mosi_shreg7_p_out[7]; |
| 844 | 3'd1: mosi_wdata_bit = mosi_shreg6_p_out[7]; |
| 845 | 3'd2: mosi_wdata_bit = mosi_shreg5_p_out[7]; |
| 846 | 3'd3: mosi_wdata_bit = mosi_shreg4_p_out[7]; |
| 847 | 3'd4: mosi_wdata_bit = mosi_shreg3_p_out[7]; |
| 848 | 3'd5: mosi_wdata_bit = mosi_shreg2_p_out[7]; |
| 849 | 3'd6: mosi_wdata_bit = mosi_shreg1_p_out[7]; |
| 850 | 3'd7: mosi_wdata_bit = mosi_shreg0_p_out[7]; |
| 851 | endcase |
| 852 | end |
| 853 | |
| 854 | // Generate parity |
| 855 | assign par_en = ( sck_posedge_d2 // gen par |
| 856 | & (ssi_sm[2:0] == `SSI_REQ | ssi_sm[2:0] == `SSI_WDATA)) |
| 857 | | ( sck_posedge_d4 // check par |
| 858 | & (ssi_sm[2:0] == `SSI_ACK | ssi_sm[2:0] == `SSI_RDATA | ssi_sm[2:0] == `SSI_ACK_PAR)); |
| 859 | |
| 860 | assign par_rst_l = ~( ssi_sm[2:0] == `SSI_IDLE |
| 861 | | ssi_sm[2:0] == `SSI_ACK & ~(sck_posedge_d4 & io_jbi_ssi_miso_ff)); |
| 862 | |
| 863 | always @ ( /*AUTOSENSE*/io_jbi_ssi_miso_ff or next_jbi_io_ssi_mosi |
| 864 | or par or ssi_sm) begin |
| 865 | case (ssi_sm[2:0]) |
| 866 | `SSI_REQ, |
| 867 | `SSI_WDATA : next_par = par ^ next_jbi_io_ssi_mosi; |
| 868 | `SSI_ACK, |
| 869 | `SSI_RDATA, |
| 870 | `SSI_ACK_PAR : next_par = par ^ io_jbi_ssi_miso_ff; |
| 871 | default : next_par = 1'b0; |
| 872 | endcase |
| 873 | end |
| 874 | |
| 875 | |
| 876 | // Output MOSI |
| 877 | always @ ( /*AUTOSENSE*/mosi_shreg3_p_out or mosi_wdata_bit or par |
| 878 | or ssi_sm) begin |
| 879 | case (ssi_sm[2:0]) |
| 880 | `SSI_REQ: next_jbi_io_ssi_mosi = mosi_shreg3_p_out[7]; // include start bit |
| 881 | `SSI_WDATA: next_jbi_io_ssi_mosi = mosi_wdata_bit; |
| 882 | `SSI_REQ_PAR: next_jbi_io_ssi_mosi = par; |
| 883 | default: next_jbi_io_ssi_mosi = 1'b0; |
| 884 | endcase |
| 885 | end |
| 886 | |
| 887 | //******************************************************************************* |
| 888 | // SO Packing |
| 889 | //******************************************************************************* |
| 890 | |
| 891 | //assign rdata_shift_n = ~(ssi_sm[2:0] == `SSI_RDATA & sck_posedge_d2); |
| 892 | assign rdata_shift_n = ~(ssi_sm[2:0] == `SSI_RDATA & sck_posedge_d4); |
| 893 | |
| 894 | assign srg64p_out_next[63:0] = rdata_shift_n ? srg64p_out[63:0] : |
| 895 | {srg64p_out[62:0],io_jbi_ssi_miso_ff} ; |
| 896 | assign rdata_shreg[63:0]=srg64p_out[63:0]; |
| 897 | |
| 898 | ncu_ssisif_ctl_msff_ctl_macro__width_64 srg64p_out_ff |
| 899 | ( |
| 900 | .scan_in(srg64p_out_ff_scanin), |
| 901 | .scan_out(srg64p_out_ff_scanout), |
| 902 | .dout (srg64p_out[63:0]), |
| 903 | .l1clk (l1clk), |
| 904 | .din (srg64p_out_next[63:0]), |
| 905 | .siclk(siclk), |
| 906 | .soclk(soclk) |
| 907 | ); |
| 908 | |
| 909 | // Signal read return data |
| 910 | assign sif_ucbif_rdata_en = ssi_sm[2:0] == `SSI_ACK_PAR ; |
| 911 | always @ ( /*AUTOSENSE*/rdata_shreg or size) begin |
| 912 | case (size[1:0]) |
| 913 | 2'b00: next_sif_ucbif_rdata[63:0] = {8{rdata_shreg[7:0]}}; |
| 914 | 2'b01: next_sif_ucbif_rdata[63:0] = {4{rdata_shreg[15:0]}}; |
| 915 | 2'b10: next_sif_ucbif_rdata[63:0] = {2{rdata_shreg[31:0]}}; |
| 916 | 2'b11: next_sif_ucbif_rdata[63:0] = rdata_shreg; |
| 917 | //default: next_sif_ucbif_rdata[63:0] = 64'bx; |
| 918 | endcase |
| 919 | end |
| 920 | |
| 921 | assign next_sif_ucbif_rdata_vld = ack_par_rdy & rw |
| 922 | | (sif_ucbif_rdata_vld |
| 923 | & ~ucbif_sif_rdata_accpt); |
| 924 | |
| 925 | //******************************************************************************* |
| 926 | // Error Handling |
| 927 | // - Ack Timeout |
| 928 | // - Parity |
| 929 | //******************************************************************************* |
| 930 | |
| 931 | // Timeout |
| 932 | assign timeout_cnt_en = ssi_sm[2:0] == `SSI_ACK ; |
| 933 | assign timeout_cnt_rst_l = ssi_sm[2:0] == `SSI_ACK ; |
| 934 | assign next_timeout_cnt[23:0] = timeout_cnt[23:0] + 24'd1; |
| 935 | |
| 936 | assign sif_ucbif_timeout_rst_l = ~ucbif_sif_timeout_accpt; |
| 937 | |
| 938 | assign next_sif_ucbif_timeout = sif_ucbif_timeout | (timeout_cnt[23:0] == |
| 939 | ucbif_sif_timeval[23:0]); |
| 940 | |
| 941 | assign sif_ucbif_timeout_rw = rw; |
| 942 | |
| 943 | // Parity - even parity |
| 944 | assign ack_par_rdy = (ssi_sm[2:0] == `SSI_ACK_PAR) & (next_ssi_sm[2:0] != `SSI_ACK_PAR); |
| 945 | assign next_sif_ucbif_par_err = ack_par_rdy & par |
| 946 | | (sif_ucbif_par_err |
| 947 | & sif_ucbif_rdata_vld |
| 948 | & ~ucbif_sif_rdata_accpt); |
| 949 | |
| 950 | |
| 951 | //******************************************************************************* |
| 952 | // Async Reset DFFRL Instantiations |
| 953 | //******************************************************************************* |
| 954 | assign cntr_n[2:0] = cntr[2:0] + 3'd1 ; |
| 955 | //assign iol2clk_by8 = cntr[2]; |
| 956 | //assign iol2clk_by4 = cntr[1]; |
| 957 | |
| 958 | reg iol2clk_div; |
| 959 | reg sck_posedge_next; |
| 960 | //reg sck_negedge_next; |
| 961 | |
| 962 | always @(ncu_scksel[1:0] or cntr[2:0]) |
| 963 | begin |
| 964 | case(ncu_scksel[1:0]) |
| 965 | 2'b00: begin iol2clk_div = cntr[2]; |
| 966 | sck_posedge_next = cntr[2:0]==3'b011; |
| 967 | //sck_negedge_next = cntr[2:0]==3'b111 ; |
| 968 | end |
| 969 | 2'b01: begin iol2clk_div = cntr[1]; |
| 970 | sck_posedge_next = cntr[1:0]==2'b01; |
| 971 | //sck_negedge_next = cntr[1:0]==2'b11 ; |
| 972 | end |
| 973 | default: begin iol2clk_div = cntr[2]; |
| 974 | sck_posedge_next = cntr[2:0]==3'b011; |
| 975 | //sck_negedge_next = cntr[2:0]==3'b111 ; |
| 976 | end |
| 977 | endcase |
| 978 | end |
| 979 | |
| 980 | ncu_ssisif_ctl_msff_ctl_macro__width_3 cntr_ff |
| 981 | ( |
| 982 | .scan_in(cntr_ff_scanin), |
| 983 | .scan_out(cntr_ff_scanout), |
| 984 | .dout (cntr[2:0]), |
| 985 | .l1clk (l1clk), |
| 986 | .din (cntr_n[2:0]), |
| 987 | .siclk(siclk), |
| 988 | .soclk(soclk) |
| 989 | ); |
| 990 | |
| 991 | ncu_ssisif_ctl_msff_ctl_macro__width_1 u_dffrl_async_ctu_jbi_ssiclk_ff |
| 992 | ( |
| 993 | .scan_in(u_dffrl_async_ctu_jbi_ssiclk_ff_scanin), |
| 994 | .scan_out(u_dffrl_async_ctu_jbi_ssiclk_ff_scanout), |
| 995 | .dout (ctu_jbi_ssiclk_ff), |
| 996 | .l1clk (l1clk), |
| 997 | .din (iol2clk_div), |
| 998 | .siclk(siclk), |
| 999 | .soclk(soclk) |
| 1000 | ); |
| 1001 | //.rst_l (arst_l), |
| 1002 | |
| 1003 | assign next_jbi_io_ssi_sck = ctu_jbi_ssiclk_ff; |
| 1004 | ncu_ssisif_ctl_msff_ctl_macro__width_1 u_dffrl_async_jbi_io_ssi_sck |
| 1005 | ( |
| 1006 | .scan_in(u_dffrl_async_jbi_io_ssi_sck_scanin), |
| 1007 | .scan_out(u_dffrl_async_jbi_io_ssi_sck_scanout), |
| 1008 | .dout (jbi_io_ssi_sck), |
| 1009 | .l1clk (l1clk), |
| 1010 | .din (next_jbi_io_ssi_sck), |
| 1011 | .siclk(siclk), |
| 1012 | .soclk(soclk) |
| 1013 | ); |
| 1014 | //.rst_l(arst_l), |
| 1015 | |
| 1016 | //******************************************************************************* |
| 1017 | // DFF Instantiations |
| 1018 | //******************************************************************************* |
| 1019 | |
| 1020 | ncu_ssisif_ctl_msff_ctl_macro__width_1 u_dff_io_jbi_ssi_miso_ff |
| 1021 | ( |
| 1022 | .scan_in(u_dff_io_jbi_ssi_miso_ff_scanin), |
| 1023 | .scan_out(u_dff_io_jbi_ssi_miso_ff_scanout), |
| 1024 | .dout (io_jbi_ssi_miso_ff), |
| 1025 | .l1clk (l1clk), |
| 1026 | .din (io_jbi_ssi_miso), |
| 1027 | .siclk(siclk), |
| 1028 | .soclk(soclk) |
| 1029 | ); |
| 1030 | |
| 1031 | ncu_ssisif_ctl_msff_ctl_macro__width_1 sck_posedge_ff |
| 1032 | ( |
| 1033 | .scan_in(sck_posedge_ff_scanin), |
| 1034 | .scan_out(sck_posedge_ff_scanout), |
| 1035 | .dout (sck_posedge), |
| 1036 | .l1clk (l1clk), |
| 1037 | .din (sck_posedge_next), |
| 1038 | .siclk(siclk), |
| 1039 | .soclk(soclk) |
| 1040 | ); |
| 1041 | ncu_ssisif_ctl_msff_ctl_macro__width_1 sck_posedge_d1_ff |
| 1042 | ( |
| 1043 | .scan_in(sck_posedge_d1_ff_scanin), |
| 1044 | .scan_out(sck_posedge_d1_ff_scanout), |
| 1045 | .dout (sck_posedge_d1), |
| 1046 | .l1clk (l1clk), |
| 1047 | .din (sck_posedge), |
| 1048 | .siclk(siclk), |
| 1049 | .soclk(soclk) |
| 1050 | ); |
| 1051 | ncu_ssisif_ctl_msff_ctl_macro__width_1 sck_posedge_d2_ff |
| 1052 | ( |
| 1053 | .scan_in(sck_posedge_d2_ff_scanin), |
| 1054 | .scan_out(sck_posedge_d2_ff_scanout), |
| 1055 | .dout (sck_posedge_d2), |
| 1056 | .l1clk (l1clk), |
| 1057 | .din (sck_posedge_d1), |
| 1058 | .siclk(siclk), |
| 1059 | .soclk(soclk) |
| 1060 | ); |
| 1061 | |
| 1062 | ncu_ssisif_ctl_msff_ctl_macro__width_1 sck_posedge_d3_ff |
| 1063 | ( |
| 1064 | .scan_in(sck_posedge_d3_ff_scanin), |
| 1065 | .scan_out(sck_posedge_d3_ff_scanout), |
| 1066 | .dout (sck_posedge_d3), |
| 1067 | .l1clk (l1clk), |
| 1068 | .din (sck_posedge_d2), |
| 1069 | .siclk(siclk), |
| 1070 | .soclk(soclk) |
| 1071 | ); |
| 1072 | |
| 1073 | ncu_ssisif_ctl_msff_ctl_macro__width_1 sck_posedge_d4_ff |
| 1074 | ( |
| 1075 | .scan_in(sck_posedge_d4_ff_scanin), |
| 1076 | .scan_out(sck_posedge_d4_ff_scanout), |
| 1077 | .dout (sck_posedge_d4), |
| 1078 | .l1clk (l1clk), |
| 1079 | .din (sck_posedge_d3), |
| 1080 | .siclk(siclk), |
| 1081 | .soclk(soclk) |
| 1082 | ); |
| 1083 | |
| 1084 | //msff_ctl_macro sck_negedge_ff (width=1) |
| 1085 | //( |
| 1086 | //.scan_in(sck_negedge_ff_scanin), |
| 1087 | //.scan_out(sck_negedge_ff_scanout), |
| 1088 | //.dout (sck_negedge), |
| 1089 | //.l1clk (l1clk), |
| 1090 | //.din (sck_negedge_next) |
| 1091 | //); |
| 1092 | //msff_ctl_macro sck_negedge_d1_ff (width=1) |
| 1093 | //( |
| 1094 | //.scan_in(sck_negedge_d1_ff_scanin), |
| 1095 | //.scan_out(sck_negedge_d1_ff_scanout), |
| 1096 | //.dout (sck_negedge_d1), |
| 1097 | //.l1clk (l1clk), |
| 1098 | //.din (sck_negedge) |
| 1099 | //); |
| 1100 | |
| 1101 | ////dff #(1) u_dff_ctu_jbi_ssiclk_d1 |
| 1102 | ////(.din(ctu_jbi_ssiclk_ff), |
| 1103 | ////.clk(iol2clk), |
| 1104 | ////.q(ctu_jbi_ssiclk_d1) |
| 1105 | ////); |
| 1106 | |
| 1107 | //dff_ns #(1) u_dff_sck_posedge_d2 |
| 1108 | // (.din(sck_posedge_d1), |
| 1109 | // .clk(clk), |
| 1110 | // .q(sck_posedge_d2) |
| 1111 | // ); |
| 1112 | |
| 1113 | //******************************************************************************* |
| 1114 | // DFFR Instantiations |
| 1115 | //******************************************************************************* |
| 1116 | assign n_ssi_sm[2:0] = ssi_sm_rst_l ? next_ssi_sm[2:0] : 3'b0 ; |
| 1117 | ncu_ssisif_ctl_msff_ctl_macro__width_3 u_dffrl_ssi_sm |
| 1118 | ( |
| 1119 | .scan_in(u_dffrl_ssi_sm_scanin), |
| 1120 | .scan_out(u_dffrl_ssi_sm_scanout), |
| 1121 | .dout (ssi_sm[2:0]), |
| 1122 | .l1clk (l1clk), |
| 1123 | .din (n_ssi_sm[2:0]), |
| 1124 | .siclk(siclk), |
| 1125 | .soclk(soclk) |
| 1126 | ); |
| 1127 | |
| 1128 | assign n_sck_cyc_cnt[6:0] = sck_cyc_cnt_rst_l ? next_sck_cyc_cnt[6:0] : 7'b0 ; |
| 1129 | ncu_ssisif_ctl_msff_ctl_macro__width_7 u_dffrl_sck_cyc_cnt |
| 1130 | ( |
| 1131 | .scan_in(u_dffrl_sck_cyc_cnt_scanin), |
| 1132 | .scan_out(u_dffrl_sck_cyc_cnt_scanout), |
| 1133 | .dout (sck_cyc_cnt[6:0]), |
| 1134 | .l1clk (l1clk), |
| 1135 | .din (n_sck_cyc_cnt[6:0]), |
| 1136 | .siclk(siclk), |
| 1137 | .soclk(soclk) |
| 1138 | ); |
| 1139 | |
| 1140 | ncu_ssisif_ctl_msff_ctl_macro__width_1 u_dffrl_sif_ucbif_rdata_vld |
| 1141 | ( |
| 1142 | .scan_in(u_dffrl_sif_ucbif_rdata_vld_scanin), |
| 1143 | .scan_out(u_dffrl_sif_ucbif_rdata_vld_scanout), |
| 1144 | .dout (sif_ucbif_rdata_vld), |
| 1145 | .l1clk (l1clk), |
| 1146 | .din (next_sif_ucbif_rdata_vld), |
| 1147 | .siclk(siclk), |
| 1148 | .soclk(soclk) |
| 1149 | ); |
| 1150 | |
| 1151 | assign n_sif_ucbif_timeout = sif_ucbif_timeout_rst_l ? next_sif_ucbif_timeout : 1'b0 ; |
| 1152 | ncu_ssisif_ctl_msff_ctl_macro__width_1 u_dffrl_sif_ucbif_timeout |
| 1153 | ( |
| 1154 | .scan_in(u_dffrl_sif_ucbif_timeout_scanin), |
| 1155 | .scan_out(u_dffrl_sif_ucbif_timeout_scanout), |
| 1156 | .dout (sif_ucbif_timeout), |
| 1157 | .l1clk (l1clk), |
| 1158 | .din (n_sif_ucbif_timeout), |
| 1159 | .siclk(siclk), |
| 1160 | .soclk(soclk) |
| 1161 | ); |
| 1162 | |
| 1163 | ncu_ssisif_ctl_msff_ctl_macro__width_1 u_dffrl_sif_ucbif_par_err |
| 1164 | ( |
| 1165 | .scan_in(u_dffrl_sif_ucbif_par_err_scanin), |
| 1166 | .scan_out(u_dffrl_sif_ucbif_par_err_scanout), |
| 1167 | .dout (sif_ucbif_par_err), |
| 1168 | .l1clk (l1clk), |
| 1169 | .din (next_sif_ucbif_par_err), |
| 1170 | .siclk(siclk), |
| 1171 | .soclk(soclk) |
| 1172 | ); |
| 1173 | |
| 1174 | ncu_ssisif_ctl_msff_ctl_macro__width_1 u_dffrl_jbi_io_ssi_mosi |
| 1175 | ( |
| 1176 | .scan_in(u_dffrl_jbi_io_ssi_mosi_scanin), |
| 1177 | .scan_out(u_dffrl_jbi_io_ssi_mosi_scanout), |
| 1178 | .dout (jbi_io_ssi_mosi), |
| 1179 | .l1clk (l1clk), |
| 1180 | .din (next_jbi_io_ssi_mosi), |
| 1181 | .siclk(siclk), |
| 1182 | .soclk(soclk) |
| 1183 | ); |
| 1184 | //******************************************************************************* |
| 1185 | //sck_cnt[17:0] (lock counter) starting all 0's and inc to all 1's, then |
| 1186 | //allow busy signal to be drop and can accept request from uif block |
| 1187 | //counting is bypassed if tcu_sck_bypass is 1 (for testing or debugging use) |
| 1188 | //******************************************************************************* |
| 1189 | |
| 1190 | ncu_ssisif_ctl_msff_ctl_macro__width_18 sck_cnt_ff |
| 1191 | ( |
| 1192 | .scan_in(sck_cnt_ff_scanin), |
| 1193 | .scan_out(sck_cnt_ff_scanout), |
| 1194 | .dout (sck_cnt[17:0]), |
| 1195 | .l1clk (l1clk), |
| 1196 | .din (next_sck_cnt[17:0]), |
| 1197 | .siclk(siclk), |
| 1198 | .soclk(soclk) |
| 1199 | ); |
| 1200 | |
| 1201 | ncu_ssisif_ctl_msff_ctl_macro__width_1 sck_bypass_ff |
| 1202 | ( |
| 1203 | .scan_in(sck_bypass_ff_scanin), |
| 1204 | .scan_out(sck_bypass_ff_scanout), |
| 1205 | .dout (sck_bypass), |
| 1206 | .l1clk (l1clk), |
| 1207 | .din (tcu_sck_bypass), |
| 1208 | .siclk(siclk), |
| 1209 | .soclk(soclk) |
| 1210 | ); |
| 1211 | |
| 1212 | assign sck_cntexp = (sck_cnt[17:0] == 18'h3FFFF); |
| 1213 | assign next_sck_cnt[17:0] = sck_bypass ? 18'h3FFFF : |
| 1214 | (~sck_cntexp & sck_posedge) ? (sck_cnt[17:0] + 18'b1) : |
| 1215 | sck_cnt[17:0]; |
| 1216 | |
| 1217 | //******************************************************************************* |
| 1218 | // SSI State Machine |
| 1219 | //******************************************************************************* |
| 1220 | |
| 1221 | assign ssi_sm_rst_l = ~sif_ucbif_timeout; // stop processing after timeout |
| 1222 | |
| 1223 | //jimmy: sm runs at d1 and change at d2 for IDLE->REQ-WDATA-REQPAR |
| 1224 | always @(/*AUTOSENSE*/io_jbi_ssi_miso_ff or rw or sck_cyc_cnt |
| 1225 | or sck_posedge_d4 or sck_posedge_d1 or sif_ucbif_timeout or size |
| 1226 | or ssi_sm or ucbif_sif_vld) begin |
| 1227 | case(ssi_sm[2:0]) |
| 1228 | `SSI_IDLE: begin |
| 1229 | if (ucbif_sif_vld & sck_posedge_d1) // must line up with mosi |
| 1230 | next_ssi_sm[2:0] = `SSI_REQ ; |
| 1231 | else |
| 1232 | next_ssi_sm[2:0] = `SSI_IDLE ; |
| 1233 | end |
| 1234 | |
| 1235 | `SSI_REQ: begin |
| 1236 | if (sck_cyc_cnt[5]) begin // == 32 which includes start bit |
| 1237 | if (rw) |
| 1238 | next_ssi_sm[2:0] = `SSI_REQ_PAR ; |
| 1239 | else |
| 1240 | next_ssi_sm[2:0] = `SSI_WDATA ; |
| 1241 | end |
| 1242 | else |
| 1243 | next_ssi_sm[2:0] = `SSI_REQ ; |
| 1244 | end |
| 1245 | |
| 1246 | `SSI_WDATA: begin |
| 1247 | if ( (size[1:0] == 2'b00 & sck_cyc_cnt[3]) |
| 1248 | | (size[1:0] == 2'b01 & sck_cyc_cnt[4]) |
| 1249 | | (size[1:0] == 2'b10 & sck_cyc_cnt[5]) |
| 1250 | | (size[1:0] == 2'b11 & sck_cyc_cnt[6])) |
| 1251 | next_ssi_sm[2:0] = `SSI_REQ_PAR ; |
| 1252 | else |
| 1253 | next_ssi_sm[2:0] = `SSI_WDATA ; |
| 1254 | end |
| 1255 | |
| 1256 | `SSI_REQ_PAR: begin |
| 1257 | if (sck_cyc_cnt[0]) |
| 1258 | next_ssi_sm[2:0] = `SSI_ACK ; |
| 1259 | else |
| 1260 | next_ssi_sm[2:0] = `SSI_REQ_PAR ; |
| 1261 | end |
| 1262 | |
| 1263 | `SSI_ACK: begin |
| 1264 | //sample at posedge of sck period + 10 cycle delay from io_ssi_sck gen to recv |
| 1265 | if (sck_posedge_d4 & io_jbi_ssi_miso_ff) begin |
| 1266 | if (rw) |
| 1267 | next_ssi_sm[2:0] = `SSI_RDATA ; |
| 1268 | else |
| 1269 | next_ssi_sm[2:0] = `SSI_ACK_PAR ; |
| 1270 | end |
| 1271 | else if (sif_ucbif_timeout) |
| 1272 | next_ssi_sm[2:0] = `SSI_IDLE ; |
| 1273 | else |
| 1274 | next_ssi_sm[2:0] = `SSI_ACK ; |
| 1275 | end |
| 1276 | |
| 1277 | `SSI_RDATA: begin |
| 1278 | //sample at posedge of sck period + 10 cycle delay from io_ssi_sck gen to recv |
| 1279 | if ( (size[1:0] == 2'b00 & sck_cyc_cnt[3]) |
| 1280 | | (size[1:0] == 2'b01 & sck_cyc_cnt[4]) |
| 1281 | | (size[1:0] == 2'b10 & sck_cyc_cnt[5]) |
| 1282 | | (size[1:0] == 2'b11 & sck_cyc_cnt[6])) |
| 1283 | next_ssi_sm[2:0] = `SSI_ACK_PAR ; |
| 1284 | else |
| 1285 | next_ssi_sm[2:0] = `SSI_RDATA ; |
| 1286 | end |
| 1287 | |
| 1288 | `SSI_ACK_PAR: begin |
| 1289 | if (sck_cyc_cnt[0]) |
| 1290 | next_ssi_sm[2:0] = `SSI_IDLE ; |
| 1291 | else |
| 1292 | next_ssi_sm[2:0] = `SSI_ACK_PAR ; |
| 1293 | end |
| 1294 | |
| 1295 | default: begin |
| 1296 | next_ssi_sm[2:0] = `SSI_IDLE ; |
| 1297 | end |
| 1298 | endcase |
| 1299 | end |
| 1300 | |
| 1301 | /* spare gate, 4531 cells / 450 = 11 */ |
| 1302 | |
| 1303 | ncu_ssisif_ctl_spare_ctl_macro__num_11 spares ( |
| 1304 | .scan_in(spares_scanin), |
| 1305 | .scan_out(spares_scanout), |
| 1306 | .l1clk (l1clk), |
| 1307 | .siclk(siclk), |
| 1308 | .soclk(soclk) |
| 1309 | ); |
| 1310 | |
| 1311 | |
| 1312 | |
| 1313 | /**** adding clock header ****/ |
| 1314 | ncu_ssisif_ctl_l1clkhdr_ctl_macro clkgen ( |
| 1315 | .l2clk (iol2clk), |
| 1316 | .l1en (1'b1), |
| 1317 | .l1clk (l1clk), |
| 1318 | .pce_ov(pce_ov), |
| 1319 | .stop(stop), |
| 1320 | .se(se) |
| 1321 | ); |
| 1322 | |
| 1323 | /*** building tcu port ***/ |
| 1324 | assign siclk = tcu_aclk; |
| 1325 | assign soclk = tcu_bclk; |
| 1326 | assign se = tcu_scan_en; |
| 1327 | assign pce_ov = tcu_pce_ov; |
| 1328 | assign stop = tcu_clk_stop; |
| 1329 | |
| 1330 | // fixscan start: |
| 1331 | assign u_dffrle_rw_scanin = scan_in ; |
| 1332 | assign u_dffrle_size_scanin = u_dffrle_rw_scanout ; |
| 1333 | assign u_dffrle_wdata_scanin = u_dffrle_size_scanout ; |
| 1334 | assign u_dffrle_wdata_sel_scanin = u_dffrle_wdata_scanout ; |
| 1335 | assign u_dffrle_sif_ucbif_rdata_scanin = u_dffrle_wdata_sel_scanout; |
| 1336 | assign u_dffrle_par_scanin = u_dffrle_sif_ucbif_rdata_scanout; |
| 1337 | assign u_dffrle_timeout_cnt_scanin = u_dffrle_par_scanout ; |
| 1338 | assign u_mosi_shreg0_scanin = u_dffrle_timeout_cnt_scanout; |
| 1339 | assign u_mosi_shreg1_scanin = u_mosi_shreg0_scanout ; |
| 1340 | assign u_mosi_shreg2_scanin = u_mosi_shreg1_scanout ; |
| 1341 | assign u_mosi_shreg3_scanin = u_mosi_shreg2_scanout ; |
| 1342 | assign u_mosi_shreg4_scanin = u_mosi_shreg3_scanout ; |
| 1343 | assign u_mosi_shreg5_scanin = u_mosi_shreg4_scanout ; |
| 1344 | assign u_mosi_shreg6_scanin = u_mosi_shreg5_scanout ; |
| 1345 | assign u_mosi_shreg7_scanin = u_mosi_shreg6_scanout ; |
| 1346 | assign srg64p_out_ff_scanin = u_mosi_shreg7_scanout ; |
| 1347 | assign cntr_ff_scanin = srg64p_out_ff_scanout ; |
| 1348 | assign u_dffrl_async_ctu_jbi_ssiclk_ff_scanin = cntr_ff_scanout ; |
| 1349 | assign u_dffrl_async_jbi_io_ssi_sck_scanin = u_dffrl_async_ctu_jbi_ssiclk_ff_scanout; |
| 1350 | assign u_dff_io_jbi_ssi_miso_ff_scanin = u_dffrl_async_jbi_io_ssi_sck_scanout; |
| 1351 | assign sck_posedge_ff_scanin = u_dff_io_jbi_ssi_miso_ff_scanout; |
| 1352 | assign sck_posedge_d1_ff_scanin = sck_posedge_ff_scanout ; |
| 1353 | assign sck_posedge_d2_ff_scanin = sck_posedge_d1_ff_scanout; |
| 1354 | assign sck_posedge_d3_ff_scanin = sck_posedge_d2_ff_scanout; |
| 1355 | assign sck_posedge_d4_ff_scanin = sck_posedge_d3_ff_scanout; |
| 1356 | //assign sck_negedge_ff_scanin = sck_posedge_d2_ff_scanout; |
| 1357 | //assign sck_negedge_d1_ff_scanin = sck_negedge_ff_scanout ; |
| 1358 | //assign u_dffrl_ssi_sm_scanin = sck_negedge_d1_ff_scanout; |
| 1359 | assign u_dffrl_ssi_sm_scanin = sck_posedge_d4_ff_scanout; |
| 1360 | assign u_dffrl_sck_cyc_cnt_scanin = u_dffrl_ssi_sm_scanout ; |
| 1361 | assign u_dffrl_sif_ucbif_rdata_vld_scanin = u_dffrl_sck_cyc_cnt_scanout; |
| 1362 | assign u_dffrl_sif_ucbif_timeout_scanin = u_dffrl_sif_ucbif_rdata_vld_scanout; |
| 1363 | assign u_dffrl_sif_ucbif_par_err_scanin = u_dffrl_sif_ucbif_timeout_scanout; |
| 1364 | assign u_dffrl_jbi_io_ssi_mosi_scanin = u_dffrl_sif_ucbif_par_err_scanout; |
| 1365 | assign sck_cnt_ff_scanin = u_dffrl_jbi_io_ssi_mosi_scanout; |
| 1366 | assign sck_bypass_ff_scanin = sck_cnt_ff_scanout; |
| 1367 | assign spares_scanin = sck_bypass_ff_scanout ; |
| 1368 | assign scan_out = spares_scanout ; |
| 1369 | // fixscan end: |
| 1370 | endmodule |
| 1371 | |
| 1372 | // Local Variables: |
| 1373 | // verilog-library-directories:("." "/import/datools/vendor/synopsys/v2003.03-beta1/dw/dw03/src_ver/") |
| 1374 | // verilog-auto-sense-defines-constant:t |
| 1375 | // End: |
| 1376 | |
| 1377 | |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | |
| 1384 | // any PARAMS parms go into naming of macro |
| 1385 | |
| 1386 | module ncu_ssisif_ctl_msff_ctl_macro__en_1__width_1 ( |
| 1387 | din, |
| 1388 | en, |
| 1389 | l1clk, |
| 1390 | scan_in, |
| 1391 | siclk, |
| 1392 | soclk, |
| 1393 | dout, |
| 1394 | scan_out); |
| 1395 | wire [0:0] fdin; |
| 1396 | |
| 1397 | input [0:0] din; |
| 1398 | input en; |
| 1399 | input l1clk; |
| 1400 | input scan_in; |
| 1401 | |
| 1402 | |
| 1403 | input siclk; |
| 1404 | input soclk; |
| 1405 | |
| 1406 | output [0:0] dout; |
| 1407 | output scan_out; |
| 1408 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 1409 | |
| 1410 | |
| 1411 | |
| 1412 | |
| 1413 | |
| 1414 | |
| 1415 | dff #(1) d0_0 ( |
| 1416 | .l1clk(l1clk), |
| 1417 | .siclk(siclk), |
| 1418 | .soclk(soclk), |
| 1419 | .d(fdin[0:0]), |
| 1420 | .si(scan_in), |
| 1421 | .so(scan_out), |
| 1422 | .q(dout[0:0]) |
| 1423 | ); |
| 1424 | |
| 1425 | |
| 1426 | |
| 1427 | |
| 1428 | |
| 1429 | |
| 1430 | |
| 1431 | |
| 1432 | |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | endmodule |
| 1437 | |
| 1438 | |
| 1439 | |
| 1440 | |
| 1441 | |
| 1442 | |
| 1443 | |
| 1444 | |
| 1445 | |
| 1446 | |
| 1447 | |
| 1448 | |
| 1449 | |
| 1450 | // any PARAMS parms go into naming of macro |
| 1451 | |
| 1452 | module ncu_ssisif_ctl_msff_ctl_macro__en_1__width_2 ( |
| 1453 | din, |
| 1454 | en, |
| 1455 | l1clk, |
| 1456 | scan_in, |
| 1457 | siclk, |
| 1458 | soclk, |
| 1459 | dout, |
| 1460 | scan_out); |
| 1461 | wire [1:0] fdin; |
| 1462 | wire [0:0] so; |
| 1463 | |
| 1464 | input [1:0] din; |
| 1465 | input en; |
| 1466 | input l1clk; |
| 1467 | input scan_in; |
| 1468 | |
| 1469 | |
| 1470 | input siclk; |
| 1471 | input soclk; |
| 1472 | |
| 1473 | output [1:0] dout; |
| 1474 | output scan_out; |
| 1475 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); |
| 1476 | |
| 1477 | |
| 1478 | |
| 1479 | |
| 1480 | |
| 1481 | |
| 1482 | dff #(2) d0_0 ( |
| 1483 | .l1clk(l1clk), |
| 1484 | .siclk(siclk), |
| 1485 | .soclk(soclk), |
| 1486 | .d(fdin[1:0]), |
| 1487 | .si({scan_in,so[0:0]}), |
| 1488 | .so({so[0:0],scan_out}), |
| 1489 | .q(dout[1:0]) |
| 1490 | ); |
| 1491 | |
| 1492 | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | |
| 1498 | |
| 1499 | |
| 1500 | |
| 1501 | |
| 1502 | |
| 1503 | endmodule |
| 1504 | |
| 1505 | |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | |
| 1510 | |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | |
| 1517 | // any PARAMS parms go into naming of macro |
| 1518 | |
| 1519 | module ncu_ssisif_ctl_msff_ctl_macro__en_1__width_64 ( |
| 1520 | din, |
| 1521 | en, |
| 1522 | l1clk, |
| 1523 | scan_in, |
| 1524 | siclk, |
| 1525 | soclk, |
| 1526 | dout, |
| 1527 | scan_out); |
| 1528 | wire [63:0] fdin; |
| 1529 | wire [62:0] so; |
| 1530 | |
| 1531 | input [63:0] din; |
| 1532 | input en; |
| 1533 | input l1clk; |
| 1534 | input scan_in; |
| 1535 | |
| 1536 | |
| 1537 | input siclk; |
| 1538 | input soclk; |
| 1539 | |
| 1540 | output [63:0] dout; |
| 1541 | output scan_out; |
| 1542 | assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}}); |
| 1543 | |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | |
| 1548 | |
| 1549 | dff #(64) d0_0 ( |
| 1550 | .l1clk(l1clk), |
| 1551 | .siclk(siclk), |
| 1552 | .soclk(soclk), |
| 1553 | .d(fdin[63:0]), |
| 1554 | .si({scan_in,so[62:0]}), |
| 1555 | .so({so[62:0],scan_out}), |
| 1556 | .q(dout[63:0]) |
| 1557 | ); |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | |
| 1568 | |
| 1569 | |
| 1570 | endmodule |
| 1571 | |
| 1572 | |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | // any PARAMS parms go into naming of macro |
| 1585 | |
| 1586 | module ncu_ssisif_ctl_msff_ctl_macro__en_1__width_3 ( |
| 1587 | din, |
| 1588 | en, |
| 1589 | l1clk, |
| 1590 | scan_in, |
| 1591 | siclk, |
| 1592 | soclk, |
| 1593 | dout, |
| 1594 | scan_out); |
| 1595 | wire [2:0] fdin; |
| 1596 | wire [1:0] so; |
| 1597 | |
| 1598 | input [2:0] din; |
| 1599 | input en; |
| 1600 | input l1clk; |
| 1601 | input scan_in; |
| 1602 | |
| 1603 | |
| 1604 | input siclk; |
| 1605 | input soclk; |
| 1606 | |
| 1607 | output [2:0] dout; |
| 1608 | output scan_out; |
| 1609 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); |
| 1610 | |
| 1611 | |
| 1612 | |
| 1613 | |
| 1614 | |
| 1615 | |
| 1616 | dff #(3) d0_0 ( |
| 1617 | .l1clk(l1clk), |
| 1618 | .siclk(siclk), |
| 1619 | .soclk(soclk), |
| 1620 | .d(fdin[2:0]), |
| 1621 | .si({scan_in,so[1:0]}), |
| 1622 | .so({so[1:0],scan_out}), |
| 1623 | .q(dout[2:0]) |
| 1624 | ); |
| 1625 | |
| 1626 | |
| 1627 | |
| 1628 | |
| 1629 | |
| 1630 | |
| 1631 | |
| 1632 | |
| 1633 | |
| 1634 | |
| 1635 | |
| 1636 | |
| 1637 | endmodule |
| 1638 | |
| 1639 | |
| 1640 | |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | |
| 1650 | |
| 1651 | // any PARAMS parms go into naming of macro |
| 1652 | |
| 1653 | module ncu_ssisif_ctl_msff_ctl_macro__en_1__width_24 ( |
| 1654 | din, |
| 1655 | en, |
| 1656 | l1clk, |
| 1657 | scan_in, |
| 1658 | siclk, |
| 1659 | soclk, |
| 1660 | dout, |
| 1661 | scan_out); |
| 1662 | wire [23:0] fdin; |
| 1663 | wire [22:0] so; |
| 1664 | |
| 1665 | input [23:0] din; |
| 1666 | input en; |
| 1667 | input l1clk; |
| 1668 | input scan_in; |
| 1669 | |
| 1670 | |
| 1671 | input siclk; |
| 1672 | input soclk; |
| 1673 | |
| 1674 | output [23:0] dout; |
| 1675 | output scan_out; |
| 1676 | assign fdin[23:0] = (din[23:0] & {24{en}}) | (dout[23:0] & ~{24{en}}); |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | |
| 1681 | |
| 1682 | |
| 1683 | dff #(24) d0_0 ( |
| 1684 | .l1clk(l1clk), |
| 1685 | .siclk(siclk), |
| 1686 | .soclk(soclk), |
| 1687 | .d(fdin[23:0]), |
| 1688 | .si({scan_in,so[22:0]}), |
| 1689 | .so({so[22:0],scan_out}), |
| 1690 | .q(dout[23:0]) |
| 1691 | ); |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | endmodule |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | |
| 1709 | |
| 1710 | |
| 1711 | // any PARAMS parms go into naming of macro |
| 1712 | |
| 1713 | module ncu_ssisif_ctl_msff_ctl_macro__width_8 ( |
| 1714 | din, |
| 1715 | l1clk, |
| 1716 | scan_in, |
| 1717 | siclk, |
| 1718 | soclk, |
| 1719 | dout, |
| 1720 | scan_out); |
| 1721 | wire [7:0] fdin; |
| 1722 | wire [6:0] so; |
| 1723 | |
| 1724 | input [7:0] din; |
| 1725 | input l1clk; |
| 1726 | input scan_in; |
| 1727 | |
| 1728 | |
| 1729 | input siclk; |
| 1730 | input soclk; |
| 1731 | |
| 1732 | output [7:0] dout; |
| 1733 | output scan_out; |
| 1734 | assign fdin[7:0] = din[7:0]; |
| 1735 | |
| 1736 | |
| 1737 | |
| 1738 | |
| 1739 | |
| 1740 | |
| 1741 | dff #(8) d0_0 ( |
| 1742 | .l1clk(l1clk), |
| 1743 | .siclk(siclk), |
| 1744 | .soclk(soclk), |
| 1745 | .d(fdin[7:0]), |
| 1746 | .si({scan_in,so[6:0]}), |
| 1747 | .so({so[6:0],scan_out}), |
| 1748 | .q(dout[7:0]) |
| 1749 | ); |
| 1750 | |
| 1751 | |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | |
| 1761 | |
| 1762 | endmodule |
| 1763 | |
| 1764 | |
| 1765 | |
| 1766 | |
| 1767 | |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | |
| 1772 | |
| 1773 | |
| 1774 | |
| 1775 | |
| 1776 | // any PARAMS parms go into naming of macro |
| 1777 | |
| 1778 | module ncu_ssisif_ctl_l1clkhdr_ctl_macro ( |
| 1779 | l2clk, |
| 1780 | l1en, |
| 1781 | pce_ov, |
| 1782 | stop, |
| 1783 | se, |
| 1784 | l1clk); |
| 1785 | |
| 1786 | |
| 1787 | input l2clk; |
| 1788 | input l1en; |
| 1789 | input pce_ov; |
| 1790 | input stop; |
| 1791 | input se; |
| 1792 | output l1clk; |
| 1793 | |
| 1794 | |
| 1795 | |
| 1796 | |
| 1797 | |
| 1798 | cl_sc1_l1hdr_8x c_0 ( |
| 1799 | |
| 1800 | |
| 1801 | .l2clk(l2clk), |
| 1802 | .pce(l1en), |
| 1803 | .l1clk(l1clk), |
| 1804 | .se(se), |
| 1805 | .pce_ov(pce_ov), |
| 1806 | .stop(stop) |
| 1807 | ); |
| 1808 | |
| 1809 | |
| 1810 | |
| 1811 | endmodule |
| 1812 | |
| 1813 | |
| 1814 | |
| 1815 | |
| 1816 | |
| 1817 | |
| 1818 | |
| 1819 | |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | |
| 1824 | |
| 1825 | // any PARAMS parms go into naming of macro |
| 1826 | |
| 1827 | module ncu_ssisif_ctl_msff_ctl_macro__width_64 ( |
| 1828 | din, |
| 1829 | l1clk, |
| 1830 | scan_in, |
| 1831 | siclk, |
| 1832 | soclk, |
| 1833 | dout, |
| 1834 | scan_out); |
| 1835 | wire [63:0] fdin; |
| 1836 | wire [62:0] so; |
| 1837 | |
| 1838 | input [63:0] din; |
| 1839 | input l1clk; |
| 1840 | input scan_in; |
| 1841 | |
| 1842 | |
| 1843 | input siclk; |
| 1844 | input soclk; |
| 1845 | |
| 1846 | output [63:0] dout; |
| 1847 | output scan_out; |
| 1848 | assign fdin[63:0] = din[63:0]; |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | |
| 1855 | dff #(64) d0_0 ( |
| 1856 | .l1clk(l1clk), |
| 1857 | .siclk(siclk), |
| 1858 | .soclk(soclk), |
| 1859 | .d(fdin[63:0]), |
| 1860 | .si({scan_in,so[62:0]}), |
| 1861 | .so({so[62:0],scan_out}), |
| 1862 | .q(dout[63:0]) |
| 1863 | ); |
| 1864 | |
| 1865 | |
| 1866 | |
| 1867 | |
| 1868 | |
| 1869 | |
| 1870 | |
| 1871 | |
| 1872 | |
| 1873 | |
| 1874 | |
| 1875 | |
| 1876 | endmodule |
| 1877 | |
| 1878 | |
| 1879 | |
| 1880 | |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | |
| 1889 | |
| 1890 | // any PARAMS parms go into naming of macro |
| 1891 | |
| 1892 | module ncu_ssisif_ctl_msff_ctl_macro__width_3 ( |
| 1893 | din, |
| 1894 | l1clk, |
| 1895 | scan_in, |
| 1896 | siclk, |
| 1897 | soclk, |
| 1898 | dout, |
| 1899 | scan_out); |
| 1900 | wire [2:0] fdin; |
| 1901 | wire [1:0] so; |
| 1902 | |
| 1903 | input [2:0] din; |
| 1904 | input l1clk; |
| 1905 | input scan_in; |
| 1906 | |
| 1907 | |
| 1908 | input siclk; |
| 1909 | input soclk; |
| 1910 | |
| 1911 | output [2:0] dout; |
| 1912 | output scan_out; |
| 1913 | assign fdin[2:0] = din[2:0]; |
| 1914 | |
| 1915 | |
| 1916 | |
| 1917 | |
| 1918 | |
| 1919 | |
| 1920 | dff #(3) d0_0 ( |
| 1921 | .l1clk(l1clk), |
| 1922 | .siclk(siclk), |
| 1923 | .soclk(soclk), |
| 1924 | .d(fdin[2:0]), |
| 1925 | .si({scan_in,so[1:0]}), |
| 1926 | .so({so[1:0],scan_out}), |
| 1927 | .q(dout[2:0]) |
| 1928 | ); |
| 1929 | |
| 1930 | |
| 1931 | |
| 1932 | |
| 1933 | |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | |
| 1938 | |
| 1939 | |
| 1940 | |
| 1941 | endmodule |
| 1942 | |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | |
| 1950 | |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | // any PARAMS parms go into naming of macro |
| 1956 | |
| 1957 | module ncu_ssisif_ctl_msff_ctl_macro__width_1 ( |
| 1958 | din, |
| 1959 | l1clk, |
| 1960 | scan_in, |
| 1961 | siclk, |
| 1962 | soclk, |
| 1963 | dout, |
| 1964 | scan_out); |
| 1965 | wire [0:0] fdin; |
| 1966 | |
| 1967 | input [0:0] din; |
| 1968 | input l1clk; |
| 1969 | input scan_in; |
| 1970 | |
| 1971 | |
| 1972 | input siclk; |
| 1973 | input soclk; |
| 1974 | |
| 1975 | output [0:0] dout; |
| 1976 | output scan_out; |
| 1977 | assign fdin[0:0] = din[0:0]; |
| 1978 | |
| 1979 | |
| 1980 | |
| 1981 | |
| 1982 | |
| 1983 | |
| 1984 | dff #(1) d0_0 ( |
| 1985 | .l1clk(l1clk), |
| 1986 | .siclk(siclk), |
| 1987 | .soclk(soclk), |
| 1988 | .d(fdin[0:0]), |
| 1989 | .si(scan_in), |
| 1990 | .so(scan_out), |
| 1991 | .q(dout[0:0]) |
| 1992 | ); |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | |
| 2000 | |
| 2001 | |
| 2002 | |
| 2003 | |
| 2004 | |
| 2005 | endmodule |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | // any PARAMS parms go into naming of macro |
| 2020 | |
| 2021 | module ncu_ssisif_ctl_msff_ctl_macro__width_7 ( |
| 2022 | din, |
| 2023 | l1clk, |
| 2024 | scan_in, |
| 2025 | siclk, |
| 2026 | soclk, |
| 2027 | dout, |
| 2028 | scan_out); |
| 2029 | wire [6:0] fdin; |
| 2030 | wire [5:0] so; |
| 2031 | |
| 2032 | input [6:0] din; |
| 2033 | input l1clk; |
| 2034 | input scan_in; |
| 2035 | |
| 2036 | |
| 2037 | input siclk; |
| 2038 | input soclk; |
| 2039 | |
| 2040 | output [6:0] dout; |
| 2041 | output scan_out; |
| 2042 | assign fdin[6:0] = din[6:0]; |
| 2043 | |
| 2044 | |
| 2045 | |
| 2046 | |
| 2047 | |
| 2048 | |
| 2049 | dff #(7) d0_0 ( |
| 2050 | .l1clk(l1clk), |
| 2051 | .siclk(siclk), |
| 2052 | .soclk(soclk), |
| 2053 | .d(fdin[6:0]), |
| 2054 | .si({scan_in,so[5:0]}), |
| 2055 | .so({so[5:0],scan_out}), |
| 2056 | .q(dout[6:0]) |
| 2057 | ); |
| 2058 | |
| 2059 | |
| 2060 | |
| 2061 | |
| 2062 | |
| 2063 | |
| 2064 | |
| 2065 | |
| 2066 | |
| 2067 | |
| 2068 | |
| 2069 | |
| 2070 | endmodule |
| 2071 | |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | |
| 2084 | // any PARAMS parms go into naming of macro |
| 2085 | |
| 2086 | module ncu_ssisif_ctl_msff_ctl_macro__width_18 ( |
| 2087 | din, |
| 2088 | l1clk, |
| 2089 | scan_in, |
| 2090 | siclk, |
| 2091 | soclk, |
| 2092 | dout, |
| 2093 | scan_out); |
| 2094 | wire [17:0] fdin; |
| 2095 | wire [16:0] so; |
| 2096 | |
| 2097 | input [17:0] din; |
| 2098 | input l1clk; |
| 2099 | input scan_in; |
| 2100 | |
| 2101 | |
| 2102 | input siclk; |
| 2103 | input soclk; |
| 2104 | |
| 2105 | output [17:0] dout; |
| 2106 | output scan_out; |
| 2107 | assign fdin[17:0] = din[17:0]; |
| 2108 | |
| 2109 | |
| 2110 | |
| 2111 | |
| 2112 | |
| 2113 | |
| 2114 | dff #(18) d0_0 ( |
| 2115 | .l1clk(l1clk), |
| 2116 | .siclk(siclk), |
| 2117 | .soclk(soclk), |
| 2118 | .d(fdin[17:0]), |
| 2119 | .si({scan_in,so[16:0]}), |
| 2120 | .so({so[16:0],scan_out}), |
| 2121 | .q(dout[17:0]) |
| 2122 | ); |
| 2123 | |
| 2124 | |
| 2125 | |
| 2126 | |
| 2127 | |
| 2128 | |
| 2129 | |
| 2130 | |
| 2131 | |
| 2132 | |
| 2133 | |
| 2134 | |
| 2135 | endmodule |
| 2136 | |
| 2137 | |
| 2138 | |
| 2139 | |
| 2140 | |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | // Description: Spare gate macro for control blocks |
| 2146 | // |
| 2147 | // Param num controls the number of times the macro is added |
| 2148 | // flops=0 can be used to use only combination spare logic |
| 2149 | |
| 2150 | |
| 2151 | module ncu_ssisif_ctl_spare_ctl_macro__num_11 ( |
| 2152 | l1clk, |
| 2153 | scan_in, |
| 2154 | siclk, |
| 2155 | soclk, |
| 2156 | scan_out); |
| 2157 | wire si_0; |
| 2158 | wire so_0; |
| 2159 | wire spare0_flop_unused; |
| 2160 | wire spare0_buf_32x_unused; |
| 2161 | wire spare0_nand3_8x_unused; |
| 2162 | wire spare0_inv_8x_unused; |
| 2163 | wire spare0_aoi22_4x_unused; |
| 2164 | wire spare0_buf_8x_unused; |
| 2165 | wire spare0_oai22_4x_unused; |
| 2166 | wire spare0_inv_16x_unused; |
| 2167 | wire spare0_nand2_16x_unused; |
| 2168 | wire spare0_nor3_4x_unused; |
| 2169 | wire spare0_nand2_8x_unused; |
| 2170 | wire spare0_buf_16x_unused; |
| 2171 | wire spare0_nor2_16x_unused; |
| 2172 | wire spare0_inv_32x_unused; |
| 2173 | wire si_1; |
| 2174 | wire so_1; |
| 2175 | wire spare1_flop_unused; |
| 2176 | wire spare1_buf_32x_unused; |
| 2177 | wire spare1_nand3_8x_unused; |
| 2178 | wire spare1_inv_8x_unused; |
| 2179 | wire spare1_aoi22_4x_unused; |
| 2180 | wire spare1_buf_8x_unused; |
| 2181 | wire spare1_oai22_4x_unused; |
| 2182 | wire spare1_inv_16x_unused; |
| 2183 | wire spare1_nand2_16x_unused; |
| 2184 | wire spare1_nor3_4x_unused; |
| 2185 | wire spare1_nand2_8x_unused; |
| 2186 | wire spare1_buf_16x_unused; |
| 2187 | wire spare1_nor2_16x_unused; |
| 2188 | wire spare1_inv_32x_unused; |
| 2189 | wire si_2; |
| 2190 | wire so_2; |
| 2191 | wire spare2_flop_unused; |
| 2192 | wire spare2_buf_32x_unused; |
| 2193 | wire spare2_nand3_8x_unused; |
| 2194 | wire spare2_inv_8x_unused; |
| 2195 | wire spare2_aoi22_4x_unused; |
| 2196 | wire spare2_buf_8x_unused; |
| 2197 | wire spare2_oai22_4x_unused; |
| 2198 | wire spare2_inv_16x_unused; |
| 2199 | wire spare2_nand2_16x_unused; |
| 2200 | wire spare2_nor3_4x_unused; |
| 2201 | wire spare2_nand2_8x_unused; |
| 2202 | wire spare2_buf_16x_unused; |
| 2203 | wire spare2_nor2_16x_unused; |
| 2204 | wire spare2_inv_32x_unused; |
| 2205 | wire si_3; |
| 2206 | wire so_3; |
| 2207 | wire spare3_flop_unused; |
| 2208 | wire spare3_buf_32x_unused; |
| 2209 | wire spare3_nand3_8x_unused; |
| 2210 | wire spare3_inv_8x_unused; |
| 2211 | wire spare3_aoi22_4x_unused; |
| 2212 | wire spare3_buf_8x_unused; |
| 2213 | wire spare3_oai22_4x_unused; |
| 2214 | wire spare3_inv_16x_unused; |
| 2215 | wire spare3_nand2_16x_unused; |
| 2216 | wire spare3_nor3_4x_unused; |
| 2217 | wire spare3_nand2_8x_unused; |
| 2218 | wire spare3_buf_16x_unused; |
| 2219 | wire spare3_nor2_16x_unused; |
| 2220 | wire spare3_inv_32x_unused; |
| 2221 | wire si_4; |
| 2222 | wire so_4; |
| 2223 | wire spare4_flop_unused; |
| 2224 | wire spare4_buf_32x_unused; |
| 2225 | wire spare4_nand3_8x_unused; |
| 2226 | wire spare4_inv_8x_unused; |
| 2227 | wire spare4_aoi22_4x_unused; |
| 2228 | wire spare4_buf_8x_unused; |
| 2229 | wire spare4_oai22_4x_unused; |
| 2230 | wire spare4_inv_16x_unused; |
| 2231 | wire spare4_nand2_16x_unused; |
| 2232 | wire spare4_nor3_4x_unused; |
| 2233 | wire spare4_nand2_8x_unused; |
| 2234 | wire spare4_buf_16x_unused; |
| 2235 | wire spare4_nor2_16x_unused; |
| 2236 | wire spare4_inv_32x_unused; |
| 2237 | wire si_5; |
| 2238 | wire so_5; |
| 2239 | wire spare5_flop_unused; |
| 2240 | wire spare5_buf_32x_unused; |
| 2241 | wire spare5_nand3_8x_unused; |
| 2242 | wire spare5_inv_8x_unused; |
| 2243 | wire spare5_aoi22_4x_unused; |
| 2244 | wire spare5_buf_8x_unused; |
| 2245 | wire spare5_oai22_4x_unused; |
| 2246 | wire spare5_inv_16x_unused; |
| 2247 | wire spare5_nand2_16x_unused; |
| 2248 | wire spare5_nor3_4x_unused; |
| 2249 | wire spare5_nand2_8x_unused; |
| 2250 | wire spare5_buf_16x_unused; |
| 2251 | wire spare5_nor2_16x_unused; |
| 2252 | wire spare5_inv_32x_unused; |
| 2253 | wire si_6; |
| 2254 | wire so_6; |
| 2255 | wire spare6_flop_unused; |
| 2256 | wire spare6_buf_32x_unused; |
| 2257 | wire spare6_nand3_8x_unused; |
| 2258 | wire spare6_inv_8x_unused; |
| 2259 | wire spare6_aoi22_4x_unused; |
| 2260 | wire spare6_buf_8x_unused; |
| 2261 | wire spare6_oai22_4x_unused; |
| 2262 | wire spare6_inv_16x_unused; |
| 2263 | wire spare6_nand2_16x_unused; |
| 2264 | wire spare6_nor3_4x_unused; |
| 2265 | wire spare6_nand2_8x_unused; |
| 2266 | wire spare6_buf_16x_unused; |
| 2267 | wire spare6_nor2_16x_unused; |
| 2268 | wire spare6_inv_32x_unused; |
| 2269 | wire si_7; |
| 2270 | wire so_7; |
| 2271 | wire spare7_flop_unused; |
| 2272 | wire spare7_buf_32x_unused; |
| 2273 | wire spare7_nand3_8x_unused; |
| 2274 | wire spare7_inv_8x_unused; |
| 2275 | wire spare7_aoi22_4x_unused; |
| 2276 | wire spare7_buf_8x_unused; |
| 2277 | wire spare7_oai22_4x_unused; |
| 2278 | wire spare7_inv_16x_unused; |
| 2279 | wire spare7_nand2_16x_unused; |
| 2280 | wire spare7_nor3_4x_unused; |
| 2281 | wire spare7_nand2_8x_unused; |
| 2282 | wire spare7_buf_16x_unused; |
| 2283 | wire spare7_nor2_16x_unused; |
| 2284 | wire spare7_inv_32x_unused; |
| 2285 | wire si_8; |
| 2286 | wire so_8; |
| 2287 | wire spare8_flop_unused; |
| 2288 | wire spare8_buf_32x_unused; |
| 2289 | wire spare8_nand3_8x_unused; |
| 2290 | wire spare8_inv_8x_unused; |
| 2291 | wire spare8_aoi22_4x_unused; |
| 2292 | wire spare8_buf_8x_unused; |
| 2293 | wire spare8_oai22_4x_unused; |
| 2294 | wire spare8_inv_16x_unused; |
| 2295 | wire spare8_nand2_16x_unused; |
| 2296 | wire spare8_nor3_4x_unused; |
| 2297 | wire spare8_nand2_8x_unused; |
| 2298 | wire spare8_buf_16x_unused; |
| 2299 | wire spare8_nor2_16x_unused; |
| 2300 | wire spare8_inv_32x_unused; |
| 2301 | wire si_9; |
| 2302 | wire so_9; |
| 2303 | wire spare9_flop_unused; |
| 2304 | wire spare9_buf_32x_unused; |
| 2305 | wire spare9_nand3_8x_unused; |
| 2306 | wire spare9_inv_8x_unused; |
| 2307 | wire spare9_aoi22_4x_unused; |
| 2308 | wire spare9_buf_8x_unused; |
| 2309 | wire spare9_oai22_4x_unused; |
| 2310 | wire spare9_inv_16x_unused; |
| 2311 | wire spare9_nand2_16x_unused; |
| 2312 | wire spare9_nor3_4x_unused; |
| 2313 | wire spare9_nand2_8x_unused; |
| 2314 | wire spare9_buf_16x_unused; |
| 2315 | wire spare9_nor2_16x_unused; |
| 2316 | wire spare9_inv_32x_unused; |
| 2317 | wire si_10; |
| 2318 | wire so_10; |
| 2319 | wire spare10_flop_unused; |
| 2320 | wire spare10_buf_32x_unused; |
| 2321 | wire spare10_nand3_8x_unused; |
| 2322 | wire spare10_inv_8x_unused; |
| 2323 | wire spare10_aoi22_4x_unused; |
| 2324 | wire spare10_buf_8x_unused; |
| 2325 | wire spare10_oai22_4x_unused; |
| 2326 | wire spare10_inv_16x_unused; |
| 2327 | wire spare10_nand2_16x_unused; |
| 2328 | wire spare10_nor3_4x_unused; |
| 2329 | wire spare10_nand2_8x_unused; |
| 2330 | wire spare10_buf_16x_unused; |
| 2331 | wire spare10_nor2_16x_unused; |
| 2332 | wire spare10_inv_32x_unused; |
| 2333 | |
| 2334 | |
| 2335 | input l1clk; |
| 2336 | input scan_in; |
| 2337 | input siclk; |
| 2338 | input soclk; |
| 2339 | output scan_out; |
| 2340 | |
| 2341 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 2342 | .siclk(siclk), |
| 2343 | .soclk(soclk), |
| 2344 | .si(si_0), |
| 2345 | .so(so_0), |
| 2346 | .d(1'b0), |
| 2347 | .q(spare0_flop_unused)); |
| 2348 | assign si_0 = scan_in; |
| 2349 | |
| 2350 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 2351 | .out(spare0_buf_32x_unused)); |
| 2352 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 2353 | .in1(1'b1), |
| 2354 | .in2(1'b1), |
| 2355 | .out(spare0_nand3_8x_unused)); |
| 2356 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 2357 | .out(spare0_inv_8x_unused)); |
| 2358 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 2359 | .in01(1'b1), |
| 2360 | .in10(1'b1), |
| 2361 | .in11(1'b1), |
| 2362 | .out(spare0_aoi22_4x_unused)); |
| 2363 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 2364 | .out(spare0_buf_8x_unused)); |
| 2365 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 2366 | .in01(1'b1), |
| 2367 | .in10(1'b1), |
| 2368 | .in11(1'b1), |
| 2369 | .out(spare0_oai22_4x_unused)); |
| 2370 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 2371 | .out(spare0_inv_16x_unused)); |
| 2372 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 2373 | .in1(1'b1), |
| 2374 | .out(spare0_nand2_16x_unused)); |
| 2375 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 2376 | .in1(1'b0), |
| 2377 | .in2(1'b0), |
| 2378 | .out(spare0_nor3_4x_unused)); |
| 2379 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 2380 | .in1(1'b1), |
| 2381 | .out(spare0_nand2_8x_unused)); |
| 2382 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 2383 | .out(spare0_buf_16x_unused)); |
| 2384 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 2385 | .in1(1'b0), |
| 2386 | .out(spare0_nor2_16x_unused)); |
| 2387 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 2388 | .out(spare0_inv_32x_unused)); |
| 2389 | |
| 2390 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 2391 | .siclk(siclk), |
| 2392 | .soclk(soclk), |
| 2393 | .si(si_1), |
| 2394 | .so(so_1), |
| 2395 | .d(1'b0), |
| 2396 | .q(spare1_flop_unused)); |
| 2397 | assign si_1 = so_0; |
| 2398 | |
| 2399 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 2400 | .out(spare1_buf_32x_unused)); |
| 2401 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 2402 | .in1(1'b1), |
| 2403 | .in2(1'b1), |
| 2404 | .out(spare1_nand3_8x_unused)); |
| 2405 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 2406 | .out(spare1_inv_8x_unused)); |
| 2407 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 2408 | .in01(1'b1), |
| 2409 | .in10(1'b1), |
| 2410 | .in11(1'b1), |
| 2411 | .out(spare1_aoi22_4x_unused)); |
| 2412 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 2413 | .out(spare1_buf_8x_unused)); |
| 2414 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 2415 | .in01(1'b1), |
| 2416 | .in10(1'b1), |
| 2417 | .in11(1'b1), |
| 2418 | .out(spare1_oai22_4x_unused)); |
| 2419 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 2420 | .out(spare1_inv_16x_unused)); |
| 2421 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 2422 | .in1(1'b1), |
| 2423 | .out(spare1_nand2_16x_unused)); |
| 2424 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 2425 | .in1(1'b0), |
| 2426 | .in2(1'b0), |
| 2427 | .out(spare1_nor3_4x_unused)); |
| 2428 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 2429 | .in1(1'b1), |
| 2430 | .out(spare1_nand2_8x_unused)); |
| 2431 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 2432 | .out(spare1_buf_16x_unused)); |
| 2433 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 2434 | .in1(1'b0), |
| 2435 | .out(spare1_nor2_16x_unused)); |
| 2436 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 2437 | .out(spare1_inv_32x_unused)); |
| 2438 | |
| 2439 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 2440 | .siclk(siclk), |
| 2441 | .soclk(soclk), |
| 2442 | .si(si_2), |
| 2443 | .so(so_2), |
| 2444 | .d(1'b0), |
| 2445 | .q(spare2_flop_unused)); |
| 2446 | assign si_2 = so_1; |
| 2447 | |
| 2448 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 2449 | .out(spare2_buf_32x_unused)); |
| 2450 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 2451 | .in1(1'b1), |
| 2452 | .in2(1'b1), |
| 2453 | .out(spare2_nand3_8x_unused)); |
| 2454 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 2455 | .out(spare2_inv_8x_unused)); |
| 2456 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 2457 | .in01(1'b1), |
| 2458 | .in10(1'b1), |
| 2459 | .in11(1'b1), |
| 2460 | .out(spare2_aoi22_4x_unused)); |
| 2461 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 2462 | .out(spare2_buf_8x_unused)); |
| 2463 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 2464 | .in01(1'b1), |
| 2465 | .in10(1'b1), |
| 2466 | .in11(1'b1), |
| 2467 | .out(spare2_oai22_4x_unused)); |
| 2468 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 2469 | .out(spare2_inv_16x_unused)); |
| 2470 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 2471 | .in1(1'b1), |
| 2472 | .out(spare2_nand2_16x_unused)); |
| 2473 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 2474 | .in1(1'b0), |
| 2475 | .in2(1'b0), |
| 2476 | .out(spare2_nor3_4x_unused)); |
| 2477 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 2478 | .in1(1'b1), |
| 2479 | .out(spare2_nand2_8x_unused)); |
| 2480 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 2481 | .out(spare2_buf_16x_unused)); |
| 2482 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 2483 | .in1(1'b0), |
| 2484 | .out(spare2_nor2_16x_unused)); |
| 2485 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 2486 | .out(spare2_inv_32x_unused)); |
| 2487 | |
| 2488 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 2489 | .siclk(siclk), |
| 2490 | .soclk(soclk), |
| 2491 | .si(si_3), |
| 2492 | .so(so_3), |
| 2493 | .d(1'b0), |
| 2494 | .q(spare3_flop_unused)); |
| 2495 | assign si_3 = so_2; |
| 2496 | |
| 2497 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 2498 | .out(spare3_buf_32x_unused)); |
| 2499 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 2500 | .in1(1'b1), |
| 2501 | .in2(1'b1), |
| 2502 | .out(spare3_nand3_8x_unused)); |
| 2503 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 2504 | .out(spare3_inv_8x_unused)); |
| 2505 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 2506 | .in01(1'b1), |
| 2507 | .in10(1'b1), |
| 2508 | .in11(1'b1), |
| 2509 | .out(spare3_aoi22_4x_unused)); |
| 2510 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 2511 | .out(spare3_buf_8x_unused)); |
| 2512 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 2513 | .in01(1'b1), |
| 2514 | .in10(1'b1), |
| 2515 | .in11(1'b1), |
| 2516 | .out(spare3_oai22_4x_unused)); |
| 2517 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 2518 | .out(spare3_inv_16x_unused)); |
| 2519 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 2520 | .in1(1'b1), |
| 2521 | .out(spare3_nand2_16x_unused)); |
| 2522 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 2523 | .in1(1'b0), |
| 2524 | .in2(1'b0), |
| 2525 | .out(spare3_nor3_4x_unused)); |
| 2526 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 2527 | .in1(1'b1), |
| 2528 | .out(spare3_nand2_8x_unused)); |
| 2529 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 2530 | .out(spare3_buf_16x_unused)); |
| 2531 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 2532 | .in1(1'b0), |
| 2533 | .out(spare3_nor2_16x_unused)); |
| 2534 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 2535 | .out(spare3_inv_32x_unused)); |
| 2536 | |
| 2537 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), |
| 2538 | .siclk(siclk), |
| 2539 | .soclk(soclk), |
| 2540 | .si(si_4), |
| 2541 | .so(so_4), |
| 2542 | .d(1'b0), |
| 2543 | .q(spare4_flop_unused)); |
| 2544 | assign si_4 = so_3; |
| 2545 | |
| 2546 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 2547 | .out(spare4_buf_32x_unused)); |
| 2548 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 2549 | .in1(1'b1), |
| 2550 | .in2(1'b1), |
| 2551 | .out(spare4_nand3_8x_unused)); |
| 2552 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 2553 | .out(spare4_inv_8x_unused)); |
| 2554 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 2555 | .in01(1'b1), |
| 2556 | .in10(1'b1), |
| 2557 | .in11(1'b1), |
| 2558 | .out(spare4_aoi22_4x_unused)); |
| 2559 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 2560 | .out(spare4_buf_8x_unused)); |
| 2561 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 2562 | .in01(1'b1), |
| 2563 | .in10(1'b1), |
| 2564 | .in11(1'b1), |
| 2565 | .out(spare4_oai22_4x_unused)); |
| 2566 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 2567 | .out(spare4_inv_16x_unused)); |
| 2568 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 2569 | .in1(1'b1), |
| 2570 | .out(spare4_nand2_16x_unused)); |
| 2571 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 2572 | .in1(1'b0), |
| 2573 | .in2(1'b0), |
| 2574 | .out(spare4_nor3_4x_unused)); |
| 2575 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 2576 | .in1(1'b1), |
| 2577 | .out(spare4_nand2_8x_unused)); |
| 2578 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 2579 | .out(spare4_buf_16x_unused)); |
| 2580 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 2581 | .in1(1'b0), |
| 2582 | .out(spare4_nor2_16x_unused)); |
| 2583 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 2584 | .out(spare4_inv_32x_unused)); |
| 2585 | |
| 2586 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), |
| 2587 | .siclk(siclk), |
| 2588 | .soclk(soclk), |
| 2589 | .si(si_5), |
| 2590 | .so(so_5), |
| 2591 | .d(1'b0), |
| 2592 | .q(spare5_flop_unused)); |
| 2593 | assign si_5 = so_4; |
| 2594 | |
| 2595 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), |
| 2596 | .out(spare5_buf_32x_unused)); |
| 2597 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), |
| 2598 | .in1(1'b1), |
| 2599 | .in2(1'b1), |
| 2600 | .out(spare5_nand3_8x_unused)); |
| 2601 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), |
| 2602 | .out(spare5_inv_8x_unused)); |
| 2603 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), |
| 2604 | .in01(1'b1), |
| 2605 | .in10(1'b1), |
| 2606 | .in11(1'b1), |
| 2607 | .out(spare5_aoi22_4x_unused)); |
| 2608 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), |
| 2609 | .out(spare5_buf_8x_unused)); |
| 2610 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), |
| 2611 | .in01(1'b1), |
| 2612 | .in10(1'b1), |
| 2613 | .in11(1'b1), |
| 2614 | .out(spare5_oai22_4x_unused)); |
| 2615 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), |
| 2616 | .out(spare5_inv_16x_unused)); |
| 2617 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), |
| 2618 | .in1(1'b1), |
| 2619 | .out(spare5_nand2_16x_unused)); |
| 2620 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), |
| 2621 | .in1(1'b0), |
| 2622 | .in2(1'b0), |
| 2623 | .out(spare5_nor3_4x_unused)); |
| 2624 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), |
| 2625 | .in1(1'b1), |
| 2626 | .out(spare5_nand2_8x_unused)); |
| 2627 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), |
| 2628 | .out(spare5_buf_16x_unused)); |
| 2629 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), |
| 2630 | .in1(1'b0), |
| 2631 | .out(spare5_nor2_16x_unused)); |
| 2632 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), |
| 2633 | .out(spare5_inv_32x_unused)); |
| 2634 | |
| 2635 | cl_sc1_msff_8x spare6_flop (.l1clk(l1clk), |
| 2636 | .siclk(siclk), |
| 2637 | .soclk(soclk), |
| 2638 | .si(si_6), |
| 2639 | .so(so_6), |
| 2640 | .d(1'b0), |
| 2641 | .q(spare6_flop_unused)); |
| 2642 | assign si_6 = so_5; |
| 2643 | |
| 2644 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), |
| 2645 | .out(spare6_buf_32x_unused)); |
| 2646 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), |
| 2647 | .in1(1'b1), |
| 2648 | .in2(1'b1), |
| 2649 | .out(spare6_nand3_8x_unused)); |
| 2650 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), |
| 2651 | .out(spare6_inv_8x_unused)); |
| 2652 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), |
| 2653 | .in01(1'b1), |
| 2654 | .in10(1'b1), |
| 2655 | .in11(1'b1), |
| 2656 | .out(spare6_aoi22_4x_unused)); |
| 2657 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), |
| 2658 | .out(spare6_buf_8x_unused)); |
| 2659 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), |
| 2660 | .in01(1'b1), |
| 2661 | .in10(1'b1), |
| 2662 | .in11(1'b1), |
| 2663 | .out(spare6_oai22_4x_unused)); |
| 2664 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), |
| 2665 | .out(spare6_inv_16x_unused)); |
| 2666 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), |
| 2667 | .in1(1'b1), |
| 2668 | .out(spare6_nand2_16x_unused)); |
| 2669 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), |
| 2670 | .in1(1'b0), |
| 2671 | .in2(1'b0), |
| 2672 | .out(spare6_nor3_4x_unused)); |
| 2673 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), |
| 2674 | .in1(1'b1), |
| 2675 | .out(spare6_nand2_8x_unused)); |
| 2676 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), |
| 2677 | .out(spare6_buf_16x_unused)); |
| 2678 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), |
| 2679 | .in1(1'b0), |
| 2680 | .out(spare6_nor2_16x_unused)); |
| 2681 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), |
| 2682 | .out(spare6_inv_32x_unused)); |
| 2683 | |
| 2684 | cl_sc1_msff_8x spare7_flop (.l1clk(l1clk), |
| 2685 | .siclk(siclk), |
| 2686 | .soclk(soclk), |
| 2687 | .si(si_7), |
| 2688 | .so(so_7), |
| 2689 | .d(1'b0), |
| 2690 | .q(spare7_flop_unused)); |
| 2691 | assign si_7 = so_6; |
| 2692 | |
| 2693 | cl_u1_buf_32x spare7_buf_32x (.in(1'b1), |
| 2694 | .out(spare7_buf_32x_unused)); |
| 2695 | cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1), |
| 2696 | .in1(1'b1), |
| 2697 | .in2(1'b1), |
| 2698 | .out(spare7_nand3_8x_unused)); |
| 2699 | cl_u1_inv_8x spare7_inv_8x (.in(1'b1), |
| 2700 | .out(spare7_inv_8x_unused)); |
| 2701 | cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1), |
| 2702 | .in01(1'b1), |
| 2703 | .in10(1'b1), |
| 2704 | .in11(1'b1), |
| 2705 | .out(spare7_aoi22_4x_unused)); |
| 2706 | cl_u1_buf_8x spare7_buf_8x (.in(1'b1), |
| 2707 | .out(spare7_buf_8x_unused)); |
| 2708 | cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1), |
| 2709 | .in01(1'b1), |
| 2710 | .in10(1'b1), |
| 2711 | .in11(1'b1), |
| 2712 | .out(spare7_oai22_4x_unused)); |
| 2713 | cl_u1_inv_16x spare7_inv_16x (.in(1'b1), |
| 2714 | .out(spare7_inv_16x_unused)); |
| 2715 | cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1), |
| 2716 | .in1(1'b1), |
| 2717 | .out(spare7_nand2_16x_unused)); |
| 2718 | cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0), |
| 2719 | .in1(1'b0), |
| 2720 | .in2(1'b0), |
| 2721 | .out(spare7_nor3_4x_unused)); |
| 2722 | cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1), |
| 2723 | .in1(1'b1), |
| 2724 | .out(spare7_nand2_8x_unused)); |
| 2725 | cl_u1_buf_16x spare7_buf_16x (.in(1'b1), |
| 2726 | .out(spare7_buf_16x_unused)); |
| 2727 | cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0), |
| 2728 | .in1(1'b0), |
| 2729 | .out(spare7_nor2_16x_unused)); |
| 2730 | cl_u1_inv_32x spare7_inv_32x (.in(1'b1), |
| 2731 | .out(spare7_inv_32x_unused)); |
| 2732 | |
| 2733 | cl_sc1_msff_8x spare8_flop (.l1clk(l1clk), |
| 2734 | .siclk(siclk), |
| 2735 | .soclk(soclk), |
| 2736 | .si(si_8), |
| 2737 | .so(so_8), |
| 2738 | .d(1'b0), |
| 2739 | .q(spare8_flop_unused)); |
| 2740 | assign si_8 = so_7; |
| 2741 | |
| 2742 | cl_u1_buf_32x spare8_buf_32x (.in(1'b1), |
| 2743 | .out(spare8_buf_32x_unused)); |
| 2744 | cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1), |
| 2745 | .in1(1'b1), |
| 2746 | .in2(1'b1), |
| 2747 | .out(spare8_nand3_8x_unused)); |
| 2748 | cl_u1_inv_8x spare8_inv_8x (.in(1'b1), |
| 2749 | .out(spare8_inv_8x_unused)); |
| 2750 | cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1), |
| 2751 | .in01(1'b1), |
| 2752 | .in10(1'b1), |
| 2753 | .in11(1'b1), |
| 2754 | .out(spare8_aoi22_4x_unused)); |
| 2755 | cl_u1_buf_8x spare8_buf_8x (.in(1'b1), |
| 2756 | .out(spare8_buf_8x_unused)); |
| 2757 | cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1), |
| 2758 | .in01(1'b1), |
| 2759 | .in10(1'b1), |
| 2760 | .in11(1'b1), |
| 2761 | .out(spare8_oai22_4x_unused)); |
| 2762 | cl_u1_inv_16x spare8_inv_16x (.in(1'b1), |
| 2763 | .out(spare8_inv_16x_unused)); |
| 2764 | cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1), |
| 2765 | .in1(1'b1), |
| 2766 | .out(spare8_nand2_16x_unused)); |
| 2767 | cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0), |
| 2768 | .in1(1'b0), |
| 2769 | .in2(1'b0), |
| 2770 | .out(spare8_nor3_4x_unused)); |
| 2771 | cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1), |
| 2772 | .in1(1'b1), |
| 2773 | .out(spare8_nand2_8x_unused)); |
| 2774 | cl_u1_buf_16x spare8_buf_16x (.in(1'b1), |
| 2775 | .out(spare8_buf_16x_unused)); |
| 2776 | cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0), |
| 2777 | .in1(1'b0), |
| 2778 | .out(spare8_nor2_16x_unused)); |
| 2779 | cl_u1_inv_32x spare8_inv_32x (.in(1'b1), |
| 2780 | .out(spare8_inv_32x_unused)); |
| 2781 | |
| 2782 | cl_sc1_msff_8x spare9_flop (.l1clk(l1clk), |
| 2783 | .siclk(siclk), |
| 2784 | .soclk(soclk), |
| 2785 | .si(si_9), |
| 2786 | .so(so_9), |
| 2787 | .d(1'b0), |
| 2788 | .q(spare9_flop_unused)); |
| 2789 | assign si_9 = so_8; |
| 2790 | |
| 2791 | cl_u1_buf_32x spare9_buf_32x (.in(1'b1), |
| 2792 | .out(spare9_buf_32x_unused)); |
| 2793 | cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1), |
| 2794 | .in1(1'b1), |
| 2795 | .in2(1'b1), |
| 2796 | .out(spare9_nand3_8x_unused)); |
| 2797 | cl_u1_inv_8x spare9_inv_8x (.in(1'b1), |
| 2798 | .out(spare9_inv_8x_unused)); |
| 2799 | cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1), |
| 2800 | .in01(1'b1), |
| 2801 | .in10(1'b1), |
| 2802 | .in11(1'b1), |
| 2803 | .out(spare9_aoi22_4x_unused)); |
| 2804 | cl_u1_buf_8x spare9_buf_8x (.in(1'b1), |
| 2805 | .out(spare9_buf_8x_unused)); |
| 2806 | cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1), |
| 2807 | .in01(1'b1), |
| 2808 | .in10(1'b1), |
| 2809 | .in11(1'b1), |
| 2810 | .out(spare9_oai22_4x_unused)); |
| 2811 | cl_u1_inv_16x spare9_inv_16x (.in(1'b1), |
| 2812 | .out(spare9_inv_16x_unused)); |
| 2813 | cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1), |
| 2814 | .in1(1'b1), |
| 2815 | .out(spare9_nand2_16x_unused)); |
| 2816 | cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0), |
| 2817 | .in1(1'b0), |
| 2818 | .in2(1'b0), |
| 2819 | .out(spare9_nor3_4x_unused)); |
| 2820 | cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1), |
| 2821 | .in1(1'b1), |
| 2822 | .out(spare9_nand2_8x_unused)); |
| 2823 | cl_u1_buf_16x spare9_buf_16x (.in(1'b1), |
| 2824 | .out(spare9_buf_16x_unused)); |
| 2825 | cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0), |
| 2826 | .in1(1'b0), |
| 2827 | .out(spare9_nor2_16x_unused)); |
| 2828 | cl_u1_inv_32x spare9_inv_32x (.in(1'b1), |
| 2829 | .out(spare9_inv_32x_unused)); |
| 2830 | |
| 2831 | cl_sc1_msff_8x spare10_flop (.l1clk(l1clk), |
| 2832 | .siclk(siclk), |
| 2833 | .soclk(soclk), |
| 2834 | .si(si_10), |
| 2835 | .so(so_10), |
| 2836 | .d(1'b0), |
| 2837 | .q(spare10_flop_unused)); |
| 2838 | assign si_10 = so_9; |
| 2839 | |
| 2840 | cl_u1_buf_32x spare10_buf_32x (.in(1'b1), |
| 2841 | .out(spare10_buf_32x_unused)); |
| 2842 | cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1), |
| 2843 | .in1(1'b1), |
| 2844 | .in2(1'b1), |
| 2845 | .out(spare10_nand3_8x_unused)); |
| 2846 | cl_u1_inv_8x spare10_inv_8x (.in(1'b1), |
| 2847 | .out(spare10_inv_8x_unused)); |
| 2848 | cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1), |
| 2849 | .in01(1'b1), |
| 2850 | .in10(1'b1), |
| 2851 | .in11(1'b1), |
| 2852 | .out(spare10_aoi22_4x_unused)); |
| 2853 | cl_u1_buf_8x spare10_buf_8x (.in(1'b1), |
| 2854 | .out(spare10_buf_8x_unused)); |
| 2855 | cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1), |
| 2856 | .in01(1'b1), |
| 2857 | .in10(1'b1), |
| 2858 | .in11(1'b1), |
| 2859 | .out(spare10_oai22_4x_unused)); |
| 2860 | cl_u1_inv_16x spare10_inv_16x (.in(1'b1), |
| 2861 | .out(spare10_inv_16x_unused)); |
| 2862 | cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1), |
| 2863 | .in1(1'b1), |
| 2864 | .out(spare10_nand2_16x_unused)); |
| 2865 | cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0), |
| 2866 | .in1(1'b0), |
| 2867 | .in2(1'b0), |
| 2868 | .out(spare10_nor3_4x_unused)); |
| 2869 | cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1), |
| 2870 | .in1(1'b1), |
| 2871 | .out(spare10_nand2_8x_unused)); |
| 2872 | cl_u1_buf_16x spare10_buf_16x (.in(1'b1), |
| 2873 | .out(spare10_buf_16x_unused)); |
| 2874 | cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0), |
| 2875 | .in1(1'b0), |
| 2876 | .out(spare10_nor2_16x_unused)); |
| 2877 | cl_u1_inv_32x spare10_inv_32x (.in(1'b1), |
| 2878 | .out(spare10_inv_32x_unused)); |
| 2879 | assign scan_out = so_10; |
| 2880 | |
| 2881 | |
| 2882 | |
| 2883 | endmodule |
| 2884 | |