| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mac_clk_driver.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /************************************************************************* |
| 38 | * |
| 39 | * File Name : mac_clk_driver.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : mac clock driver for ASIC vendor. |
| 42 | * Parent Module: non |
| 43 | * Child Module: |
| 44 | * Interface Mod: |
| 45 | * Date Created : 12/04/2001 |
| 46 | * |
| 47 | * Copyright (c) 2020, Sun Microsystems, Inc. |
| 48 | * Sun Proprietary and Confidential |
| 49 | * |
| 50 | * Modification : |
| 51 | * |
| 52 | * Synthesis Notes: |
| 53 | * |
| 54 | *************************************************************************/ |
| 55 | |
| 56 | module mac_clk_driver ( |
| 57 | // port0 |
| 58 | rbc0_a0, |
| 59 | rbc0_b0, |
| 60 | rbc0_c0, |
| 61 | rbc0_d0, |
| 62 | rx_clk0, |
| 63 | rx_nbclk0, |
| 64 | tx_clk0, |
| 65 | tx_nbclk0, |
| 66 | tx_clk_312mhz0, |
| 67 | rbc0_a_muxd0, |
| 68 | rbc0_b_muxd0, |
| 69 | rbc0_c_muxd0, |
| 70 | rbc0_d_muxd0, |
| 71 | rx_nbclk_muxd0, |
| 72 | rx_clk_muxd0, |
| 73 | tx_nbclk_muxd0, |
| 74 | tx_clk_muxd0, |
| 75 | tx_clk_312mhz_muxd0, |
| 76 | // port1 |
| 77 | rbc0_a1, |
| 78 | rbc0_b1, |
| 79 | rbc0_c1, |
| 80 | rbc0_d1, |
| 81 | rx_clk1, |
| 82 | rx_nbclk1, |
| 83 | tx_clk1, |
| 84 | tx_nbclk1, |
| 85 | tx_clk_312mhz1, |
| 86 | rbc0_a_muxd1, |
| 87 | rbc0_b_muxd1, |
| 88 | rbc0_c_muxd1, |
| 89 | rbc0_d_muxd1, |
| 90 | rx_nbclk_muxd1, |
| 91 | rx_clk_muxd1, |
| 92 | tx_nbclk_muxd1, |
| 93 | tx_clk_muxd1, |
| 94 | tx_clk_312mhz_muxd1, |
| 95 | `ifdef NEPTUNE |
| 96 | // port2 |
| 97 | rx_bclk2, |
| 98 | rx_nclk2, |
| 99 | tx_bclk2, |
| 100 | tx_nclk2, |
| 101 | rx_bclk_muxd2, |
| 102 | rx_nclk_muxd2, |
| 103 | tx_bclk_muxd2, |
| 104 | tx_nclk_muxd2, |
| 105 | // port3 |
| 106 | rx_bclk3, |
| 107 | rx_nclk3, |
| 108 | tx_bclk3, |
| 109 | tx_nclk3, |
| 110 | rx_bclk_muxd3, |
| 111 | rx_nclk_muxd3, |
| 112 | tx_bclk_muxd3, |
| 113 | tx_nclk_muxd3, |
| 114 | `else // n2 |
| 115 | tcu_scan_mode, |
| 116 | tcu_scan_en, |
| 117 | tcu_mac_312tx_clk_stop, |
| 118 | tcu_mac_312rx_clk_stop, |
| 119 | tcu_mac_156tx_clk_stop, |
| 120 | tcu_mac_156rx_clk_stop, |
| 121 | tcu_mac_125tx_clk_stop, |
| 122 | tcu_mac_125rx_clk_stop, |
| 123 | `endif // !ifdef NEPTUNE |
| 124 | // core clock |
| 125 | clk, |
| 126 | niu_clk |
| 127 | ); |
| 128 | // port0 |
| 129 | output rbc0_a0; |
| 130 | output rbc0_b0; |
| 131 | output rbc0_c0; |
| 132 | output rbc0_d0; |
| 133 | output rx_clk0; |
| 134 | output rx_nbclk0; |
| 135 | output tx_clk0; |
| 136 | output tx_nbclk0; |
| 137 | output tx_clk_312mhz0; |
| 138 | input rbc0_a_muxd0; |
| 139 | input rbc0_b_muxd0; |
| 140 | input rbc0_c_muxd0; |
| 141 | input rbc0_d_muxd0; |
| 142 | input rx_nbclk_muxd0; |
| 143 | input rx_clk_muxd0; |
| 144 | input tx_nbclk_muxd0; |
| 145 | input tx_clk_muxd0; |
| 146 | input tx_clk_312mhz_muxd0; // TI uses esr_mac_tclk_0[1], Agere uses esr_mac_tclk_0[0] |
| 147 | // port1 |
| 148 | output rbc0_a1; |
| 149 | output rbc0_b1; |
| 150 | output rbc0_c1; |
| 151 | output rbc0_d1; |
| 152 | output rx_clk1; |
| 153 | output rx_nbclk1; |
| 154 | output tx_clk1; |
| 155 | output tx_nbclk1; |
| 156 | output tx_clk_312mhz1; |
| 157 | input rbc0_a_muxd1; |
| 158 | input rbc0_b_muxd1; |
| 159 | input rbc0_c_muxd1; |
| 160 | input rbc0_d_muxd1; |
| 161 | input rx_nbclk_muxd1; |
| 162 | input rx_clk_muxd1; |
| 163 | input tx_nbclk_muxd1; |
| 164 | input tx_clk_muxd1; |
| 165 | input tx_clk_312mhz_muxd1; // TI uses esr_mac_tclk_1[1], Agere uses esr_mac_tclk_1[0] |
| 166 | `ifdef NEPTUNE |
| 167 | // port2 |
| 168 | output rx_bclk2; |
| 169 | output rx_nclk2; |
| 170 | output tx_bclk2; |
| 171 | output tx_nclk2; |
| 172 | input rx_bclk_muxd2; |
| 173 | input rx_nclk_muxd2; |
| 174 | input tx_bclk_muxd2; |
| 175 | input tx_nclk_muxd2; |
| 176 | // port3 |
| 177 | output rx_bclk3; |
| 178 | output rx_nclk3; |
| 179 | output tx_bclk3; |
| 180 | output tx_nclk3; |
| 181 | input rx_bclk_muxd3; |
| 182 | input rx_nclk_muxd3; |
| 183 | input tx_bclk_muxd3; |
| 184 | input tx_nclk_muxd3; |
| 185 | `else // n2 |
| 186 | input tcu_scan_mode; |
| 187 | input tcu_scan_en; |
| 188 | input tcu_mac_312tx_clk_stop; |
| 189 | input tcu_mac_312rx_clk_stop; |
| 190 | input tcu_mac_156tx_clk_stop; |
| 191 | input tcu_mac_156rx_clk_stop; |
| 192 | input tcu_mac_125tx_clk_stop; |
| 193 | input tcu_mac_125rx_clk_stop; |
| 194 | `endif // !ifdef NEPTUNE |
| 195 | // core clock |
| 196 | output clk; |
| 197 | input niu_clk; |
| 198 | |
| 199 | // port0 |
| 200 | wire rbc0_a0 ; |
| 201 | wire rbc0_b0 ; |
| 202 | wire rbc0_c0 ; |
| 203 | wire rbc0_d0 ; |
| 204 | wire rx_nbclk0 ; |
| 205 | wire rx_clk0 ; |
| 206 | wire tx_nbclk0 ; |
| 207 | wire tx_clk0 ; |
| 208 | wire tx_clk_312mhz0 ; |
| 209 | // port1 |
| 210 | wire rbc0_a1 ; |
| 211 | wire rbc0_b1 ; |
| 212 | wire rbc0_c1 ; |
| 213 | wire rbc0_d1 ; |
| 214 | wire rx_nbclk1 ; |
| 215 | wire rx_clk1 ; |
| 216 | wire tx_nbclk1 ; |
| 217 | wire tx_clk1 ; |
| 218 | wire tx_clk_312mhz1 ; |
| 219 | `ifdef NEPTUNE |
| 220 | // port2 |
| 221 | wire rx_bclk2 ; |
| 222 | wire rx_nclk2 ; |
| 223 | wire tx_bclk2 ; |
| 224 | wire tx_nclk2 ; |
| 225 | // port3 |
| 226 | wire rx_bclk3 ; |
| 227 | wire rx_nclk3 ; |
| 228 | wire tx_bclk3 ; |
| 229 | wire tx_nclk3 ; |
| 230 | `else // n2 |
| 231 | `endif |
| 232 | // core clk |
| 233 | wire clk ; |
| 234 | wire niu_clk ; |
| 235 | |
| 236 | /* -------- clock tree synthesis buffer ---------- */ |
| 237 | |
| 238 | |
| 239 | `ifdef NEPTUNE |
| 240 | CtsRoot clk_CtsRoot (.Z(clk) ,.A(niu_clk)); |
| 241 | // port0 |
| 242 | CtsRoot rbc0_a0_CtsRoot (.Z(rbc0_a0) ,.A(rbc0_a_muxd0)); |
| 243 | CtsRoot rbc0_b0_CtsRoot (.Z(rbc0_b0) ,.A(rbc0_b_muxd0)); |
| 244 | CtsRoot rbc0_c0_CtsRoot (.Z(rbc0_c0) ,.A(rbc0_c_muxd0)); |
| 245 | CtsRoot rbc0_d0_CtsRoot (.Z(rbc0_d0) ,.A(rbc0_d_muxd0)); |
| 246 | CtsRoot rx_nbclk0_CtsRoot (.Z(rx_nbclk0) ,.A(rx_nbclk_muxd0)); |
| 247 | CtsRoot rx_clk0_CtsRoot (.Z(rx_clk0) ,.A(rx_clk_muxd0)); |
| 248 | CtsRoot tx_nbclk0_CtsRoot (.Z(tx_nbclk0) ,.A(tx_nbclk_muxd0)); |
| 249 | CtsRoot tx_clk0_CtsRoot (.Z(tx_clk0) ,.A(tx_clk_muxd0)); |
| 250 | CtsRoot tx_clk_312mhz0_CtsRoot (.Z(tx_clk_312mhz0) ,.A(tx_clk_312mhz_muxd0)); |
| 251 | // port1 |
| 252 | CtsRoot rbc0_a1_CtsRoot (.Z(rbc0_a1) ,.A(rbc0_a_muxd1)); |
| 253 | CtsRoot rbc0_b1_CtsRoot (.Z(rbc0_b1) ,.A(rbc0_b_muxd1)); |
| 254 | CtsRoot rbc0_c1_CtsRoot (.Z(rbc0_c1) ,.A(rbc0_c_muxd1)); |
| 255 | CtsRoot rbc0_d1_CtsRoot (.Z(rbc0_d1) ,.A(rbc0_d_muxd1)); |
| 256 | CtsRoot rx_nbclk1_CtsRoot (.Z(rx_nbclk1) ,.A(rx_nbclk_muxd1)); |
| 257 | CtsRoot rx_clk1_CtsRoot (.Z(rx_clk1) ,.A(rx_clk_muxd1)); |
| 258 | CtsRoot tx_nbclk1_CtsRoot (.Z(tx_nbclk1) ,.A(tx_nbclk_muxd1)); |
| 259 | CtsRoot tx_clk1_CtsRoot (.Z(tx_clk1) ,.A(tx_clk_muxd1)); |
| 260 | CtsRoot tx_clk_312mhz1_CtsRoot (.Z(tx_clk_312mhz1) ,.A(tx_clk_312mhz_muxd1)); |
| 261 | // port2 |
| 262 | CtsRoot rx_bclk2_CtsRoot (.Z(rx_bclk2) ,.A(rx_bclk_muxd2)); |
| 263 | CtsRoot rx_nclk2_CtsRoot (.Z(rx_nclk2) ,.A(rx_nclk_muxd2)); |
| 264 | CtsRoot tx_bclk2_CtsRoot (.Z(tx_bclk2) ,.A(tx_bclk_muxd2)); |
| 265 | CtsRoot tx_nclk2_CtsRoot (.Z(tx_nclk2) ,.A(tx_nclk_muxd2)); |
| 266 | // port3 |
| 267 | CtsRoot rx_bclk3_CtsRoot (.Z(rx_bclk3) ,.A(rx_bclk_muxd3)); |
| 268 | CtsRoot rx_nclk3_CtsRoot (.Z(rx_nclk3) ,.A(rx_nclk_muxd3)); |
| 269 | CtsRoot tx_bclk3_CtsRoot (.Z(tx_bclk3) ,.A(tx_bclk_muxd3)); |
| 270 | CtsRoot tx_nclk3_CtsRoot (.Z(tx_nclk3) ,.A(tx_nclk_muxd3)); |
| 271 | `else // n2 |
| 272 | |
| 273 | wire tcu_scan_mode; |
| 274 | wire tcu_scan_en; |
| 275 | |
| 276 | wire mac_125rx_clk_stop0; |
| 277 | wire mac_156rx_clk_stop0; |
| 278 | wire mac_312rx_clkastop0; |
| 279 | wire mac_312rx_clkbstop0; |
| 280 | wire mac_312rx_clkcstop0; |
| 281 | wire mac_312rx_clkdstop0; |
| 282 | wire mac_125tx_clk_stop0; |
| 283 | wire mac_156tx_clk_stop0; |
| 284 | wire mac_312tx_clk_stop0; |
| 285 | |
| 286 | wire mac_125rx_clk_stop1; |
| 287 | wire mac_156rx_clk_stop1; |
| 288 | wire mac_312rx_clkastop1; |
| 289 | wire mac_312rx_clkbstop1; |
| 290 | wire mac_312rx_clkcstop1; |
| 291 | wire mac_312rx_clkdstop1; |
| 292 | wire mac_125tx_clk_stop1; |
| 293 | wire mac_156tx_clk_stop1; |
| 294 | wire mac_312tx_clk_stop1; |
| 295 | |
| 296 | // vlint flag_dangling_net_within_module off |
| 297 | // vlint flag_net_has_no_load off |
| 298 | wire s0_0; |
| 299 | wire s0_1; |
| 300 | wire s0_2; |
| 301 | wire s0_3; |
| 302 | wire s0_4; |
| 303 | wire s0_5; |
| 304 | wire s0_6; |
| 305 | wire s0_7; |
| 306 | wire s0_8; |
| 307 | wire s1_0; |
| 308 | wire s1_1; |
| 309 | wire s1_2; |
| 310 | wire s1_3; |
| 311 | wire s1_4; |
| 312 | wire s1_5; |
| 313 | wire s1_6; |
| 314 | wire s1_7; |
| 315 | wire s1_8; |
| 316 | // vlint flag_net_has_no_load on |
| 317 | // vlint flag_dangling_net_within_module on |
| 318 | |
| 319 | assign clk = niu_clk ; // core_clk header is done in clkgen_mac.v |
| 320 | |
| 321 | // port0 |
| 322 | // synchronize clock stop |
| 323 | cl_a1_clksyncff_4x rx_nbclk_stop0 (.l1clk(rx_nbclk_muxd0),.d(tcu_mac_125rx_clk_stop),.q(mac_125rx_clk_stop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_0)); |
| 324 | cl_a1_clksyncff_4x rx_clk_stop0 (.l1clk(rx_clk_muxd0), .d(tcu_mac_156rx_clk_stop),.q(mac_156rx_clk_stop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_1)); |
| 325 | cl_a1_clksyncff_4x rbc0_a_stop0 (.l1clk(rbc0_a_muxd0), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkastop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_2)); |
| 326 | cl_a1_clksyncff_4x rbc0_b_stop0 (.l1clk(rbc0_b_muxd0), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkbstop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_3)); |
| 327 | cl_a1_clksyncff_4x rbc0_c_stop0 (.l1clk(rbc0_c_muxd0), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkcstop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_4)); |
| 328 | cl_a1_clksyncff_4x rbc0_d_stop0 (.l1clk(rbc0_d_muxd0), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkdstop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_5)); |
| 329 | cl_a1_clksyncff_4x tx_nbclk_stop0 (.l1clk(tx_nbclk_muxd0),.d(tcu_mac_125tx_clk_stop),.q(mac_125tx_clk_stop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_6)); |
| 330 | cl_a1_clksyncff_4x tx_clk_stop0 (.l1clk(tx_clk_muxd0), .d(tcu_mac_156tx_clk_stop),.q(mac_156tx_clk_stop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_7)); |
| 331 | cl_a1_clksyncff_4x t312_stop0(.l1clk(tx_clk_312mhz_muxd0),.d(tcu_mac_312tx_clk_stop),.q(mac_312tx_clk_stop0),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s0_8)); |
| 332 | // |
| 333 | wire mac_125rx_clk_stop_gated0 = tcu_scan_mode ? tcu_mac_125rx_clk_stop : mac_125rx_clk_stop0 ; |
| 334 | wire mac_156rx_clk_stop_gated0 = tcu_scan_mode ? tcu_mac_156rx_clk_stop : mac_156rx_clk_stop0 ; |
| 335 | wire mac_312rx_clkastop_gated0 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkastop0 ; |
| 336 | wire mac_312rx_clkbstop_gated0 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkbstop0 ; |
| 337 | wire mac_312rx_clkcstop_gated0 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkcstop0 ; |
| 338 | wire mac_312rx_clkdstop_gated0 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkdstop0 ; |
| 339 | wire mac_125tx_clk_stop_gated0 = tcu_scan_mode ? tcu_mac_125tx_clk_stop : mac_125tx_clk_stop0 ; |
| 340 | wire mac_156tx_clk_stop_gated0 = tcu_scan_mode ? tcu_mac_156tx_clk_stop : mac_156tx_clk_stop0 ; |
| 341 | wire mac_312tx_clk_stop_gated0 = tcu_scan_mode ? tcu_mac_312tx_clk_stop : mac_312tx_clk_stop0 ; |
| 342 | // Clock Tree Synthesis buffer |
| 343 | cl_a1_l1hdr_12x rx_nbclk_muxd0_l1 (.l2clk(rx_nbclk_muxd0),.se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_125rx_clk_stop_gated0),.l1clk(rx_nbclk0)); |
| 344 | cl_a1_l1hdr_12x rx_clk_muxd0_l1 (.l2clk(rx_clk_muxd0), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_156rx_clk_stop_gated0),.l1clk(rx_clk0)); |
| 345 | cl_a1_l1hdr_12x rbc0_a_muxd0_l1 (.l2clk(rbc0_a_muxd0), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkastop_gated0),.l1clk(rbc0_a0)); |
| 346 | cl_a1_l1hdr_12x rbc0_b_muxd0_l1 (.l2clk(rbc0_b_muxd0), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkbstop_gated0),.l1clk(rbc0_b0)); |
| 347 | cl_a1_l1hdr_12x rbc0_c_muxd0_l1 (.l2clk(rbc0_c_muxd0), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkcstop_gated0),.l1clk(rbc0_c0)); |
| 348 | cl_a1_l1hdr_12x rbc0_d_muxd0_l1 (.l2clk(rbc0_d_muxd0), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkdstop_gated0),.l1clk(rbc0_d0)); |
| 349 | cl_a1_l1hdr_12x tx_nbclk_muxd0_l1 (.l2clk(tx_nbclk_muxd0),.se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_125tx_clk_stop_gated0),.l1clk(tx_nbclk0)); |
| 350 | cl_a1_l1hdr_12x tx_clk_muxd0_l1 (.l2clk(tx_clk_muxd0), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_156tx_clk_stop_gated0),.l1clk(tx_clk0)); |
| 351 | cl_a1_l1hdr_12x t312_muxd0_l1(.l2clk(tx_clk_312mhz_muxd0),.se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312tx_clk_stop_gated0),.l1clk(tx_clk_312mhz0)); |
| 352 | |
| 353 | // port1 ******************************************************* |
| 354 | // synchronize clock stop |
| 355 | cl_a1_clksyncff_4x rx_nbclk_stop1 (.l1clk(rx_nbclk_muxd1),.d(tcu_mac_125rx_clk_stop),.q(mac_125rx_clk_stop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_0)); |
| 356 | cl_a1_clksyncff_4x rx_clk_stop1 (.l1clk(rx_clk_muxd1), .d(tcu_mac_156rx_clk_stop),.q(mac_156rx_clk_stop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_1)); |
| 357 | cl_a1_clksyncff_4x rbc0_a_stop1 (.l1clk(rbc0_a_muxd1), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkastop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_2)); |
| 358 | cl_a1_clksyncff_4x rbc0_b_stop1 (.l1clk(rbc0_b_muxd1), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkbstop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_3)); |
| 359 | cl_a1_clksyncff_4x rbc0_c_stop1 (.l1clk(rbc0_c_muxd1), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkcstop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_4)); |
| 360 | cl_a1_clksyncff_4x rbc0_d_stop1 (.l1clk(rbc0_d_muxd1), .d(tcu_mac_312rx_clk_stop),.q(mac_312rx_clkdstop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_5)); |
| 361 | cl_a1_clksyncff_4x tx_nbclk_stop1 (.l1clk(tx_nbclk_muxd1),.d(tcu_mac_125tx_clk_stop),.q(mac_125tx_clk_stop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_6)); |
| 362 | cl_a1_clksyncff_4x tx_clk_stop1 (.l1clk(tx_clk_muxd1), .d(tcu_mac_156tx_clk_stop),.q(mac_156tx_clk_stop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_7)); |
| 363 | cl_a1_clksyncff_4x t312_stop1(.l1clk(tx_clk_312mhz_muxd1),.d(tcu_mac_312tx_clk_stop),.q(mac_312tx_clk_stop1),.si(1'b0),.siclk(1'b0),.soclk(1'b0),.so(s1_8)); |
| 364 | // |
| 365 | wire mac_125rx_clk_stop_gated1 = tcu_scan_mode ? tcu_mac_125rx_clk_stop : mac_125rx_clk_stop1 ; |
| 366 | wire mac_156rx_clk_stop_gated1 = tcu_scan_mode ? tcu_mac_156rx_clk_stop : mac_156rx_clk_stop1 ; |
| 367 | wire mac_312rx_clkastop_gated1 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkastop1 ; |
| 368 | wire mac_312rx_clkbstop_gated1 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkbstop1 ; |
| 369 | wire mac_312rx_clkcstop_gated1 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkcstop1 ; |
| 370 | wire mac_312rx_clkdstop_gated1 = tcu_scan_mode ? tcu_mac_312rx_clk_stop : mac_312rx_clkdstop1 ; |
| 371 | wire mac_125tx_clk_stop_gated1 = tcu_scan_mode ? tcu_mac_125tx_clk_stop : mac_125tx_clk_stop1 ; |
| 372 | wire mac_156tx_clk_stop_gated1 = tcu_scan_mode ? tcu_mac_156tx_clk_stop : mac_156tx_clk_stop1 ; |
| 373 | wire mac_312tx_clk_stop_gated1 = tcu_scan_mode ? tcu_mac_312tx_clk_stop : mac_312tx_clk_stop1 ; |
| 374 | // Clock Tree Synthesis buffer |
| 375 | cl_a1_l1hdr_12x rx_nbclk_muxd1_l1 (.l2clk(rx_nbclk_muxd1),.se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_125rx_clk_stop_gated1),.l1clk(rx_nbclk1)); |
| 376 | cl_a1_l1hdr_12x rx_clk_muxd1_l1 (.l2clk(rx_clk_muxd1), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_156rx_clk_stop_gated1),.l1clk(rx_clk1)); |
| 377 | cl_a1_l1hdr_12x rbc0_a_muxd1_l1 (.l2clk(rbc0_a_muxd1), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkastop_gated1),.l1clk(rbc0_a1)); |
| 378 | cl_a1_l1hdr_12x rbc0_b_muxd1_l1 (.l2clk(rbc0_b_muxd1), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkbstop_gated1),.l1clk(rbc0_b1)); |
| 379 | cl_a1_l1hdr_12x rbc0_c_muxd1_l1 (.l2clk(rbc0_c_muxd1), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkcstop_gated1),.l1clk(rbc0_c1)); |
| 380 | cl_a1_l1hdr_12x rbc0_d_muxd1_l1 (.l2clk(rbc0_d_muxd1), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312rx_clkdstop_gated1),.l1clk(rbc0_d1)); |
| 381 | cl_a1_l1hdr_12x tx_nbclk_muxd1_l1 (.l2clk(tx_nbclk_muxd1),.se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_125tx_clk_stop_gated1),.l1clk(tx_nbclk1)); |
| 382 | cl_a1_l1hdr_12x tx_clk_muxd1_l1 (.l2clk(tx_clk_muxd1), .se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_156tx_clk_stop_gated1),.l1clk(tx_clk1)); |
| 383 | cl_a1_l1hdr_12x t312_muxd1_l1(.l2clk(tx_clk_312mhz_muxd1),.se(tcu_scan_en),.pce(1'b1),.pce_ov(1'b0),.stop(mac_312tx_clk_stop_gated1),.l1clk(tx_clk_312mhz1)); |
| 384 | // port0 |
| 385 | // assign rbc0_a0 = rbc0_a_muxd0 ; |
| 386 | // assign rbc0_b0 = rbc0_b_muxd0 ; |
| 387 | // assign rbc0_c0 = rbc0_c_muxd0 ; |
| 388 | // assign rbc0_d0 = rbc0_d_muxd0 ; |
| 389 | // assign rx_nbclk0 = rx_nbclk_muxd0 ; |
| 390 | // assign rx_clk0 = rx_clk_muxd0 ; |
| 391 | // assign tx_nbclk0 = tx_nbclk_muxd0 ; |
| 392 | // assign tx_clk0 = tx_clk_muxd0 ; |
| 393 | // assign tx_clk_312mhz0 = tx_clk_312mhz_muxd0 ; |
| 394 | // port1 |
| 395 | // assign rbc0_a1 = rbc0_a_muxd1 ; |
| 396 | // assign rbc0_b1 = rbc0_b_muxd1 ; |
| 397 | // assign rbc0_c1 = rbc0_c_muxd1 ; |
| 398 | // assign rbc0_d1 = rbc0_d_muxd1 ; |
| 399 | // assign rx_nbclk1 = rx_nbclk_muxd1 ; |
| 400 | // assign rx_clk1 = rx_clk_muxd1 ; |
| 401 | // assign tx_nbclk1 = tx_nbclk_muxd1 ; |
| 402 | // assign tx_clk1 = tx_clk_muxd1 ; |
| 403 | // assign tx_clk_312mhz1 = tx_clk_312mhz_muxd1 ; |
| 404 | // port2 |
| 405 | // assign rx_bclk2 = rx_bclk_muxd2 ; |
| 406 | // assign rx_nclk2 = rx_nclk_muxd2 ; |
| 407 | // assign tx_bclk2 = tx_bclk_muxd2 ; |
| 408 | // assign tx_nclk2 = tx_nclk_muxd2 ; |
| 409 | // port3 |
| 410 | // assign rx_bclk3 = rx_bclk_muxd3 ; |
| 411 | // assign rx_nclk3 = rx_nclk_muxd3 ; |
| 412 | // assign tx_bclk3 = tx_bclk_muxd3 ; |
| 413 | // assign tx_nclk3 = tx_nclk_muxd3 ; |
| 414 | `endif |
| 415 | |
| 416 | endmodule // mac_clk_driver |
| 417 | |
| 418 | |