| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `include "fc.vh" |
| 36 | `include "defines.vh" |
| 37 | |
| 38 | `timescale 1ps / 1ps |
| 39 | |
| 40 | module niu ( |
| 41 | XAUI0_REFCLK_N, |
| 42 | XAUI0_REFCLK_P, |
| 43 | XAUI0_RX_N, |
| 44 | XAUI0_RX_P, |
| 45 | XAUI1_RX_N, |
| 46 | XAUI1_RX_P, |
| 47 | cluster_arst_l, |
| 48 | cmp_gclk_c0_rdp, |
| 49 | cmp_gclk_c0_rtx, |
| 50 | cmp_gclk_c0_tds, |
| 51 | cmp_gclk_c1_mac, |
| 52 | dbg1_niu_dbg_sel, |
| 53 | dbg1_niu_resume, |
| 54 | dbg1_niu_stall, |
| 55 | efu_niu_4k_clr, |
| 56 | efu_niu_4k_data, |
| 57 | efu_niu_4k_xfer_en, |
| 58 | efu_niu_cfifo0_clr, |
| 59 | efu_niu_cfifo0_xfer_en, |
| 60 | efu_niu_cfifo1_clr, |
| 61 | efu_niu_cfifo1_xfer_en, |
| 62 | efu_niu_cfifo_data, |
| 63 | efu_niu_ipp0_clr, |
| 64 | efu_niu_ipp0_xfer_en, |
| 65 | efu_niu_ipp1_clr, |
| 66 | efu_niu_ipp1_xfer_en, |
| 67 | efu_niu_mac01_sfro_data, |
| 68 | efu_niu_mac0_ro_clr, |
| 69 | efu_niu_mac0_ro_xfer_en, |
| 70 | efu_niu_mac0_sf_clr, |
| 71 | efu_niu_mac0_sf_xfer_en, |
| 72 | efu_niu_mac1_ro_clr, |
| 73 | efu_niu_mac1_ro_xfer_en, |
| 74 | efu_niu_mac1_sf_clr, |
| 75 | efu_niu_mac1_sf_xfer_en, |
| 76 | efu_niu_ram0_clr, |
| 77 | efu_niu_ram0_xfer_en, |
| 78 | efu_niu_ram1_clr, |
| 79 | efu_niu_ram1_xfer_en, |
| 80 | efu_niu_ram_clr, |
| 81 | efu_niu_ram_data, |
| 82 | efu_niu_ram_xfer_en, |
| 83 | esr_atpgd, |
| 84 | gl_mac_io_clk_stop, |
| 85 | mac_125rx_test_clk, |
| 86 | mac_125tx_test_clk, |
| 87 | mac_156rx_test_clk, |
| 88 | mac_156tx_test_clk, |
| 89 | mac_312rx_test_clk, |
| 90 | mac_312tx_test_clk, |
| 91 | mdi, |
| 92 | ncu_niu_ctag_cei, |
| 93 | ncu_niu_ctag_uei, |
| 94 | ncu_niu_d_pei, |
| 95 | ncu_niu_data, |
| 96 | ncu_niu_stall, |
| 97 | ncu_niu_vld, |
| 98 | peu_mac_sbs_input, |
| 99 | rdp_rdmc_mbist_scan_in, |
| 100 | rtx_mbist_scan_in, |
| 101 | sii_niu_bqdq, |
| 102 | sii_niu_oqdq, |
| 103 | sio_niu_data, |
| 104 | sio_niu_datareq, |
| 105 | sio_niu_hdr_vld, |
| 106 | sio_niu_parity, |
| 107 | tcu_div_bypass, |
| 108 | tcu_mbist_bisi_en, |
| 109 | tcu_mbist_user_mode, |
| 110 | tcu_pce_ov, |
| 111 | tcu_rdp_rdmc_mbist_start, |
| 112 | tcu_rtx_dmo_ctl, |
| 113 | tcu_rtx_rxc_ipp0_mbist_start, |
| 114 | tcu_rtx_rxc_ipp1_mbist_start, |
| 115 | tcu_rtx_rxc_mb5_mbist_start, |
| 116 | tcu_rtx_rxc_mb6_mbist_start, |
| 117 | tcu_rtx_rxc_zcp0_mbist_start, |
| 118 | tcu_rtx_rxc_zcp1_mbist_start, |
| 119 | tcu_rtx_txc_txe0_mbist_start, |
| 120 | tcu_rtx_txc_txe1_mbist_start, |
| 121 | tcu_sbs_aclk, |
| 122 | tcu_sbs_acmode, |
| 123 | tcu_sbs_actestsignal, |
| 124 | tcu_sbs_bclk, |
| 125 | tcu_sbs_clk, |
| 126 | tcu_sbs_enbspt, |
| 127 | tcu_sbs_enbsrx, |
| 128 | tcu_sbs_enbstx, |
| 129 | tcu_sbs_scan_en, |
| 130 | tcu_sbs_uclk, |
| 131 | tcu_tds_smx_mbist_start, |
| 132 | tcu_tds_tdmc_mbist_start, |
| 133 | tds_mbist_scan_in, |
| 134 | XAUI0_AMUX, |
| 135 | XAUI0_TX_N, |
| 136 | XAUI0_TX_P, |
| 137 | XAUI1_AMUX, |
| 138 | XAUI1_TX_N, |
| 139 | XAUI1_TX_P, |
| 140 | arb0_rcr_data_req, |
| 141 | arb0_rcr_req_accept, |
| 142 | arb0_rdc_data_req, |
| 143 | arb0_rdc_req_accept, |
| 144 | arb1_rbr_req_accept, |
| 145 | arb1_rbr_req_errors, |
| 146 | esr_atpgq, |
| 147 | mac_mcu_3_sbs_output, |
| 148 | mdoe, |
| 149 | niu_dbg1_stall_ack, |
| 150 | niu_efu_4k_data, |
| 151 | niu_efu_4k_xfer_en, |
| 152 | niu_efu_cfifo0_data, |
| 153 | niu_efu_cfifo0_xfer_en, |
| 154 | niu_efu_cfifo1_data, |
| 155 | niu_efu_cfifo1_xfer_en, |
| 156 | niu_efu_ipp0_data, |
| 157 | niu_efu_ipp0_xfer_en, |
| 158 | niu_efu_ipp1_data, |
| 159 | niu_efu_ipp1_xfer_en, |
| 160 | niu_efu_mac0_ro_data, |
| 161 | niu_efu_mac0_ro_xfer_en, |
| 162 | niu_efu_mac0_sf_data, |
| 163 | niu_efu_mac0_sf_xfer_en, |
| 164 | niu_efu_mac1_ro_data, |
| 165 | niu_efu_mac1_ro_xfer_en, |
| 166 | niu_efu_mac1_sf_data, |
| 167 | niu_efu_mac1_sf_xfer_en, |
| 168 | niu_efu_ram0_data, |
| 169 | niu_efu_ram0_xfer_en, |
| 170 | niu_efu_ram1_data, |
| 171 | niu_efu_ram1_xfer_en, |
| 172 | niu_efu_ram_data, |
| 173 | niu_efu_ram_xfer_en, |
| 174 | niu_mio_debug_clock, |
| 175 | niu_mio_debug_data, |
| 176 | niu_ncu_ctag_ce, |
| 177 | niu_ncu_ctag_ue, |
| 178 | niu_ncu_d_pe, |
| 179 | niu_ncu_data, |
| 180 | niu_ncu_stall, |
| 181 | niu_ncu_vld, |
| 182 | niu_sii_data, |
| 183 | niu_sii_datareq, |
| 184 | niu_sii_hdr_vld, |
| 185 | niu_sii_parity, |
| 186 | niu_sii_reqbypass, |
| 187 | niu_sio_dq, |
| 188 | niu_txc_interrupts, |
| 189 | rdp_rdmc_mbist_scan_out, |
| 190 | rdp_rdmc_tcu_mbist_done, |
| 191 | rdp_rdmc_tcu_mbist_fail, |
| 192 | rdp_tcu_dmo_dout, |
| 193 | rtx_mbist_scan_out, |
| 194 | rtx_rxc_ipp0_tcu_mbist_done, |
| 195 | rtx_rxc_ipp0_tcu_mbist_fail, |
| 196 | rtx_rxc_ipp1_tcu_mbist_done, |
| 197 | rtx_rxc_ipp1_tcu_mbist_fail, |
| 198 | rtx_rxc_mb5_tcu_mbist_done, |
| 199 | rtx_rxc_mb5_tcu_mbist_fail, |
| 200 | rtx_rxc_mb6_tcu_mbist_done, |
| 201 | rtx_rxc_mb6_tcu_mbist_fail, |
| 202 | rtx_rxc_zcp0_tcu_mbist_done, |
| 203 | rtx_rxc_zcp0_tcu_mbist_fail, |
| 204 | rtx_rxc_zcp1_tcu_mbist_done, |
| 205 | rtx_rxc_zcp1_tcu_mbist_fail, |
| 206 | rtx_tcu_dmo_data_out, |
| 207 | rtx_txc_txe0_tcu_mbist_done, |
| 208 | rtx_txc_txe0_tcu_mbist_fail, |
| 209 | rtx_txc_txe1_tcu_mbist_done, |
| 210 | rtx_txc_txe1_tcu_mbist_fail, |
| 211 | tdmc_pio_intr, |
| 212 | tds_mbist_scan_out, |
| 213 | tds_smx_tcu_mbist_done, |
| 214 | tds_smx_tcu_mbist_fail, |
| 215 | tds_tcu_dmo_dout, |
| 216 | tds_tdmc_tcu_mbist_done, |
| 217 | tds_tdmc_tcu_mbist_fail, |
| 218 | xaui_act_led_0, |
| 219 | xaui_act_led_1, |
| 220 | xaui_link_led_0, |
| 221 | xaui_link_led_1 , |
| 222 | VDDT_ESR, |
| 223 | VDDA_ESR, |
| 224 | VDDD_ESR, |
| 225 | VDDR_ESR, |
| 226 | VSSA_ESR, |
| 227 | gl_io2x_out_c1b, |
| 228 | gl_io_out_c1b, |
| 229 | gl_rst_niu_wmr_c1b, |
| 230 | tcu_asic_aclk, |
| 231 | tcu_asic_bclk, |
| 232 | tcu_asic_scan_en, |
| 233 | tcu_asic_se_scancollar_in, |
| 234 | tcu_asic_se_scancollar_out, |
| 235 | tcu_asic_array_wr_inhibit, |
| 236 | tcu_soce_scan_out, |
| 237 | gl_rdp_io_clk_stop, |
| 238 | tcu_soc4_scan_out, |
| 239 | gl_tds_io_clk_stop, |
| 240 | tcu_socf_scan_out, |
| 241 | gl_rtx_io_clk_stop, |
| 242 | gl_rst_mac_c1b, |
| 243 | tcu_soc5_scan_out, |
| 244 | tcu_mac_testmode, |
| 245 | tcu_stcicfg, |
| 246 | tcu_stciclk, |
| 247 | esr_stcid, |
| 248 | mio_esr_testclkr, |
| 249 | mio_esr_testclkt, |
| 250 | efu_niu_fclk, |
| 251 | efu_niu_fclrz, |
| 252 | efu_niu_fdi, |
| 253 | tcu_sbs_bsinitclk, |
| 254 | tcu_srd_atpgse, |
| 255 | tcu_srd_atpgmode, |
| 256 | rdp_scan_out, |
| 257 | tds_scan_out, |
| 258 | rtx_scan_out, |
| 259 | mac_scan_out, |
| 260 | mdc, |
| 261 | esr_stciq, |
| 262 | niu_efu_fdo |
| 263 | ); |
| 264 | |
| 265 | |
| 266 | input XAUI0_REFCLK_N; |
| 267 | input XAUI0_REFCLK_P; |
| 268 | input [3:0] XAUI0_RX_N; |
| 269 | input [3:0] XAUI0_RX_P; |
| 270 | input [3:0] XAUI1_RX_N; |
| 271 | input [3:0] XAUI1_RX_P; |
| 272 | input cluster_arst_l; |
| 273 | input cmp_gclk_c0_rdp; |
| 274 | input cmp_gclk_c0_rtx; |
| 275 | input cmp_gclk_c0_tds; |
| 276 | input cmp_gclk_c1_mac; |
| 277 | input [4:0] dbg1_niu_dbg_sel; |
| 278 | input dbg1_niu_resume; |
| 279 | input dbg1_niu_stall; |
| 280 | input efu_niu_4k_clr; |
| 281 | input efu_niu_4k_data; |
| 282 | input efu_niu_4k_xfer_en; |
| 283 | input efu_niu_cfifo0_clr; |
| 284 | input efu_niu_cfifo0_xfer_en; |
| 285 | input efu_niu_cfifo1_clr; |
| 286 | input efu_niu_cfifo1_xfer_en; |
| 287 | input efu_niu_cfifo_data; |
| 288 | input efu_niu_ipp0_clr; |
| 289 | input efu_niu_ipp0_xfer_en; |
| 290 | input efu_niu_ipp1_clr; |
| 291 | input efu_niu_ipp1_xfer_en; |
| 292 | input efu_niu_mac01_sfro_data; |
| 293 | input efu_niu_mac0_ro_clr; |
| 294 | input efu_niu_mac0_ro_xfer_en; |
| 295 | input efu_niu_mac0_sf_clr; |
| 296 | input efu_niu_mac0_sf_xfer_en; |
| 297 | input efu_niu_mac1_ro_clr; |
| 298 | input efu_niu_mac1_ro_xfer_en; |
| 299 | input efu_niu_mac1_sf_clr; |
| 300 | input efu_niu_mac1_sf_xfer_en; |
| 301 | input efu_niu_ram0_clr; |
| 302 | input efu_niu_ram0_xfer_en; |
| 303 | input efu_niu_ram1_clr; |
| 304 | input efu_niu_ram1_xfer_en; |
| 305 | input efu_niu_ram_clr; |
| 306 | input efu_niu_ram_data; |
| 307 | input efu_niu_ram_xfer_en; |
| 308 | input esr_atpgd; |
| 309 | input gl_mac_io_clk_stop; |
| 310 | input mac_125rx_test_clk; |
| 311 | input mac_125tx_test_clk; |
| 312 | input mac_156rx_test_clk; |
| 313 | input mac_156tx_test_clk; |
| 314 | input mac_312rx_test_clk; |
| 315 | input mac_312tx_test_clk; |
| 316 | input mdi; |
| 317 | input ncu_niu_ctag_cei; |
| 318 | input ncu_niu_ctag_uei; |
| 319 | input ncu_niu_d_pei; |
| 320 | input [31:0] ncu_niu_data; |
| 321 | input ncu_niu_stall; |
| 322 | input ncu_niu_vld; |
| 323 | input peu_mac_sbs_input; |
| 324 | input rdp_rdmc_mbist_scan_in; |
| 325 | input rtx_mbist_scan_in; |
| 326 | input sii_niu_bqdq; |
| 327 | input sii_niu_oqdq; |
| 328 | input [127:0] sio_niu_data; |
| 329 | input sio_niu_datareq; |
| 330 | input sio_niu_hdr_vld; |
| 331 | input [7:0] sio_niu_parity; |
| 332 | input tcu_div_bypass; |
| 333 | input tcu_mbist_bisi_en; |
| 334 | input tcu_mbist_user_mode; |
| 335 | input tcu_pce_ov; |
| 336 | input tcu_rdp_rdmc_mbist_start; |
| 337 | input [2:0] tcu_rtx_dmo_ctl; |
| 338 | input tcu_rtx_rxc_ipp0_mbist_start; |
| 339 | input tcu_rtx_rxc_ipp1_mbist_start; |
| 340 | input tcu_rtx_rxc_mb5_mbist_start; |
| 341 | input tcu_rtx_rxc_mb6_mbist_start; |
| 342 | input tcu_rtx_rxc_zcp0_mbist_start; |
| 343 | input tcu_rtx_rxc_zcp1_mbist_start; |
| 344 | input tcu_rtx_txc_txe0_mbist_start; |
| 345 | input tcu_rtx_txc_txe1_mbist_start; |
| 346 | input tcu_sbs_aclk; |
| 347 | input tcu_sbs_acmode; |
| 348 | input tcu_sbs_actestsignal; |
| 349 | input tcu_sbs_bclk; |
| 350 | input tcu_sbs_clk; |
| 351 | input tcu_sbs_enbspt; |
| 352 | input tcu_sbs_enbsrx; |
| 353 | input tcu_sbs_enbstx; |
| 354 | input tcu_sbs_scan_en; |
| 355 | input tcu_sbs_uclk; |
| 356 | input tcu_tds_smx_mbist_start; |
| 357 | input tcu_tds_tdmc_mbist_start; |
| 358 | input tds_mbist_scan_in; |
| 359 | output XAUI0_AMUX; |
| 360 | output [3:0] XAUI0_TX_N; |
| 361 | output [3:0] XAUI0_TX_P; |
| 362 | output XAUI1_AMUX; |
| 363 | output [3:0] XAUI1_TX_N; |
| 364 | output [3:0] XAUI1_TX_P; |
| 365 | output arb0_rcr_data_req; |
| 366 | output arb0_rcr_req_accept; |
| 367 | output arb0_rdc_data_req; |
| 368 | output arb0_rdc_req_accept; |
| 369 | output arb1_rbr_req_accept; |
| 370 | output arb1_rbr_req_errors; |
| 371 | output esr_atpgq; |
| 372 | output mac_mcu_3_sbs_output; |
| 373 | output mdoe; |
| 374 | output niu_dbg1_stall_ack; |
| 375 | output niu_efu_4k_data; |
| 376 | output niu_efu_4k_xfer_en; |
| 377 | output niu_efu_cfifo0_data; |
| 378 | output niu_efu_cfifo0_xfer_en; |
| 379 | output niu_efu_cfifo1_data; |
| 380 | output niu_efu_cfifo1_xfer_en; |
| 381 | output niu_efu_ipp0_data; |
| 382 | output niu_efu_ipp0_xfer_en; |
| 383 | output niu_efu_ipp1_data; |
| 384 | output niu_efu_ipp1_xfer_en; |
| 385 | output niu_efu_mac0_ro_data; |
| 386 | output niu_efu_mac0_ro_xfer_en; |
| 387 | output niu_efu_mac0_sf_data; |
| 388 | output niu_efu_mac0_sf_xfer_en; |
| 389 | output niu_efu_mac1_ro_data; |
| 390 | output niu_efu_mac1_ro_xfer_en; |
| 391 | output niu_efu_mac1_sf_data; |
| 392 | output niu_efu_mac1_sf_xfer_en; |
| 393 | output niu_efu_ram0_data; |
| 394 | output niu_efu_ram0_xfer_en; |
| 395 | output niu_efu_ram1_data; |
| 396 | output niu_efu_ram1_xfer_en; |
| 397 | output niu_efu_ram_data; |
| 398 | output niu_efu_ram_xfer_en; |
| 399 | output [1:0] niu_mio_debug_clock; |
| 400 | output [31:0] niu_mio_debug_data; |
| 401 | output niu_ncu_ctag_ce; |
| 402 | output niu_ncu_ctag_ue; |
| 403 | output niu_ncu_d_pe; |
| 404 | output [31:0] niu_ncu_data; |
| 405 | output niu_ncu_stall; |
| 406 | output niu_ncu_vld; |
| 407 | output [127:0] niu_sii_data; |
| 408 | output niu_sii_datareq; |
| 409 | output niu_sii_hdr_vld; |
| 410 | output [7:0] niu_sii_parity; |
| 411 | output niu_sii_reqbypass; |
| 412 | output niu_sio_dq; |
| 413 | output niu_txc_interrupts; |
| 414 | output rdp_rdmc_mbist_scan_out; |
| 415 | output rdp_rdmc_tcu_mbist_done; |
| 416 | output rdp_rdmc_tcu_mbist_fail; |
| 417 | output [39:0] rdp_tcu_dmo_dout; |
| 418 | output rtx_mbist_scan_out; |
| 419 | output rtx_rxc_ipp0_tcu_mbist_done; |
| 420 | output rtx_rxc_ipp0_tcu_mbist_fail; |
| 421 | output rtx_rxc_ipp1_tcu_mbist_done; |
| 422 | output rtx_rxc_ipp1_tcu_mbist_fail; |
| 423 | output rtx_rxc_mb5_tcu_mbist_done; |
| 424 | output rtx_rxc_mb5_tcu_mbist_fail; |
| 425 | output rtx_rxc_mb6_tcu_mbist_done; |
| 426 | output rtx_rxc_mb6_tcu_mbist_fail; |
| 427 | output rtx_rxc_zcp0_tcu_mbist_done; |
| 428 | output rtx_rxc_zcp0_tcu_mbist_fail; |
| 429 | output rtx_rxc_zcp1_tcu_mbist_done; |
| 430 | output rtx_rxc_zcp1_tcu_mbist_fail; |
| 431 | output [39:0] rtx_tcu_dmo_data_out; |
| 432 | output rtx_txc_txe0_tcu_mbist_done; |
| 433 | output rtx_txc_txe0_tcu_mbist_fail; |
| 434 | output rtx_txc_txe1_tcu_mbist_done; |
| 435 | output rtx_txc_txe1_tcu_mbist_fail; |
| 436 | output [63:0] tdmc_pio_intr; |
| 437 | output tds_mbist_scan_out; |
| 438 | output tds_smx_tcu_mbist_done; |
| 439 | output tds_smx_tcu_mbist_fail; |
| 440 | output [39:0] tds_tcu_dmo_dout; |
| 441 | output tds_tdmc_tcu_mbist_done; |
| 442 | output tds_tdmc_tcu_mbist_fail; |
| 443 | output xaui_act_led_0; |
| 444 | output xaui_act_led_1; |
| 445 | output xaui_link_led_0; |
| 446 | output xaui_link_led_1; |
| 447 | input VDDT_ESR; |
| 448 | input VDDA_ESR; |
| 449 | input VDDD_ESR; |
| 450 | input VDDR_ESR; |
| 451 | input VSSA_ESR; |
| 452 | |
| 453 | input gl_io2x_out_c1b; |
| 454 | input gl_io_out_c1b; |
| 455 | input gl_rst_niu_wmr_c1b; |
| 456 | input tcu_asic_aclk; |
| 457 | input tcu_asic_bclk; |
| 458 | input tcu_asic_scan_en; |
| 459 | input tcu_asic_se_scancollar_in; |
| 460 | input tcu_asic_se_scancollar_out; |
| 461 | input tcu_asic_array_wr_inhibit; |
| 462 | input tcu_soce_scan_out; |
| 463 | input gl_rdp_io_clk_stop; |
| 464 | input tcu_soc4_scan_out; |
| 465 | input gl_tds_io_clk_stop; |
| 466 | input tcu_socf_scan_out; |
| 467 | input gl_rtx_io_clk_stop; |
| 468 | input gl_rst_mac_c1b; |
| 469 | input tcu_soc5_scan_out; |
| 470 | input tcu_mac_testmode; |
| 471 | input [1:0] tcu_stcicfg; |
| 472 | input tcu_stciclk; |
| 473 | input esr_stcid; |
| 474 | input mio_esr_testclkr; |
| 475 | input mio_esr_testclkt; |
| 476 | input efu_niu_fclk; |
| 477 | input efu_niu_fclrz; |
| 478 | input efu_niu_fdi; |
| 479 | input tcu_sbs_bsinitclk; |
| 480 | input tcu_srd_atpgse; |
| 481 | input [2:0] tcu_srd_atpgmode; |
| 482 | output rdp_scan_out; |
| 483 | output tds_scan_out; |
| 484 | output rtx_scan_out; |
| 485 | output mac_scan_out; |
| 486 | output mdc; |
| 487 | output esr_stciq; |
| 488 | output niu_efu_fdo; |
| 489 | |
| 490 | wire [9:0] esr_mac_rxd0_0; |
| 491 | wire [9:0] esr_mac_rxd0_1; |
| 492 | wire [9:0] esr_mac_rxd1_0; |
| 493 | wire [9:0] esr_mac_rxd1_1; |
| 494 | wire [9:0] esr_mac_rxd2_0; |
| 495 | wire [9:0] esr_mac_rxd2_1; |
| 496 | wire [9:0] esr_mac_rxd3_0; |
| 497 | wire [9:0] esr_mac_rxd3_1; |
| 498 | wire [9:0] mac_esr_txd0_0; |
| 499 | wire [9:0] mac_esr_txd0_1; |
| 500 | wire [9:0] mac_esr_txd1_0; |
| 501 | wire [9:0] mac_esr_txd1_1; |
| 502 | wire [9:0] mac_esr_txd2_0; |
| 503 | wire [9:0] mac_esr_txd2_1; |
| 504 | wire [9:0] mac_esr_txd3_0; |
| 505 | wire [9:0] mac_esr_txd3_1; |
| 506 | wire xaui_clk; |
| 507 | |
| 508 | |
| 509 | wire [23:0] dummy; |
| 510 | |
| 511 | |
| 512 | reg rdp_niu_pio_ucb_niu_clk; |
| 513 | reg rtx_txc_niu_clk; |
| 514 | reg tds_niu_smx_niu_clk; |
| 515 | reg tds_niu_smx_niu_reset_l; |
| 516 | |
| 517 | initial begin |
| 518 | rdp_niu_pio_ucb_niu_clk = 1'b0; |
| 519 | rtx_txc_niu_clk = 1'b0; |
| 520 | tds_niu_smx_niu_clk = 1'b0; |
| 521 | tds_niu_smx_niu_reset_l = 1'b0; |
| 522 | end |
| 523 | |
| 524 | always @(posedge cmp_gclk_c0_rdp) |
| 525 | rdp_niu_pio_ucb_niu_clk = #1 gl_io_out_c1b; |
| 526 | |
| 527 | always @(posedge cmp_gclk_c0_tds) |
| 528 | tds_niu_smx_niu_clk = #1 gl_io_out_c1b; |
| 529 | |
| 530 | always @(posedge cmp_gclk_c0_rtx) |
| 531 | rtx_txc_niu_clk = #1 gl_io_out_c1b; |
| 532 | |
| 533 | |
| 534 | always @(posedge tds_niu_smx_niu_clk) |
| 535 | tds_niu_smx_niu_reset_l <= cluster_arst_l; |
| 536 | |
| 537 | |
| 538 | integer shmem_key; |
| 539 | integer status; |
| 540 | initial shmem_key = 0; |
| 541 | |
| 542 | integer live_interval; |
| 543 | initial begin |
| 544 | live_interval = 0; |
| 545 | if ($test$plusargs("live_interval=")) |
| 546 | status = $value$plusargs("live_interval=%d", live_interval); |
| 547 | if(live_interval != 0) |
| 548 | forever begin |
| 549 | $display($time, " SYSTEMC: live"); |
| 550 | #live_interval; |
| 551 | end |
| 552 | end |
| 553 | |
| 554 | initial begin |
| 555 | if ($test$plusargs("dump_niu=")) begin |
| 556 | $fsdbDumpvars(0, tb_top.cpu.niu); |
| 557 | $fsdbDumpvars(0, tb_top.enet_model); |
| 558 | end |
| 559 | end |
| 560 | |
| 561 | |
| 562 | |
| 563 | niu_setup niu_setup (); |
| 564 | |
| 565 | |
| 566 | wire niu_rd; |
| 567 | wire [26:0] niu_rd_addr; |
| 568 | wire [63:0] niu_rd_data; |
| 569 | |
| 570 | niu_ncu_interface niu_ncu_interface( |
| 571 | .niu_ncu_data (niu_ncu_data), |
| 572 | .niu_ncu_vld (niu_ncu_vld), |
| 573 | .niu_ncu_stall (niu_ncu_stall), |
| 574 | .ncu_niu_data (ncu_niu_data), |
| 575 | .ncu_niu_vld (ncu_niu_vld), |
| 576 | .ncu_niu_stall (ncu_niu_stall), |
| 577 | .clk (rdp_niu_pio_ucb_niu_clk), |
| 578 | .niu_rd (niu_rd), |
| 579 | .niu_rd_addr (niu_rd_addr), |
| 580 | .niu_rd_data (niu_rd_data)); |
| 581 | |
| 582 | integer niu_csr; |
| 583 | |
| 584 | always @(niu_rd) begin |
| 585 | if(niu_rd) begin |
| 586 | $display("NIU_READ to sas: %h %h", {8'h81, 5'h0, niu_rd_addr}, niu_rd_data); |
| 587 | if (`PARGS.nas_check_on ) |
| 588 | niu_csr = $sim_send(`PLI_CSR_READ, {24'h0, 8'h81, 5'h0, niu_rd_addr}, niu_rd_data, 8'h01); |
| 589 | end |
| 590 | end |
| 591 | |
| 592 | |
| 593 | niu_siu_interface niu_siu_interface( |
| 594 | .clk (rdp_niu_pio_ucb_niu_clk), |
| 595 | .niu_sii_hdr_vld (niu_sii_hdr_vld), |
| 596 | .niu_sii_reqbypass (niu_sii_reqbypass), |
| 597 | .sio_niu_data (sio_niu_data), |
| 598 | .sio_niu_datareq (sio_niu_datareq), |
| 599 | .sio_niu_parity (sio_niu_parity), |
| 600 | .niu_sio_dq (niu_sio_dq), |
| 601 | .niu_sii_data (niu_sii_data), |
| 602 | .niu_sii_parity (niu_sii_parity), |
| 603 | .niu_sii_datareq (niu_sii_datareq), |
| 604 | .sio_niu_hdr_vld (sio_niu_hdr_vld), |
| 605 | .sii_niu_bqdq (sii_niu_bqdq), |
| 606 | .sii_niu_oqdq (sii_niu_oqdq)); |
| 607 | |
| 608 | xaui xaui0 ( |
| 609 | .XAUI_RX_N (XAUI0_RX_N), |
| 610 | .XAUI_RX_P (XAUI0_RX_P), |
| 611 | .XAUI_AMUX (XAUI0_AMUX), |
| 612 | .XAUI_TX_N (XAUI0_TX_N), |
| 613 | .XAUI_TX_P (XAUI0_TX_P), |
| 614 | .esr_mac_rxd0 (esr_mac_rxd0_0), |
| 615 | .esr_mac_rxd1 (esr_mac_rxd1_0), |
| 616 | .esr_mac_rxd2 (esr_mac_rxd2_0), |
| 617 | .esr_mac_rxd3 (esr_mac_rxd3_0), |
| 618 | .mac_esr_txd0 (mac_esr_txd0_0), |
| 619 | .mac_esr_txd1 (mac_esr_txd1_0), |
| 620 | .mac_esr_txd2 (mac_esr_txd2_0), |
| 621 | .mac_esr_txd3 (mac_esr_txd3_0), |
| 622 | .xaui_clk (xaui_clk), |
| 623 | .mac_clk (XAUI0_REFCLK_P), |
| 624 | .reset (~gl_rst_mac_c1b)); |
| 625 | |
| 626 | xaui xaui1 ( |
| 627 | .XAUI_RX_N (XAUI1_RX_N), |
| 628 | .XAUI_RX_P (XAUI1_RX_P), |
| 629 | .XAUI_AMUX (XAUI1_AMUX), |
| 630 | .XAUI_TX_N (XAUI1_TX_N), |
| 631 | .XAUI_TX_P (XAUI1_TX_P), |
| 632 | .esr_mac_rxd0 (esr_mac_rxd0_1), |
| 633 | .esr_mac_rxd1 (esr_mac_rxd1_1), |
| 634 | .esr_mac_rxd2 (esr_mac_rxd2_1), |
| 635 | .esr_mac_rxd3 (esr_mac_rxd3_1), |
| 636 | .mac_esr_txd0 (mac_esr_txd0_1), |
| 637 | .mac_esr_txd1 (mac_esr_txd1_1), |
| 638 | .mac_esr_txd2 (mac_esr_txd2_1), |
| 639 | .mac_esr_txd3 (mac_esr_txd3_1), |
| 640 | .xaui_clk (xaui_clk), |
| 641 | .mac_clk (XAUI0_REFCLK_P), |
| 642 | .reset (~gl_rst_mac_c1b)); |
| 643 | |
| 644 | niu_mac_interface niu_mac_interface ( |
| 645 | .reset (~gl_rst_mac_c1b), |
| 646 | .mac_clk (XAUI0_REFCLK_P), |
| 647 | .esr_mac_rxd0_0 (esr_mac_rxd0_0), |
| 648 | .esr_mac_rxd0_1 (esr_mac_rxd0_1), |
| 649 | .esr_mac_rxd1_0 (esr_mac_rxd1_0), |
| 650 | .esr_mac_rxd1_1 (esr_mac_rxd1_1), |
| 651 | .esr_mac_rxd2_0 (esr_mac_rxd2_0), |
| 652 | .esr_mac_rxd2_1 (esr_mac_rxd2_1), |
| 653 | .esr_mac_rxd3_0 (esr_mac_rxd3_0), |
| 654 | .esr_mac_rxd3_1 (esr_mac_rxd3_1), |
| 655 | .mac_esr_txd0_0 (mac_esr_txd0_0), |
| 656 | .mac_esr_txd0_1 (mac_esr_txd0_1), |
| 657 | .mac_esr_txd1_0 (mac_esr_txd1_0), |
| 658 | .mac_esr_txd1_1 (mac_esr_txd1_1), |
| 659 | .mac_esr_txd2_0 (mac_esr_txd2_0), |
| 660 | .mac_esr_txd2_1 (mac_esr_txd2_1), |
| 661 | .mac_esr_txd3_0 (mac_esr_txd3_0), |
| 662 | .mac_esr_txd3_1 (mac_esr_txd3_1) |
| 663 | ); |
| 664 | |
| 665 | clock_multiplier_10x clock_multiplier_10x(XAUI0_REFCLK_P, xaui_clk); |
| 666 | |
| 667 | assign arb0_rcr_data_req = 1'b0; |
| 668 | assign arb0_rcr_req_accept = 1'b0; |
| 669 | assign arb0_rdc_data_req = 1'b0; |
| 670 | assign arb0_rdc_req_accept = 1'b0; |
| 671 | assign arb1_rbr_req_accept = 1'b0; |
| 672 | assign arb1_rbr_req_errors = 1'b0; |
| 673 | assign esr_atpgq = 1'b0; |
| 674 | assign esr_stciq = 1'b0; |
| 675 | assign mac_mcu_3_sbs_output = 1'b0; |
| 676 | assign mac_scan_out = 1'b0; |
| 677 | assign mdc = 1'b1; |
| 678 | assign mdoe = 1'b1; |
| 679 | assign niu_efu_4k_data = 1'b0; |
| 680 | assign niu_efu_4k_xfer_en = 1'b0; |
| 681 | assign niu_efu_cfifo0_data = 1'b0; |
| 682 | assign niu_efu_cfifo0_xfer_en = 1'b0; |
| 683 | assign niu_efu_cfifo1_data = 1'b0; |
| 684 | assign niu_efu_cfifo1_xfer_en = 1'b0; |
| 685 | assign niu_efu_fdo = 1'b0; |
| 686 | assign niu_efu_ipp0_data = 1'b0; |
| 687 | assign niu_efu_ipp0_xfer_en = 1'b0; |
| 688 | assign niu_efu_ipp1_data = 1'b0; |
| 689 | assign niu_efu_ipp1_xfer_en = 1'b0; |
| 690 | assign niu_efu_mac0_ro_data = 1'b0; |
| 691 | assign niu_efu_mac0_ro_xfer_en = 1'b0; |
| 692 | assign niu_efu_mac0_sf_data = 1'b0; |
| 693 | assign niu_efu_mac0_sf_xfer_en = 1'b0; |
| 694 | assign niu_efu_mac1_ro_data = 1'b0; |
| 695 | assign niu_efu_mac1_ro_xfer_en = 1'b0; |
| 696 | assign niu_efu_mac1_sf_data = 1'b0; |
| 697 | assign niu_efu_mac1_sf_xfer_en = 1'b0; |
| 698 | assign niu_efu_ram0_data = 1'b0; |
| 699 | assign niu_efu_ram0_xfer_en = 1'b0; |
| 700 | assign niu_efu_ram1_data = 1'b0; |
| 701 | assign niu_efu_ram1_xfer_en = 1'b0; |
| 702 | assign niu_efu_ram_data = 1'b0; |
| 703 | assign niu_efu_ram_xfer_en = 1'b0; |
| 704 | assign niu_mio_debug_clock = 2'b00; |
| 705 | assign niu_mio_debug_data = 32'h00000000; |
| 706 | assign niu_dbg1_stall_ack = 1'b0; |
| 707 | assign niu_ncu_ctag_ce = 1'b0; |
| 708 | assign niu_ncu_ctag_ue = 1'b0; |
| 709 | assign niu_ncu_d_pe = 1'b0; |
| 710 | |
| 711 | //assign niu_ncu_data = [31:0] |
| 712 | //assign niu_ncu_stall = |
| 713 | //assign niu_ncu_vld = |
| 714 | |
| 715 | assign niu_txc_interrupts = 1'b0; |
| 716 | assign rdp_rdmc_mbist_scan_out = 1'b0; |
| 717 | assign rdp_rdmc_tcu_mbist_done = 1'b0; |
| 718 | assign rdp_rdmc_tcu_mbist_fail = 1'b0; |
| 719 | assign rdp_scan_out = 1'b0; |
| 720 | assign rdp_tcu_dmo_dout = 1'b0; |
| 721 | assign rtx_mbist_scan_out = 1'b0; |
| 722 | assign rtx_rxc_ipp0_tcu_mbist_done = 1'b0; |
| 723 | assign rtx_rxc_ipp0_tcu_mbist_fail = 1'b0; |
| 724 | assign rtx_rxc_ipp1_tcu_mbist_done = 1'b0; |
| 725 | assign rtx_rxc_ipp1_tcu_mbist_fail = 1'b0; |
| 726 | assign rtx_rxc_mb5_tcu_mbist_done = 1'b0; |
| 727 | assign rtx_rxc_mb5_tcu_mbist_fail = 1'b0; |
| 728 | assign rtx_rxc_mb6_tcu_mbist_done = 1'b0; |
| 729 | assign rtx_rxc_mb6_tcu_mbist_fail = 1'b0; |
| 730 | assign rtx_rxc_zcp0_tcu_mbist_done = 1'b0; |
| 731 | assign rtx_rxc_zcp0_tcu_mbist_fail = 1'b0; |
| 732 | assign rtx_rxc_zcp1_tcu_mbist_done = 1'b0; |
| 733 | assign rtx_rxc_zcp1_tcu_mbist_fail = 1'b0; |
| 734 | assign rtx_txc_txe0_tcu_mbist_done = 1'b0; |
| 735 | assign rtx_txc_txe0_tcu_mbist_fail = 1'b0; |
| 736 | assign rtx_txc_txe1_tcu_mbist_done = 1'b0; |
| 737 | assign rtx_txc_txe1_tcu_mbist_fail = 1'b0; |
| 738 | assign rtx_scan_out = 1'b0; |
| 739 | assign rtx_tcu_dmo_data_out = 40'h0000000000; |
| 740 | assign tdmc_pio_intr = 64'h0000000000000000; |
| 741 | assign tds_mbist_scan_out = 1'b0; |
| 742 | assign tds_scan_out = 1'b0; |
| 743 | assign tds_smx_tcu_mbist_done = 1'b0; |
| 744 | assign tds_smx_tcu_mbist_fail = 1'b0; |
| 745 | assign tds_tcu_dmo_dout = 40'h0000000000; |
| 746 | assign tds_tdmc_tcu_mbist_done = 1'b0; |
| 747 | assign tds_tdmc_tcu_mbist_fail = 1'b0; |
| 748 | assign xaui_act_led_0 = 1'b0; |
| 749 | assign xaui_act_led_1 = 1'b0; |
| 750 | assign xaui_link_led_0 = 1'b0; |
| 751 | assign xaui_link_led_1 = 1'b0; |
| 752 | |
| 753 | endmodule |
| 754 | |
| 755 | |