| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_ipp_dat_fifo_1ke.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************** |
| 36 | *********************************************************** |
| 37 | |
| 38 | Project : Niu |
| 39 | |
| 40 | File name : niu_ipp_dat_fifo_1ke.v |
| 41 | |
| 42 | Module(s) name : niu_ipp_dat_fifo_1ke |
| 43 | |
| 44 | Parent modules : niu_ipp.v |
| 45 | |
| 46 | Child modules : niu_ipp.h, sram module |
| 47 | |
| 48 | Author's name : George chu |
| 49 | |
| 50 | Date : Dec. 2003 |
| 51 | |
| 52 | Description : This file contains a 130-bit by 1k-entry regs used as |
| 53 | FIFO for receiving data from niu_ipp_hdr_fifo, and sending |
| 54 | data to DMC. |
| 55 | |
| 56 | Synthesis Notes: |
| 57 | |
| 58 | Modification History: |
| 59 | |
| 60 | Date Description |
| 61 | ---- ----------- |
| 62 | |
| 63 | ************************************************************ |
| 64 | ***********************************************************/ |
| 65 | |
| 66 | `timescale 1ns/10ps |
| 67 | |
| 68 | module niu_ipp_dat_fifo_1ke ( |
| 69 | `ifdef NEPTUNE |
| 70 | `else tcu_aclk, |
| 71 | tcu_bclk, |
| 72 | tcu_scan_en, |
| 73 | tcu_se_scancollar_in, |
| 74 | tcu_se_scancollar_out, |
| 75 | tcu_array_wr_inhibit, |
| 76 | scan_in, |
| 77 | scan_out, |
| 78 | hdr_sram_rvalue, |
| 79 | hdr_sram_rid, |
| 80 | hdr_sram_wr_en, |
| 81 | hdr_sram_red_clr, |
| 82 | sram_hdr_read_data, |
| 83 | iol2clk, |
| 84 | l2clk_2x, |
| 85 | mbi_wdata, |
| 86 | mbi_rd_adr, |
| 87 | mbi_wr_adr, |
| 88 | mbi_wr_en, |
| 89 | mbi_rd_en, |
| 90 | mbi_run, |
| 91 | mbi_rx_data_fifo_data_out, |
| 92 | `endif |
| 93 | ipp_dfifo_rden, |
| 94 | ipp_dfifo_rptr, |
| 95 | ipp_dfifo_wptr, |
| 96 | ipp_dfifo_wten, |
| 97 | ipp_dfifo_wten_2nd, |
| 98 | ipp_dfifo_dinp, |
| 99 | ipp_ecc_corrupt_sop, |
| 100 | ipp_ecc_corrupt_2nd, |
| 101 | ipp_ecc_corrupt_eop, |
| 102 | ipp_ecc_corrupt_sing, |
| 103 | ipp_ecc_corrupt_doub, |
| 104 | ipp_ecc_corrupt_no_uncor, |
| 105 | dfifo_ecc_correct_en, |
| 106 | ecc_pkt_corrupted_clr, |
| 107 | reset, |
| 108 | clk, |
| 109 | ipp_dfifo_dout, |
| 110 | ipp_dfifo_dout0_tag, |
| 111 | ipp_dmc_dat_err, |
| 112 | ipp_dmc_dat_err1, |
| 113 | ipp_dfifo_dout1, |
| 114 | ipp_dfifo_dout1_ecc, |
| 115 | ipp_dfifo_dout1_ecc_syn, |
| 116 | ecc_pkt_corrupted |
| 117 | ); |
| 118 | |
| 119 | `ifdef NEPTUNE |
| 120 | `else |
| 121 | parameter DATA_WIDTH_MINUS1 = 145; |
| 122 | parameter ADDR_WIDTH_MINUS1 = 9; |
| 123 | |
| 124 | input tcu_aclk; |
| 125 | input tcu_bclk; |
| 126 | input tcu_scan_en; |
| 127 | input tcu_se_scancollar_in; |
| 128 | input tcu_se_scancollar_out; |
| 129 | input tcu_array_wr_inhibit; |
| 130 | input scan_in; |
| 131 | output scan_out; |
| 132 | |
| 133 | input [6:0] hdr_sram_rvalue; |
| 134 | input [2:0] hdr_sram_rid; |
| 135 | input hdr_sram_wr_en; |
| 136 | input hdr_sram_red_clr; |
| 137 | output [6:0] sram_hdr_read_data; |
| 138 | |
| 139 | input iol2clk; |
| 140 | input l2clk_2x; |
| 141 | |
| 142 | input [DATA_WIDTH_MINUS1:0] mbi_wdata; |
| 143 | input [ADDR_WIDTH_MINUS1:0] mbi_rd_adr; |
| 144 | input [ADDR_WIDTH_MINUS1:0] mbi_wr_adr; |
| 145 | input mbi_wr_en; |
| 146 | input mbi_rd_en; |
| 147 | input mbi_run; |
| 148 | output [DATA_WIDTH_MINUS1:0] mbi_rx_data_fifo_data_out; |
| 149 | `endif |
| 150 | |
| 151 | input ipp_dfifo_rden; // from ipp_unload_ctl |
| 152 | input [9:0] ipp_dfifo_rptr; // from ipp_unload_ctl |
| 153 | input [9:0] ipp_dfifo_wptr; // from ipp_unload_ctl, addr[ 9:0] of 16k-byte data |
| 154 | input ipp_dfifo_wten; // from ipp_unload_ctl |
| 155 | input ipp_dfifo_wten_2nd; // from ipp_unload_ctl |
| 156 | input [129:0] ipp_dfifo_dinp; // from ipp_hfifo |
| 157 | input ipp_ecc_corrupt_sop; |
| 158 | input ipp_ecc_corrupt_2nd; |
| 159 | input ipp_ecc_corrupt_eop; |
| 160 | input ipp_ecc_corrupt_sing; |
| 161 | input ipp_ecc_corrupt_doub; |
| 162 | input ipp_ecc_corrupt_no_uncor; |
| 163 | input dfifo_ecc_correct_en; |
| 164 | input ecc_pkt_corrupted_clr; |
| 165 | |
| 166 | input reset; |
| 167 | input clk; // clock |
| 168 | |
| 169 | output [129:0] ipp_dfifo_dout; // to dmc |
| 170 | output [1:0] ipp_dfifo_dout0_tag; // to dmc |
| 171 | output ipp_dmc_dat_err; // to dmc |
| 172 | output ipp_dmc_dat_err1; |
| 173 | |
| 174 | output [129:0] ipp_dfifo_dout1; |
| 175 | output [31:0] ipp_dfifo_dout1_ecc; |
| 176 | output [15:0] ipp_dfifo_dout1_ecc_syn; |
| 177 | output ecc_pkt_corrupted; |
| 178 | |
| 179 | wire [129:0] ipp_dfifo_dout; |
| 180 | wire [1:0] ipp_dfifo_dout0_tag; |
| 181 | wire ipp_dmc_dat_err; |
| 182 | wire ipp_dmc_dat_err1; |
| 183 | |
| 184 | wire [129:0] ipp_dfifo_dout1; |
| 185 | wire [31:0] ipp_dfifo_dout1_ecc; |
| 186 | wire [15:0] ipp_dfifo_dout1_ecc_syn; |
| 187 | wire ecc_pkt_corrupted; |
| 188 | |
| 189 | wire [129:0] ipp_dfifo_dout0; |
| 190 | wire [15:0] ecc_dfifo_dout0; |
| 191 | wire [15:0] ecc_dfifo_dout1; |
| 192 | |
| 193 | wire [9:0] ipp_dfifo_rptr0; // from ipp_unload_ctl |
| 194 | wire [9:0] ipp_dfifo_rptr1; // from ipp_unload_ctl |
| 195 | |
| 196 | wire [129:0] dinp_ecc_gen_dat; |
| 197 | wire [15:0] dinp_ecc_gen_chk; |
| 198 | wire flip_ecc_gen_sop; |
| 199 | wire flip_ecc_gen_2nd; |
| 200 | wire flip_ecc_gen_eop; |
| 201 | wire flip_ecc_gen_s_e = flip_ecc_gen_sop || flip_ecc_gen_eop; |
| 202 | wire corrupt_single_bit = ipp_ecc_corrupt_doub || ipp_ecc_corrupt_sing; |
| 203 | wire corrupt_double_bit = ipp_ecc_corrupt_doub; |
| 204 | wire n_ecc_pkt_corrupted; |
| 205 | wire dinp_ecc_gen_dt98, dinp_ecc_gen_dt97, dinp_ecc_gen_dt1, dinp_ecc_gen_dt0; |
| 206 | wire [129:0] ipp_dfifo_dout1_ecc_dat_chk; |
| 207 | wire [129:0] ipp_dfifo_dout1_ecc_dat; |
| 208 | wire [129:0] ipp_dfifo_dout2_ecc_dat; |
| 209 | |
| 210 | wire [1:0] uncorr_error1_chk; |
| 211 | |
| 212 | wire [1:0] no_error1; |
| 213 | wire [1:0] error1; |
| 214 | wire [1:0] corr_error1; |
| 215 | wire [1:0] uncorr_error1; |
| 216 | wire uncorr_error1_found; |
| 217 | |
| 218 | wire corr_error1_ori_1; |
| 219 | wire uncorr_error1_chk_ori_1; |
| 220 | wire bad_tag1; |
| 221 | |
| 222 | wire uncorr_error2; |
| 223 | |
| 224 | `ifdef NEPTUNE |
| 225 | `else |
| 226 | wire scan_out; |
| 227 | wire [DATA_WIDTH_MINUS1:0] mbi_rx_data_fifo_data_out = {ecc_dfifo_dout0[15:0],ipp_dfifo_dout0[129:0]}; |
| 228 | wire [6:0] sram_hdr_read_data; |
| 229 | `endif |
| 230 | |
| 231 | //********************************************************* |
| 232 | //***** ipp_dfifo_mem (130+16)-bit x 1k-entry 16K-byte data |
| 233 | //********************************************************* |
| 234 | |
| 235 | niu_ram_1024_146 ram_1024_146_0 ( |
| 236 | `ifdef NEPTUNE |
| 237 | .clk (clk), |
| 238 | `else |
| 239 | .reset (reset), |
| 240 | .tcu_aclk (tcu_aclk), |
| 241 | .tcu_bclk (tcu_bclk), |
| 242 | .tcu_scan_en (tcu_scan_en), |
| 243 | .tcu_se_scancollar_in (tcu_se_scancollar_in), |
| 244 | .tcu_se_scancollar_out (tcu_se_scancollar_out), |
| 245 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), |
| 246 | .scan_in (scan_in), |
| 247 | .scan_out (scan_out), |
| 248 | .hdr_sram_rvalue (hdr_sram_rvalue), |
| 249 | .hdr_sram_rid (hdr_sram_rid), |
| 250 | .hdr_sram_wr_en (hdr_sram_wr_en), |
| 251 | .hdr_sram_red_clr (hdr_sram_red_clr), |
| 252 | .sram_hdr_read_data (sram_hdr_read_data), |
| 253 | .clk (iol2clk), |
| 254 | .l2clk_2x (l2clk_2x), |
| 255 | .mbi_wdata (mbi_wdata), |
| 256 | .mbi_rd_adr (mbi_rd_adr), |
| 257 | .mbi_wr_adr (mbi_wr_adr), |
| 258 | .mbi_wr_en (mbi_wr_en), |
| 259 | .mbi_rd_en (mbi_rd_en), |
| 260 | .mbi_run (mbi_run), |
| 261 | `endif .data_inp ({dinp_ecc_gen_chk[15:0],dinp_ecc_gen_dat[129:0]}), |
| 262 | .addr_rd (ipp_dfifo_rptr[9:0]), |
| 263 | .addr_wt (ipp_dfifo_wptr[9:0]), |
| 264 | .wt_enable (ipp_dfifo_wten), |
| 265 | .cs_rd (ipp_dfifo_rden /* geo 1'h */), |
| 266 | .data_out ({ecc_dfifo_dout0[15:0],ipp_dfifo_dout0[129:0]}) |
| 267 | ); |
| 268 | |
| 269 | //****** ecc generation & correction *********************************************** |
| 270 | assign flip_ecc_gen_sop = ipp_ecc_corrupt_sop && ipp_dfifo_dinp[128]; |
| 271 | assign flip_ecc_gen_2nd = ipp_ecc_corrupt_2nd && ipp_dfifo_wten_2nd; |
| 272 | assign flip_ecc_gen_eop = ipp_ecc_corrupt_eop && ipp_dfifo_dinp[129]; |
| 273 | |
| 274 | assign dinp_ecc_gen_dat[0] = flip_ecc_gen_2nd && corrupt_single_bit ? !dinp_ecc_gen_dt0 : dinp_ecc_gen_dt0; |
| 275 | assign dinp_ecc_gen_dat[1] = flip_ecc_gen_2nd && corrupt_double_bit ? !dinp_ecc_gen_dt1 : dinp_ecc_gen_dt1; |
| 276 | assign dinp_ecc_gen_dat[97] = flip_ecc_gen_s_e && corrupt_single_bit ? !dinp_ecc_gen_dt97 : dinp_ecc_gen_dt97; |
| 277 | assign dinp_ecc_gen_dat[98] = flip_ecc_gen_s_e && corrupt_double_bit ? !dinp_ecc_gen_dt98 : dinp_ecc_gen_dt98; |
| 278 | |
| 279 | assign n_ecc_pkt_corrupted = ipp_dfifo_wten && (flip_ecc_gen_sop || flip_ecc_gen_2nd || flip_ecc_gen_eop); |
| 280 | |
| 281 | niu_65data_ecc_generate niu_65data_ecc_generate_dfifo_0 ( |
| 282 | .din (ipp_dfifo_dinp[064:00]), |
| 283 | .dout ({dinp_ecc_gen_dat[064:02],dinp_ecc_gen_dt1, dinp_ecc_gen_dt0, dinp_ecc_gen_chk[07:00]}) |
| 284 | ); |
| 285 | |
| 286 | niu_65data_ecc_generate niu_65data_ecc_generate_dfifo_1 ( |
| 287 | .din (ipp_dfifo_dinp[129:65]), |
| 288 | .dout ({dinp_ecc_gen_dat[129:99],dinp_ecc_gen_dt98,dinp_ecc_gen_dt97,dinp_ecc_gen_dat[96:65], |
| 289 | dinp_ecc_gen_chk[15:08]}) |
| 290 | ); |
| 291 | |
| 292 | niu_65data_ecc_check niu_65data_ecc_check_dfifo_0 ( |
| 293 | .din ({ipp_dfifo_dout1[064:00], ecc_dfifo_dout1[07:0]}), |
| 294 | .dout ({ipp_dfifo_dout1_ecc_dat_chk[064:00],ipp_dfifo_dout1_ecc_syn[07:0]}), |
| 295 | .no_error (no_error1[0]), |
| 296 | .error (error1[0]), |
| 297 | .corr_error (corr_error1[0]), |
| 298 | .uncorr_error (uncorr_error1_chk[0]) |
| 299 | ); |
| 300 | |
| 301 | niu_65data_ecc_check niu_65data_ecc_check_dfifo_1 ( |
| 302 | .din ({ipp_dfifo_dout1[129:65], ecc_dfifo_dout1[15:8]}), |
| 303 | .dout ({ipp_dfifo_dout1_ecc_dat_chk[129:65],ipp_dfifo_dout1_ecc_syn[15:8]}), |
| 304 | .no_error (no_error1[1]), |
| 305 | .error (error1[1]), |
| 306 | .corr_error (corr_error1_ori_1), |
| 307 | .uncorr_error (uncorr_error1_chk_ori_1) |
| 308 | ); |
| 309 | |
| 310 | assign bad_tag1 = (ipp_dfifo_dout1[129] ^ ipp_dfifo_dout1_ecc_dat_chk[129]) || |
| 311 | (ipp_dfifo_dout1[128] ^ ipp_dfifo_dout1_ecc_dat_chk[128]); |
| 312 | assign corr_error1[1] = !bad_tag1 && corr_error1_ori_1; |
| 313 | assign uncorr_error1_chk[1] = bad_tag1 || uncorr_error1_chk_ori_1; |
| 314 | |
| 315 | assign uncorr_error1_found = |uncorr_error1_chk[1:0]; |
| 316 | assign uncorr_error1 = dfifo_ecc_correct_en ? uncorr_error1_chk[1:0] & {2{!ipp_ecc_corrupt_no_uncor}} : |
| 317 | error1[1:0] & {2{!ipp_ecc_corrupt_no_uncor}}; |
| 318 | assign ipp_dfifo_dout1_ecc_dat = dfifo_ecc_correct_en ? ipp_dfifo_dout1_ecc_dat_chk[129:0] : ipp_dfifo_dout1[129:0]; |
| 319 | |
| 320 | // geo_1: SOP/eop is before or after ECC?! |
| 321 | |
| 322 | //*********************************************************************************** |
| 323 | assign ipp_dfifo_dout = ipp_dfifo_dout2_ecc_dat[129:0]; |
| 324 | assign ipp_dfifo_dout0_tag = ipp_dfifo_dout0[129:128]; |
| 325 | assign ipp_dmc_dat_err1 = |uncorr_error1[1:0]; |
| 326 | assign ipp_dmc_dat_err = uncorr_error2; |
| 327 | |
| 328 | assign ipp_dfifo_dout1_ecc = {13'h0, |
| 329 | uncorr_error1_found, |
| 330 | 1'h0, |
| 331 | ipp_dfifo_rptr1[9:0], |
| 332 | uncorr_error1[1:0], |
| 333 | corr_error1[1:0], |
| 334 | error1[1:0], |
| 335 | no_error1[1] && no_error1[0] |
| 336 | }; |
| 337 | |
| 338 | ipp_reg_r_130 reg_r_130_dat1 (.di(ipp_dfifo_dout0[129:0]), .rs(reset), .ck(clk), .qo(ipp_dfifo_dout1[129:0])); |
| 339 | ipp_reg_r_16 reg_r_16_ecc1 (.di(ecc_dfifo_dout0[15:0]), .rs(reset), .ck(clk), .qo(ecc_dfifo_dout1[15:0])); |
| 340 | |
| 341 | ipp_reg_r_130 reg_r_130_dat2 (.di(ipp_dfifo_dout1_ecc_dat[129:0]), .rs(reset), .ck(clk), .qo(ipp_dfifo_dout2_ecc_dat[129:0])); |
| 342 | |
| 343 | ipp_reg_r_10 reg_r_10_rpt0 (.di(ipp_dfifo_rptr[9:0]), .rs(reset), .ck(clk), .qo(ipp_dfifo_rptr0[9:0])); |
| 344 | ipp_reg_r_10 reg_r_10_rpt1 (.di(ipp_dfifo_rptr0[9:0]), .rs(reset), .ck(clk), .qo(ipp_dfifo_rptr1[9:0])); |
| 345 | |
| 346 | ipp_reg_r_1 reg_r_1_err2 (.di(ipp_dmc_dat_err1), .rs(reset), .ck(clk), .qo(uncorr_error2)); |
| 347 | |
| 348 | ipp_reg_r_1 reg_r_1_corr (.di(n_ecc_pkt_corrupted), .rs(ecc_pkt_corrupted_clr), .ck(clk), .qo(ecc_pkt_corrupted)); |
| 349 | |
| 350 | endmodule |
| 351 | |