| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_mb0.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | /////////////////////////////////////////////////////////////////////////////// |
| 37 | // |
| 38 | // |
| 39 | // Released: 1/16/05 |
| 40 | // Contacts: carlos.castil@sun.com / shahryar.aryani@sun.com |
| 41 | // Description: Memory BIST Controller for Niagara2 NIU core |
| 42 | // Block Type: Control Block |
| 43 | // Chip Name: |
| 44 | // Unit Name: |
| 45 | // Module: |
| 46 | // Where Instantiated: |
| 47 | // |
| 48 | // |
| 49 | // (c) 2005 Sun Microsystems, Inc. |
| 50 | // Sun Proprietary/Confidential |
| 51 | // Internal use only. |
| 52 | // |
| 53 | // All rights reserved. No part of this design may be reproduced stored |
| 54 | // in a retrieval system, or transmitted, in any form or by any means, |
| 55 | // electronic, mechanical, photocopying, recording, or otherwise, without |
| 56 | // prior written permission of Sun Microsystems, Inc. |
| 57 | // |
| 58 | /////////////////////////////////////////////////////////////////////////////// |
| 59 | |
| 60 | |
| 61 | module niu_mb0 ( |
| 62 | niu_mb0_smx_table_rd_en, |
| 63 | niu_mb0_smx_table_wr_en, |
| 64 | niu_mb0_smx_store_rd_en, |
| 65 | niu_mb0_smx_store_wr_en, |
| 66 | niu_mb0_addr, |
| 67 | niu_mb0_wdata, |
| 68 | niu_mb0_run, |
| 69 | niu_tcu_mbist_fail_0, |
| 70 | niu_tcu_mbist_done_0, |
| 71 | mb0_scan_out, |
| 72 | l1clk, |
| 73 | rst_l, |
| 74 | tcu_mbist_user_mode, |
| 75 | mb0_scan_in, |
| 76 | tcu_aclk, |
| 77 | tcu_bclk, |
| 78 | tcu_niu_mbist_start_0, |
| 79 | niu_mb0_smx_table_data_out, |
| 80 | niu_mb0_smx_store_data_out, |
| 81 | tcu_mbist_bisi_en); |
| 82 | wire siclk; |
| 83 | wire soclk; |
| 84 | wire reset; |
| 85 | wire config_reg_scanin; |
| 86 | wire config_reg_scanout; |
| 87 | wire [8:0] config_in; |
| 88 | wire [8:0] config_out; |
| 89 | wire start_transition; |
| 90 | wire reset_engine; |
| 91 | wire mbist_user_loop_mode; |
| 92 | wire mbist_done; |
| 93 | wire run; |
| 94 | wire bisi; |
| 95 | wire user_mode; |
| 96 | wire user_data_mode; |
| 97 | wire user_addr_mode; |
| 98 | wire user_loop_mode; |
| 99 | wire user_cmpsel_hold; |
| 100 | wire ten_n_mode; |
| 101 | wire mbist_user_data_mode; |
| 102 | wire mbist_user_addr_mode; |
| 103 | wire mbist_user_cmpsel_hold; |
| 104 | wire mbist_ten_n_mode; |
| 105 | wire user_data_reg_scanin; |
| 106 | wire user_data_reg_scanout; |
| 107 | wire [7:0] user_data_in; |
| 108 | wire [7:0] user_data_out; |
| 109 | wire user_start_addr_reg_scanin; |
| 110 | wire user_start_addr_reg_scanout; |
| 111 | wire [5:0] user_start_addr_in; |
| 112 | wire [5:0] user_start_addr; |
| 113 | wire user_stop_addr_reg_scanin; |
| 114 | wire user_stop_addr_reg_scanout; |
| 115 | wire [5:0] user_stop_addr_in; |
| 116 | wire [5:0] user_stop_addr; |
| 117 | wire user_incr_addr_reg_scanin; |
| 118 | wire user_incr_addr_reg_scanout; |
| 119 | wire [5:0] user_incr_addr_in; |
| 120 | wire [5:0] user_incr_addr; |
| 121 | wire user_array_sel_reg_scanin; |
| 122 | wire user_array_sel_reg_scanout; |
| 123 | wire user_array_sel_in; |
| 124 | wire user_array_sel; |
| 125 | wire user_cmpsel_reg_scanin; |
| 126 | wire user_cmpsel_reg_scanout; |
| 127 | wire [1:0] user_cmpsel_in; |
| 128 | wire [1:0] user_cmpsel; |
| 129 | wire user_bisi_wr_reg_scanin; |
| 130 | wire user_bisi_wr_reg_scanout; |
| 131 | wire user_bisi_wr_mode_in; |
| 132 | wire user_bisi_wr_mode; |
| 133 | wire user_bisi_rd_reg_scanin; |
| 134 | wire user_bisi_rd_reg_scanout; |
| 135 | wire user_bisi_rd_mode_in; |
| 136 | wire user_bisi_rd_mode; |
| 137 | wire mbist_user_bisi_wr_mode; |
| 138 | wire mbist_user_bisi_wr_rd_mode; |
| 139 | wire start_transition_reg_scanin; |
| 140 | wire start_transition_reg_scanout; |
| 141 | wire start_transition_piped; |
| 142 | wire run_reg_scanin; |
| 143 | wire run_reg_scanout; |
| 144 | wire run1_reg_scanin; |
| 145 | wire run1_reg_scanout; |
| 146 | wire run1_in; |
| 147 | wire run1_out; |
| 148 | wire run2_reg_scanin; |
| 149 | wire run2_reg_scanout; |
| 150 | wire run2_in; |
| 151 | wire run2_out; |
| 152 | wire run_piped3; |
| 153 | wire msb; |
| 154 | wire control_reg_scanin; |
| 155 | wire control_reg_scanout; |
| 156 | wire [20:0] control_in; |
| 157 | wire [20:0] control_out; |
| 158 | wire bisi_wr_rd; |
| 159 | wire array_sel; |
| 160 | wire [1:0] cmpsel; |
| 161 | wire [1:0] data_control; |
| 162 | wire address_mix; |
| 163 | wire [3:0] march_element; |
| 164 | wire [5:0] array_address; |
| 165 | wire upaddress_march; |
| 166 | wire [2:0] read_write_control; |
| 167 | wire five_cycle_march; |
| 168 | wire one_cycle_march; |
| 169 | wire increment_addr; |
| 170 | wire [5:0] start_addr; |
| 171 | wire [5:0] next_array_address; |
| 172 | wire next_upaddr_march; |
| 173 | wire next_downaddr_march; |
| 174 | wire [5:0] stop_addr; |
| 175 | wire [6:0] overflow_addr; |
| 176 | wire array_sel1; |
| 177 | wire [5:0] incr_addr; |
| 178 | wire overflow; |
| 179 | wire [6:0] compare_addr; |
| 180 | wire [5:0] add; |
| 181 | wire [5:0] adj_address; |
| 182 | wire [5:0] mbist_address; |
| 183 | wire array_sel0; |
| 184 | wire increment_march_elem; |
| 185 | wire next_array_sel; |
| 186 | wire [1:0] next_cmpsel; |
| 187 | wire [1:0] next_data_control; |
| 188 | wire next_address_mix; |
| 189 | wire [3:0] next_march_element; |
| 190 | wire array_write; |
| 191 | wire array_read; |
| 192 | wire [7:0] mbist_wdata; |
| 193 | wire true_data; |
| 194 | wire [7:0] data_pattern; |
| 195 | wire done_counter_reg_scanin; |
| 196 | wire done_counter_reg_scanout; |
| 197 | wire [2:0] done_counter_in; |
| 198 | wire [2:0] done_counter_out; |
| 199 | wire done_reg_in; |
| 200 | wire done_reg_out; |
| 201 | wire done_reg_scanin; |
| 202 | wire done_reg_scanout; |
| 203 | wire data_pipe_reg1_scanin; |
| 204 | wire data_pipe_reg1_scanout; |
| 205 | wire [7:0] data_pipe_reg1_in; |
| 206 | wire [7:0] data_pipe_out1; |
| 207 | wire data_pipe_reg2_scanin; |
| 208 | wire data_pipe_reg2_scanout; |
| 209 | wire [7:0] data_pipe_reg2_in; |
| 210 | wire [7:0] data_pipe_out2; |
| 211 | wire [7:0] old_piped_data; |
| 212 | wire ren_pipe_reg1_scanin; |
| 213 | wire ren_pipe_reg1_scanout; |
| 214 | wire ren_pipe_reg1_in; |
| 215 | wire ren_pipe_out1; |
| 216 | wire ren_pipe_reg2_scanin; |
| 217 | wire ren_pipe_reg2_scanout; |
| 218 | wire ren_pipe_reg2_in; |
| 219 | wire ren_pipe_out2; |
| 220 | wire old_piped_ren; |
| 221 | wire sel_pipe_reg1_scanin; |
| 222 | wire sel_pipe_reg1_scanout; |
| 223 | wire sel_pipe_reg1_in; |
| 224 | wire sel_pipe_out1; |
| 225 | wire sel_pipe_reg2_scanin; |
| 226 | wire sel_pipe_reg2_scanout; |
| 227 | wire sel_pipe_reg2_in; |
| 228 | wire sel_pipe_out2; |
| 229 | wire old_piped_sel2; |
| 230 | wire old_piped_sel1; |
| 231 | wire cmpsel_reg1_scanin; |
| 232 | wire cmpsel_reg1_scanout; |
| 233 | wire [1:0] cmpsel_reg1_in; |
| 234 | wire [1:0] cmpsel_reg1_out1; |
| 235 | wire [1:0] cmpsel_pipe1; |
| 236 | wire read_data_pipe_reg_scanin; |
| 237 | wire read_data_pipe_reg_scanout; |
| 238 | wire [39:0] read_data_reg_in; |
| 239 | wire [39:0] read_data_reg_out; |
| 240 | wire [39:0] read_data_mux2; |
| 241 | wire [39:0] mb0_dout; |
| 242 | wire fail_out_reg_in; |
| 243 | wire fail; |
| 244 | wire fail_out_reg_out; |
| 245 | wire fail_out_reg_scanin; |
| 246 | wire fail_out_reg_scanout; |
| 247 | wire fail_reg_scanin; |
| 248 | wire fail_reg_scanout; |
| 249 | wire [1:0] fail_reg_in; |
| 250 | wire [1:0] fail_reg_out; |
| 251 | wire qual_old_fail1; |
| 252 | wire qual_old_fail0; |
| 253 | wire fail_detect; |
| 254 | wire qual_old_fail; |
| 255 | wire [145:0] read_data_mux1; |
| 256 | |
| 257 | |
| 258 | |
| 259 | |
| 260 | |
| 261 | // ///////////////////////////////////////////////////////////////////////////// |
| 262 | // Outputs |
| 263 | // ///////////////////////////////////////////////////////////////////////////// |
| 264 | |
| 265 | output niu_mb0_smx_table_rd_en; |
| 266 | output niu_mb0_smx_table_wr_en; |
| 267 | |
| 268 | output niu_mb0_smx_store_rd_en; |
| 269 | output niu_mb0_smx_store_wr_en; |
| 270 | |
| 271 | output [5:0] niu_mb0_addr; |
| 272 | output [7:0] niu_mb0_wdata; |
| 273 | |
| 274 | output niu_mb0_run; |
| 275 | |
| 276 | output niu_tcu_mbist_fail_0; |
| 277 | output niu_tcu_mbist_done_0; |
| 278 | |
| 279 | output mb0_scan_out; |
| 280 | |
| 281 | |
| 282 | // ///////////////////////////////////////////////////////////////////////////// |
| 283 | // Inputs |
| 284 | // ///////////////////////////////////////////////////////////////////////////// |
| 285 | |
| 286 | input l1clk; |
| 287 | input rst_l; |
| 288 | input tcu_mbist_user_mode; |
| 289 | |
| 290 | input mb0_scan_in; |
| 291 | |
| 292 | input tcu_aclk; |
| 293 | input tcu_bclk; |
| 294 | |
| 295 | input tcu_niu_mbist_start_0; |
| 296 | |
| 297 | input [145:0] niu_mb0_smx_table_data_out; |
| 298 | input [145:0] niu_mb0_smx_store_data_out; |
| 299 | |
| 300 | input tcu_mbist_bisi_en; |
| 301 | |
| 302 | |
| 303 | // ///////////////////////////////////////////////////////////////////////////// |
| 304 | // Scan Renames |
| 305 | // ///////////////////////////////////////////////////////////////////////////// |
| 306 | |
| 307 | // assign se = tcu_scan_en; |
| 308 | // assign pce_ov = tcu_pce_ov; |
| 309 | // assign stop = tcu_clk_stop; |
| 310 | |
| 311 | assign siclk = tcu_aclk; |
| 312 | assign soclk = tcu_bclk; |
| 313 | |
| 314 | // ///////////////////////////////////////////////////////////////////////////// |
| 315 | // Invert reset |
| 316 | // ///////////////////////////////////////////////////////////////////////////// |
| 317 | |
| 318 | assign reset = rst_l; |
| 319 | |
| 320 | |
| 321 | //////////////////////////////////////////////////////////////////////////////// |
| 322 | // Clock header |
| 323 | |
| 324 | // l1clkhdr_ctl_macro clkgen ( |
| 325 | // .l2clk (iol2clk ), |
| 326 | // .l1en (1'b1 ), |
| 327 | // .l1clk (l1clk ) |
| 328 | // ); |
| 329 | //assign siclk = 1'b0; |
| 330 | //assign soclk = 1'b0; |
| 331 | |
| 332 | |
| 333 | // ///////////////////////////////////////////////////////////////////////////// |
| 334 | // |
| 335 | // MBIST Config Register |
| 336 | // |
| 337 | // ///////////////////////////////////////////////////////////////////////////// |
| 338 | // |
| 339 | // A low to high transition on mbist_start will reset and start the engine. |
| 340 | // mbist_start must remain active high for the duration of MBIST. |
| 341 | // If mbist_start deasserts the engine will stop but not reset. |
| 342 | // Once MBIST has completed niu_tcu_mbist_done_0 will assert and the fail status |
| 343 | // signals will be valid. |
| 344 | // To run MBIST again the mbist_start signal must transition low then high. |
| 345 | // |
| 346 | // Loop on Address will disable the address mix function. |
| 347 | // |
| 348 | // ///////////////////////////////////////////////////////////////////////////// |
| 349 | |
| 350 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 config_reg ( |
| 351 | .scan_in(config_reg_scanin), |
| 352 | .scan_out(config_reg_scanout), |
| 353 | .din ( config_in[8:0] ), |
| 354 | .dout ( config_out[8:0] ), |
| 355 | .reset(reset), |
| 356 | .l1clk(l1clk), |
| 357 | .siclk(siclk), |
| 358 | .soclk(soclk)); |
| 359 | |
| 360 | |
| 361 | assign config_in[0] = tcu_niu_mbist_start_0; |
| 362 | assign config_in[1] = config_out[0]; |
| 363 | assign start_transition = config_out[0] & ~config_out[1]; |
| 364 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); |
| 365 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! |
| 366 | |
| 367 | assign config_in[2] = start_transition ? tcu_mbist_bisi_en: config_out[2]; |
| 368 | assign bisi = config_out[2]; |
| 369 | |
| 370 | assign config_in[3] = start_transition ? tcu_mbist_user_mode : config_out[3]; |
| 371 | assign user_mode = config_out[3]; |
| 372 | |
| 373 | assign config_in[4] = config_out[4]; |
| 374 | assign user_data_mode = config_out[4]; |
| 375 | |
| 376 | assign config_in[5] = config_out[5]; |
| 377 | assign user_addr_mode = config_out[5]; |
| 378 | |
| 379 | assign config_in[6] = config_out[6]; |
| 380 | assign user_loop_mode = config_out[6]; |
| 381 | |
| 382 | assign config_in[7] = config_out[7]; |
| 383 | assign user_cmpsel_hold = config_out[7]; //cmpsel_hold = 0 : Default, All cominations |
| 384 | // = 1 : |
| 385 | // User-specified cmpsel |
| 386 | |
| 387 | assign config_in[8] = config_out[8]; |
| 388 | assign ten_n_mode = config_out[8]; |
| 389 | |
| 390 | |
| 391 | assign mbist_user_data_mode = user_mode & user_data_mode; |
| 392 | assign mbist_user_addr_mode = user_mode & user_addr_mode; |
| 393 | assign mbist_user_loop_mode = user_mode & user_loop_mode; |
| 394 | assign mbist_user_cmpsel_hold = user_mode & user_cmpsel_hold; |
| 395 | assign mbist_ten_n_mode = user_mode & ten_n_mode; |
| 396 | |
| 397 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 user_data_reg ( |
| 398 | .scan_in(user_data_reg_scanin), |
| 399 | .scan_out(user_data_reg_scanout), |
| 400 | .din ( user_data_in[7:0] ), |
| 401 | .dout ( user_data_out[7:0] ), |
| 402 | .reset(reset), |
| 403 | .l1clk(l1clk), |
| 404 | .siclk(siclk), |
| 405 | .soclk(soclk)); |
| 406 | |
| 407 | |
| 408 | assign user_data_in[7:0] = user_data_out[7:0]; |
| 409 | |
| 410 | |
| 411 | // Defining User start, stop, and increment addresses. |
| 412 | |
| 413 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_6 user_start_addr_reg ( |
| 414 | .scan_in(user_start_addr_reg_scanin), |
| 415 | .scan_out(user_start_addr_reg_scanout), |
| 416 | .din ( user_start_addr_in[5:0] ), |
| 417 | .dout ( user_start_addr[5:0] ), |
| 418 | .reset(reset), |
| 419 | .l1clk(l1clk), |
| 420 | .siclk(siclk), |
| 421 | .soclk(soclk)); |
| 422 | |
| 423 | assign user_start_addr_in[5:0] = user_start_addr[5:0]; |
| 424 | |
| 425 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_6 user_stop_addr_reg ( |
| 426 | .scan_in(user_stop_addr_reg_scanin), |
| 427 | .scan_out(user_stop_addr_reg_scanout), |
| 428 | .din ( user_stop_addr_in[5:0] ), |
| 429 | .dout ( user_stop_addr[5:0] ), |
| 430 | .reset(reset), |
| 431 | .l1clk(l1clk), |
| 432 | .siclk(siclk), |
| 433 | .soclk(soclk)); |
| 434 | |
| 435 | assign user_stop_addr_in[5:0] = user_stop_addr[5:0]; |
| 436 | |
| 437 | |
| 438 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_6 user_incr_addr_reg ( |
| 439 | .scan_in(user_incr_addr_reg_scanin), |
| 440 | .scan_out(user_incr_addr_reg_scanout), |
| 441 | .din ( user_incr_addr_in[5:0] ), |
| 442 | .dout ( user_incr_addr[5:0] ), |
| 443 | .reset(reset), |
| 444 | .l1clk(l1clk), |
| 445 | .siclk(siclk), |
| 446 | .soclk(soclk)); |
| 447 | |
| 448 | assign user_incr_addr_in[5:0] = user_incr_addr[5:0]; |
| 449 | |
| 450 | // Defining User array_sel. |
| 451 | |
| 452 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 user_array_sel_reg ( |
| 453 | .scan_in(user_array_sel_reg_scanin), |
| 454 | .scan_out(user_array_sel_reg_scanout), |
| 455 | .din ( user_array_sel_in ), |
| 456 | .dout ( user_array_sel ), |
| 457 | .reset(reset), |
| 458 | .l1clk(l1clk), |
| 459 | .siclk(siclk), |
| 460 | .soclk(soclk)); |
| 461 | |
| 462 | assign user_array_sel_in = user_array_sel; |
| 463 | |
| 464 | // Defining User cmpsel. |
| 465 | |
| 466 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 user_cmpsel_reg ( |
| 467 | .scan_in(user_cmpsel_reg_scanin), |
| 468 | .scan_out(user_cmpsel_reg_scanout), |
| 469 | .din ( user_cmpsel_in[1:0] ), |
| 470 | .dout ( user_cmpsel[1:0] ), |
| 471 | .reset(reset), |
| 472 | .l1clk(l1clk), |
| 473 | .siclk(siclk), |
| 474 | .soclk(soclk)); |
| 475 | |
| 476 | assign user_cmpsel_in[1:0] = user_cmpsel[1:0]; |
| 477 | |
| 478 | // Defining user_bisi write and read registers |
| 479 | |
| 480 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_wr_reg ( |
| 481 | .scan_in(user_bisi_wr_reg_scanin), |
| 482 | .scan_out(user_bisi_wr_reg_scanout), |
| 483 | .din ( user_bisi_wr_mode_in ), |
| 484 | .dout ( user_bisi_wr_mode ), |
| 485 | .reset(reset), |
| 486 | .l1clk(l1clk), |
| 487 | .siclk(siclk), |
| 488 | .soclk(soclk)); |
| 489 | |
| 490 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; |
| 491 | |
| 492 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_rd_reg ( |
| 493 | .scan_in(user_bisi_rd_reg_scanin), |
| 494 | .scan_out(user_bisi_rd_reg_scanout), |
| 495 | .din ( user_bisi_rd_mode_in ), |
| 496 | .dout ( user_bisi_rd_mode ), |
| 497 | .reset(reset), |
| 498 | .l1clk(l1clk), |
| 499 | .siclk(siclk), |
| 500 | .soclk(soclk)); |
| 501 | |
| 502 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; |
| 503 | |
| 504 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; |
| 505 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; |
| 506 | |
| 507 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & |
| 508 | ((user_bisi_wr_mode & user_bisi_rd_mode) | |
| 509 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); |
| 510 | |
| 511 | |
| 512 | //////////////////////////////////////////////////////////////////////////////// |
| 513 | // Piping start_transition |
| 514 | //////////////////////////////////////////////////////////////////////////////// |
| 515 | |
| 516 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 start_transition_reg ( |
| 517 | .scan_in(start_transition_reg_scanin), |
| 518 | .scan_out(start_transition_reg_scanout), |
| 519 | .din ( start_transition ), |
| 520 | .dout ( start_transition_piped ), |
| 521 | .reset(reset), |
| 522 | .l1clk(l1clk), |
| 523 | .siclk(siclk), |
| 524 | .soclk(soclk)); |
| 525 | |
| 526 | |
| 527 | //////////////////////////////////////////////////////////////////////////////// |
| 528 | // Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. |
| 529 | //////////////////////////////////////////////////////////////////////////////// |
| 530 | |
| 531 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 run_reg ( |
| 532 | .scan_in(run_reg_scanin), |
| 533 | .scan_out(run_reg_scanout), |
| 534 | .din ( run ), |
| 535 | .dout ( niu_mb0_run ), |
| 536 | .reset(reset), |
| 537 | .l1clk(l1clk), |
| 538 | .siclk(siclk), |
| 539 | .soclk(soclk)); |
| 540 | |
| 541 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 run1_reg ( |
| 542 | .scan_in(run1_reg_scanin), |
| 543 | .scan_out(run1_reg_scanout), |
| 544 | .din ( run1_in ), |
| 545 | .dout ( run1_out ), |
| 546 | .reset(reset), |
| 547 | .l1clk(l1clk), |
| 548 | .siclk(siclk), |
| 549 | .soclk(soclk)); |
| 550 | |
| 551 | assign run1_in = reset_engine ? 1'b0: niu_mb0_run; |
| 552 | |
| 553 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 run2_reg ( |
| 554 | .scan_in(run2_reg_scanin), |
| 555 | .scan_out(run2_reg_scanout), |
| 556 | .din ( run2_in ), |
| 557 | .dout ( run2_out ), |
| 558 | .reset(reset), |
| 559 | .l1clk(l1clk), |
| 560 | .siclk(siclk), |
| 561 | .soclk(soclk)); |
| 562 | |
| 563 | assign run2_in = reset_engine ? 1'b0: run1_out; |
| 564 | assign run_piped3 = config_out[0] & run2_out & ~msb; |
| 565 | |
| 566 | |
| 567 | |
| 568 | |
| 569 | // ///////////////////////////////////////////////////////////////////////////// |
| 570 | // |
| 571 | // MBIST Control Register |
| 572 | // |
| 573 | // ///////////////////////////////////////////////////////////////////////////// |
| 574 | // Remove Address mix disable before delivery |
| 575 | // ///////////////////////////////////////////////////////////////////////////// |
| 576 | |
| 577 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_21 control_reg ( |
| 578 | .scan_in(control_reg_scanin), |
| 579 | .scan_out(control_reg_scanout), |
| 580 | .din ( control_in[20:0] ), |
| 581 | .dout ( control_out[20:0] ), |
| 582 | .reset(reset), |
| 583 | .l1clk(l1clk), |
| 584 | .siclk(siclk), |
| 585 | .soclk(soclk)); |
| 586 | |
| 587 | assign msb = control_out[20]; |
| 588 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[19] : 1'b1; |
| 589 | assign array_sel = user_mode ? user_array_sel : control_out[18]; |
| 590 | assign cmpsel[1:0] = mbist_user_cmpsel_hold ? user_cmpsel[1:0] : control_out[17:16]; |
| 591 | assign data_control[1:0] = control_out[15:14]; |
| 592 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0 : control_out[13]; |
| 593 | assign march_element[3:0] = control_out[12:9]; |
| 594 | |
| 595 | assign array_address[5:0] = array_sel & upaddress_march ? {1'b1, control_out[7:3]} : |
| 596 | array_sel & (~upaddress_march) ? {1'b1,~control_out[7:3]} : |
| 597 | (~array_sel) & upaddress_march ? {control_out[8:3]} : ~control_out[8:3]; |
| 598 | |
| 599 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : |
| 600 | control_out[2:0]; |
| 601 | |
| 602 | |
| 603 | assign control_in[2:0] = reset_engine ? 3'b0: |
| 604 | ~run_piped3 ? control_out[2:0]: |
| 605 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: |
| 606 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: |
| 607 | control_out[2:0] + 3'b001; |
| 608 | |
| 609 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || |
| 610 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || |
| 611 | (read_write_control[2:0] == 3'b111); |
| 612 | |
| 613 | // start_transition_piped was added to have the correct start_addr at the start |
| 614 | // of mbist during user_addr_mode |
| 615 | assign control_in[8:3] = start_transition_piped || reset_engine ? start_addr[5:0]: |
| 616 | ~run_piped3 || ~increment_addr ? control_out[8:3]: |
| 617 | next_array_address[5:0]; |
| 618 | |
| 619 | assign next_array_address[5:0] = next_upaddr_march ? start_addr[5:0]: |
| 620 | next_downaddr_march ? ~stop_addr[5:0]: |
| 621 | (overflow_addr[5:0]); // array_addr + incr_addr |
| 622 | |
| 623 | assign start_addr[5:0] = mbist_user_addr_mode ? user_start_addr[5:0]: 6'b000000; |
| 624 | assign stop_addr[5:0] = mbist_user_addr_mode ? user_stop_addr[5:0] : |
| 625 | array_sel1 ? 6'b011111 : 6'b111111; |
| 626 | |
| 627 | assign incr_addr[5:0] = mbist_user_addr_mode ? user_incr_addr[5:0] : 6'b000001; |
| 628 | |
| 629 | assign overflow_addr[6:0] = {1'b0,control_out[8:3]} + {1'b0,incr_addr[5:0]}; |
| 630 | assign overflow = compare_addr[6:0] < overflow_addr[6:0]; |
| 631 | |
| 632 | assign compare_addr[6:0] = upaddress_march ? {1'b0, stop_addr[5:0]} : |
| 633 | {1'b0, ~start_addr[5:0]}; |
| 634 | |
| 635 | |
| 636 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 637 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || |
| 638 | (march_element[3:0] == 4'h8) ) && overflow; |
| 639 | |
| 640 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || |
| 641 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && |
| 642 | overflow; |
| 643 | |
| 644 | |
| 645 | assign add[5:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || |
| 646 | (read_write_control[2:0] == 3'h3)) ? |
| 647 | adj_address[5:0]: array_address[5:0]; |
| 648 | |
| 649 | assign adj_address[5:0] = { array_address[5:2], ~array_address[1], array_address[0] }; // For all other memories, addresses are bank or row!! |
| 650 | |
| 651 | |
| 652 | assign mbist_address[5:0] = (address_mix & array_sel0) ? {add[0], add[5:1]} : |
| 653 | (address_mix & array_sel1) ? {add[5], add[0], add[4:1]} : add[5:0]; |
| 654 | |
| 655 | // Definition of the rest of the control register |
| 656 | |
| 657 | assign increment_march_elem = increment_addr && overflow; |
| 658 | |
| 659 | assign control_in[20:9] = reset_engine ? 12'b0: |
| 660 | ~run_piped3 ? control_out[20:9]: |
| 661 | {msb, bisi_wr_rd, next_array_sel, next_cmpsel[1:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} + |
| 662 | {11'b0, increment_march_elem}; |
| 663 | |
| 664 | assign next_address_mix = ( bisi | mbist_user_addr_mode) ? 1'b1 : address_mix; |
| 665 | |
| 666 | assign next_array_sel = user_mode ? 1'b1 : control_out[18]; |
| 667 | |
| 668 | assign next_cmpsel[1:0] = ( mbist_user_cmpsel_hold || (~bisi_wr_rd) || mbist_user_bisi_wr_mode ) ? 2'b11 : control_out[17:16]; |
| 669 | |
| 670 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: |
| 671 | data_control[1:0]; |
| 672 | |
| 673 | // Incorporated ten_n_mode! |
| 674 | assign next_march_element[3:0] = ( bisi || |
| 675 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || |
| 676 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) |
| 677 | && overflow ? 4'b1111: march_element[3:0]; |
| 678 | |
| 679 | |
| 680 | assign array_write = ~run_piped3 ? 1'b0: |
| 681 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || |
| 682 | (read_write_control[2:0] == 3'h1) || |
| 683 | (read_write_control[2:0] == 3'h4): |
| 684 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: |
| 685 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7) ); |
| 686 | |
| 687 | assign array_read = ~array_write && run_piped3; // && ~initialize; |
| 688 | |
| 689 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; |
| 690 | |
| 691 | |
| 692 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); |
| 693 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || |
| 694 | (march_element[3:0] == 4'h7); |
| 695 | |
| 696 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 697 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || |
| 698 | (march_element[3:0] == 4'h7); |
| 699 | |
| 700 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? |
| 701 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): |
| 702 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? |
| 703 | ((read_write_control[2:0] == 3'h1) || |
| 704 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): |
| 705 | one_cycle_march ? (march_element[3:0] == 4'h7): |
| 706 | ~(read_write_control[0] ^ march_element[0]); |
| 707 | |
| 708 | |
| 709 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: |
| 710 | mbist_user_data_mode ? user_data_out[7:0]: |
| 711 | bisi ? 8'hFF: // true_data function will invert to 8'h00 |
| 712 | (data_control[1:0] == 2'h0) ? 8'hAA: |
| 713 | (data_control[1:0] == 2'h1) ? 8'h99: |
| 714 | (data_control[1:0] == 2'h2) ? 8'hCC: |
| 715 | 8'h00; |
| 716 | |
| 717 | // ///////////////////////////////////////////////////////////////////////////// |
| 718 | // Write data and address may need pipelining !!! |
| 719 | // ///////////////////////////////////////////////////////////////////////////// |
| 720 | |
| 721 | assign niu_mb0_wdata[7:0] = mbist_wdata[7:0]; |
| 722 | assign niu_mb0_addr[5:0] = mbist_address[5:0]; |
| 723 | |
| 724 | // ///////////////////////////////////////////////////////////////////////////// |
| 725 | // Read and write selects |
| 726 | // ///////////////////////////////////////////////////////////////////////////// |
| 727 | |
| 728 | assign array_sel0 = ~array_sel; |
| 729 | assign array_sel1 = array_sel; |
| 730 | |
| 731 | assign niu_mb0_smx_table_rd_en = (array_sel0) && array_read; |
| 732 | assign niu_mb0_smx_table_wr_en = (array_sel0) && array_write; |
| 733 | |
| 734 | assign niu_mb0_smx_store_rd_en = (array_sel1) && array_read; |
| 735 | assign niu_mb0_smx_store_wr_en = (array_sel1) && array_write; |
| 736 | |
| 737 | ///////////////////////////////////////////////////////////////////////// |
| 738 | // Creating the mbist_done signal |
| 739 | ///////////////////////////////////////////////////////////////////////// |
| 740 | // Delaying mbist_done 8 clock signals after msb going high, to provide |
| 741 | // a generic solution for done going high after the last fail has come back! |
| 742 | |
| 743 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_3 done_counter_reg ( |
| 744 | .scan_in(done_counter_reg_scanin), |
| 745 | .scan_out(done_counter_reg_scanout), |
| 746 | .din ( done_counter_in[2:0] ), |
| 747 | .dout ( done_counter_out[2:0] ), |
| 748 | .reset(reset), |
| 749 | .l1clk(l1clk), |
| 750 | .siclk(siclk), |
| 751 | .soclk(soclk)); |
| 752 | |
| 753 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start |
| 754 | // goes low. |
| 755 | |
| 756 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; |
| 757 | assign done_counter_in[2:0] = reset_engine ? 3'b000: |
| 758 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: |
| 759 | done_counter_out[2:0]; |
| 760 | |
| 761 | |
| 762 | // ///////////////////////////////////////////////////////////////////////////// |
| 763 | // Done Detection |
| 764 | // ///////////////////////////////////////////////////////////////////////////// |
| 765 | |
| 766 | assign done_reg_in = mbist_done; |
| 767 | assign niu_tcu_mbist_done_0 = done_reg_out; |
| 768 | |
| 769 | |
| 770 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 done_reg ( |
| 771 | .scan_in(done_reg_scanin), |
| 772 | .scan_out(done_reg_scanout), |
| 773 | .din ( done_reg_in ), |
| 774 | .dout ( done_reg_out ), |
| 775 | .reset(reset), |
| 776 | .l1clk(l1clk), |
| 777 | .siclk(siclk), |
| 778 | .soclk(soclk)); |
| 779 | |
| 780 | |
| 781 | |
| 782 | // ///////////////////////////////////////////////////////////////////////////// |
| 783 | // Pipeline for wdata, and Read_en |
| 784 | // ///////////////////////////////////////////////////////////////////////////// |
| 785 | |
| 786 | // ///////////////////////////////////////////////////////////////////////////// |
| 787 | // Pipeline for wdata |
| 788 | // ///////////////////////////////////////////////////////////////////////////// |
| 789 | |
| 790 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg1 ( |
| 791 | .scan_in(data_pipe_reg1_scanin), |
| 792 | .scan_out(data_pipe_reg1_scanout), |
| 793 | .din ( data_pipe_reg1_in[7:0] ), |
| 794 | .dout ( data_pipe_out1[7:0] ), |
| 795 | .reset(reset), |
| 796 | .l1clk(l1clk), |
| 797 | .siclk(siclk), |
| 798 | .soclk(soclk)); |
| 799 | |
| 800 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg2 ( |
| 801 | .scan_in(data_pipe_reg2_scanin), |
| 802 | .scan_out(data_pipe_reg2_scanout), |
| 803 | .din ( data_pipe_reg2_in[7:0] ), |
| 804 | .dout ( data_pipe_out2[7:0] ), |
| 805 | .reset(reset), |
| 806 | .l1clk(l1clk), |
| 807 | .siclk(siclk), |
| 808 | .soclk(soclk)); |
| 809 | |
| 810 | //Adding an extra level of pipe since piping the read_data |
| 811 | //msff_ctl_macro data_pipe_reg3 (width=8, library=a1, reset=1)( |
| 812 | // .scan_in(data_pipe_reg3_scanin), |
| 813 | // .scan_out(data_pipe_reg3_scanout), |
| 814 | // .din ( data_pipe_reg3_in[7:0] ), |
| 815 | // .dout ( data_pipe_out3[7:0] )); |
| 816 | |
| 817 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: niu_mb0_wdata[7:0]; |
| 818 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; |
| 819 | //assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; |
| 820 | //assign old_piped_data[7:0] = data_pipe_out3[7:0]; |
| 821 | assign old_piped_data[7:0] = data_pipe_out2[7:0]; |
| 822 | |
| 823 | // ///////////////////////////////////////////////////////////////////////////// |
| 824 | // Pipeline for Read_en |
| 825 | // ///////////////////////////////////////////////////////////////////////////// |
| 826 | |
| 827 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg1 ( |
| 828 | .scan_in(ren_pipe_reg1_scanin), |
| 829 | .scan_out(ren_pipe_reg1_scanout), |
| 830 | .din ( ren_pipe_reg1_in ), |
| 831 | .dout ( ren_pipe_out1 ), |
| 832 | .reset(reset), |
| 833 | .l1clk(l1clk), |
| 834 | .siclk(siclk), |
| 835 | .soclk(soclk)); |
| 836 | |
| 837 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg2 ( |
| 838 | .scan_in(ren_pipe_reg2_scanin), |
| 839 | .scan_out(ren_pipe_reg2_scanout), |
| 840 | .din ( ren_pipe_reg2_in ), |
| 841 | .dout ( ren_pipe_out2 ), |
| 842 | .reset(reset), |
| 843 | .l1clk(l1clk), |
| 844 | .siclk(siclk), |
| 845 | .soclk(soclk)); |
| 846 | |
| 847 | //Adding an extra level of pipe since piping the read_data |
| 848 | //msff_ctl_macro ren_pipe_reg3 (width=1, library=a1, reset=1)( |
| 849 | // .scan_in(ren_pipe_reg3_scanin), |
| 850 | // .scan_out(ren_pipe_reg3_scanout), |
| 851 | // .din ( ren_pipe_reg3_in ), |
| 852 | // .dout ( ren_pipe_out3 )); |
| 853 | |
| 854 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; |
| 855 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; |
| 856 | //assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; |
| 857 | //assign old_piped_ren = ren_pipe_out3; |
| 858 | assign old_piped_ren = ren_pipe_out2; |
| 859 | |
| 860 | // piped sel |
| 861 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 sel_pipe_reg1 ( |
| 862 | .scan_in(sel_pipe_reg1_scanin), |
| 863 | .scan_out(sel_pipe_reg1_scanout), |
| 864 | .din ( sel_pipe_reg1_in ), |
| 865 | .dout ( sel_pipe_out1 ), |
| 866 | .reset(reset), |
| 867 | .l1clk(l1clk), |
| 868 | .siclk(siclk), |
| 869 | .soclk(soclk)); |
| 870 | |
| 871 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 sel_pipe_reg2 ( |
| 872 | .scan_in(sel_pipe_reg2_scanin), |
| 873 | .scan_out(sel_pipe_reg2_scanout), |
| 874 | .din ( sel_pipe_reg2_in ), |
| 875 | .dout ( sel_pipe_out2 ), |
| 876 | .reset(reset), |
| 877 | .l1clk(l1clk), |
| 878 | .siclk(siclk), |
| 879 | .soclk(soclk)); |
| 880 | |
| 881 | assign sel_pipe_reg1_in = reset_engine ? 1'b0: array_sel; |
| 882 | assign sel_pipe_reg2_in = reset_engine ? 1'b0: sel_pipe_out1; |
| 883 | assign old_piped_sel2 = sel_pipe_out2; |
| 884 | assign old_piped_sel1 = sel_pipe_out1; |
| 885 | |
| 886 | // ///////////////////////////////////////////////////////////////////////////// |
| 887 | // Pipeline for comp sel |
| 888 | // ///////////////////////////////////////////////////////////////////////////// |
| 889 | |
| 890 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 cmpsel_reg1 ( |
| 891 | .scan_in(cmpsel_reg1_scanin), |
| 892 | .scan_out(cmpsel_reg1_scanout), |
| 893 | .din ( cmpsel_reg1_in[1:0] ), |
| 894 | .dout ( cmpsel_reg1_out1[1:0] ), |
| 895 | .reset(reset), |
| 896 | .l1clk(l1clk), |
| 897 | .siclk(siclk), |
| 898 | .soclk(soclk)); |
| 899 | |
| 900 | assign cmpsel_reg1_in[1:0] = cmpsel[1:0]; |
| 901 | |
| 902 | assign cmpsel_pipe1[1:0] = cmpsel_reg1_out1[1:0]; |
| 903 | |
| 904 | // ///////////////////////////////////////////////////////////////////////////// |
| 905 | // Pipeline for data out |
| 906 | // ///////////////////////////////////////////////////////////////////////////// |
| 907 | |
| 908 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_40 read_data_pipe_reg ( |
| 909 | .scan_in(read_data_pipe_reg_scanin), |
| 910 | .scan_out(read_data_pipe_reg_scanout), |
| 911 | .din ( read_data_reg_in[39:0] ), |
| 912 | .dout ( read_data_reg_out[39:0] ), |
| 913 | .reset(reset), |
| 914 | .l1clk(l1clk), |
| 915 | .siclk(siclk), |
| 916 | .soclk(soclk)); |
| 917 | |
| 918 | assign read_data_reg_in[39:0] = read_data_mux2[39:0]; |
| 919 | assign mb0_dout[39:0] = read_data_reg_out[39:0]; |
| 920 | |
| 921 | // ///////////////////////////////////////////////////////////////////////////// |
| 922 | // Fail Detection |
| 923 | // ///////////////////////////////////////////////////////////////////////////// |
| 924 | |
| 925 | assign fail_out_reg_in = fail; |
| 926 | assign niu_tcu_mbist_fail_0 = fail_out_reg_out; |
| 927 | |
| 928 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 fail_out_reg ( |
| 929 | .scan_in(fail_out_reg_scanin), |
| 930 | .scan_out(fail_out_reg_scanout), |
| 931 | .din ( fail_out_reg_in ), |
| 932 | .dout ( fail_out_reg_out ), |
| 933 | .reset(reset), |
| 934 | .l1clk(l1clk), |
| 935 | .siclk(siclk), |
| 936 | .soclk(soclk)); |
| 937 | |
| 938 | // ///////////////////////////////////////////////////////////////////////////// |
| 939 | // Fail Detection |
| 940 | // ///////////////////////////////////////////////////////////////////////////// |
| 941 | |
| 942 | niu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 fail_reg ( |
| 943 | .scan_in(fail_reg_scanin), |
| 944 | .scan_out(fail_reg_scanout), |
| 945 | .din ( fail_reg_in ), |
| 946 | .dout ( fail_reg_out ), |
| 947 | .reset(reset), |
| 948 | .l1clk(l1clk), |
| 949 | .siclk(siclk), |
| 950 | .soclk(soclk)); |
| 951 | |
| 952 | assign fail_reg_in[1:0] = reset_engine ? 2'b00 : {qual_old_fail1, qual_old_fail0} | fail_reg_out[1:0]; |
| 953 | |
| 954 | assign qual_old_fail0 = fail_detect && !old_piped_sel2; |
| 955 | assign qual_old_fail1 = fail_detect && old_piped_sel2; |
| 956 | assign qual_old_fail = qual_old_fail0 || qual_old_fail1; |
| 957 | |
| 958 | assign fail_detect = ({old_piped_data[7:0], |
| 959 | old_piped_data[7:0], |
| 960 | old_piped_data[7:0], |
| 961 | old_piped_data[7:0], |
| 962 | old_piped_data[7:0]}) != mb0_dout[39:0] && old_piped_ren; |
| 963 | |
| 964 | assign fail = mbist_done ? |fail_reg_out[1:0] : qual_old_fail; |
| 965 | |
| 966 | // Pipelining the read_data to meet the timing requirement |
| 967 | // Check if need to reset?? |
| 968 | |
| 969 | assign read_data_mux1[145:0] = old_piped_sel1 ? niu_mb0_smx_store_data_out[145:0] : |
| 970 | niu_mb0_smx_table_data_out[145:0]; |
| 971 | |
| 972 | assign read_data_mux2[39:0] = (cmpsel_pipe1[1:0] == 2'b00) ? read_data_mux1[39:0] : |
| 973 | (cmpsel_pipe1[1:0] == 2'b01) ? read_data_mux1[79:40] : |
| 974 | (cmpsel_pipe1[1:0] == 2'b10) ? read_data_mux1[119:80] : |
| 975 | {data_pipe_out1[7:0], data_pipe_out1[7:2], read_data_mux1[145:120]} ; |
| 976 | |
| 977 | |
| 978 | supply0 vss; // <- port for ground |
| 979 | supply1 vdd; // <- port for power |
| 980 | // ///////////////////////////////////////////////////////////////////////////// |
| 981 | // fixscan start: |
| 982 | assign config_reg_scanin = mb0_scan_in ; |
| 983 | assign user_data_reg_scanin = config_reg_scanout ; |
| 984 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; |
| 985 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; |
| 986 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; |
| 987 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; |
| 988 | assign user_cmpsel_reg_scanin = user_array_sel_reg_scanout; |
| 989 | assign user_bisi_wr_reg_scanin = user_cmpsel_reg_scanout ; |
| 990 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; |
| 991 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; |
| 992 | assign run_reg_scanin = start_transition_reg_scanout; |
| 993 | assign run1_reg_scanin = run_reg_scanout ; |
| 994 | assign run2_reg_scanin = run1_reg_scanout ; |
| 995 | assign control_reg_scanin = run2_reg_scanout ; |
| 996 | assign done_counter_reg_scanin = control_reg_scanout ; |
| 997 | assign done_reg_scanin = done_counter_reg_scanout ; |
| 998 | assign data_pipe_reg1_scanin = done_reg_scanout ; |
| 999 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; |
| 1000 | assign ren_pipe_reg1_scanin = data_pipe_reg2_scanout ; |
| 1001 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; |
| 1002 | assign sel_pipe_reg1_scanin = ren_pipe_reg2_scanout ; |
| 1003 | assign sel_pipe_reg2_scanin = sel_pipe_reg1_scanout ; |
| 1004 | assign cmpsel_reg1_scanin = sel_pipe_reg2_scanout ; |
| 1005 | assign read_data_pipe_reg_scanin = cmpsel_reg1_scanout ; |
| 1006 | assign fail_out_reg_scanin = read_data_pipe_reg_scanout; |
| 1007 | assign fail_reg_scanin = fail_out_reg_scanout ; |
| 1008 | assign mb0_scan_out = fail_reg_scanout ; |
| 1009 | // fixscan end: |
| 1010 | endmodule |
| 1011 | // ///////////////////////////////////////////////////////////////////////////// |
| 1012 | |
| 1013 | |
| 1014 | |
| 1015 | |
| 1016 | |
| 1017 | |
| 1018 | // any PARAMS parms go into naming of macro |
| 1019 | |
| 1020 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 ( |
| 1021 | din, |
| 1022 | reset, |
| 1023 | l1clk, |
| 1024 | scan_in, |
| 1025 | siclk, |
| 1026 | soclk, |
| 1027 | dout, |
| 1028 | scan_out); |
| 1029 | wire [8:0] fdin; |
| 1030 | wire [8:1] sout; |
| 1031 | |
| 1032 | input [8:0] din; |
| 1033 | input reset; |
| 1034 | input l1clk; |
| 1035 | input scan_in; |
| 1036 | |
| 1037 | |
| 1038 | input siclk; |
| 1039 | input soclk; |
| 1040 | |
| 1041 | output [8:0] dout; |
| 1042 | output scan_out; |
| 1043 | assign fdin[8:0] = din[8:0] & {9 {reset}}; |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | |
| 1049 | |
| 1050 | |
| 1051 | |
| 1052 | |
| 1053 | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | |
| 1060 | |
| 1061 | cl_a1_msff_syrst_4x d0_0 ( |
| 1062 | .l1clk(l1clk), |
| 1063 | .siclk(siclk), |
| 1064 | .soclk(soclk), |
| 1065 | .d(fdin[0]), |
| 1066 | .si(sout[1]), |
| 1067 | .so(scan_out), |
| 1068 | .reset(reset), |
| 1069 | .q(dout[0]) |
| 1070 | ); |
| 1071 | cl_a1_msff_syrst_4x d0_1 ( |
| 1072 | .l1clk(l1clk), |
| 1073 | .siclk(siclk), |
| 1074 | .soclk(soclk), |
| 1075 | .d(fdin[1]), |
| 1076 | .si(sout[2]), |
| 1077 | .so(sout[1]), |
| 1078 | .reset(reset), |
| 1079 | .q(dout[1]) |
| 1080 | ); |
| 1081 | cl_a1_msff_syrst_4x d0_2 ( |
| 1082 | .l1clk(l1clk), |
| 1083 | .siclk(siclk), |
| 1084 | .soclk(soclk), |
| 1085 | .d(fdin[2]), |
| 1086 | .si(sout[3]), |
| 1087 | .so(sout[2]), |
| 1088 | .reset(reset), |
| 1089 | .q(dout[2]) |
| 1090 | ); |
| 1091 | cl_a1_msff_syrst_4x d0_3 ( |
| 1092 | .l1clk(l1clk), |
| 1093 | .siclk(siclk), |
| 1094 | .soclk(soclk), |
| 1095 | .d(fdin[3]), |
| 1096 | .si(sout[4]), |
| 1097 | .so(sout[3]), |
| 1098 | .reset(reset), |
| 1099 | .q(dout[3]) |
| 1100 | ); |
| 1101 | cl_a1_msff_syrst_4x d0_4 ( |
| 1102 | .l1clk(l1clk), |
| 1103 | .siclk(siclk), |
| 1104 | .soclk(soclk), |
| 1105 | .d(fdin[4]), |
| 1106 | .si(sout[5]), |
| 1107 | .so(sout[4]), |
| 1108 | .reset(reset), |
| 1109 | .q(dout[4]) |
| 1110 | ); |
| 1111 | cl_a1_msff_syrst_4x d0_5 ( |
| 1112 | .l1clk(l1clk), |
| 1113 | .siclk(siclk), |
| 1114 | .soclk(soclk), |
| 1115 | .d(fdin[5]), |
| 1116 | .si(sout[6]), |
| 1117 | .so(sout[5]), |
| 1118 | .reset(reset), |
| 1119 | .q(dout[5]) |
| 1120 | ); |
| 1121 | cl_a1_msff_syrst_4x d0_6 ( |
| 1122 | .l1clk(l1clk), |
| 1123 | .siclk(siclk), |
| 1124 | .soclk(soclk), |
| 1125 | .d(fdin[6]), |
| 1126 | .si(sout[7]), |
| 1127 | .so(sout[6]), |
| 1128 | .reset(reset), |
| 1129 | .q(dout[6]) |
| 1130 | ); |
| 1131 | cl_a1_msff_syrst_4x d0_7 ( |
| 1132 | .l1clk(l1clk), |
| 1133 | .siclk(siclk), |
| 1134 | .soclk(soclk), |
| 1135 | .d(fdin[7]), |
| 1136 | .si(sout[8]), |
| 1137 | .so(sout[7]), |
| 1138 | .reset(reset), |
| 1139 | .q(dout[7]) |
| 1140 | ); |
| 1141 | cl_a1_msff_syrst_4x d0_8 ( |
| 1142 | .l1clk(l1clk), |
| 1143 | .siclk(siclk), |
| 1144 | .soclk(soclk), |
| 1145 | .d(fdin[8]), |
| 1146 | .si(scan_in), |
| 1147 | .so(sout[8]), |
| 1148 | .reset(reset), |
| 1149 | .q(dout[8]) |
| 1150 | ); |
| 1151 | |
| 1152 | |
| 1153 | |
| 1154 | |
| 1155 | endmodule |
| 1156 | |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | |
| 1161 | |
| 1162 | |
| 1163 | |
| 1164 | |
| 1165 | |
| 1166 | |
| 1167 | |
| 1168 | |
| 1169 | // any PARAMS parms go into naming of macro |
| 1170 | |
| 1171 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 ( |
| 1172 | din, |
| 1173 | reset, |
| 1174 | l1clk, |
| 1175 | scan_in, |
| 1176 | siclk, |
| 1177 | soclk, |
| 1178 | dout, |
| 1179 | scan_out); |
| 1180 | wire [7:0] fdin; |
| 1181 | wire [7:1] sout; |
| 1182 | |
| 1183 | input [7:0] din; |
| 1184 | input reset; |
| 1185 | input l1clk; |
| 1186 | input scan_in; |
| 1187 | |
| 1188 | |
| 1189 | input siclk; |
| 1190 | input soclk; |
| 1191 | |
| 1192 | output [7:0] dout; |
| 1193 | output scan_out; |
| 1194 | assign fdin[7:0] = din[7:0] & {8 {reset}}; |
| 1195 | |
| 1196 | |
| 1197 | |
| 1198 | |
| 1199 | |
| 1200 | |
| 1201 | |
| 1202 | |
| 1203 | |
| 1204 | |
| 1205 | |
| 1206 | |
| 1207 | |
| 1208 | |
| 1209 | |
| 1210 | |
| 1211 | |
| 1212 | cl_a1_msff_syrst_4x d0_0 ( |
| 1213 | .l1clk(l1clk), |
| 1214 | .siclk(siclk), |
| 1215 | .soclk(soclk), |
| 1216 | .d(fdin[0]), |
| 1217 | .si(sout[1]), |
| 1218 | .so(scan_out), |
| 1219 | .reset(reset), |
| 1220 | .q(dout[0]) |
| 1221 | ); |
| 1222 | cl_a1_msff_syrst_4x d0_1 ( |
| 1223 | .l1clk(l1clk), |
| 1224 | .siclk(siclk), |
| 1225 | .soclk(soclk), |
| 1226 | .d(fdin[1]), |
| 1227 | .si(sout[2]), |
| 1228 | .so(sout[1]), |
| 1229 | .reset(reset), |
| 1230 | .q(dout[1]) |
| 1231 | ); |
| 1232 | cl_a1_msff_syrst_4x d0_2 ( |
| 1233 | .l1clk(l1clk), |
| 1234 | .siclk(siclk), |
| 1235 | .soclk(soclk), |
| 1236 | .d(fdin[2]), |
| 1237 | .si(sout[3]), |
| 1238 | .so(sout[2]), |
| 1239 | .reset(reset), |
| 1240 | .q(dout[2]) |
| 1241 | ); |
| 1242 | cl_a1_msff_syrst_4x d0_3 ( |
| 1243 | .l1clk(l1clk), |
| 1244 | .siclk(siclk), |
| 1245 | .soclk(soclk), |
| 1246 | .d(fdin[3]), |
| 1247 | .si(sout[4]), |
| 1248 | .so(sout[3]), |
| 1249 | .reset(reset), |
| 1250 | .q(dout[3]) |
| 1251 | ); |
| 1252 | cl_a1_msff_syrst_4x d0_4 ( |
| 1253 | .l1clk(l1clk), |
| 1254 | .siclk(siclk), |
| 1255 | .soclk(soclk), |
| 1256 | .d(fdin[4]), |
| 1257 | .si(sout[5]), |
| 1258 | .so(sout[4]), |
| 1259 | .reset(reset), |
| 1260 | .q(dout[4]) |
| 1261 | ); |
| 1262 | cl_a1_msff_syrst_4x d0_5 ( |
| 1263 | .l1clk(l1clk), |
| 1264 | .siclk(siclk), |
| 1265 | .soclk(soclk), |
| 1266 | .d(fdin[5]), |
| 1267 | .si(sout[6]), |
| 1268 | .so(sout[5]), |
| 1269 | .reset(reset), |
| 1270 | .q(dout[5]) |
| 1271 | ); |
| 1272 | cl_a1_msff_syrst_4x d0_6 ( |
| 1273 | .l1clk(l1clk), |
| 1274 | .siclk(siclk), |
| 1275 | .soclk(soclk), |
| 1276 | .d(fdin[6]), |
| 1277 | .si(sout[7]), |
| 1278 | .so(sout[6]), |
| 1279 | .reset(reset), |
| 1280 | .q(dout[6]) |
| 1281 | ); |
| 1282 | cl_a1_msff_syrst_4x d0_7 ( |
| 1283 | .l1clk(l1clk), |
| 1284 | .siclk(siclk), |
| 1285 | .soclk(soclk), |
| 1286 | .d(fdin[7]), |
| 1287 | .si(scan_in), |
| 1288 | .so(sout[7]), |
| 1289 | .reset(reset), |
| 1290 | .q(dout[7]) |
| 1291 | ); |
| 1292 | |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | endmodule |
| 1297 | |
| 1298 | |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | |
| 1303 | |
| 1304 | |
| 1305 | |
| 1306 | |
| 1307 | |
| 1308 | |
| 1309 | |
| 1310 | // any PARAMS parms go into naming of macro |
| 1311 | |
| 1312 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_6 ( |
| 1313 | din, |
| 1314 | reset, |
| 1315 | l1clk, |
| 1316 | scan_in, |
| 1317 | siclk, |
| 1318 | soclk, |
| 1319 | dout, |
| 1320 | scan_out); |
| 1321 | wire [5:0] fdin; |
| 1322 | wire [5:1] sout; |
| 1323 | |
| 1324 | input [5:0] din; |
| 1325 | input reset; |
| 1326 | input l1clk; |
| 1327 | input scan_in; |
| 1328 | |
| 1329 | |
| 1330 | input siclk; |
| 1331 | input soclk; |
| 1332 | |
| 1333 | output [5:0] dout; |
| 1334 | output scan_out; |
| 1335 | assign fdin[5:0] = din[5:0] & {6 {reset}}; |
| 1336 | |
| 1337 | |
| 1338 | |
| 1339 | |
| 1340 | |
| 1341 | |
| 1342 | |
| 1343 | |
| 1344 | |
| 1345 | |
| 1346 | |
| 1347 | |
| 1348 | |
| 1349 | |
| 1350 | |
| 1351 | |
| 1352 | |
| 1353 | cl_a1_msff_syrst_4x d0_0 ( |
| 1354 | .l1clk(l1clk), |
| 1355 | .siclk(siclk), |
| 1356 | .soclk(soclk), |
| 1357 | .d(fdin[0]), |
| 1358 | .si(sout[1]), |
| 1359 | .so(scan_out), |
| 1360 | .reset(reset), |
| 1361 | .q(dout[0]) |
| 1362 | ); |
| 1363 | cl_a1_msff_syrst_4x d0_1 ( |
| 1364 | .l1clk(l1clk), |
| 1365 | .siclk(siclk), |
| 1366 | .soclk(soclk), |
| 1367 | .d(fdin[1]), |
| 1368 | .si(sout[2]), |
| 1369 | .so(sout[1]), |
| 1370 | .reset(reset), |
| 1371 | .q(dout[1]) |
| 1372 | ); |
| 1373 | cl_a1_msff_syrst_4x d0_2 ( |
| 1374 | .l1clk(l1clk), |
| 1375 | .siclk(siclk), |
| 1376 | .soclk(soclk), |
| 1377 | .d(fdin[2]), |
| 1378 | .si(sout[3]), |
| 1379 | .so(sout[2]), |
| 1380 | .reset(reset), |
| 1381 | .q(dout[2]) |
| 1382 | ); |
| 1383 | cl_a1_msff_syrst_4x d0_3 ( |
| 1384 | .l1clk(l1clk), |
| 1385 | .siclk(siclk), |
| 1386 | .soclk(soclk), |
| 1387 | .d(fdin[3]), |
| 1388 | .si(sout[4]), |
| 1389 | .so(sout[3]), |
| 1390 | .reset(reset), |
| 1391 | .q(dout[3]) |
| 1392 | ); |
| 1393 | cl_a1_msff_syrst_4x d0_4 ( |
| 1394 | .l1clk(l1clk), |
| 1395 | .siclk(siclk), |
| 1396 | .soclk(soclk), |
| 1397 | .d(fdin[4]), |
| 1398 | .si(sout[5]), |
| 1399 | .so(sout[4]), |
| 1400 | .reset(reset), |
| 1401 | .q(dout[4]) |
| 1402 | ); |
| 1403 | cl_a1_msff_syrst_4x d0_5 ( |
| 1404 | .l1clk(l1clk), |
| 1405 | .siclk(siclk), |
| 1406 | .soclk(soclk), |
| 1407 | .d(fdin[5]), |
| 1408 | .si(scan_in), |
| 1409 | .so(sout[5]), |
| 1410 | .reset(reset), |
| 1411 | .q(dout[5]) |
| 1412 | ); |
| 1413 | |
| 1414 | |
| 1415 | |
| 1416 | |
| 1417 | endmodule |
| 1418 | |
| 1419 | |
| 1420 | |
| 1421 | |
| 1422 | |
| 1423 | |
| 1424 | |
| 1425 | |
| 1426 | |
| 1427 | |
| 1428 | |
| 1429 | |
| 1430 | |
| 1431 | // any PARAMS parms go into naming of macro |
| 1432 | |
| 1433 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 ( |
| 1434 | din, |
| 1435 | reset, |
| 1436 | l1clk, |
| 1437 | scan_in, |
| 1438 | siclk, |
| 1439 | soclk, |
| 1440 | dout, |
| 1441 | scan_out); |
| 1442 | wire [0:0] fdin; |
| 1443 | |
| 1444 | input [0:0] din; |
| 1445 | input reset; |
| 1446 | input l1clk; |
| 1447 | input scan_in; |
| 1448 | |
| 1449 | |
| 1450 | input siclk; |
| 1451 | input soclk; |
| 1452 | |
| 1453 | output [0:0] dout; |
| 1454 | output scan_out; |
| 1455 | assign fdin[0:0] = din[0:0] & {1 {reset}}; |
| 1456 | |
| 1457 | |
| 1458 | |
| 1459 | |
| 1460 | |
| 1461 | |
| 1462 | |
| 1463 | |
| 1464 | |
| 1465 | |
| 1466 | |
| 1467 | |
| 1468 | |
| 1469 | |
| 1470 | |
| 1471 | |
| 1472 | |
| 1473 | cl_a1_msff_syrst_4x d0_0 ( |
| 1474 | .l1clk(l1clk), |
| 1475 | .siclk(siclk), |
| 1476 | .soclk(soclk), |
| 1477 | .d(fdin[0]), |
| 1478 | .si(scan_in), |
| 1479 | .so(scan_out), |
| 1480 | .reset(reset), |
| 1481 | .q(dout[0]) |
| 1482 | ); |
| 1483 | |
| 1484 | |
| 1485 | |
| 1486 | |
| 1487 | endmodule |
| 1488 | |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | |
| 1498 | |
| 1499 | |
| 1500 | |
| 1501 | // any PARAMS parms go into naming of macro |
| 1502 | |
| 1503 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 ( |
| 1504 | din, |
| 1505 | reset, |
| 1506 | l1clk, |
| 1507 | scan_in, |
| 1508 | siclk, |
| 1509 | soclk, |
| 1510 | dout, |
| 1511 | scan_out); |
| 1512 | wire [1:0] fdin; |
| 1513 | wire [1:1] sout; |
| 1514 | |
| 1515 | input [1:0] din; |
| 1516 | input reset; |
| 1517 | input l1clk; |
| 1518 | input scan_in; |
| 1519 | |
| 1520 | |
| 1521 | input siclk; |
| 1522 | input soclk; |
| 1523 | |
| 1524 | output [1:0] dout; |
| 1525 | output scan_out; |
| 1526 | assign fdin[1:0] = din[1:0] & {2 {reset}}; |
| 1527 | |
| 1528 | |
| 1529 | |
| 1530 | |
| 1531 | |
| 1532 | |
| 1533 | |
| 1534 | |
| 1535 | |
| 1536 | |
| 1537 | |
| 1538 | |
| 1539 | |
| 1540 | |
| 1541 | |
| 1542 | |
| 1543 | |
| 1544 | cl_a1_msff_syrst_4x d0_0 ( |
| 1545 | .l1clk(l1clk), |
| 1546 | .siclk(siclk), |
| 1547 | .soclk(soclk), |
| 1548 | .d(fdin[0]), |
| 1549 | .si(sout[1]), |
| 1550 | .so(scan_out), |
| 1551 | .reset(reset), |
| 1552 | .q(dout[0]) |
| 1553 | ); |
| 1554 | cl_a1_msff_syrst_4x d0_1 ( |
| 1555 | .l1clk(l1clk), |
| 1556 | .siclk(siclk), |
| 1557 | .soclk(soclk), |
| 1558 | .d(fdin[1]), |
| 1559 | .si(scan_in), |
| 1560 | .so(sout[1]), |
| 1561 | .reset(reset), |
| 1562 | .q(dout[1]) |
| 1563 | ); |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | |
| 1568 | endmodule |
| 1569 | |
| 1570 | |
| 1571 | |
| 1572 | |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | // any PARAMS parms go into naming of macro |
| 1583 | |
| 1584 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_21 ( |
| 1585 | din, |
| 1586 | reset, |
| 1587 | l1clk, |
| 1588 | scan_in, |
| 1589 | siclk, |
| 1590 | soclk, |
| 1591 | dout, |
| 1592 | scan_out); |
| 1593 | wire [20:0] fdin; |
| 1594 | wire [20:1] sout; |
| 1595 | |
| 1596 | input [20:0] din; |
| 1597 | input reset; |
| 1598 | input l1clk; |
| 1599 | input scan_in; |
| 1600 | |
| 1601 | |
| 1602 | input siclk; |
| 1603 | input soclk; |
| 1604 | |
| 1605 | output [20:0] dout; |
| 1606 | output scan_out; |
| 1607 | assign fdin[20:0] = din[20:0] & {21 {reset}}; |
| 1608 | |
| 1609 | |
| 1610 | |
| 1611 | |
| 1612 | |
| 1613 | |
| 1614 | |
| 1615 | |
| 1616 | |
| 1617 | |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | |
| 1622 | |
| 1623 | |
| 1624 | |
| 1625 | cl_a1_msff_syrst_4x d0_0 ( |
| 1626 | .l1clk(l1clk), |
| 1627 | .siclk(siclk), |
| 1628 | .soclk(soclk), |
| 1629 | .d(fdin[0]), |
| 1630 | .si(sout[1]), |
| 1631 | .so(scan_out), |
| 1632 | .reset(reset), |
| 1633 | .q(dout[0]) |
| 1634 | ); |
| 1635 | cl_a1_msff_syrst_4x d0_1 ( |
| 1636 | .l1clk(l1clk), |
| 1637 | .siclk(siclk), |
| 1638 | .soclk(soclk), |
| 1639 | .d(fdin[1]), |
| 1640 | .si(sout[2]), |
| 1641 | .so(sout[1]), |
| 1642 | .reset(reset), |
| 1643 | .q(dout[1]) |
| 1644 | ); |
| 1645 | cl_a1_msff_syrst_4x d0_2 ( |
| 1646 | .l1clk(l1clk), |
| 1647 | .siclk(siclk), |
| 1648 | .soclk(soclk), |
| 1649 | .d(fdin[2]), |
| 1650 | .si(sout[3]), |
| 1651 | .so(sout[2]), |
| 1652 | .reset(reset), |
| 1653 | .q(dout[2]) |
| 1654 | ); |
| 1655 | cl_a1_msff_syrst_4x d0_3 ( |
| 1656 | .l1clk(l1clk), |
| 1657 | .siclk(siclk), |
| 1658 | .soclk(soclk), |
| 1659 | .d(fdin[3]), |
| 1660 | .si(sout[4]), |
| 1661 | .so(sout[3]), |
| 1662 | .reset(reset), |
| 1663 | .q(dout[3]) |
| 1664 | ); |
| 1665 | cl_a1_msff_syrst_4x d0_4 ( |
| 1666 | .l1clk(l1clk), |
| 1667 | .siclk(siclk), |
| 1668 | .soclk(soclk), |
| 1669 | .d(fdin[4]), |
| 1670 | .si(sout[5]), |
| 1671 | .so(sout[4]), |
| 1672 | .reset(reset), |
| 1673 | .q(dout[4]) |
| 1674 | ); |
| 1675 | cl_a1_msff_syrst_4x d0_5 ( |
| 1676 | .l1clk(l1clk), |
| 1677 | .siclk(siclk), |
| 1678 | .soclk(soclk), |
| 1679 | .d(fdin[5]), |
| 1680 | .si(sout[6]), |
| 1681 | .so(sout[5]), |
| 1682 | .reset(reset), |
| 1683 | .q(dout[5]) |
| 1684 | ); |
| 1685 | cl_a1_msff_syrst_4x d0_6 ( |
| 1686 | .l1clk(l1clk), |
| 1687 | .siclk(siclk), |
| 1688 | .soclk(soclk), |
| 1689 | .d(fdin[6]), |
| 1690 | .si(sout[7]), |
| 1691 | .so(sout[6]), |
| 1692 | .reset(reset), |
| 1693 | .q(dout[6]) |
| 1694 | ); |
| 1695 | cl_a1_msff_syrst_4x d0_7 ( |
| 1696 | .l1clk(l1clk), |
| 1697 | .siclk(siclk), |
| 1698 | .soclk(soclk), |
| 1699 | .d(fdin[7]), |
| 1700 | .si(sout[8]), |
| 1701 | .so(sout[7]), |
| 1702 | .reset(reset), |
| 1703 | .q(dout[7]) |
| 1704 | ); |
| 1705 | cl_a1_msff_syrst_4x d0_8 ( |
| 1706 | .l1clk(l1clk), |
| 1707 | .siclk(siclk), |
| 1708 | .soclk(soclk), |
| 1709 | .d(fdin[8]), |
| 1710 | .si(sout[9]), |
| 1711 | .so(sout[8]), |
| 1712 | .reset(reset), |
| 1713 | .q(dout[8]) |
| 1714 | ); |
| 1715 | cl_a1_msff_syrst_4x d0_9 ( |
| 1716 | .l1clk(l1clk), |
| 1717 | .siclk(siclk), |
| 1718 | .soclk(soclk), |
| 1719 | .d(fdin[9]), |
| 1720 | .si(sout[10]), |
| 1721 | .so(sout[9]), |
| 1722 | .reset(reset), |
| 1723 | .q(dout[9]) |
| 1724 | ); |
| 1725 | cl_a1_msff_syrst_4x d0_10 ( |
| 1726 | .l1clk(l1clk), |
| 1727 | .siclk(siclk), |
| 1728 | .soclk(soclk), |
| 1729 | .d(fdin[10]), |
| 1730 | .si(sout[11]), |
| 1731 | .so(sout[10]), |
| 1732 | .reset(reset), |
| 1733 | .q(dout[10]) |
| 1734 | ); |
| 1735 | cl_a1_msff_syrst_4x d0_11 ( |
| 1736 | .l1clk(l1clk), |
| 1737 | .siclk(siclk), |
| 1738 | .soclk(soclk), |
| 1739 | .d(fdin[11]), |
| 1740 | .si(sout[12]), |
| 1741 | .so(sout[11]), |
| 1742 | .reset(reset), |
| 1743 | .q(dout[11]) |
| 1744 | ); |
| 1745 | cl_a1_msff_syrst_4x d0_12 ( |
| 1746 | .l1clk(l1clk), |
| 1747 | .siclk(siclk), |
| 1748 | .soclk(soclk), |
| 1749 | .d(fdin[12]), |
| 1750 | .si(sout[13]), |
| 1751 | .so(sout[12]), |
| 1752 | .reset(reset), |
| 1753 | .q(dout[12]) |
| 1754 | ); |
| 1755 | cl_a1_msff_syrst_4x d0_13 ( |
| 1756 | .l1clk(l1clk), |
| 1757 | .siclk(siclk), |
| 1758 | .soclk(soclk), |
| 1759 | .d(fdin[13]), |
| 1760 | .si(sout[14]), |
| 1761 | .so(sout[13]), |
| 1762 | .reset(reset), |
| 1763 | .q(dout[13]) |
| 1764 | ); |
| 1765 | cl_a1_msff_syrst_4x d0_14 ( |
| 1766 | .l1clk(l1clk), |
| 1767 | .siclk(siclk), |
| 1768 | .soclk(soclk), |
| 1769 | .d(fdin[14]), |
| 1770 | .si(sout[15]), |
| 1771 | .so(sout[14]), |
| 1772 | .reset(reset), |
| 1773 | .q(dout[14]) |
| 1774 | ); |
| 1775 | cl_a1_msff_syrst_4x d0_15 ( |
| 1776 | .l1clk(l1clk), |
| 1777 | .siclk(siclk), |
| 1778 | .soclk(soclk), |
| 1779 | .d(fdin[15]), |
| 1780 | .si(sout[16]), |
| 1781 | .so(sout[15]), |
| 1782 | .reset(reset), |
| 1783 | .q(dout[15]) |
| 1784 | ); |
| 1785 | cl_a1_msff_syrst_4x d0_16 ( |
| 1786 | .l1clk(l1clk), |
| 1787 | .siclk(siclk), |
| 1788 | .soclk(soclk), |
| 1789 | .d(fdin[16]), |
| 1790 | .si(sout[17]), |
| 1791 | .so(sout[16]), |
| 1792 | .reset(reset), |
| 1793 | .q(dout[16]) |
| 1794 | ); |
| 1795 | cl_a1_msff_syrst_4x d0_17 ( |
| 1796 | .l1clk(l1clk), |
| 1797 | .siclk(siclk), |
| 1798 | .soclk(soclk), |
| 1799 | .d(fdin[17]), |
| 1800 | .si(sout[18]), |
| 1801 | .so(sout[17]), |
| 1802 | .reset(reset), |
| 1803 | .q(dout[17]) |
| 1804 | ); |
| 1805 | cl_a1_msff_syrst_4x d0_18 ( |
| 1806 | .l1clk(l1clk), |
| 1807 | .siclk(siclk), |
| 1808 | .soclk(soclk), |
| 1809 | .d(fdin[18]), |
| 1810 | .si(sout[19]), |
| 1811 | .so(sout[18]), |
| 1812 | .reset(reset), |
| 1813 | .q(dout[18]) |
| 1814 | ); |
| 1815 | cl_a1_msff_syrst_4x d0_19 ( |
| 1816 | .l1clk(l1clk), |
| 1817 | .siclk(siclk), |
| 1818 | .soclk(soclk), |
| 1819 | .d(fdin[19]), |
| 1820 | .si(sout[20]), |
| 1821 | .so(sout[19]), |
| 1822 | .reset(reset), |
| 1823 | .q(dout[19]) |
| 1824 | ); |
| 1825 | cl_a1_msff_syrst_4x d0_20 ( |
| 1826 | .l1clk(l1clk), |
| 1827 | .siclk(siclk), |
| 1828 | .soclk(soclk), |
| 1829 | .d(fdin[20]), |
| 1830 | .si(scan_in), |
| 1831 | .so(sout[20]), |
| 1832 | .reset(reset), |
| 1833 | .q(dout[20]) |
| 1834 | ); |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | |
| 1839 | endmodule |
| 1840 | |
| 1841 | |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | |
| 1847 | |
| 1848 | |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | |
| 1853 | // any PARAMS parms go into naming of macro |
| 1854 | |
| 1855 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_3 ( |
| 1856 | din, |
| 1857 | reset, |
| 1858 | l1clk, |
| 1859 | scan_in, |
| 1860 | siclk, |
| 1861 | soclk, |
| 1862 | dout, |
| 1863 | scan_out); |
| 1864 | wire [2:0] fdin; |
| 1865 | wire [2:1] sout; |
| 1866 | |
| 1867 | input [2:0] din; |
| 1868 | input reset; |
| 1869 | input l1clk; |
| 1870 | input scan_in; |
| 1871 | |
| 1872 | |
| 1873 | input siclk; |
| 1874 | input soclk; |
| 1875 | |
| 1876 | output [2:0] dout; |
| 1877 | output scan_out; |
| 1878 | assign fdin[2:0] = din[2:0] & {3 {reset}}; |
| 1879 | |
| 1880 | |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | |
| 1894 | |
| 1895 | |
| 1896 | cl_a1_msff_syrst_4x d0_0 ( |
| 1897 | .l1clk(l1clk), |
| 1898 | .siclk(siclk), |
| 1899 | .soclk(soclk), |
| 1900 | .d(fdin[0]), |
| 1901 | .si(sout[1]), |
| 1902 | .so(scan_out), |
| 1903 | .reset(reset), |
| 1904 | .q(dout[0]) |
| 1905 | ); |
| 1906 | cl_a1_msff_syrst_4x d0_1 ( |
| 1907 | .l1clk(l1clk), |
| 1908 | .siclk(siclk), |
| 1909 | .soclk(soclk), |
| 1910 | .d(fdin[1]), |
| 1911 | .si(sout[2]), |
| 1912 | .so(sout[1]), |
| 1913 | .reset(reset), |
| 1914 | .q(dout[1]) |
| 1915 | ); |
| 1916 | cl_a1_msff_syrst_4x d0_2 ( |
| 1917 | .l1clk(l1clk), |
| 1918 | .siclk(siclk), |
| 1919 | .soclk(soclk), |
| 1920 | .d(fdin[2]), |
| 1921 | .si(scan_in), |
| 1922 | .so(sout[2]), |
| 1923 | .reset(reset), |
| 1924 | .q(dout[2]) |
| 1925 | ); |
| 1926 | |
| 1927 | |
| 1928 | |
| 1929 | |
| 1930 | endmodule |
| 1931 | |
| 1932 | |
| 1933 | |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | |
| 1938 | |
| 1939 | |
| 1940 | |
| 1941 | |
| 1942 | |
| 1943 | |
| 1944 | // any PARAMS parms go into naming of macro |
| 1945 | |
| 1946 | module niu_mb0_msff_ctl_macro__library_a1__reset_1__width_40 ( |
| 1947 | din, |
| 1948 | reset, |
| 1949 | l1clk, |
| 1950 | scan_in, |
| 1951 | siclk, |
| 1952 | soclk, |
| 1953 | dout, |
| 1954 | scan_out); |
| 1955 | wire [39:0] fdin; |
| 1956 | wire [39:1] sout; |
| 1957 | |
| 1958 | input [39:0] din; |
| 1959 | input reset; |
| 1960 | input l1clk; |
| 1961 | input scan_in; |
| 1962 | |
| 1963 | |
| 1964 | input siclk; |
| 1965 | input soclk; |
| 1966 | |
| 1967 | output [39:0] dout; |
| 1968 | output scan_out; |
| 1969 | assign fdin[39:0] = din[39:0] & {40 {reset}}; |
| 1970 | |
| 1971 | |
| 1972 | |
| 1973 | |
| 1974 | |
| 1975 | |
| 1976 | |
| 1977 | |
| 1978 | |
| 1979 | |
| 1980 | |
| 1981 | |
| 1982 | |
| 1983 | |
| 1984 | |
| 1985 | |
| 1986 | |
| 1987 | cl_a1_msff_syrst_4x d0_0 ( |
| 1988 | .l1clk(l1clk), |
| 1989 | .siclk(siclk), |
| 1990 | .soclk(soclk), |
| 1991 | .d(fdin[0]), |
| 1992 | .si(sout[1]), |
| 1993 | .so(scan_out), |
| 1994 | .reset(reset), |
| 1995 | .q(dout[0]) |
| 1996 | ); |
| 1997 | cl_a1_msff_syrst_4x d0_1 ( |
| 1998 | .l1clk(l1clk), |
| 1999 | .siclk(siclk), |
| 2000 | .soclk(soclk), |
| 2001 | .d(fdin[1]), |
| 2002 | .si(sout[2]), |
| 2003 | .so(sout[1]), |
| 2004 | .reset(reset), |
| 2005 | .q(dout[1]) |
| 2006 | ); |
| 2007 | cl_a1_msff_syrst_4x d0_2 ( |
| 2008 | .l1clk(l1clk), |
| 2009 | .siclk(siclk), |
| 2010 | .soclk(soclk), |
| 2011 | .d(fdin[2]), |
| 2012 | .si(sout[3]), |
| 2013 | .so(sout[2]), |
| 2014 | .reset(reset), |
| 2015 | .q(dout[2]) |
| 2016 | ); |
| 2017 | cl_a1_msff_syrst_4x d0_3 ( |
| 2018 | .l1clk(l1clk), |
| 2019 | .siclk(siclk), |
| 2020 | .soclk(soclk), |
| 2021 | .d(fdin[3]), |
| 2022 | .si(sout[4]), |
| 2023 | .so(sout[3]), |
| 2024 | .reset(reset), |
| 2025 | .q(dout[3]) |
| 2026 | ); |
| 2027 | cl_a1_msff_syrst_4x d0_4 ( |
| 2028 | .l1clk(l1clk), |
| 2029 | .siclk(siclk), |
| 2030 | .soclk(soclk), |
| 2031 | .d(fdin[4]), |
| 2032 | .si(sout[5]), |
| 2033 | .so(sout[4]), |
| 2034 | .reset(reset), |
| 2035 | .q(dout[4]) |
| 2036 | ); |
| 2037 | cl_a1_msff_syrst_4x d0_5 ( |
| 2038 | .l1clk(l1clk), |
| 2039 | .siclk(siclk), |
| 2040 | .soclk(soclk), |
| 2041 | .d(fdin[5]), |
| 2042 | .si(sout[6]), |
| 2043 | .so(sout[5]), |
| 2044 | .reset(reset), |
| 2045 | .q(dout[5]) |
| 2046 | ); |
| 2047 | cl_a1_msff_syrst_4x d0_6 ( |
| 2048 | .l1clk(l1clk), |
| 2049 | .siclk(siclk), |
| 2050 | .soclk(soclk), |
| 2051 | .d(fdin[6]), |
| 2052 | .si(sout[7]), |
| 2053 | .so(sout[6]), |
| 2054 | .reset(reset), |
| 2055 | .q(dout[6]) |
| 2056 | ); |
| 2057 | cl_a1_msff_syrst_4x d0_7 ( |
| 2058 | .l1clk(l1clk), |
| 2059 | .siclk(siclk), |
| 2060 | .soclk(soclk), |
| 2061 | .d(fdin[7]), |
| 2062 | .si(sout[8]), |
| 2063 | .so(sout[7]), |
| 2064 | .reset(reset), |
| 2065 | .q(dout[7]) |
| 2066 | ); |
| 2067 | cl_a1_msff_syrst_4x d0_8 ( |
| 2068 | .l1clk(l1clk), |
| 2069 | .siclk(siclk), |
| 2070 | .soclk(soclk), |
| 2071 | .d(fdin[8]), |
| 2072 | .si(sout[9]), |
| 2073 | .so(sout[8]), |
| 2074 | .reset(reset), |
| 2075 | .q(dout[8]) |
| 2076 | ); |
| 2077 | cl_a1_msff_syrst_4x d0_9 ( |
| 2078 | .l1clk(l1clk), |
| 2079 | .siclk(siclk), |
| 2080 | .soclk(soclk), |
| 2081 | .d(fdin[9]), |
| 2082 | .si(sout[10]), |
| 2083 | .so(sout[9]), |
| 2084 | .reset(reset), |
| 2085 | .q(dout[9]) |
| 2086 | ); |
| 2087 | cl_a1_msff_syrst_4x d0_10 ( |
| 2088 | .l1clk(l1clk), |
| 2089 | .siclk(siclk), |
| 2090 | .soclk(soclk), |
| 2091 | .d(fdin[10]), |
| 2092 | .si(sout[11]), |
| 2093 | .so(sout[10]), |
| 2094 | .reset(reset), |
| 2095 | .q(dout[10]) |
| 2096 | ); |
| 2097 | cl_a1_msff_syrst_4x d0_11 ( |
| 2098 | .l1clk(l1clk), |
| 2099 | .siclk(siclk), |
| 2100 | .soclk(soclk), |
| 2101 | .d(fdin[11]), |
| 2102 | .si(sout[12]), |
| 2103 | .so(sout[11]), |
| 2104 | .reset(reset), |
| 2105 | .q(dout[11]) |
| 2106 | ); |
| 2107 | cl_a1_msff_syrst_4x d0_12 ( |
| 2108 | .l1clk(l1clk), |
| 2109 | .siclk(siclk), |
| 2110 | .soclk(soclk), |
| 2111 | .d(fdin[12]), |
| 2112 | .si(sout[13]), |
| 2113 | .so(sout[12]), |
| 2114 | .reset(reset), |
| 2115 | .q(dout[12]) |
| 2116 | ); |
| 2117 | cl_a1_msff_syrst_4x d0_13 ( |
| 2118 | .l1clk(l1clk), |
| 2119 | .siclk(siclk), |
| 2120 | .soclk(soclk), |
| 2121 | .d(fdin[13]), |
| 2122 | .si(sout[14]), |
| 2123 | .so(sout[13]), |
| 2124 | .reset(reset), |
| 2125 | .q(dout[13]) |
| 2126 | ); |
| 2127 | cl_a1_msff_syrst_4x d0_14 ( |
| 2128 | .l1clk(l1clk), |
| 2129 | .siclk(siclk), |
| 2130 | .soclk(soclk), |
| 2131 | .d(fdin[14]), |
| 2132 | .si(sout[15]), |
| 2133 | .so(sout[14]), |
| 2134 | .reset(reset), |
| 2135 | .q(dout[14]) |
| 2136 | ); |
| 2137 | cl_a1_msff_syrst_4x d0_15 ( |
| 2138 | .l1clk(l1clk), |
| 2139 | .siclk(siclk), |
| 2140 | .soclk(soclk), |
| 2141 | .d(fdin[15]), |
| 2142 | .si(sout[16]), |
| 2143 | .so(sout[15]), |
| 2144 | .reset(reset), |
| 2145 | .q(dout[15]) |
| 2146 | ); |
| 2147 | cl_a1_msff_syrst_4x d0_16 ( |
| 2148 | .l1clk(l1clk), |
| 2149 | .siclk(siclk), |
| 2150 | .soclk(soclk), |
| 2151 | .d(fdin[16]), |
| 2152 | .si(sout[17]), |
| 2153 | .so(sout[16]), |
| 2154 | .reset(reset), |
| 2155 | .q(dout[16]) |
| 2156 | ); |
| 2157 | cl_a1_msff_syrst_4x d0_17 ( |
| 2158 | .l1clk(l1clk), |
| 2159 | .siclk(siclk), |
| 2160 | .soclk(soclk), |
| 2161 | .d(fdin[17]), |
| 2162 | .si(sout[18]), |
| 2163 | .so(sout[17]), |
| 2164 | .reset(reset), |
| 2165 | .q(dout[17]) |
| 2166 | ); |
| 2167 | cl_a1_msff_syrst_4x d0_18 ( |
| 2168 | .l1clk(l1clk), |
| 2169 | .siclk(siclk), |
| 2170 | .soclk(soclk), |
| 2171 | .d(fdin[18]), |
| 2172 | .si(sout[19]), |
| 2173 | .so(sout[18]), |
| 2174 | .reset(reset), |
| 2175 | .q(dout[18]) |
| 2176 | ); |
| 2177 | cl_a1_msff_syrst_4x d0_19 ( |
| 2178 | .l1clk(l1clk), |
| 2179 | .siclk(siclk), |
| 2180 | .soclk(soclk), |
| 2181 | .d(fdin[19]), |
| 2182 | .si(sout[20]), |
| 2183 | .so(sout[19]), |
| 2184 | .reset(reset), |
| 2185 | .q(dout[19]) |
| 2186 | ); |
| 2187 | cl_a1_msff_syrst_4x d0_20 ( |
| 2188 | .l1clk(l1clk), |
| 2189 | .siclk(siclk), |
| 2190 | .soclk(soclk), |
| 2191 | .d(fdin[20]), |
| 2192 | .si(sout[21]), |
| 2193 | .so(sout[20]), |
| 2194 | .reset(reset), |
| 2195 | .q(dout[20]) |
| 2196 | ); |
| 2197 | cl_a1_msff_syrst_4x d0_21 ( |
| 2198 | .l1clk(l1clk), |
| 2199 | .siclk(siclk), |
| 2200 | .soclk(soclk), |
| 2201 | .d(fdin[21]), |
| 2202 | .si(sout[22]), |
| 2203 | .so(sout[21]), |
| 2204 | .reset(reset), |
| 2205 | .q(dout[21]) |
| 2206 | ); |
| 2207 | cl_a1_msff_syrst_4x d0_22 ( |
| 2208 | .l1clk(l1clk), |
| 2209 | .siclk(siclk), |
| 2210 | .soclk(soclk), |
| 2211 | .d(fdin[22]), |
| 2212 | .si(sout[23]), |
| 2213 | .so(sout[22]), |
| 2214 | .reset(reset), |
| 2215 | .q(dout[22]) |
| 2216 | ); |
| 2217 | cl_a1_msff_syrst_4x d0_23 ( |
| 2218 | .l1clk(l1clk), |
| 2219 | .siclk(siclk), |
| 2220 | .soclk(soclk), |
| 2221 | .d(fdin[23]), |
| 2222 | .si(sout[24]), |
| 2223 | .so(sout[23]), |
| 2224 | .reset(reset), |
| 2225 | .q(dout[23]) |
| 2226 | ); |
| 2227 | cl_a1_msff_syrst_4x d0_24 ( |
| 2228 | .l1clk(l1clk), |
| 2229 | .siclk(siclk), |
| 2230 | .soclk(soclk), |
| 2231 | .d(fdin[24]), |
| 2232 | .si(sout[25]), |
| 2233 | .so(sout[24]), |
| 2234 | .reset(reset), |
| 2235 | .q(dout[24]) |
| 2236 | ); |
| 2237 | cl_a1_msff_syrst_4x d0_25 ( |
| 2238 | .l1clk(l1clk), |
| 2239 | .siclk(siclk), |
| 2240 | .soclk(soclk), |
| 2241 | .d(fdin[25]), |
| 2242 | .si(sout[26]), |
| 2243 | .so(sout[25]), |
| 2244 | .reset(reset), |
| 2245 | .q(dout[25]) |
| 2246 | ); |
| 2247 | cl_a1_msff_syrst_4x d0_26 ( |
| 2248 | .l1clk(l1clk), |
| 2249 | .siclk(siclk), |
| 2250 | .soclk(soclk), |
| 2251 | .d(fdin[26]), |
| 2252 | .si(sout[27]), |
| 2253 | .so(sout[26]), |
| 2254 | .reset(reset), |
| 2255 | .q(dout[26]) |
| 2256 | ); |
| 2257 | cl_a1_msff_syrst_4x d0_27 ( |
| 2258 | .l1clk(l1clk), |
| 2259 | .siclk(siclk), |
| 2260 | .soclk(soclk), |
| 2261 | .d(fdin[27]), |
| 2262 | .si(sout[28]), |
| 2263 | .so(sout[27]), |
| 2264 | .reset(reset), |
| 2265 | .q(dout[27]) |
| 2266 | ); |
| 2267 | cl_a1_msff_syrst_4x d0_28 ( |
| 2268 | .l1clk(l1clk), |
| 2269 | .siclk(siclk), |
| 2270 | .soclk(soclk), |
| 2271 | .d(fdin[28]), |
| 2272 | .si(sout[29]), |
| 2273 | .so(sout[28]), |
| 2274 | .reset(reset), |
| 2275 | .q(dout[28]) |
| 2276 | ); |
| 2277 | cl_a1_msff_syrst_4x d0_29 ( |
| 2278 | .l1clk(l1clk), |
| 2279 | .siclk(siclk), |
| 2280 | .soclk(soclk), |
| 2281 | .d(fdin[29]), |
| 2282 | .si(sout[30]), |
| 2283 | .so(sout[29]), |
| 2284 | .reset(reset), |
| 2285 | .q(dout[29]) |
| 2286 | ); |
| 2287 | cl_a1_msff_syrst_4x d0_30 ( |
| 2288 | .l1clk(l1clk), |
| 2289 | .siclk(siclk), |
| 2290 | .soclk(soclk), |
| 2291 | .d(fdin[30]), |
| 2292 | .si(sout[31]), |
| 2293 | .so(sout[30]), |
| 2294 | .reset(reset), |
| 2295 | .q(dout[30]) |
| 2296 | ); |
| 2297 | cl_a1_msff_syrst_4x d0_31 ( |
| 2298 | .l1clk(l1clk), |
| 2299 | .siclk(siclk), |
| 2300 | .soclk(soclk), |
| 2301 | .d(fdin[31]), |
| 2302 | .si(sout[32]), |
| 2303 | .so(sout[31]), |
| 2304 | .reset(reset), |
| 2305 | .q(dout[31]) |
| 2306 | ); |
| 2307 | cl_a1_msff_syrst_4x d0_32 ( |
| 2308 | .l1clk(l1clk), |
| 2309 | .siclk(siclk), |
| 2310 | .soclk(soclk), |
| 2311 | .d(fdin[32]), |
| 2312 | .si(sout[33]), |
| 2313 | .so(sout[32]), |
| 2314 | .reset(reset), |
| 2315 | .q(dout[32]) |
| 2316 | ); |
| 2317 | cl_a1_msff_syrst_4x d0_33 ( |
| 2318 | .l1clk(l1clk), |
| 2319 | .siclk(siclk), |
| 2320 | .soclk(soclk), |
| 2321 | .d(fdin[33]), |
| 2322 | .si(sout[34]), |
| 2323 | .so(sout[33]), |
| 2324 | .reset(reset), |
| 2325 | .q(dout[33]) |
| 2326 | ); |
| 2327 | cl_a1_msff_syrst_4x d0_34 ( |
| 2328 | .l1clk(l1clk), |
| 2329 | .siclk(siclk), |
| 2330 | .soclk(soclk), |
| 2331 | .d(fdin[34]), |
| 2332 | .si(sout[35]), |
| 2333 | .so(sout[34]), |
| 2334 | .reset(reset), |
| 2335 | .q(dout[34]) |
| 2336 | ); |
| 2337 | cl_a1_msff_syrst_4x d0_35 ( |
| 2338 | .l1clk(l1clk), |
| 2339 | .siclk(siclk), |
| 2340 | .soclk(soclk), |
| 2341 | .d(fdin[35]), |
| 2342 | .si(sout[36]), |
| 2343 | .so(sout[35]), |
| 2344 | .reset(reset), |
| 2345 | .q(dout[35]) |
| 2346 | ); |
| 2347 | cl_a1_msff_syrst_4x d0_36 ( |
| 2348 | .l1clk(l1clk), |
| 2349 | .siclk(siclk), |
| 2350 | .soclk(soclk), |
| 2351 | .d(fdin[36]), |
| 2352 | .si(sout[37]), |
| 2353 | .so(sout[36]), |
| 2354 | .reset(reset), |
| 2355 | .q(dout[36]) |
| 2356 | ); |
| 2357 | cl_a1_msff_syrst_4x d0_37 ( |
| 2358 | .l1clk(l1clk), |
| 2359 | .siclk(siclk), |
| 2360 | .soclk(soclk), |
| 2361 | .d(fdin[37]), |
| 2362 | .si(sout[38]), |
| 2363 | .so(sout[37]), |
| 2364 | .reset(reset), |
| 2365 | .q(dout[37]) |
| 2366 | ); |
| 2367 | cl_a1_msff_syrst_4x d0_38 ( |
| 2368 | .l1clk(l1clk), |
| 2369 | .siclk(siclk), |
| 2370 | .soclk(soclk), |
| 2371 | .d(fdin[38]), |
| 2372 | .si(sout[39]), |
| 2373 | .so(sout[38]), |
| 2374 | .reset(reset), |
| 2375 | .q(dout[38]) |
| 2376 | ); |
| 2377 | cl_a1_msff_syrst_4x d0_39 ( |
| 2378 | .l1clk(l1clk), |
| 2379 | .siclk(siclk), |
| 2380 | .soclk(soclk), |
| 2381 | .d(fdin[39]), |
| 2382 | .si(scan_in), |
| 2383 | .so(sout[39]), |
| 2384 | .reset(reset), |
| 2385 | .q(dout[39]) |
| 2386 | ); |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | |
| 2391 | endmodule |
| 2392 | |
| 2393 | |
| 2394 | |
| 2395 | |
| 2396 | |
| 2397 | |
| 2398 | |
| 2399 | |