| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_meta_arb_syncfifo.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
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| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
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| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * niu_meta_arb_syncfifo.v |
| 38 | * |
| 39 | * Parameterized synchronous fifo |
| 40 | * |
| 41 | * Original Author(s): Nimita Taneja |
| 42 | * Modifier(s): |
| 43 | * Project(s): Neptune |
| 44 | * |
| 45 | * Copyright (c) 2004 Sun Microsystems, Inc. |
| 46 | * |
| 47 | * Revision History: 03-01-2004 : Initial Release |
| 48 | * |
| 49 | * All Rights Reserved. |
| 50 | * |
| 51 | * This verilog model is the confidential and proprietary property of |
| 52 | * Sun Microsystems, Inc., and the possession or use of this model |
| 53 | * requires a written license from Sun Microsystems, Inc. |
| 54 | * |
| 55 | **********************************************************************/ |
| 56 | |
| 57 | module niu_meta_arb_syncfifo (core_clk, reset , inc_rp, inc_wp, fifo_not_empty, |
| 58 | fifo_full, din, rdout, dout, count); |
| 59 | |
| 60 | parameter WIDTH = 16; |
| 61 | parameter [31:0] DEPTH = 4; |
| 62 | parameter ASIZE = 2; |
| 63 | |
| 64 | input core_clk, reset , inc_rp, inc_wp; |
| 65 | input [WIDTH-1:0] din; |
| 66 | |
| 67 | output fifo_not_empty, fifo_full; |
| 68 | output [WIDTH-1:0] rdout; |
| 69 | output [WIDTH-1:0] dout; |
| 70 | output [ASIZE:0] count; |
| 71 | |
| 72 | |
| 73 | reg [WIDTH-1:0] fifo[0:DEPTH-1]; |
| 74 | reg [ASIZE-1:0] wp; |
| 75 | reg [ASIZE-1:0] rp; |
| 76 | wire [WIDTH-1:0] dout; |
| 77 | reg [WIDTH-1:0] rdout; |
| 78 | reg [ASIZE:0] fifosize; |
| 79 | wire fifo_not_empty; |
| 80 | wire fifo_empty; |
| 81 | wire fifo_full; |
| 82 | integer i; |
| 83 | wire [ASIZE:0] count; |
| 84 | assign count = fifosize; |
| 85 | |
| 86 | assign fifo_full = (fifosize==DEPTH[ASIZE:0]); |
| 87 | |
| 88 | // synopsys translate_off |
| 89 | `ifdef META_ERR_CHECK |
| 90 | reg error; |
| 91 | always@(posedge core_clk) begin |
| 92 | if (reset) error <= 0; |
| 93 | else if (fifo_full & inc_wp) begin |
| 94 | error = 1; |
| 95 | $display($time, " %m -ERROR: fifo overrun !!!!!!!!!"); |
| 96 | repeat(10) @(posedge core_clk); |
| 97 | end |
| 98 | else if ((fifosize == 0) & inc_rp) begin |
| 99 | error = 1; |
| 100 | $display($time, " %m -ERROR: fifo underrun !!!!!!!!!"); |
| 101 | repeat(10) @(posedge core_clk); |
| 102 | end |
| 103 | end |
| 104 | `endif |
| 105 | // synopsys translate_on |
| 106 | |
| 107 | always@(posedge core_clk) |
| 108 | if (reset) fifosize <= 0; |
| 109 | else if (inc_wp & !inc_rp) fifosize <= fifosize +1'b1; |
| 110 | else if (!inc_wp & inc_rp) fifosize <= fifosize -1'b1; |
| 111 | else fifosize <= fifosize; |
| 112 | |
| 113 | |
| 114 | |
| 115 | assign fifo_not_empty = fifosize > 0; |
| 116 | assign fifo_empty = (fifosize == 0); |
| 117 | |
| 118 | always@(posedge core_clk) |
| 119 | if (reset) wp <= 0; |
| 120 | else if (inc_wp & !fifo_full) wp <= wp + 1'b1; |
| 121 | |
| 122 | always@(posedge core_clk) |
| 123 | if (reset) rp <= 0; |
| 124 | else if (inc_rp & !fifo_empty) rp <= rp + 1'b1; |
| 125 | |
| 126 | always@(posedge core_clk) |
| 127 | if (reset) begin |
| 128 | for (i=0; i<DEPTH; i=i+1) fifo[i] <= 0; |
| 129 | end |
| 130 | else if (inc_wp) |
| 131 | fifo[wp] <= din; |
| 132 | else begin |
| 133 | for (i=0; i<DEPTH; i=i+1) fifo[i] <= fifo[i]; |
| 134 | end |
| 135 | /* |
| 136 | always@(rp or fifo[0] or fifo[1] or fifo_not_empty) |
| 137 | case(rp) // synopsys parallel_case |
| 138 | 1'b0: dout = fifo[0] & {WIDTH{fifo_not_empty}}; |
| 139 | 1'b1: dout = fifo[1] & {WIDTH{fifo_not_empty}}; |
| 140 | default: dout = fifo[0] & {WIDTH{fifo_not_empty}}; |
| 141 | endcase |
| 142 | */ |
| 143 | |
| 144 | assign dout = fifo[rp] & {WIDTH{fifo_not_empty}}; |
| 145 | |
| 146 | always@(posedge core_clk) |
| 147 | if (reset) |
| 148 | rdout <= 0; |
| 149 | else |
| 150 | rdout <= dout; |
| 151 | |
| 152 | endmodule |