| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_rd_meta_arb.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
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| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*----------------------------------------------------------------------------- |
| 36 | ------------------------------------------------------------------------------- |
| 37 | -- Company: Sun Microsystems, Inc. |
| 38 | -- SUN CONFIDENTIAL/PROPRIETARY - Copyright 2004 |
| 39 | -- Description: [Verilog RTL Code] |
| 40 | -- Read META Arb |
| 41 | -- TransID Management |
| 42 | -- Project: Niagara2/Neptune |
| 43 | -- Platform: |
| 44 | -- Parent Module: NIU |
| 45 | -- Module: NIU_RD_META_ARB |
| 46 | -- Designer: Carl Childers |
| 47 | : Nimita Taneja |
| 48 | -- Date Created: 07/01/2004 |
| 49 | -- Date Modified 10/11/2004 |
| 50 | -- Notes: |
| 51 | -- 1. |
| 52 | -- 2. |
| 53 | -- Rev: 0.1; Board Rev: P1.0 |
| 54 | ------------------------------------------------------------------------------- |
| 55 | -----------------------------------------------------------------------------*/ |
| 56 | |
| 57 | /*-------------------------------------- |
| 58 | -- Module |
| 59 | --------------------------------------*/ |
| 60 | |
| 61 | module niu_rd_meta_arb ( /*AUTOARG*/ |
| 62 | // Outputs |
| 63 | dmc_meta1_req_cmd, dmc_meta1_req_address, dmc_meta1_req_length, |
| 64 | dmc_meta1_req_transID, dmc_meta1_req_port_num, |
| 65 | dmc_meta1_req_dma_num, dmc_meta1_req_func_num, |
| 66 | dmc_meta1_req_client, dmc_meta1_req, arb1_zcp_req_accept, |
| 67 | arb1_zcp_req_errors, arb1_txc_req_accept, arb1_txc_req_errors, |
| 68 | arb1_tdmc_req_accept, arb1_tdmc_req_errors, arb1_rbr_req_accept, |
| 69 | arb1_rbr_req_errors, arb_pio_dirtid_rdstatus, arb_pio_all_rddirty, |
| 70 | // Inputs |
| 71 | meta_dmc1_req_accept, meta_dmc1_req_errors, zcp_arb1_req_cmd, |
| 72 | zcp_arb1_req_address, zcp_arb1_req_length, zcp_arb1_req_port_num, |
| 73 | zcp_arb1_req_dma_num, zcp_arb1_req_func_num, zcp_arb1_req, |
| 74 | txc_arb1_req_cmd, txc_arb1_req_address, txc_arb1_req_length, |
| 75 | txc_arb1_req_port_num, txc_arb1_req_dma_num, |
| 76 | txc_arb1_req_func_num, txc_arb1_req, tdmc_arb1_req_cmd, |
| 77 | tdmc_arb1_req_address, tdmc_arb1_req_length, |
| 78 | tdmc_arb1_req_port_num, tdmc_arb1_req_dma_num, |
| 79 | tdmc_arb1_req_func_num, tdmc_arb1_req, rbr_arb1_req_cmd, |
| 80 | rbr_arb1_req_address, rbr_arb1_req_length, rbr_arb1_req_port_num, |
| 81 | rbr_arb1_req_dma_num, rbr_arb1_req_func_num, rbr_arb1_req, |
| 82 | meta_dmc_resp_transID, dmc_meta_resp_accept, |
| 83 | meta_dmc_resp_transfer_cmpl, meta_dmc_resp_cmd_status, |
| 84 | pio_arb_dirtid_enable, pio_arb_dirtid_clr, pio_arb_rd_threshold, |
| 85 | clk, reset |
| 86 | ); // from reset |
| 87 | |
| 88 | |
| 89 | /*----------------------------------------------------------------------------- |
| 90 | -- Declarations |
| 91 | -----------------------------------------------------------------------------*/ |
| 92 | /*-------------------------------------- |
| 93 | -- Port Declaration |
| 94 | --------------------------------------*/ |
| 95 | |
| 96 | // META Request Outputs |
| 97 | output [7:0] dmc_meta1_req_cmd; // Command Request |
| 98 | output [63:0] dmc_meta1_req_address; // Memory Address |
| 99 | output [13:0] dmc_meta1_req_length; // Packet Length |
| 100 | output [5:0] dmc_meta1_req_transID; // Transaction ID |
| 101 | output [1:0] dmc_meta1_req_port_num; // Port Number |
| 102 | output [4:0] dmc_meta1_req_dma_num; // Channel Number |
| 103 | output [1:0] dmc_meta1_req_func_num; // Channel Number |
| 104 | output [7:0] dmc_meta1_req_client; // Client [vector] |
| 105 | output dmc_meta1_req; // Req Command Request |
| 106 | |
| 107 | // ZCP I/F Outputs |
| 108 | output arb1_zcp_req_accept; // Response to REQ |
| 109 | output arb1_zcp_req_errors; // Error flag |
| 110 | |
| 111 | // TXC I/F Output |
| 112 | output arb1_txc_req_accept; // Response to REQ |
| 113 | output arb1_txc_req_errors; // Error flag |
| 114 | |
| 115 | // TDMC I/F Output |
| 116 | output arb1_tdmc_req_accept; // Response to REQ |
| 117 | output arb1_tdmc_req_errors; // Error flag |
| 118 | |
| 119 | // RCR I/F Output |
| 120 | // output arb1_rcr_req_accept; // Response to REQ |
| 121 | // output arb1_rcr_req_errors; // Error flag |
| 122 | |
| 123 | // RBR I/F Output |
| 124 | output arb1_rbr_req_accept; // Response to REQ |
| 125 | output arb1_rbr_req_errors; // Error flag |
| 126 | |
| 127 | // Read Dirty TID status |
| 128 | output [5:0] arb_pio_dirtid_rdstatus; // count for number of read TID's dirty |
| 129 | output arb_pio_all_rddirty; // all dirty bin entries are dirty |
| 130 | |
| 131 | |
| 132 | // META Request Inputs |
| 133 | input meta_dmc1_req_accept; // Response to REQ |
| 134 | input meta_dmc1_req_errors; // Error flag |
| 135 | |
| 136 | // ZCP I/F Inputs |
| 137 | input [7:0] zcp_arb1_req_cmd; // Command Request |
| 138 | input [63:0] zcp_arb1_req_address; // Memory Address |
| 139 | input [13:0] zcp_arb1_req_length; // Packet Length |
| 140 | input [1:0] zcp_arb1_req_port_num; // Port Number |
| 141 | input [4:0] zcp_arb1_req_dma_num; // Channel Number |
| 142 | input [1:0] zcp_arb1_req_func_num; // Channel Number |
| 143 | input zcp_arb1_req; // Req Command Request |
| 144 | |
| 145 | // TXC I/F Inputs |
| 146 | input [7:0] txc_arb1_req_cmd; // Command Request |
| 147 | input [63:0] txc_arb1_req_address; // Memory Address |
| 148 | input [13:0] txc_arb1_req_length; // Packet Length |
| 149 | input [1:0] txc_arb1_req_port_num; // Port Number |
| 150 | input [4:0] txc_arb1_req_dma_num; // Channel Number |
| 151 | input [1:0] txc_arb1_req_func_num; // Channel Number |
| 152 | input txc_arb1_req; // Req Command Request |
| 153 | |
| 154 | // TDMC I/F Inputs |
| 155 | input [7:0] tdmc_arb1_req_cmd; // Command Request |
| 156 | input [63:0] tdmc_arb1_req_address; // Memory Address |
| 157 | input [13:0] tdmc_arb1_req_length; // Packet Length |
| 158 | input [1:0] tdmc_arb1_req_port_num; // Port Number |
| 159 | input [4:0] tdmc_arb1_req_dma_num; // Channel Number |
| 160 | input [1:0] tdmc_arb1_req_func_num; // Channel Number |
| 161 | input tdmc_arb1_req; // Req Command Request |
| 162 | |
| 163 | // RCR I/F Inputs |
| 164 | // input [7:0] rcr_arb1_req_cmd; // Command Request |
| 165 | // input [63:0] rcr_arb1_req_address; // Memory Address |
| 166 | // input [13:0] rcr_arb1_req_length; // Packet Length |
| 167 | // input [1:0] rcr_arb1_req_port_num; // Port Number |
| 168 | // input [4:0] rcr_arb1_req_dma_num; // Channel Number |
| 169 | // input rcr_arb1_req; // Req Command Request |
| 170 | |
| 171 | // RBR I/F Inputs |
| 172 | input [7:0] rbr_arb1_req_cmd; // Command Request |
| 173 | input [63:0] rbr_arb1_req_address; // Memory Address |
| 174 | input [13:0] rbr_arb1_req_length; // Packet Length |
| 175 | input [1:0] rbr_arb1_req_port_num; // Port Number |
| 176 | input [4:0] rbr_arb1_req_dma_num; // Channel Number |
| 177 | input [1:0] rbr_arb1_req_func_num; // Channel Number |
| 178 | input rbr_arb1_req; // Req Command Request |
| 179 | |
| 180 | // META Response Input |
| 181 | input [5:0] meta_dmc_resp_transID; // Free TransID |
| 182 | input [7:0] dmc_meta_resp_accept; // Valid TransID |
| 183 | input [7:0] meta_dmc_resp_transfer_cmpl; // Last trans of TransID |
| 184 | input [3:0] meta_dmc_resp_cmd_status; // status in command phase |
| 185 | |
| 186 | //Dirty TID Interface |
| 187 | input pio_arb_dirtid_enable; // Enable Dirty TID logic |
| 188 | input pio_arb_dirtid_clr; // Clear all Dirty TID Entries |
| 189 | input [5:0] pio_arb_rd_threshold; // read threshold |
| 190 | |
| 191 | // other inputs |
| 192 | input clk; // core clock |
| 193 | input reset; // reset |
| 194 | |
| 195 | |
| 196 | /***************************************/ |
| 197 | /* Wire Declaration */ |
| 198 | /***************************************/ |
| 199 | |
| 200 | /*AUTOWIRE*/ |
| 201 | // Beginning of automatic wires (for undeclared instantiated-module outputs) |
| 202 | // End of automatics |
| 203 | |
| 204 | |
| 205 | |
| 206 | |
| 207 | wire arb1_fifo_not_empty; // From arb_tagfifo of arb_tagfifo.v |
| 208 | wire [4:0] rdtagoutR; // From arb_tagfifo of arb_tagfifo.v |
| 209 | |
| 210 | |
| 211 | |
| 212 | |
| 213 | wire meta_dmc_resp_transfer_cmpl_ORd; |
| 214 | wire dmc_meta_resp_accept_ORd; |
| 215 | |
| 216 | wire transaction_timeout; |
| 217 | wire [5:0] dirty_tag_count; |
| 218 | wire dirtybinfifo_not_empty; |
| 219 | wire dirtybinfifo_full; |
| 220 | wire [4:0] dirty_tag; |
| 221 | wire arb_pio_all_rddirty; |
| 222 | wire rd_threshold_reached; |
| 223 | |
| 224 | /***************************************/ |
| 225 | /* Reg Declaration */ |
| 226 | /***************************************/ |
| 227 | /*AUTOREG*/ |
| 228 | // Beginning of automatic regs (for this module's undeclared outputs) |
| 229 | // End of automatics |
| 230 | |
| 231 | reg [2:0] arb_control_sel_ff, |
| 232 | arb_control_sel_in; |
| 233 | reg arb_control_sel_ld; |
| 234 | |
| 235 | |
| 236 | // Transaction ID tag read and write pointer incrementer |
| 237 | reg read_tag; |
| 238 | reg write_tag; |
| 239 | reg write_dirty_tag; |
| 240 | reg [4:0] meta_dmc_resp_transID_cmpl; |
| 241 | reg [4:0] meta_dmc_resp_transIDR; |
| 242 | reg [4:0] meta_dmc_resp_transID0R; |
| 243 | reg [4:0] meta_dmc_resp_transID1R; |
| 244 | reg [4:0] meta_dmc_resp_transID2R; |
| 245 | reg [4:0] meta_dmc_resp_transID3R; |
| 246 | reg [4:0] meta_dmc_resp_transID4R; |
| 247 | reg [4:0] meta_dmc_resp_transID5R; |
| 248 | reg [4:0] meta_dmc_resp_transID6R; |
| 249 | reg [4:0] meta_dmc_resp_transID7R; |
| 250 | reg [3:0] meta_dmc_resp_cmd_statusR; |
| 251 | reg [4:0] reclaimed_transID; |
| 252 | |
| 253 | // Arb Control MUX |
| 254 | reg [7:0] mux_dmc_meta1_req_cmd; |
| 255 | reg [63:0] mux_dmc_meta1_req_address; |
| 256 | reg [13:0] mux_dmc_meta1_req_length; |
| 257 | reg [1:0] mux_dmc_meta1_req_port_num; |
| 258 | reg [4:0] mux_dmc_meta1_req_dma_num; |
| 259 | reg [1:0] mux_dmc_meta1_req_func_num; |
| 260 | reg [7:0] mux_dmc_meta1_req_client; |
| 261 | reg mux_dmc_meta1_req; |
| 262 | |
| 263 | reg demux_arb1_zcp_req_accept; |
| 264 | reg demux_arb1_zcp_req_errors; |
| 265 | |
| 266 | reg demux_arb1_txc_req_accept; |
| 267 | reg demux_arb1_txc_req_errors; |
| 268 | |
| 269 | reg demux_arb1_tdmc_req_accept; |
| 270 | reg demux_arb1_tdmc_req_errors; |
| 271 | |
| 272 | // reg demux_arb1_rcr_req_accept; |
| 273 | // reg demux_arb1_rcr_req_errors; |
| 274 | |
| 275 | reg demux_arb1_rbr_req_accept; |
| 276 | reg demux_arb1_rbr_req_errors; |
| 277 | |
| 278 | |
| 279 | reg [3:0] current_arb_control_state_ff, |
| 280 | next_arb_control_state; |
| 281 | |
| 282 | // dirty bin registers |
| 283 | reg transfer_cmpl_pending; |
| 284 | reg [5:0] arb_pio_dirtid_rdstatus; |
| 285 | reg [1:0] dirbin_state, dirbin_stateR; |
| 286 | reg inc_dirtybinfifo_rp; |
| 287 | reg return_dirty_tag; |
| 288 | reg [5:0] outstanding_tid_cnt; |
| 289 | |
| 290 | wire inc_outstanding_tid_cnt= meta_dmc1_req_accept & ~meta_dmc_resp_transfer_cmpl_ORd; |
| 291 | wire dec_outstanding_tid_cnt= meta_dmc_resp_transfer_cmpl_ORd & ~meta_dmc1_req_accept; |
| 292 | wire [5:0] outstanding_tid_cnt_plus1= outstanding_tid_cnt + 1'b1; |
| 293 | wire [5:0] outstanding_tid_cnt_minus1= outstanding_tid_cnt - 1'b1; |
| 294 | wire [5:0] outstanding_tid_cnt_add_n= (outstanding_tid_cnt==6'd32)? 6'h0 : outstanding_tid_cnt_plus1; |
| 295 | wire [5:0] outstanding_tid_cnt_sub_n= (outstanding_tid_cnt==6'd0)? 6'h0 : outstanding_tid_cnt_minus1; |
| 296 | |
| 297 | /***************************************/ |
| 298 | /* Parameter Declaration */ |
| 299 | /***************************************/ |
| 300 | |
| 301 | parameter [2:0] NULL = 3'b000, |
| 302 | ZCP = 3'b001, |
| 303 | TXC = 3'b010, |
| 304 | TDMC = 3'b011, |
| 305 | RBR = 3'b101; |
| 306 | |
| 307 | // RCR = 3'b100 |
| 308 | |
| 309 | parameter [7:0] NULL_CLIENT = 8'h00, |
| 310 | ZCP_CLIENT = 8'h01, |
| 311 | TXC_CLIENT = 8'h02, |
| 312 | TDMC_CLIENT = 8'h04, |
| 313 | RBR_CLIENT = 8'h20; |
| 314 | |
| 315 | // RDC_CLIENT = 8'h08 |
| 316 | |
| 317 | parameter [3:0] CACS0 = 4'b0000, |
| 318 | CACS1 = 4'b0001, |
| 319 | CACS2 = 4'b0010, |
| 320 | CACS3 = 4'b0011, |
| 321 | CACS4 = 4'b0100, |
| 322 | CACS5 = 4'b0101, |
| 323 | CACS6 = 4'b0110, |
| 324 | CACS7 = 4'b0111, |
| 325 | CACS8 = 4'b1000, |
| 326 | CACS9 = 4'b1001; |
| 327 | |
| 328 | parameter ZERO_1 = 1'b0; |
| 329 | parameter [1:0] ZEROES_2 = 2'b00; |
| 330 | parameter [4:0] ZEROES_5 = 5'b00000; |
| 331 | parameter [7:0] ZEROES_8 = 8'b00000000; |
| 332 | parameter [13:0] ZEROES_14 = 14'b00000000000000; |
| 333 | parameter [63:0] ZEROES_64 = 64'h0000; |
| 334 | |
| 335 | // misc |
| 336 | parameter ASSERT_H = 1'b1, |
| 337 | DEASSERT_L = 1'b0, |
| 338 | TRUE_H = 1'b1; |
| 339 | |
| 340 | parameter [1:0] IDLEBIN = 2'b00, |
| 341 | CLRBIN = 2'b01, |
| 342 | RDBIN = 2'b10; |
| 343 | |
| 344 | |
| 345 | /*----------------------------------------------------------------------------- |
| 346 | -- Output Assignments |
| 347 | -----------------------------------------------------------------------------*/ |
| 348 | // META Request Outputs |
| 349 | assign dmc_meta1_req_cmd = mux_dmc_meta1_req_cmd; |
| 350 | assign dmc_meta1_req_address = mux_dmc_meta1_req_address; |
| 351 | assign dmc_meta1_req_length = mux_dmc_meta1_req_length; |
| 352 | assign dmc_meta1_req_transID = {1'b0,rdtagoutR}; |
| 353 | assign dmc_meta1_req_port_num = mux_dmc_meta1_req_port_num; |
| 354 | assign dmc_meta1_req_dma_num = mux_dmc_meta1_req_dma_num; |
| 355 | assign dmc_meta1_req_func_num = mux_dmc_meta1_req_func_num; |
| 356 | assign dmc_meta1_req_client = mux_dmc_meta1_req_client; |
| 357 | assign dmc_meta1_req = mux_dmc_meta1_req; |
| 358 | |
| 359 | // ZCP I/F Outputs |
| 360 | assign arb1_zcp_req_accept = demux_arb1_zcp_req_accept; |
| 361 | assign arb1_zcp_req_errors = demux_arb1_zcp_req_errors; |
| 362 | |
| 363 | // TXC I/F Outputs |
| 364 | assign arb1_txc_req_accept = demux_arb1_txc_req_accept; |
| 365 | assign arb1_txc_req_errors = demux_arb1_txc_req_errors; |
| 366 | |
| 367 | // TDMC I/F Outputs |
| 368 | assign arb1_tdmc_req_accept = demux_arb1_tdmc_req_accept; |
| 369 | assign arb1_tdmc_req_errors = demux_arb1_tdmc_req_errors; |
| 370 | |
| 371 | // RCR I/F Outputs |
| 372 | // assign arb1_rcr_req_accept = demux_arb1_rcr_req_accept; |
| 373 | // assign arb1_rcr_req_errors = demux_arb1_rcr_req_errors; |
| 374 | |
| 375 | // RBR I/F Outputs |
| 376 | assign arb1_rbr_req_accept = demux_arb1_rbr_req_accept; |
| 377 | assign arb1_rbr_req_errors = demux_arb1_rbr_req_errors; |
| 378 | |
| 379 | |
| 380 | /*----------------------------------------------------------------------------- |
| 381 | -- Arbitration CONTROL |
| 382 | -----------------------------------------------------------------------------*/ |
| 383 | /*-------------------------------------- |
| 384 | -- Concurrent combinatorial logic: Arbitration CONTROL MUX |
| 385 | --------------------------------------*/ |
| 386 | |
| 387 | always @ (/*AUTOSENSE*/arb_control_sel_ff or meta_dmc1_req_accept |
| 388 | or meta_dmc1_req_errors or rbr_arb1_req |
| 389 | or rbr_arb1_req_address or rbr_arb1_req_cmd |
| 390 | or rbr_arb1_req_dma_num or rbr_arb1_req_func_num |
| 391 | or rbr_arb1_req_length or rbr_arb1_req_port_num |
| 392 | or tdmc_arb1_req or tdmc_arb1_req_address |
| 393 | or tdmc_arb1_req_cmd or tdmc_arb1_req_dma_num |
| 394 | or tdmc_arb1_req_func_num or tdmc_arb1_req_length |
| 395 | or tdmc_arb1_req_port_num or txc_arb1_req |
| 396 | or txc_arb1_req_address or txc_arb1_req_cmd |
| 397 | or txc_arb1_req_dma_num or txc_arb1_req_func_num |
| 398 | or txc_arb1_req_length or txc_arb1_req_port_num |
| 399 | or zcp_arb1_req or zcp_arb1_req_address |
| 400 | or zcp_arb1_req_cmd or zcp_arb1_req_dma_num |
| 401 | or zcp_arb1_req_func_num or zcp_arb1_req_length |
| 402 | or zcp_arb1_req_port_num) |
| 403 | |
| 404 | begin: arbitration_control_mux |
| 405 | mux_dmc_meta1_req_cmd = ZEROES_8; |
| 406 | mux_dmc_meta1_req_address = ZEROES_64; |
| 407 | mux_dmc_meta1_req_length = ZEROES_14; |
| 408 | mux_dmc_meta1_req_port_num = ZEROES_2; |
| 409 | mux_dmc_meta1_req_dma_num = ZEROES_5; |
| 410 | mux_dmc_meta1_req_func_num = ZEROES_2; |
| 411 | mux_dmc_meta1_req_client = NULL_CLIENT; |
| 412 | mux_dmc_meta1_req = ZERO_1; |
| 413 | |
| 414 | demux_arb1_zcp_req_accept = ZERO_1; |
| 415 | demux_arb1_zcp_req_errors = ZERO_1; |
| 416 | |
| 417 | demux_arb1_txc_req_accept = ZERO_1; |
| 418 | demux_arb1_txc_req_errors = ZERO_1; |
| 419 | |
| 420 | demux_arb1_tdmc_req_accept = ZERO_1; |
| 421 | demux_arb1_tdmc_req_errors = ZERO_1; |
| 422 | |
| 423 | // demux_arb1_rcr_req_accept = ZERO_1; |
| 424 | // demux_arb1_rcr_req_errors = ZERO_1; |
| 425 | |
| 426 | demux_arb1_rbr_req_accept = ZERO_1; |
| 427 | demux_arb1_rbr_req_errors = ZERO_1; |
| 428 | |
| 429 | case (arb_control_sel_ff) /* synopsys parallel_case full_case */ |
| 430 | NULL: begin |
| 431 | mux_dmc_meta1_req_cmd = ZEROES_8; |
| 432 | mux_dmc_meta1_req_address = ZEROES_64; |
| 433 | mux_dmc_meta1_req_length = ZEROES_14; |
| 434 | mux_dmc_meta1_req_port_num = ZEROES_2; |
| 435 | mux_dmc_meta1_req_dma_num = ZEROES_5; |
| 436 | mux_dmc_meta1_req_func_num = ZEROES_2; |
| 437 | mux_dmc_meta1_req_client = NULL_CLIENT; |
| 438 | mux_dmc_meta1_req = ZERO_1; |
| 439 | |
| 440 | demux_arb1_zcp_req_accept = ZERO_1; |
| 441 | demux_arb1_zcp_req_errors = ZERO_1; |
| 442 | |
| 443 | demux_arb1_txc_req_accept = ZERO_1; |
| 444 | demux_arb1_txc_req_errors = ZERO_1; |
| 445 | |
| 446 | demux_arb1_tdmc_req_accept = ZERO_1; |
| 447 | demux_arb1_tdmc_req_errors = ZERO_1; |
| 448 | |
| 449 | // demux_arb1_rcr_req_accept = ZERO_1; |
| 450 | // demux_arb1_rcr_req_errors = ZERO_1; |
| 451 | |
| 452 | demux_arb1_rbr_req_accept = ZERO_1; |
| 453 | demux_arb1_rbr_req_errors = ZERO_1; |
| 454 | end |
| 455 | ZCP: begin |
| 456 | mux_dmc_meta1_req_cmd = zcp_arb1_req_cmd; |
| 457 | mux_dmc_meta1_req_address = zcp_arb1_req_address; |
| 458 | mux_dmc_meta1_req_length = zcp_arb1_req_length; |
| 459 | mux_dmc_meta1_req_port_num = zcp_arb1_req_port_num; |
| 460 | mux_dmc_meta1_req_dma_num = zcp_arb1_req_dma_num; |
| 461 | mux_dmc_meta1_req_func_num = zcp_arb1_req_func_num; |
| 462 | mux_dmc_meta1_req_client = ZCP_CLIENT; |
| 463 | mux_dmc_meta1_req = zcp_arb1_req; |
| 464 | |
| 465 | demux_arb1_zcp_req_accept = meta_dmc1_req_accept; |
| 466 | demux_arb1_zcp_req_errors = meta_dmc1_req_errors; |
| 467 | end |
| 468 | TXC: begin |
| 469 | mux_dmc_meta1_req_cmd = txc_arb1_req_cmd; |
| 470 | mux_dmc_meta1_req_address = txc_arb1_req_address; |
| 471 | mux_dmc_meta1_req_length = txc_arb1_req_length; |
| 472 | mux_dmc_meta1_req_port_num = txc_arb1_req_port_num; |
| 473 | mux_dmc_meta1_req_dma_num = txc_arb1_req_dma_num; |
| 474 | mux_dmc_meta1_req_func_num = txc_arb1_req_func_num; |
| 475 | mux_dmc_meta1_req_client = TXC_CLIENT; |
| 476 | mux_dmc_meta1_req = txc_arb1_req; |
| 477 | |
| 478 | demux_arb1_txc_req_accept = meta_dmc1_req_accept; |
| 479 | demux_arb1_txc_req_errors = meta_dmc1_req_errors; |
| 480 | end |
| 481 | TDMC: begin |
| 482 | mux_dmc_meta1_req_cmd = tdmc_arb1_req_cmd; |
| 483 | mux_dmc_meta1_req_address = tdmc_arb1_req_address; |
| 484 | mux_dmc_meta1_req_length = tdmc_arb1_req_length; |
| 485 | mux_dmc_meta1_req_port_num = tdmc_arb1_req_port_num; |
| 486 | mux_dmc_meta1_req_dma_num = tdmc_arb1_req_dma_num; |
| 487 | mux_dmc_meta1_req_func_num = tdmc_arb1_req_func_num; |
| 488 | mux_dmc_meta1_req_client = TDMC_CLIENT; |
| 489 | mux_dmc_meta1_req = tdmc_arb1_req; |
| 490 | |
| 491 | demux_arb1_tdmc_req_accept = meta_dmc1_req_accept; |
| 492 | demux_arb1_tdmc_req_errors = meta_dmc1_req_errors; |
| 493 | end |
| 494 | // RCR: begin |
| 495 | // mux_dmc_meta1_req_cmd = rcr_arb1_req_cmd; |
| 496 | // mux_dmc_meta1_req_address = rcr_arb1_req_address; |
| 497 | // mux_dmc_meta1_req_length = rcr_arb1_req_length; |
| 498 | // mux_dmc_meta1_req_port_num = rcr_arb1_req_port_num; |
| 499 | // mux_dmc_meta1_req_dma_num = rcr_arb1_req_dma_num; |
| 500 | // mux_dmc_meta1_req_client = RCR_CLIENT; |
| 501 | // mux_dmc_meta1_req = rcr_arb1_req; |
| 502 | |
| 503 | // demux_arb1_rcr_req_accept = meta_dmc1_req_accept; |
| 504 | // demux_arb1_rcr_req_errors = meta_dmc1_req_errors; |
| 505 | // end |
| 506 | RBR: begin |
| 507 | mux_dmc_meta1_req_cmd = rbr_arb1_req_cmd; |
| 508 | mux_dmc_meta1_req_address = rbr_arb1_req_address; |
| 509 | mux_dmc_meta1_req_length = rbr_arb1_req_length; |
| 510 | mux_dmc_meta1_req_port_num = rbr_arb1_req_port_num; |
| 511 | mux_dmc_meta1_req_dma_num = rbr_arb1_req_dma_num; |
| 512 | mux_dmc_meta1_req_func_num = rbr_arb1_req_func_num; |
| 513 | mux_dmc_meta1_req_client = RBR_CLIENT; |
| 514 | mux_dmc_meta1_req = rbr_arb1_req; |
| 515 | |
| 516 | demux_arb1_rbr_req_accept = meta_dmc1_req_accept; |
| 517 | demux_arb1_rbr_req_errors = meta_dmc1_req_errors; |
| 518 | end |
| 519 | default: begin |
| 520 | mux_dmc_meta1_req_cmd = ZEROES_8; |
| 521 | mux_dmc_meta1_req_address = ZEROES_64; |
| 522 | mux_dmc_meta1_req_length = ZEROES_14; |
| 523 | mux_dmc_meta1_req_port_num = ZEROES_2; |
| 524 | mux_dmc_meta1_req_dma_num = ZEROES_5; |
| 525 | mux_dmc_meta1_req_func_num = ZEROES_2; |
| 526 | mux_dmc_meta1_req_client = NULL_CLIENT; |
| 527 | mux_dmc_meta1_req = ZERO_1; |
| 528 | |
| 529 | demux_arb1_zcp_req_accept = ZERO_1; |
| 530 | demux_arb1_zcp_req_errors = ZERO_1; |
| 531 | |
| 532 | demux_arb1_txc_req_accept = ZERO_1; |
| 533 | demux_arb1_txc_req_errors = ZERO_1; |
| 534 | |
| 535 | demux_arb1_tdmc_req_accept = ZERO_1; |
| 536 | demux_arb1_tdmc_req_errors = ZERO_1; |
| 537 | |
| 538 | // demux_arb1_rcr_req_accept = ZERO_1; |
| 539 | // demux_arb1_rcr_req_errors = ZERO_1; |
| 540 | |
| 541 | demux_arb1_rbr_req_accept = ZERO_1; |
| 542 | demux_arb1_rbr_req_errors = ZERO_1; |
| 543 | end |
| 544 | endcase |
| 545 | end |
| 546 | |
| 547 | /*-------------------------------------- |
| 548 | -- Concurrent combinatorial logic:Round Robin Arbitration CONTROL State Machine |
| 549 | --------------------------------------*/ |
| 550 | always @ (/*AUTOSENSE*/arb1_fifo_not_empty |
| 551 | or current_arb_control_state_ff or meta_dmc1_req_accept |
| 552 | or rbr_arb1_req or rd_threshold_reached or tdmc_arb1_req |
| 553 | or txc_arb1_req or zcp_arb1_req) |
| 554 | begin: arbitration_control_fsm |
| 555 | arb_control_sel_in = NULL; |
| 556 | arb_control_sel_ld = DEASSERT_L; |
| 557 | read_tag = DEASSERT_L; |
| 558 | next_arb_control_state = CACS0; |
| 559 | case (current_arb_control_state_ff) /* synopsys parallel_case full_case */ |
| 560 | CACS0: begin |
| 561 | if (arb1_fifo_not_empty & ~rd_threshold_reached ) begin |
| 562 | if (zcp_arb1_req == TRUE_H) begin // ZCP Request |
| 563 | arb_control_sel_in = ZCP; // Select ZCP module |
| 564 | next_arb_control_state = CACS5; // next state |
| 565 | end |
| 566 | else if (txc_arb1_req == TRUE_H) begin // TXC Request |
| 567 | arb_control_sel_in = TXC; // Select TXC module |
| 568 | next_arb_control_state = CACS6; // next state |
| 569 | end |
| 570 | else if (tdmc_arb1_req == TRUE_H) begin // TDMC Request |
| 571 | arb_control_sel_in = TDMC; // Select TDMC module |
| 572 | next_arb_control_state = CACS7; // next state |
| 573 | end |
| 574 | // else if (rcr_arb1_req == TRUE_H) begin // RCR Request |
| 575 | // arb_control_sel_in = RCR; // Select RCR module |
| 576 | // next_arb_control_state = CACS8; // next state |
| 577 | // end |
| 578 | else if (rbr_arb1_req == TRUE_H) begin // RBR Request |
| 579 | arb_control_sel_in = RBR; // Select RBR module |
| 580 | next_arb_control_state = CACS9; // next state |
| 581 | end |
| 582 | else begin // No Request |
| 583 | arb_control_sel_in = NULL; // Select NULL module |
| 584 | next_arb_control_state = CACS0; // loop |
| 585 | end // else: !if(rbr_arb1_req == TRUE_H) |
| 586 | end // if (arb1_fifo_not_empty) |
| 587 | else begin // No Request |
| 588 | arb_control_sel_in = NULL; // Select NULL module |
| 589 | next_arb_control_state = CACS0; // loop |
| 590 | end // else: !if(arb1_fifo_not_empty) |
| 591 | arb_control_sel_ld = ASSERT_H; // load register |
| 592 | end |
| 593 | CACS1: begin |
| 594 | if (arb1_fifo_not_empty & ~rd_threshold_reached) begin |
| 595 | if (txc_arb1_req == TRUE_H) begin // TXC Request |
| 596 | arb_control_sel_in = TXC; // Select TXC module |
| 597 | next_arb_control_state = CACS6; // next state |
| 598 | end |
| 599 | else if (tdmc_arb1_req == TRUE_H) begin // TDMC Request |
| 600 | arb_control_sel_in = TDMC; // Select TDMC module |
| 601 | next_arb_control_state = CACS7; // next state |
| 602 | end |
| 603 | // else if (rcr_arb1_req == TRUE_H) begin // RCR Request |
| 604 | // arb_control_sel_in = RCR; // Select RCR module |
| 605 | // next_arb_control_state = CACS8; // next state |
| 606 | // end |
| 607 | else if (rbr_arb1_req == TRUE_H) begin // RBR Request |
| 608 | arb_control_sel_in = RBR; // Select RBR module |
| 609 | next_arb_control_state = CACS9; // next state |
| 610 | end |
| 611 | else if (zcp_arb1_req == TRUE_H) begin // ZCP Request |
| 612 | arb_control_sel_in = ZCP; // Select ZCP module |
| 613 | next_arb_control_state = CACS5; // next state |
| 614 | end |
| 615 | else begin // No Request |
| 616 | arb_control_sel_in = NULL; // Select NULL module |
| 617 | next_arb_control_state = CACS0; // loop |
| 618 | end |
| 619 | end |
| 620 | else begin // No Request |
| 621 | arb_control_sel_in = NULL; // Select NULL module |
| 622 | next_arb_control_state = CACS1; // loop |
| 623 | end |
| 624 | arb_control_sel_ld = ASSERT_H; // load register |
| 625 | end |
| 626 | CACS2: begin |
| 627 | if (arb1_fifo_not_empty & ~rd_threshold_reached) begin |
| 628 | if (tdmc_arb1_req == TRUE_H) begin // TDMC Request |
| 629 | arb_control_sel_in = TDMC; // Select TDMC module |
| 630 | next_arb_control_state = CACS7; // next state |
| 631 | end |
| 632 | // else if (rcr_arb1_req == TRUE_H) begin // RCR Request |
| 633 | // arb_control_sel_in = RCR; // Select RCR module |
| 634 | // next_arb_control_state = CACS8; // next state |
| 635 | // end |
| 636 | else if (rbr_arb1_req == TRUE_H) begin // RBR Request |
| 637 | arb_control_sel_in = RBR; // Select RBR module |
| 638 | next_arb_control_state = CACS9; // next state |
| 639 | end |
| 640 | else if (zcp_arb1_req == TRUE_H) begin // ZCP Request |
| 641 | arb_control_sel_in = ZCP; // Select ZCP module |
| 642 | next_arb_control_state = CACS5; // next state |
| 643 | end |
| 644 | else if (txc_arb1_req == TRUE_H) begin // TXC Request |
| 645 | arb_control_sel_in = TXC; // Select TXC module |
| 646 | next_arb_control_state = CACS6; // next state |
| 647 | end |
| 648 | else begin // No Request |
| 649 | arb_control_sel_in = NULL; // Select NULL module |
| 650 | next_arb_control_state = CACS0; // loop |
| 651 | end // else: !if(txc_arb1_req == TRUE_H) |
| 652 | end |
| 653 | else begin // No Request |
| 654 | arb_control_sel_in = NULL; // Select NULL module |
| 655 | next_arb_control_state = CACS2; // loop |
| 656 | end // else: !if(txc_arb1_req == TRUE_H) |
| 657 | |
| 658 | arb_control_sel_ld = ASSERT_H; // load register |
| 659 | end |
| 660 | CACS3: begin |
| 661 | // if (rcr_arb1_req == TRUE_H) begin // RCR Request |
| 662 | // arb_control_sel_in = RCR; // Select RCR module |
| 663 | // next_arb_control_state = CACS8; // next state |
| 664 | // end |
| 665 | // else if (rbr_arb1_req == TRUE_H) begin // RBR Request |
| 666 | |
| 667 | if (arb1_fifo_not_empty & ~rd_threshold_reached) begin |
| 668 | if (rbr_arb1_req == TRUE_H) begin // RBR Request |
| 669 | arb_control_sel_in = RBR; // Select RBR module |
| 670 | next_arb_control_state = CACS9; // next state |
| 671 | end |
| 672 | else if (zcp_arb1_req == TRUE_H) begin // ZCP Request |
| 673 | arb_control_sel_in = ZCP; // Select ZCP module |
| 674 | next_arb_control_state = CACS5; // next state |
| 675 | end |
| 676 | else if (txc_arb1_req == TRUE_H) begin // TXC Request |
| 677 | arb_control_sel_in = TXC; // Select TXC module |
| 678 | next_arb_control_state = CACS6; // next state |
| 679 | end |
| 680 | else if (tdmc_arb1_req == TRUE_H) begin // TDMC Request |
| 681 | arb_control_sel_in = TDMC; // Select TDMC module |
| 682 | next_arb_control_state = CACS7; // next state |
| 683 | end |
| 684 | else begin // No Request |
| 685 | arb_control_sel_in = NULL; // Select NULL module |
| 686 | next_arb_control_state = CACS3; // loop |
| 687 | end // else: !if(tdmc_arb1_req == TRUE_H) |
| 688 | end // if (arb1_fifo_not_empty) |
| 689 | else begin // No Request |
| 690 | arb_control_sel_in = NULL; // Select NULL module |
| 691 | next_arb_control_state = CACS3; // loop |
| 692 | end |
| 693 | arb_control_sel_ld = ASSERT_H; // load register |
| 694 | end |
| 695 | CACS4: begin |
| 696 | if (arb1_fifo_not_empty & ~rd_threshold_reached ) begin |
| 697 | if (rbr_arb1_req == TRUE_H) begin // RBR Request |
| 698 | arb_control_sel_in = RBR; // Select RBR module |
| 699 | next_arb_control_state = CACS9; // next state |
| 700 | end |
| 701 | else if (zcp_arb1_req == TRUE_H) begin // ZCP Request |
| 702 | arb_control_sel_in = ZCP; // Select ZCP module |
| 703 | next_arb_control_state = CACS5; // next state |
| 704 | end |
| 705 | else if (txc_arb1_req == TRUE_H) begin // TXC Request |
| 706 | arb_control_sel_in = TXC; // Select TXC module |
| 707 | next_arb_control_state = CACS6; // next state |
| 708 | end |
| 709 | else if (tdmc_arb1_req == TRUE_H) begin // TDMC Request |
| 710 | arb_control_sel_in = TDMC; // Select TDMC module |
| 711 | next_arb_control_state = CACS7; // next state |
| 712 | end |
| 713 | // else if (rcr_arb1_req == TRUE_H) begin // RCR Request |
| 714 | // arb_control_sel_in = RCR; // Select RCR module |
| 715 | // next_arb_control_state = CACS8; // next state |
| 716 | // end |
| 717 | else begin // No Request |
| 718 | arb_control_sel_in = NULL; // Select NULL module |
| 719 | next_arb_control_state = CACS0; // loop |
| 720 | end // else: !if(tdmc_arb1_req == TRUE_H) |
| 721 | end // if (arb1_fifo_not_empty) |
| 722 | else begin // No Request |
| 723 | arb_control_sel_in = NULL; // Select NULL module |
| 724 | next_arb_control_state = CACS4; // loop |
| 725 | end |
| 726 | arb_control_sel_ld = ASSERT_H; // load register |
| 727 | end |
| 728 | CACS5: begin |
| 729 | if (meta_dmc1_req_accept == TRUE_H) begin // Control Complete |
| 730 | read_tag = ASSERT_H; |
| 731 | next_arb_control_state = CACS1; // next state |
| 732 | end |
| 733 | else begin |
| 734 | next_arb_control_state = CACS5; // loop |
| 735 | end |
| 736 | end |
| 737 | CACS6: begin |
| 738 | if (meta_dmc1_req_accept == TRUE_H) begin // Control Complete |
| 739 | read_tag = ASSERT_H; // Select a new TransID |
| 740 | next_arb_control_state = CACS2; // next state |
| 741 | end |
| 742 | else begin |
| 743 | next_arb_control_state = CACS6; // loop |
| 744 | end |
| 745 | end |
| 746 | CACS7: begin |
| 747 | if (meta_dmc1_req_accept == TRUE_H) begin // Control Complete |
| 748 | read_tag = ASSERT_H; // Select a new TransID |
| 749 | next_arb_control_state = CACS3; // next state |
| 750 | end |
| 751 | else begin |
| 752 | next_arb_control_state = CACS7; // loop |
| 753 | end |
| 754 | end |
| 755 | CACS8: begin |
| 756 | if (meta_dmc1_req_accept == TRUE_H) begin // Control Complete |
| 757 | read_tag = ASSERT_H; // Select a new TransID |
| 758 | next_arb_control_state = CACS0; // next state |
| 759 | end |
| 760 | else begin |
| 761 | next_arb_control_state = CACS8; // loop |
| 762 | end |
| 763 | end |
| 764 | CACS9: begin |
| 765 | if (meta_dmc1_req_accept == TRUE_H) begin // Control Complete |
| 766 | read_tag = ASSERT_H; // Select a new TransID |
| 767 | next_arb_control_state = CACS0; // next state |
| 768 | end |
| 769 | else begin |
| 770 | next_arb_control_state = CACS9; // loop |
| 771 | end |
| 772 | end |
| 773 | default: begin |
| 774 | next_arb_control_state = CACS0; // next state |
| 775 | end |
| 776 | endcase |
| 777 | end |
| 778 | |
| 779 | |
| 780 | |
| 781 | /*--------------------------------------------------------------------------- |
| 782 | ----Dirty TID handing state machine |
| 783 | ---------------------------------------------------------------------------*/ |
| 784 | |
| 785 | |
| 786 | // synopsys translate_off |
| 787 | |
| 788 | reg [55:0] DIR_BIN_STATE; |
| 789 | always @(dirbin_stateR) |
| 790 | begin |
| 791 | case(dirbin_stateR) |
| 792 | IDLEBIN : DIR_BIN_STATE = "IDLEBIN"; |
| 793 | CLRBIN : DIR_BIN_STATE = "CLRBIN"; |
| 794 | RDBIN : DIR_BIN_STATE = "RDBIN"; |
| 795 | default : DIR_BIN_STATE = "UNKNOWN"; |
| 796 | endcase |
| 797 | end |
| 798 | |
| 799 | // synopsys translate_on |
| 800 | |
| 801 | always @ (/*AUTOSENSE*/dirbin_stateR or dirtybinfifo_not_empty |
| 802 | or pio_arb_dirtid_clr or transfer_cmpl_pending) |
| 803 | begin |
| 804 | // set all default values here |
| 805 | return_dirty_tag = 1'b0; |
| 806 | inc_dirtybinfifo_rp = 1'b0; |
| 807 | dirbin_state = dirbin_stateR; |
| 808 | case(dirbin_stateR) |
| 809 | IDLEBIN: |
| 810 | begin |
| 811 | if (pio_arb_dirtid_clr ) begin |
| 812 | dirbin_state = CLRBIN; |
| 813 | end |
| 814 | else |
| 815 | dirbin_state = IDLEBIN; |
| 816 | end // case: IDLEBIN |
| 817 | CLRBIN: |
| 818 | begin |
| 819 | if (dirtybinfifo_not_empty) begin |
| 820 | if (transfer_cmpl_pending) |
| 821 | dirbin_state = CLRBIN; |
| 822 | else begin |
| 823 | return_dirty_tag = 1'b1; |
| 824 | inc_dirtybinfifo_rp = 1'b1; |
| 825 | end |
| 826 | end // if (dirtybinfifo_not_empty) |
| 827 | else |
| 828 | dirbin_state = IDLEBIN; |
| 829 | end // case: CLRBIN |
| 830 | RDBIN: |
| 831 | begin |
| 832 | inc_dirtybinfifo_rp = 1'b1; |
| 833 | dirbin_state = CLRBIN; |
| 834 | end |
| 835 | default: dirbin_state = IDLEBIN; |
| 836 | endcase |
| 837 | end |
| 838 | |
| 839 | |
| 840 | |
| 841 | |
| 842 | |
| 843 | |
| 844 | |
| 845 | /*----------------------------------------------------------------------------- |
| 846 | -- TransID Management |
| 847 | -----------------------------------------------------------------------------*/ |
| 848 | |
| 849 | niu_meta_rd_tagfifo niu_meta_rd_tagfifo ( |
| 850 | // Outputs |
| 851 | .fifo_not_empty(arb1_fifo_not_empty), |
| 852 | .fifo_full (), |
| 853 | .rdout (rdtagoutR), |
| 854 | .dout (), |
| 855 | .count (), |
| 856 | // Inputs |
| 857 | .core_clk (clk), |
| 858 | .reset (reset), |
| 859 | .inc_rp (read_tag), |
| 860 | .inc_wp (write_tag | return_dirty_tag), |
| 861 | .din (reclaimed_transID)); |
| 862 | |
| 863 | |
| 864 | /*------------------------------------------------------------------------ |
| 865 | ---Dirty Bin Fifo ----------------------------- |
| 866 | -------------------------------------------------------------------------*/ |
| 867 | niu_meta_arb_syncfifo #(5,32,5) rddirtybinfifo ( |
| 868 | .core_clk (clk), |
| 869 | .reset (reset), |
| 870 | .inc_rp (inc_dirtybinfifo_rp), |
| 871 | .inc_wp (write_dirty_tag), |
| 872 | .fifo_not_empty (dirtybinfifo_not_empty), |
| 873 | .fifo_full (dirtybinfifo_full), |
| 874 | .count (dirty_tag_count), |
| 875 | .din (meta_dmc_resp_transIDR), |
| 876 | .rdout (), |
| 877 | .dout (dirty_tag)); |
| 878 | |
| 879 | |
| 880 | |
| 881 | |
| 882 | //------------------------------------------------------------------ |
| 883 | |
| 884 | assign dmc_meta_resp_accept_ORd = dmc_meta_resp_accept[7] | |
| 885 | dmc_meta_resp_accept[6] | |
| 886 | dmc_meta_resp_accept[5] | |
| 887 | dmc_meta_resp_accept[4] | |
| 888 | dmc_meta_resp_accept[3] | |
| 889 | dmc_meta_resp_accept[2] | |
| 890 | dmc_meta_resp_accept[1] | |
| 891 | dmc_meta_resp_accept[0]; |
| 892 | |
| 893 | assign meta_dmc_resp_transfer_cmpl_ORd = meta_dmc_resp_transfer_cmpl[7] | |
| 894 | meta_dmc_resp_transfer_cmpl[6] | |
| 895 | meta_dmc_resp_transfer_cmpl[5] | |
| 896 | meta_dmc_resp_transfer_cmpl[4] | |
| 897 | meta_dmc_resp_transfer_cmpl[3] | |
| 898 | meta_dmc_resp_transfer_cmpl[2] | |
| 899 | meta_dmc_resp_transfer_cmpl[1] | |
| 900 | meta_dmc_resp_transfer_cmpl[0]; |
| 901 | |
| 902 | assign transaction_timeout = (meta_dmc_resp_cmd_statusR == 4'b1111); |
| 903 | |
| 904 | |
| 905 | |
| 906 | always @ (/*AUTOSENSE*/meta_dmc_resp_transID0R |
| 907 | or meta_dmc_resp_transID1R or meta_dmc_resp_transID2R |
| 908 | or meta_dmc_resp_transID3R or meta_dmc_resp_transID4R |
| 909 | or meta_dmc_resp_transID5R or meta_dmc_resp_transID6R |
| 910 | or meta_dmc_resp_transID7R or meta_dmc_resp_transfer_cmpl) begin |
| 911 | if ( meta_dmc_resp_transfer_cmpl[0]) |
| 912 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID0R; |
| 913 | else if (meta_dmc_resp_transfer_cmpl[1]) |
| 914 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID1R; |
| 915 | else if (meta_dmc_resp_transfer_cmpl[2]) |
| 916 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID2R; |
| 917 | else if (meta_dmc_resp_transfer_cmpl[3]) |
| 918 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID3R; |
| 919 | else if (meta_dmc_resp_transfer_cmpl[4]) |
| 920 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID4R; |
| 921 | else if (meta_dmc_resp_transfer_cmpl[5]) |
| 922 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID5R; |
| 923 | else if (meta_dmc_resp_transfer_cmpl[6]) |
| 924 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID6R; |
| 925 | else if (meta_dmc_resp_transfer_cmpl[7]) |
| 926 | meta_dmc_resp_transID_cmpl = meta_dmc_resp_transID7R; |
| 927 | else |
| 928 | meta_dmc_resp_transID_cmpl = 5'b00000; |
| 929 | end |
| 930 | |
| 931 | always @ (/*AUTOSENSE*/dirty_tag or meta_dmc_resp_transIDR |
| 932 | or return_dirty_tag) begin |
| 933 | if (return_dirty_tag) |
| 934 | reclaimed_transID = dirty_tag; |
| 935 | else |
| 936 | reclaimed_transID = meta_dmc_resp_transIDR; |
| 937 | end |
| 938 | |
| 939 | |
| 940 | /*-------------------------------------- |
| 941 | -- Concurrent processes: State Machine Registers |
| 942 | --------------------------------------*/ |
| 943 | |
| 944 | always @ (posedge clk) begin |
| 945 | if (reset == 1'b1) |
| 946 | current_arb_control_state_ff <= 4'h0; // synchronous reset |
| 947 | else |
| 948 | current_arb_control_state_ff <= next_arb_control_state; |
| 949 | end |
| 950 | |
| 951 | |
| 952 | |
| 953 | |
| 954 | /*-------------------------------------- |
| 955 | -- Concurrent processes: Registers |
| 956 | --------------------------------------*/ |
| 957 | |
| 958 | always @ (posedge clk) begin: arb_control_sel_reg |
| 959 | if (reset == 1'b1) |
| 960 | arb_control_sel_ff <= 3'b000; // synchronous reset |
| 961 | else if (arb_control_sel_ld == TRUE_H) |
| 962 | arb_control_sel_ff <= arb_control_sel_in; |
| 963 | end |
| 964 | |
| 965 | |
| 966 | always @ (posedge clk) begin |
| 967 | if (reset == 1'b1) begin |
| 968 | write_tag <= 1'b0; |
| 969 | write_dirty_tag <= 1'b0; |
| 970 | meta_dmc_resp_transIDR <= 5'h0; |
| 971 | meta_dmc_resp_transID0R <= 5'h0; |
| 972 | meta_dmc_resp_transID1R <= 5'h0; |
| 973 | meta_dmc_resp_transID2R <= 5'h0; |
| 974 | meta_dmc_resp_transID3R <= 5'h0; |
| 975 | meta_dmc_resp_transID4R <= 5'h0; |
| 976 | meta_dmc_resp_transID5R <= 5'h0; |
| 977 | meta_dmc_resp_transID6R <= 5'h0; |
| 978 | meta_dmc_resp_transID7R <= 5'h0; |
| 979 | meta_dmc_resp_cmd_statusR <= 4'h0; |
| 980 | transfer_cmpl_pending <= 1'b0; |
| 981 | dirbin_stateR <= 2'b00; |
| 982 | arb_pio_dirtid_rdstatus <= 0; |
| 983 | outstanding_tid_cnt <= 0; |
| 984 | end |
| 985 | else begin |
| 986 | // if dirty tid enable only put non timed out tids in good bin |
| 987 | write_tag <= meta_dmc_resp_transfer_cmpl_ORd & ( pio_arb_dirtid_enable ? !transaction_timeout : 1'b1 ); |
| 988 | write_dirty_tag <= meta_dmc_resp_transfer_cmpl_ORd & transaction_timeout & pio_arb_dirtid_enable ; |
| 989 | meta_dmc_resp_transIDR <= meta_dmc_resp_transID_cmpl; |
| 990 | meta_dmc_resp_transID0R <= dmc_meta_resp_accept[0] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID0R; |
| 991 | meta_dmc_resp_transID1R <= dmc_meta_resp_accept[1] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID1R; |
| 992 | meta_dmc_resp_transID2R <= dmc_meta_resp_accept[2] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID2R; |
| 993 | meta_dmc_resp_transID3R <= dmc_meta_resp_accept[3] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID3R; |
| 994 | meta_dmc_resp_transID4R <= dmc_meta_resp_accept[4] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID4R; |
| 995 | meta_dmc_resp_transID5R <= dmc_meta_resp_accept[5] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID5R; |
| 996 | meta_dmc_resp_transID6R <= dmc_meta_resp_accept[6] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID6R; |
| 997 | meta_dmc_resp_transID7R <= dmc_meta_resp_accept[7] ? meta_dmc_resp_transID[4:0] : meta_dmc_resp_transID7R; |
| 998 | meta_dmc_resp_cmd_statusR <= dmc_meta_resp_accept_ORd ? meta_dmc_resp_cmd_status : meta_dmc_resp_cmd_statusR ; |
| 999 | transfer_cmpl_pending <= dmc_meta_resp_accept_ORd ? 1'b1 : meta_dmc_resp_transfer_cmpl_ORd ? 1'b0 : transfer_cmpl_pending; |
| 1000 | dirbin_stateR <= dirbin_state; |
| 1001 | arb_pio_dirtid_rdstatus <= dirty_tag_count; |
| 1002 | |
| 1003 | if(inc_outstanding_tid_cnt) outstanding_tid_cnt<= outstanding_tid_cnt_add_n; |
| 1004 | else if(dec_outstanding_tid_cnt) outstanding_tid_cnt<= outstanding_tid_cnt_sub_n; |
| 1005 | end // else: !if(reset == 1'b1) |
| 1006 | end |
| 1007 | |
| 1008 | |
| 1009 | |
| 1010 | // assign threshold reached |
| 1011 | |
| 1012 | assign rd_threshold_reached = (outstanding_tid_cnt >= pio_arb_rd_threshold); |
| 1013 | // assign outputs |
| 1014 | |
| 1015 | assign arb_pio_all_rddirty = dirtybinfifo_full; |
| 1016 | |
| 1017 | |
| 1018 | endmodule |
| 1019 | |