| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_rdmc_wr_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module niu_rdmc_wr_dp ( |
| 36 | clk, |
| 37 | reset, |
| 38 | muxed_port_rdc_num, |
| 39 | port_err_status, |
| 40 | full_hdr_r, |
| 41 | pkt_trans_len_r, |
| 42 | pref_buf_used_num_r, |
| 43 | drop_pkt_en_sm, |
| 44 | drop_pkt_en, |
| 45 | drop_pkt_port_gnt, |
| 46 | drop_pad_data, |
| 47 | is_zcp0_wr_req, |
| 48 | is_zcp1_wr_req, |
| 49 | is_zcp2_wr_req, |
| 50 | is_zcp3_wr_req, |
| 51 | rdmc_wr_req_accept_hdr, |
| 52 | rdmc_wr_req_accept_jmb, |
| 53 | rdmc_wr_req_accept_zcp0, |
| 54 | rdmc_wr_req_accept_zcp1, |
| 55 | rdmc_wr_req_accept_zcp2, |
| 56 | rdmc_wr_req_accept_zcp3, |
| 57 | port_gnt, |
| 58 | port_gnt_r, |
| 59 | stage0_en, |
| 60 | rdmc_meta0_wr_req_dma_num_int, |
| 61 | |
| 62 | ipp_dmc_ful_pkt0, |
| 63 | ipp_dmc_dat_ack0, |
| 64 | ipp_dmc_dat_err0, |
| 65 | ipp_dmc_data0, |
| 66 | ipp_dmc_ful_pkt1, |
| 67 | ipp_dmc_dat_ack1, |
| 68 | ipp_dmc_dat_err1, |
| 69 | ipp_dmc_data1, |
| 70 | ipp_dmc_ful_pkt2, |
| 71 | ipp_dmc_dat_ack2, |
| 72 | ipp_dmc_dat_err2, |
| 73 | ipp_dmc_data2, |
| 74 | ipp_dmc_ful_pkt3, |
| 75 | ipp_dmc_dat_ack3, |
| 76 | ipp_dmc_dat_err3, |
| 77 | ipp_dmc_data3, |
| 78 | |
| 79 | zcp_dmc_ful_pkt0, |
| 80 | zcp_dmc_ack0, |
| 81 | zcp_dmc_dat0, |
| 82 | zcp_dmc_dat_err0, |
| 83 | zcp_dmc_ful_pkt1, |
| 84 | zcp_dmc_ack1, |
| 85 | zcp_dmc_dat1, |
| 86 | zcp_dmc_dat_err1, |
| 87 | zcp_dmc_ful_pkt2, |
| 88 | zcp_dmc_ack2, |
| 89 | zcp_dmc_dat2, |
| 90 | zcp_dmc_dat_err2, |
| 91 | zcp_dmc_ful_pkt3, |
| 92 | zcp_dmc_ack3, |
| 93 | zcp_dmc_dat3, |
| 94 | zcp_dmc_dat_err3, |
| 95 | meta0_rdmc_wr_data_req, |
| 96 | |
| 97 | muxed_rdc_num_r, |
| 98 | muxed_drop_pkt_r, |
| 99 | muxed_s_event_r, |
| 100 | muxed_pkt_len, |
| 101 | muxed_pkt_len_r, |
| 102 | muxed_l2_len_r, |
| 103 | rdmc_eop_for_padding, |
| 104 | pkt_req_cnt_pre_done, |
| 105 | pkt_req_cnt_done, |
| 106 | pkt_req_cnt_done_r, |
| 107 | pkt_req_cnt_e_done_mod, |
| 108 | pkt_wrbk_data, |
| 109 | drop_pkt_done, |
| 110 | rdmc_wr_data_dma_num, |
| 111 | ipp_full_pkt, |
| 112 | zcp_full_pkt, |
| 113 | ipp_pkt_sop, |
| 114 | zcp_pkt_sop, |
| 115 | muxed_zcopy_mode_r, |
| 116 | muxed_data_err_r2, |
| 117 | zcopy_mode, |
| 118 | jmb_pkt_type, |
| 119 | zcp_wr_type, |
| 120 | zcp_rdc_num, |
| 121 | |
| 122 | zcp_vaddr0, |
| 123 | zcp_vaddr1, |
| 124 | zcp_vaddr2, |
| 125 | zcp_vaddr3, |
| 126 | zcp_len0, |
| 127 | zcp_len1, |
| 128 | zcp_len2, |
| 129 | zcp_len3, |
| 130 | zcp_func_num, |
| 131 | |
| 132 | dmc_ipp_dat_req0, |
| 133 | dmc_ipp_dat_req1, |
| 134 | dmc_ipp_dat_req2, |
| 135 | dmc_ipp_dat_req3, |
| 136 | |
| 137 | dmc_zcp_req0, |
| 138 | dmc_zcp_req1, |
| 139 | dmc_zcp_req2, |
| 140 | dmc_zcp_req3, |
| 141 | |
| 142 | rdmc_meta0_wr_data_valid, |
| 143 | rdmc_meta0_wr_data, |
| 144 | rdmc_meta0_wr_req_byteenable, |
| 145 | rdmc_meta0_wr_transfer_comp, |
| 146 | rdmc_meta0_wr_transfer_comp_int, |
| 147 | rdmc_meta0_wr_status, |
| 148 | |
| 149 | port_err_event, |
| 150 | ipp_dat_req0_data, |
| 151 | ipp_dat_req1_data, |
| 152 | ipp_dat_req2_data, |
| 153 | ipp_dat_req3_data, |
| 154 | wr_dp_sm_state |
| 155 | |
| 156 | ); |
| 157 | |
| 158 | |
| 159 | input clk; |
| 160 | input reset; |
| 161 | input[3:0] port_err_status; |
| 162 | input[4:0] muxed_port_rdc_num; |
| 163 | input full_hdr_r; |
| 164 | input[13:0] pkt_trans_len_r; |
| 165 | input[1:0] pref_buf_used_num_r; |
| 166 | input drop_pkt_en_sm; |
| 167 | input drop_pkt_en; |
| 168 | input[3:0] drop_pkt_port_gnt; |
| 169 | input drop_pad_data; |
| 170 | input is_zcp0_wr_req; |
| 171 | input is_zcp1_wr_req; |
| 172 | input is_zcp2_wr_req; |
| 173 | input is_zcp3_wr_req; |
| 174 | input rdmc_wr_req_accept_hdr; |
| 175 | input rdmc_wr_req_accept_jmb; |
| 176 | input rdmc_wr_req_accept_zcp0; |
| 177 | input rdmc_wr_req_accept_zcp1; |
| 178 | input rdmc_wr_req_accept_zcp2; |
| 179 | input rdmc_wr_req_accept_zcp3; |
| 180 | input[3:0] port_gnt; |
| 181 | input[3:0] port_gnt_r; |
| 182 | input stage0_en; |
| 183 | input[4:0] rdmc_meta0_wr_req_dma_num_int; |
| 184 | input ipp_dmc_ful_pkt0; |
| 185 | input ipp_dmc_dat_ack0; |
| 186 | input ipp_dmc_dat_err0; |
| 187 | input[129:0] ipp_dmc_data0; |
| 188 | input ipp_dmc_ful_pkt1; |
| 189 | input ipp_dmc_dat_ack1; |
| 190 | input ipp_dmc_dat_err1; |
| 191 | input[129:0] ipp_dmc_data1; |
| 192 | input ipp_dmc_ful_pkt2; |
| 193 | input ipp_dmc_dat_ack2; |
| 194 | input ipp_dmc_dat_err2; |
| 195 | input[129:0] ipp_dmc_data2; |
| 196 | input ipp_dmc_ful_pkt3; |
| 197 | input ipp_dmc_dat_ack3; |
| 198 | input ipp_dmc_dat_err3; |
| 199 | input[129:0] ipp_dmc_data3; |
| 200 | |
| 201 | input zcp_dmc_ful_pkt0; |
| 202 | input zcp_dmc_ack0; |
| 203 | input[129:0] zcp_dmc_dat0; |
| 204 | input zcp_dmc_dat_err0; |
| 205 | input zcp_dmc_ful_pkt1; |
| 206 | input zcp_dmc_ack1; |
| 207 | input[129:0] zcp_dmc_dat1; |
| 208 | input zcp_dmc_dat_err1; |
| 209 | input zcp_dmc_ful_pkt2; |
| 210 | input zcp_dmc_ack2; |
| 211 | input[129:0] zcp_dmc_dat2; |
| 212 | input zcp_dmc_dat_err2; |
| 213 | input zcp_dmc_ful_pkt3; |
| 214 | input zcp_dmc_ack3; |
| 215 | input[129:0] zcp_dmc_dat3; |
| 216 | input zcp_dmc_dat_err3; |
| 217 | input meta0_rdmc_wr_data_req; |
| 218 | |
| 219 | output[4:0] muxed_rdc_num_r; |
| 220 | output muxed_drop_pkt_r; |
| 221 | output muxed_s_event_r; |
| 222 | output[13:0] muxed_pkt_len; |
| 223 | output[13:0] muxed_pkt_len_r; |
| 224 | output[13:0] muxed_l2_len_r; |
| 225 | output rdmc_eop_for_padding; |
| 226 | output pkt_req_cnt_pre_done; |
| 227 | output pkt_req_cnt_done; |
| 228 | output pkt_req_cnt_done_r; |
| 229 | output pkt_req_cnt_e_done_mod; |
| 230 | output[22:0] pkt_wrbk_data; |
| 231 | output drop_pkt_done; |
| 232 | output[4:0] rdmc_wr_data_dma_num; |
| 233 | output[3:0] ipp_full_pkt; |
| 234 | output[3:0] zcp_full_pkt; |
| 235 | output[3:0] ipp_pkt_sop; |
| 236 | output[3:0] zcp_pkt_sop; |
| 237 | output muxed_zcopy_mode_r; |
| 238 | output muxed_data_err_r2; |
| 239 | output zcopy_mode; |
| 240 | output[1:0] jmb_pkt_type; |
| 241 | output[1:0] zcp_wr_type; |
| 242 | output[4:0] zcp_rdc_num; |
| 243 | output[63:0] zcp_vaddr0; |
| 244 | output[63:0] zcp_vaddr1; |
| 245 | output[63:0] zcp_vaddr2; |
| 246 | output[63:0] zcp_vaddr3; |
| 247 | output[13:0] zcp_len0; |
| 248 | output[13:0] zcp_len1; |
| 249 | output[13:0] zcp_len2; |
| 250 | output[13:0] zcp_len3; |
| 251 | output[1:0] zcp_func_num; |
| 252 | output dmc_ipp_dat_req0; |
| 253 | output dmc_ipp_dat_req1; |
| 254 | output dmc_ipp_dat_req2; |
| 255 | output dmc_ipp_dat_req3; |
| 256 | output dmc_zcp_req0; |
| 257 | output dmc_zcp_req1; |
| 258 | output dmc_zcp_req2; |
| 259 | output dmc_zcp_req3; |
| 260 | output rdmc_meta0_wr_data_valid; |
| 261 | output[127:0] rdmc_meta0_wr_data; |
| 262 | output[15:0] rdmc_meta0_wr_req_byteenable; |
| 263 | output rdmc_meta0_wr_transfer_comp; |
| 264 | output rdmc_meta0_wr_transfer_comp_int; |
| 265 | output[3:0] rdmc_meta0_wr_status; |
| 266 | output[8:0] port_err_event; |
| 267 | output ipp_dat_req0_data; |
| 268 | output ipp_dat_req1_data; |
| 269 | output ipp_dat_req2_data; |
| 270 | output ipp_dat_req3_data; |
| 271 | output[4:0] wr_dp_sm_state; |
| 272 | |
| 273 | reg ipp_full_pkt0; |
| 274 | reg ipp_data_ack0; |
| 275 | reg ipp_data_err0; |
| 276 | reg[129:0] ipp_data0; |
| 277 | reg ipp_full_pkt1; |
| 278 | reg ipp_data_ack1; |
| 279 | reg ipp_data_err1; |
| 280 | reg[129:0] ipp_data1; |
| 281 | reg ipp_full_pkt2; |
| 282 | reg ipp_data_ack2; |
| 283 | reg ipp_data_err2; |
| 284 | reg[129:0] ipp_data2; |
| 285 | reg ipp_full_pkt3; |
| 286 | reg ipp_data_ack3; |
| 287 | reg ipp_data_err3; |
| 288 | reg[129:0] ipp_data3; |
| 289 | reg zcp_full_pkt0; |
| 290 | reg zcp_data_ack0; |
| 291 | reg zcp_data_err0; |
| 292 | reg[129:0] zcp_data0; |
| 293 | reg zcp_full_pkt1; |
| 294 | reg zcp_data_ack1; |
| 295 | reg zcp_data_err1; |
| 296 | reg[129:0] zcp_data1; |
| 297 | reg zcp_full_pkt2; |
| 298 | reg zcp_data_ack2; |
| 299 | reg zcp_data_err2; |
| 300 | reg[129:0] zcp_data2; |
| 301 | reg zcp_full_pkt3; |
| 302 | reg zcp_data_ack3; |
| 303 | reg zcp_data_err3; |
| 304 | reg[129:0] zcp_data3; |
| 305 | |
| 306 | reg muxed_cksum_err_r; |
| 307 | reg muxed_bad_crc_r; |
| 308 | reg[3:0] muxed_ipp_pkt_id_r; |
| 309 | reg[13:0] muxed_l2_len_r; |
| 310 | reg[13:0] muxed_pkt_len_r; |
| 311 | reg[1:0] muxed_pkt_type_r; |
| 312 | reg muxed_drop_pkt_r; |
| 313 | reg muxed_s_event_r; |
| 314 | reg muxed_zcopy_mode_r; |
| 315 | reg muxed_orig_zcopy_mode_r; |
| 316 | reg muxed_fflp_hw_err_r; |
| 317 | reg muxed_mac_promis_r; |
| 318 | reg[4:0] muxed_rdc_num_r; |
| 319 | reg muxed_noport_r; |
| 320 | reg muxed_zcp_err_r; |
| 321 | reg muxed_orig_zcopy_mode_r1; |
| 322 | |
| 323 | reg rdmc_wr_data_req; |
| 324 | reg rdmc_wr_data_req_dly; |
| 325 | reg[4:0] rdmc_wr_data_dma_num; |
| 326 | reg[3:0] port_gnt_r1; |
| 327 | reg[3:0] port_gnt_r2; |
| 328 | reg is_first_accept; |
| 329 | reg ipp_data_req_p_r; |
| 330 | reg ipp_data_req_p_r1; |
| 331 | reg ipp_data_req_p_r2; |
| 332 | reg zcopy_mode; |
| 333 | reg[1:0] jmb_pkt_type; |
| 334 | reg[1:0] zcp_wr_type; |
| 335 | reg full_hdr_r1; |
| 336 | |
| 337 | reg[2:0] zcp_req_cnt; |
| 338 | reg dmc_zcp_req0; |
| 339 | reg dmc_zcp_req1; |
| 340 | reg dmc_zcp_req2; |
| 341 | reg dmc_zcp_req3; |
| 342 | reg[1:0] zcp_ack_cnt; |
| 343 | reg[127:0] zcp_data_reg0; |
| 344 | reg[31:0] zcp_data_reg1; |
| 345 | |
| 346 | `ifdef NEPTUNE |
| 347 | reg[127:0] zcp_data_reg2; |
| 348 | reg[127:0] zcp_data_reg3; |
| 349 | reg[21:0] zcp_data_reg1_lo; //for zcp page handle |
| 350 | `else |
| 351 | wire[127:0] zcp_data_reg2; |
| 352 | wire[127:0] zcp_data_reg3; |
| 353 | wire[21:0] zcp_data_reg1_lo; |
| 354 | `endif |
| 355 | |
| 356 | reg[9:0] drop_pkt_word_cnt; |
| 357 | reg[3:0] drop_pkt_en_dly; |
| 358 | reg[10:0] ipp_pkt_len_word_cnt; |
| 359 | reg dmc_ipp_dat_req0; |
| 360 | reg dmc_ipp_dat_req1; |
| 361 | reg dmc_ipp_dat_req2; |
| 362 | reg dmc_ipp_dat_req3; |
| 363 | reg ipp_data_req0_dly; |
| 364 | reg ipp_data_req1_dly; |
| 365 | reg ipp_data_req2_dly; |
| 366 | reg ipp_data_req3_dly; |
| 367 | reg ipp_data_req_dly1; |
| 368 | reg ipp_data_req_dly2; |
| 369 | reg stage0_en_r; |
| 370 | reg drop_pad_data_r; |
| 371 | reg ipp_fzcp_eop_tmp; |
| 372 | reg ipp_fzcp_eop_tmp1; |
| 373 | reg ipp_fzcp_eop_tmp2; |
| 374 | reg ipp_fzcp_eop; |
| 375 | |
| 376 | reg ipp_dat_req0_data; |
| 377 | reg ipp_dat_req1_data; |
| 378 | reg ipp_dat_req2_data; |
| 379 | reg ipp_dat_req3_data; |
| 380 | |
| 381 | reg[13:0] new_zcp_data_len_r; |
| 382 | reg[9:0] pkt_len_word_cnt; |
| 383 | reg[9:0] data_req_cnt; |
| 384 | reg pkt_req_cnt_pre_done; |
| 385 | reg pkt_req_cnt_done; |
| 386 | reg pkt_req_cnt_done_r; |
| 387 | reg pkt_req_cnt_done_r1; |
| 388 | reg pkt_req_cnt_done_r2; |
| 389 | reg pkt_req_cnt_e_done_r; |
| 390 | reg[3:0] wr_len_last_bits; |
| 391 | reg[3:0] wr_len_last_bits_r; |
| 392 | reg[15:0] wr_data_byte_dec; |
| 393 | |
| 394 | reg[3:0] next_data_offset_reg; |
| 395 | reg[3:0] data_offset_reg; |
| 396 | reg[127:0] save_reg_trans; |
| 397 | reg[127:0] date_save_reg_trans; |
| 398 | reg[127:0] data_save_reg_tmp; |
| 399 | reg[127:0] data_save_reg; |
| 400 | reg[127:0] rdmc_wr_data_tmp; |
| 401 | |
| 402 | reg muxed_data_err; |
| 403 | reg muxed_data_err_r1; |
| 404 | reg muxed_data_err_r2; |
| 405 | reg[9:0] rdmc_eop_cnt; |
| 406 | reg rdmc_cal_eop; |
| 407 | reg rdmc_cal_eop_r; |
| 408 | reg rdmc_cal_eop_tmp; |
| 409 | reg rdmc_cal_eop_tmp1; |
| 410 | reg zcp_second_data_ack_dly; |
| 411 | |
| 412 | reg zcp_sop_reg0; |
| 413 | reg zcp_sop_reg1; |
| 414 | reg zcp_sop_reg2; |
| 415 | reg zcp_sop_reg3; |
| 416 | reg ipp_sop_reg0; |
| 417 | reg ipp_sop_reg1; |
| 418 | reg ipp_sop_reg2; |
| 419 | reg ipp_sop_reg3; |
| 420 | |
| 421 | reg[127:0] rdmc_meta0_wr_data; |
| 422 | reg rdmc_meta0_wr_data_valid; |
| 423 | reg rdmc_meta0_wr_transfer_comp; |
| 424 | reg rdmc_meta0_wr_transfer_comp_int; |
| 425 | reg[15:0] rdmc_meta0_wr_req_byteenable; |
| 426 | reg rdmc_wr_last_comp; |
| 427 | reg wait_drop_pkt_eop; |
| 428 | |
| 429 | reg rdmc_wr_req_accept_hdr_r; |
| 430 | reg rdmc_wr_req_accept_hdr_r1; |
| 431 | reg[127:0] zcp_data_reg0_r; |
| 432 | reg[15:0] zcp_data_reg1_r; |
| 433 | |
| 434 | wire offset_reg_en; |
| 435 | wire[1:0] offset_sel; |
| 436 | wire wr_idle_state; |
| 437 | wire[1:0] rdmc_wr_data_sel; |
| 438 | wire rdmc_wr_data_valid_sm; |
| 439 | wire rdmc_wr_data_comp_sm; |
| 440 | wire rdmc_wr_last_comp_sm; |
| 441 | wire jmb_wr_cycle_sm; |
| 442 | |
| 443 | wire pkt_req_cnt_e_done_mod; |
| 444 | |
| 445 | wire muxed_ipp_data_ack; |
| 446 | wire[27:0] ipp_ctrl_word0; |
| 447 | wire[27:0] ipp_ctrl_word1; |
| 448 | wire[27:0] ipp_ctrl_word2; |
| 449 | wire[27:0] ipp_ctrl_word3; |
| 450 | wire[27:0] muxed_ipp_ctrl_w; |
| 451 | wire[24:0] zcp_ctrl_word0; |
| 452 | wire[24:0] zcp_ctrl_word1; |
| 453 | wire[24:0] zcp_ctrl_word2; |
| 454 | wire[24:0] zcp_ctrl_word3; |
| 455 | wire[24:0] muxed_zcp_ctrl_w; |
| 456 | |
| 457 | wire muxed_cksum_err; |
| 458 | wire muxed_bad_crc; |
| 459 | wire[13:0] muxed_l2_len; |
| 460 | wire[13:0] muxed_pkt_len; |
| 461 | wire[1:0] muxed_pkt_type; |
| 462 | wire[3:0] muxed_ipp_pkt_id; |
| 463 | wire[5:0] muxed_ipp_drop_bits; |
| 464 | wire muxed_ipp_drop_pkt; |
| 465 | wire[7:0] muxed_pkt_hdr_len; |
| 466 | wire muxed_s_event; |
| 467 | wire muxed_zcp_drop_pkt; |
| 468 | wire muxed_fflp_hw_err; |
| 469 | wire muxed_mac_promis; |
| 470 | wire muxed_zcopy_mode; |
| 471 | wire muxed_orig_zcopy_mode; |
| 472 | wire[4:0] muxed_tbl_rdc_num; |
| 473 | wire[4:0] muxed_fflp_rdc_num; |
| 474 | wire muxed_noport; |
| 475 | wire muxed_zcp_err; |
| 476 | |
| 477 | wire[3:0] ipp_pkt_sop; |
| 478 | wire[3:0] zcp_pkt_sop; |
| 479 | wire[3:0] ipp_full_pkt; |
| 480 | wire[3:0] zcp_full_pkt; |
| 481 | |
| 482 | wire is_l2_err; |
| 483 | wire[4:0] muxed_rdc_num; |
| 484 | |
| 485 | wire zcp_req_cnt_done; |
| 486 | wire zcp_data_ack; |
| 487 | wire[127:0] muxed_zcp_data; |
| 488 | wire muxed_zcp_data_eop; |
| 489 | wire[4:0] zcp_rdc_num; |
| 490 | wire[1:0] zcp_type; |
| 491 | wire[3:0] zcp_pkt_id; |
| 492 | wire[43:0] zcp_vaddr0_tmp; |
| 493 | wire[43:0] zcp_vaddr1_tmp; |
| 494 | wire[43:0] zcp_vaddr2_tmp; |
| 495 | wire[43:0] zcp_vaddr3_tmp; |
| 496 | |
| 497 | wire[63:0] zcp_vaddr0; |
| 498 | wire[13:0] zcp_len0; |
| 499 | wire[63:0] zcp_vaddr1; |
| 500 | wire[13:0] zcp_len1; |
| 501 | wire[63:0] zcp_vaddr2; |
| 502 | wire[13:0] zcp_len2; |
| 503 | wire[63:0] zcp_vaddr3; |
| 504 | wire[13:0] zcp_len3; |
| 505 | wire[1:0] zcp_func_num; |
| 506 | |
| 507 | wire is_zcp_wr_req; |
| 508 | wire rdmc_wr_req_accept_zcp; |
| 509 | wire rdmc_wr_req_accept_all; |
| 510 | wire rdmc_wr_req_accept_data; |
| 511 | |
| 512 | wire drop_pkt_len_leftover; |
| 513 | wire[9:0] drop_pkt_word_cnt_tmp; |
| 514 | wire drop_pkt_done; |
| 515 | |
| 516 | wire zcp_has_ipp_data_req; |
| 517 | wire[13:0] zcp_data_len; |
| 518 | wire[13:0] new_zcp_data_len_tmp; |
| 519 | wire[13:0] new_zcp_data_len; |
| 520 | |
| 521 | wire[13:0] ipp_pkt_len; |
| 522 | wire ipp_pkt_len_left_over; |
| 523 | wire[10:0] ipp_pkt_len_word_cnt_tmp; |
| 524 | wire ipp_data_req_en; |
| 525 | |
| 526 | wire rdmc_wr_data_req_p; |
| 527 | wire rdmc_wr_data_req_mod; |
| 528 | |
| 529 | wire ipp_data_req0_p; |
| 530 | wire ipp_data_req1_p; |
| 531 | wire ipp_data_req2_p; |
| 532 | wire ipp_data_req3_p; |
| 533 | wire ipp_data_req_p; |
| 534 | wire ipp_data_req_dly; |
| 535 | |
| 536 | wire[127:0] muxed_ipp_data; |
| 537 | wire muxed_ipp_data_eop; |
| 538 | wire muxed_ipp_data_err; |
| 539 | wire[3:0] ipp_data_req_maskout; |
| 540 | wire ipp_data_req_in; |
| 541 | wire ipp_fzcp_eop_in; |
| 542 | wire ipp_next_eop; |
| 543 | |
| 544 | wire pkt_len_left_over; |
| 545 | wire[9:0] pkt_len_word_cnt_tmp; |
| 546 | wire pkt_req_cnt_done_tmp; |
| 547 | wire[15:0] wr_data_byte_en; |
| 548 | |
| 549 | wire[3:0] next_data_offset_tmp1; |
| 550 | wire[3:0] next_data_offset_tmp2; |
| 551 | wire[3:0] next_data_offset_tmp; |
| 552 | |
| 553 | wire[4:0] wr_dp_sm_state; |
| 554 | |
| 555 | wire[3:0] port_ipp_eop_err; |
| 556 | wire[3:0] port_zcp_eop_err; |
| 557 | wire[8:0] port_err_event; |
| 558 | |
| 559 | |
| 560 | //Input registers |
| 561 | always @ (posedge clk) |
| 562 | begin |
| 563 | ipp_full_pkt0 <= ipp_dmc_ful_pkt0 & !ipp_dmc_dat_err0; |
| 564 | ipp_data_ack0 <= ipp_dmc_dat_ack0; |
| 565 | ipp_data_err0 <= ipp_dmc_dat_err0; |
| 566 | ipp_data0 <= ipp_dmc_data0; |
| 567 | |
| 568 | ipp_full_pkt1 <= ipp_dmc_ful_pkt1 & !ipp_dmc_dat_err1; |
| 569 | ipp_data_ack1 <= ipp_dmc_dat_ack1; |
| 570 | ipp_data_err1 <= ipp_dmc_dat_err1; |
| 571 | ipp_data1 <= ipp_dmc_data1; |
| 572 | |
| 573 | ipp_full_pkt2 <= ipp_dmc_ful_pkt2 & !ipp_dmc_dat_err2; |
| 574 | ipp_data_ack2 <= ipp_dmc_dat_ack2; |
| 575 | ipp_data_err2 <= ipp_dmc_dat_err2; |
| 576 | ipp_data2 <= ipp_dmc_data2; |
| 577 | |
| 578 | ipp_full_pkt3 <= ipp_dmc_ful_pkt3 & !ipp_dmc_dat_err3; |
| 579 | ipp_data_ack3 <= ipp_dmc_dat_ack3; |
| 580 | ipp_data_err3 <= ipp_dmc_dat_err3; |
| 581 | ipp_data3 <= ipp_dmc_data3; |
| 582 | |
| 583 | zcp_full_pkt0 <= zcp_dmc_ful_pkt0 & !zcp_dmc_dat_err0; |
| 584 | zcp_data_ack0 <= zcp_dmc_ack0; |
| 585 | zcp_data0 <= zcp_dmc_dat0; |
| 586 | zcp_data_err0 <= zcp_dmc_dat_err0; |
| 587 | |
| 588 | zcp_full_pkt1 <= zcp_dmc_ful_pkt1 & !zcp_dmc_dat_err1; |
| 589 | zcp_data_ack1 <= zcp_dmc_ack1; |
| 590 | zcp_data1 <= zcp_dmc_dat1; |
| 591 | zcp_data_err1 <= zcp_dmc_dat_err1; |
| 592 | |
| 593 | zcp_full_pkt2 <= zcp_dmc_ful_pkt2 & !zcp_dmc_dat_err2; |
| 594 | zcp_data_ack2 <= zcp_dmc_ack2; |
| 595 | zcp_data2 <= zcp_dmc_dat2; |
| 596 | zcp_data_err2 <= zcp_dmc_dat_err2; |
| 597 | |
| 598 | zcp_full_pkt3 <= zcp_dmc_ful_pkt3 & !zcp_dmc_dat_err3; |
| 599 | zcp_data_ack3 <= zcp_dmc_ack3; |
| 600 | zcp_data3 <= zcp_dmc_dat3; |
| 601 | zcp_data_err3 <= zcp_dmc_dat_err3; |
| 602 | end |
| 603 | |
| 604 | |
| 605 | /**********************/ |
| 606 | // Select port |
| 607 | /**********************/ |
| 608 | /* |
| 609 | assign ipp_ctrl_word0 = {ipp_data0[103], ipp_data0[60:56], ipp_data0[53:48], |
| 610 | ipp_data0[101:88], ipp_data0[102], ipp_data0[17]}; //28bits |
| 611 | |
| 612 | assign ipp_ctrl_word1 = {ipp_data1[103], ipp_data1[60:56], ipp_data1[53:48], |
| 613 | ipp_data1[101:88], ipp_data1[102], ipp_data1[17]}; //28bits |
| 614 | |
| 615 | assign ipp_ctrl_word2 = {ipp_data2[103], ipp_data2[60:56], ipp_data2[53:48], |
| 616 | ipp_data2[101:88], ipp_data2[102], ipp_data2[17]}; //28bits |
| 617 | |
| 618 | assign ipp_ctrl_word3 = {ipp_data3[103], ipp_data3[60:56], ipp_data3[53:48], |
| 619 | ipp_data3[101:88], ipp_data3[102], ipp_data3[17]}; //28bits |
| 620 | */ |
| 621 | |
| 622 | assign ipp_ctrl_word0 = {ipp_data0[57:52], ipp_data0[49:44], |
| 623 | ipp_data0[101:88], ipp_data0[102], ipp_data0[17]}; //28bits |
| 624 | |
| 625 | assign ipp_ctrl_word1 = {ipp_data1[57:52], ipp_data1[49:44], |
| 626 | ipp_data1[101:88], ipp_data1[102], ipp_data1[17]}; //28bits |
| 627 | |
| 628 | assign ipp_ctrl_word2 = {ipp_data2[57:52], ipp_data2[49:44], |
| 629 | ipp_data2[101:88], ipp_data2[102], ipp_data2[17]}; //28bits |
| 630 | |
| 631 | assign ipp_ctrl_word3 = {ipp_data3[57:52], ipp_data3[49:44], |
| 632 | ipp_data3[101:88], ipp_data3[102], ipp_data3[17]}; //28bits |
| 633 | |
| 634 | |
| 635 | assign muxed_ipp_ctrl_w = {28{port_gnt[0]}} & ipp_ctrl_word0 | |
| 636 | {28{port_gnt[1]}} & ipp_ctrl_word1 | |
| 637 | {28{port_gnt[2]}} & ipp_ctrl_word2 | |
| 638 | {28{port_gnt[3]}} & ipp_ctrl_word3; |
| 639 | |
| 640 | assign zcp_ctrl_word0 = {zcp_data0[117], zcp_data0[111:104], zcp_data0[95:94], zcp_data0[87], |
| 641 | zcp_data0[79:76], zcp_data0[63:56], zcp_data0[44]}; //25 bits |
| 642 | |
| 643 | assign zcp_ctrl_word1 = {zcp_data1[117], zcp_data1[111:104], zcp_data1[95:94], zcp_data1[87], |
| 644 | zcp_data1[79:76], zcp_data1[63:56], zcp_data1[44]}; |
| 645 | |
| 646 | assign zcp_ctrl_word2 = {zcp_data2[117], zcp_data2[111:104], zcp_data2[95:94], zcp_data2[87], |
| 647 | zcp_data2[79:76], zcp_data2[63:56], zcp_data2[44]}; |
| 648 | |
| 649 | assign zcp_ctrl_word3 = {zcp_data3[117], zcp_data3[111:104], zcp_data3[95:94], zcp_data3[87], |
| 650 | zcp_data3[79:76], zcp_data3[63:56], zcp_data3[44]}; |
| 651 | |
| 652 | assign muxed_zcp_ctrl_w = {25{port_gnt[0]}} & zcp_ctrl_word0 | |
| 653 | {25{port_gnt[1]}} & zcp_ctrl_word1 | |
| 654 | {25{port_gnt[2]}} & zcp_ctrl_word2 | |
| 655 | {25{port_gnt[3]}} & zcp_ctrl_word3; |
| 656 | |
| 657 | //assign muxed_cksum_err = muxed_ipp_data_c[17]; |
| 658 | //assign muxed_pkt_id = muxed_ipp_data_c[53:50]; |
| 659 | //assign muxed_pkt_len = muxed_ipp_data_c[101:88]; |
| 660 | //assign muxed_bad_crc = muxed_ipp_data_c[102] |
| 661 | //assign muxed_ipp_discard_bits = {muxed_ipp_data_c[103], muxed_ipp_data_c[60:56]}; |
| 662 | |
| 663 | assign muxed_cksum_err = muxed_ipp_ctrl_w[0]; |
| 664 | assign muxed_bad_crc = muxed_ipp_ctrl_w[1]; |
| 665 | assign muxed_pkt_len = muxed_zcopy_mode ? {6'b0, muxed_pkt_hdr_len} : muxed_ipp_ctrl_w[15:2]; |
| 666 | assign muxed_l2_len = muxed_ipp_ctrl_w[15:2]; |
| 667 | assign muxed_pkt_type = muxed_ipp_ctrl_w[17:16]; |
| 668 | assign muxed_ipp_pkt_id = muxed_ipp_ctrl_w[21:18]; |
| 669 | assign muxed_ipp_drop_bits = muxed_ipp_ctrl_w[27:22]; |
| 670 | assign muxed_ipp_drop_pkt = |muxed_ipp_drop_bits; |
| 671 | |
| 672 | assign muxed_zcp_err = !muxed_orig_zcopy_mode & muxed_zcp_ctrl_w[0]; |
| 673 | assign muxed_pkt_hdr_len = muxed_zcp_ctrl_w[8:1]; |
| 674 | assign muxed_s_event = muxed_zcp_ctrl_w[9]; |
| 675 | assign muxed_zcp_drop_pkt = muxed_zcp_ctrl_w[10]; |
| 676 | assign muxed_fflp_hw_err = muxed_zcp_ctrl_w[11]; |
| 677 | assign muxed_mac_promis = muxed_zcp_ctrl_w[12]; |
| 678 | assign muxed_orig_zcopy_mode = muxed_zcp_ctrl_w[13]; |
| 679 | assign muxed_zcopy_mode = muxed_orig_zcopy_mode & !(muxed_bad_crc | muxed_cksum_err); |
| 680 | assign muxed_tbl_rdc_num = muxed_zcp_ctrl_w[18:14]; |
| 681 | assign muxed_fflp_rdc_num = muxed_zcp_ctrl_w[23:19]; |
| 682 | assign muxed_noport = muxed_zcp_ctrl_w[24]; |
| 683 | |
| 684 | assign ipp_full_pkt = {ipp_full_pkt3, ipp_full_pkt2, ipp_full_pkt1, ipp_full_pkt0} & (~port_err_status); |
| 685 | assign zcp_full_pkt = {zcp_full_pkt3, zcp_full_pkt2, zcp_full_pkt1, zcp_full_pkt0} & (~port_err_status); |
| 686 | |
| 687 | assign ipp_pkt_sop = {ipp_sop_reg3, ipp_sop_reg2, ipp_sop_reg1, ipp_sop_reg0}; |
| 688 | assign zcp_pkt_sop = {zcp_sop_reg3, zcp_sop_reg2, zcp_sop_reg1, zcp_sop_reg0}; |
| 689 | |
| 690 | /**********************/ |
| 691 | //Select RDC number |
| 692 | /**********************/ |
| 693 | assign is_l2_err = muxed_mac_promis | muxed_bad_crc | muxed_ipp_drop_pkt | muxed_zcp_drop_pkt; |
| 694 | assign muxed_rdc_num = is_l2_err ? muxed_port_rdc_num : |
| 695 | muxed_cksum_err ? muxed_tbl_rdc_num : |
| 696 | muxed_fflp_rdc_num; |
| 697 | always @ (posedge clk) |
| 698 | if (reset) |
| 699 | begin |
| 700 | muxed_cksum_err_r <= 1'b0; |
| 701 | muxed_bad_crc_r <= 1'b0; |
| 702 | muxed_ipp_pkt_id_r <= 4'b0; |
| 703 | muxed_pkt_len_r <= 14'b0; |
| 704 | muxed_l2_len_r <= 14'b0; |
| 705 | muxed_drop_pkt_r <= 1'b0; |
| 706 | muxed_mac_promis_r <= 1'b0; |
| 707 | muxed_s_event_r <= 1'b0; |
| 708 | muxed_fflp_hw_err_r <= 1'b0; |
| 709 | muxed_zcopy_mode_r <= 1'b0; |
| 710 | muxed_orig_zcopy_mode_r <= 1'b0; |
| 711 | muxed_rdc_num_r <= 5'b0; |
| 712 | muxed_pkt_type_r <= 2'b0; |
| 713 | muxed_noport_r <= 1'b0; |
| 714 | muxed_zcp_err_r <= 1'b0; |
| 715 | end |
| 716 | else if (stage0_en) |
| 717 | begin |
| 718 | muxed_cksum_err_r <= muxed_cksum_err; |
| 719 | muxed_bad_crc_r <= muxed_bad_crc; |
| 720 | muxed_ipp_pkt_id_r <= muxed_ipp_pkt_id; |
| 721 | muxed_pkt_len_r <= muxed_pkt_len; |
| 722 | muxed_l2_len_r <= muxed_l2_len; |
| 723 | muxed_drop_pkt_r <= muxed_ipp_drop_pkt | muxed_zcp_drop_pkt; |
| 724 | muxed_mac_promis_r <= muxed_mac_promis; |
| 725 | muxed_s_event_r <= muxed_s_event; |
| 726 | muxed_fflp_hw_err_r <= muxed_fflp_hw_err; |
| 727 | muxed_zcopy_mode_r <= muxed_zcopy_mode; |
| 728 | muxed_orig_zcopy_mode_r <= muxed_orig_zcopy_mode; |
| 729 | muxed_rdc_num_r <= muxed_rdc_num; |
| 730 | muxed_pkt_type_r <= muxed_pkt_type; |
| 731 | muxed_noport_r <= muxed_noport; |
| 732 | muxed_zcp_err_r <= muxed_zcp_err; |
| 733 | end |
| 734 | |
| 735 | wire[2:0] err_inc = muxed_bad_crc_r ? 3'b001 : |
| 736 | muxed_cksum_err_r ? 3'b011 : |
| 737 | muxed_fflp_hw_err_r ? 3'b100 : |
| 738 | muxed_zcp_err_r ? 3'b101 : 3'b000; |
| 739 | |
| 740 | wire[22:0] pkt_wrbk_data = {muxed_pkt_type_r, muxed_zcopy_mode_r, muxed_noport_r, |
| 741 | muxed_mac_promis_r, err_inc, 1'b0, muxed_l2_len_r}; //23bits |
| 742 | |
| 743 | |
| 744 | /*************************/ |
| 745 | //Pipeline Control |
| 746 | /*************************/ |
| 747 | always @ (posedge clk) |
| 748 | if (reset) |
| 749 | port_gnt_r1 <= 4'b0; |
| 750 | else if (rdmc_wr_req_accept_hdr) |
| 751 | port_gnt_r1 <= port_gnt_r; |
| 752 | else |
| 753 | port_gnt_r1 <= port_gnt_r1; |
| 754 | |
| 755 | always @ (posedge clk) |
| 756 | if (reset) |
| 757 | is_first_accept <= 1'b0; |
| 758 | else if (rdmc_wr_req_accept_hdr) |
| 759 | is_first_accept <= 1'b1; |
| 760 | else if (ipp_data_req_p) |
| 761 | is_first_accept <= 1'b0; |
| 762 | else |
| 763 | is_first_accept <= is_first_accept; |
| 764 | |
| 765 | always @ (posedge clk) |
| 766 | if (reset) |
| 767 | begin |
| 768 | ipp_data_req_p_r <= 1'b0; |
| 769 | ipp_data_req_p_r1 <= 1'b0; |
| 770 | ipp_data_req_p_r2 <= 1'b0; |
| 771 | end |
| 772 | else |
| 773 | begin |
| 774 | ipp_data_req_p_r <= ipp_data_req_p & is_first_accept; |
| 775 | ipp_data_req_p_r1 <= ipp_data_req_p_r; |
| 776 | ipp_data_req_p_r2 <= ipp_data_req_p_r1; |
| 777 | end |
| 778 | |
| 779 | always @ (posedge clk) |
| 780 | if (reset) |
| 781 | begin |
| 782 | full_hdr_r1 <= 1'b0; |
| 783 | zcopy_mode <= 1'b0; |
| 784 | jmb_pkt_type <= 2'b0; |
| 785 | end |
| 786 | else if (rdmc_wr_req_accept_hdr) |
| 787 | begin |
| 788 | full_hdr_r1 <= full_hdr_r; |
| 789 | zcopy_mode <= muxed_zcopy_mode_r; |
| 790 | jmb_pkt_type <= pref_buf_used_num_r; |
| 791 | end |
| 792 | else |
| 793 | begin |
| 794 | full_hdr_r1 <= full_hdr_r1; |
| 795 | zcopy_mode <= zcopy_mode; |
| 796 | jmb_pkt_type <= jmb_pkt_type; |
| 797 | end |
| 798 | |
| 799 | always @ (posedge clk) |
| 800 | if (reset) |
| 801 | port_gnt_r2 <= 4'b0; |
| 802 | else if (ipp_data_req_p_r2) |
| 803 | port_gnt_r2 <= port_gnt_r1; |
| 804 | else if (drop_pkt_done) |
| 805 | port_gnt_r2 <= drop_pkt_port_gnt; |
| 806 | else if (rdmc_cal_eop_r) |
| 807 | port_gnt_r2 <= 4'b0; |
| 808 | else |
| 809 | port_gnt_r2 <= port_gnt_r2; |
| 810 | |
| 811 | |
| 812 | always @ (posedge clk) |
| 813 | if (reset) |
| 814 | zcp_wr_type <= 2'b00; |
| 815 | else if (ipp_data_req_p_r2) |
| 816 | zcp_wr_type <= zcp_type[1:0]; |
| 817 | else |
| 818 | zcp_wr_type <= zcp_wr_type; |
| 819 | |
| 820 | always @ (posedge clk) |
| 821 | if (reset) |
| 822 | rdmc_wr_data_dma_num <= 5'b0; |
| 823 | else if (rdmc_wr_req_accept_hdr) |
| 824 | rdmc_wr_data_dma_num <= rdmc_meta0_wr_req_dma_num_int; |
| 825 | else |
| 826 | rdmc_wr_data_dma_num <= rdmc_wr_data_dma_num; |
| 827 | |
| 828 | /**********************/ |
| 829 | //ZCP Req and Data |
| 830 | /**********************/ |
| 831 | assign zcp_req_cnt_done = muxed_orig_zcopy_mode ? zcp_req_cnt[2] : zcp_req_cnt[1]; |
| 832 | |
| 833 | always @ (posedge clk) |
| 834 | if (reset) |
| 835 | zcp_req_cnt <= 3'b0; |
| 836 | else if (zcp_req_cnt_done) |
| 837 | zcp_req_cnt <= 3'b0; |
| 838 | else if (stage0_en | (|zcp_req_cnt)) |
| 839 | zcp_req_cnt <= zcp_req_cnt + 3'd1; |
| 840 | else |
| 841 | zcp_req_cnt <= zcp_req_cnt; |
| 842 | |
| 843 | always @ (posedge clk) |
| 844 | if (reset) |
| 845 | dmc_zcp_req0 <= 1'b0; |
| 846 | else if (stage0_en & port_gnt[0]) |
| 847 | dmc_zcp_req0 <= 1'b1; |
| 848 | else if (zcp_req_cnt_done) |
| 849 | dmc_zcp_req0 <= 1'b0; |
| 850 | else |
| 851 | dmc_zcp_req0 <= dmc_zcp_req0; |
| 852 | |
| 853 | always @ (posedge clk) |
| 854 | if (reset) |
| 855 | dmc_zcp_req1 <= 1'b0; |
| 856 | else if (stage0_en & port_gnt[1]) |
| 857 | dmc_zcp_req1 <= 1'b1; |
| 858 | else if (zcp_req_cnt_done) |
| 859 | dmc_zcp_req1 <= 1'b0; |
| 860 | else |
| 861 | dmc_zcp_req1 <= dmc_zcp_req1; |
| 862 | |
| 863 | always @ (posedge clk) |
| 864 | if (reset) |
| 865 | dmc_zcp_req2 <= 1'b0; |
| 866 | else if (stage0_en & port_gnt[2]) |
| 867 | dmc_zcp_req2 <= 1'b1; |
| 868 | else if (zcp_req_cnt_done) |
| 869 | dmc_zcp_req2 <= 1'b0; |
| 870 | else |
| 871 | dmc_zcp_req2 <= dmc_zcp_req2; |
| 872 | |
| 873 | always @ (posedge clk) |
| 874 | if (reset) |
| 875 | dmc_zcp_req3 <= 1'b0; |
| 876 | else if (stage0_en & port_gnt[3]) |
| 877 | dmc_zcp_req3 <= 1'b1; |
| 878 | else if (zcp_req_cnt_done) |
| 879 | dmc_zcp_req3 <= 1'b0; |
| 880 | else |
| 881 | dmc_zcp_req3 <= dmc_zcp_req3; |
| 882 | |
| 883 | assign zcp_data_ack = zcp_data_ack0 | zcp_data_ack1 | zcp_data_ack2 | zcp_data_ack3; |
| 884 | assign muxed_zcp_data = {128{port_gnt_r[0]}} & zcp_data0[127:0] | |
| 885 | {128{port_gnt_r[1]}} & zcp_data1[127:0] | |
| 886 | {128{port_gnt_r[2]}} & zcp_data2[127:0] | |
| 887 | {128{port_gnt_r[3]}} & zcp_data3[127:0] ; |
| 888 | |
| 889 | assign muxed_zcp_data_eop = port_gnt_r[0] & zcp_data_ack0 & zcp_data0[129] | |
| 890 | port_gnt_r[1] & zcp_data_ack1 & zcp_data1[129] | |
| 891 | port_gnt_r[2] & zcp_data_ack2 & zcp_data2[129] | |
| 892 | port_gnt_r[3] & zcp_data_ack3 & zcp_data3[129] ; |
| 893 | |
| 894 | |
| 895 | always @ (posedge clk) |
| 896 | if (reset) |
| 897 | zcp_ack_cnt <= 2'b0; |
| 898 | else if (zcp_data_ack) |
| 899 | zcp_ack_cnt <= zcp_ack_cnt + 2'd1; |
| 900 | else |
| 901 | zcp_ack_cnt <= 2'b0; |
| 902 | |
| 903 | always @ (posedge clk) |
| 904 | if (reset) |
| 905 | zcp_data_reg0 <= 128'b0; |
| 906 | else if (zcp_data_ack & (zcp_ack_cnt == 2'b00)) |
| 907 | zcp_data_reg0 <= muxed_zcp_data; |
| 908 | else |
| 909 | zcp_data_reg0 <= zcp_data_reg0; |
| 910 | |
| 911 | always @ (posedge clk) |
| 912 | if (reset) |
| 913 | zcp_data_reg1 <= 32'b0; |
| 914 | else if (zcp_data_ack & (zcp_ack_cnt == 2'b01)) |
| 915 | zcp_data_reg1 <= muxed_zcp_data[127:96]; |
| 916 | else |
| 917 | zcp_data_reg1 <= zcp_data_reg1; |
| 918 | |
| 919 | |
| 920 | `ifdef NEPTUNE |
| 921 | always @ (posedge clk) |
| 922 | if (reset) |
| 923 | zcp_data_reg1_lo <= 22'b0; |
| 924 | else if (zcp_data_ack & (zcp_ack_cnt == 2'b01)) |
| 925 | zcp_data_reg1_lo <= muxed_zcp_data[23:2]; |
| 926 | else |
| 927 | zcp_data_reg1_lo <= zcp_data_reg1_lo; |
| 928 | |
| 929 | |
| 930 | always @ (posedge clk) |
| 931 | if (reset) |
| 932 | zcp_data_reg2 <= 128'b0; |
| 933 | else if (zcp_data_ack & (zcp_ack_cnt == 2'b10)) |
| 934 | zcp_data_reg2 <= muxed_zcp_data[127:0]; |
| 935 | else |
| 936 | zcp_data_reg2 <= zcp_data_reg2; |
| 937 | |
| 938 | always @ (posedge clk) |
| 939 | if (reset) |
| 940 | zcp_data_reg3 <= 128'b0; |
| 941 | else if (zcp_data_ack & (zcp_ack_cnt == 2'b11)) |
| 942 | zcp_data_reg3 <= muxed_zcp_data[127:0]; |
| 943 | else |
| 944 | zcp_data_reg3 <= zcp_data_reg3; |
| 945 | |
| 946 | `else |
| 947 | |
| 948 | assign zcp_data_reg2 = 128'b0; |
| 949 | assign zcp_data_reg3 = 128'b0; |
| 950 | assign zcp_data_reg1_lo = 22'b0; |
| 951 | |
| 952 | `endif |
| 953 | |
| 954 | /*********************************/ |
| 955 | //one stage pipeline zcp read data |
| 956 | /*********************************/ |
| 957 | always @ (posedge clk) |
| 958 | if (reset) |
| 959 | begin |
| 960 | rdmc_wr_req_accept_hdr_r <= 1'b0; |
| 961 | rdmc_wr_req_accept_hdr_r1 <= 1'b0; |
| 962 | end |
| 963 | else |
| 964 | begin |
| 965 | rdmc_wr_req_accept_hdr_r <= rdmc_wr_req_accept_hdr; |
| 966 | rdmc_wr_req_accept_hdr_r1 <= rdmc_wr_req_accept_hdr_r; |
| 967 | end |
| 968 | |
| 969 | always @ (posedge clk) |
| 970 | if (reset) |
| 971 | zcp_data_reg0_r <= 128'b0; |
| 972 | else if (rdmc_wr_req_accept_hdr_r1) |
| 973 | zcp_data_reg0_r <= zcp_data_reg0; |
| 974 | else |
| 975 | zcp_data_reg0_r <= zcp_data_reg0_r; |
| 976 | |
| 977 | always @ (posedge clk) |
| 978 | if (reset) |
| 979 | zcp_data_reg1_r <= 16'b0; |
| 980 | else if (rdmc_wr_req_accept_hdr_r1) |
| 981 | zcp_data_reg1_r <= zcp_data_reg1[31:16]; |
| 982 | else |
| 983 | zcp_data_reg1_r <= zcp_data_reg1_r; |
| 984 | |
| 985 | |
| 986 | wire[7:0] zcp_data_reg0_byte0 = zcp_data_reg0_r[127:120]; |
| 987 | wire[7:0] zcp_data_reg0_byte1 = zcp_data_reg0_r[119:112]; |
| 988 | wire[7:0] zcp_data_reg0_byte2 = zcp_data_reg0_r[111:104]; |
| 989 | wire[7:0] zcp_data_reg0_byte3 = zcp_data_reg0_r[103:96]; |
| 990 | wire[7:0] zcp_data_reg0_byte4 = zcp_data_reg0_r[95:88]; |
| 991 | wire[7:0] zcp_data_reg0_byte5 = zcp_data_reg0_r[87:80]; |
| 992 | wire[7:0] zcp_data_reg0_byte6 = zcp_data_reg0_r[79:72]; |
| 993 | wire[7:0] zcp_data_reg0_byte7 = zcp_data_reg0_r[71:64]; |
| 994 | wire[7:0] zcp_data_reg0_byte8 = zcp_data_reg0_r[63:56]; |
| 995 | wire[7:0] zcp_data_reg0_byte9 = zcp_data_reg0_r[55:48]; |
| 996 | wire[7:0] zcp_data_reg0_byte10 = zcp_data_reg0_r[47:40]; |
| 997 | wire[7:0] zcp_data_reg0_byte11 = zcp_data_reg0_r[39:32]; |
| 998 | wire[7:0] zcp_data_reg0_byte12 = zcp_data_reg0_r[31:24]; |
| 999 | wire[7:0] zcp_data_reg0_byte13 = zcp_data_reg0_r[23:16]; |
| 1000 | wire[7:0] zcp_data_reg0_byte14 = zcp_data_reg0_r[15:8]; |
| 1001 | wire[7:0] zcp_data_reg0_byte15 = zcp_data_reg0_r[7:0]; |
| 1002 | |
| 1003 | wire[7:0] zcp_data_reg1_byte0 = zcp_data_reg1_r[15:8]; |
| 1004 | wire[7:0] zcp_data_reg1_byte1 = zcp_data_reg1_r[7:0]; |
| 1005 | wire[7:0] zcp_data_reg1_byte2 = zcp_data_reg1[15:8]; |
| 1006 | wire[7:0] zcp_data_reg1_byte3 = zcp_data_reg1[7:0]; |
| 1007 | |
| 1008 | wire[7:0] zcp_data_reg2_byte0 = zcp_data_reg2[127:120]; |
| 1009 | wire[7:0] zcp_data_reg2_byte1 = zcp_data_reg2[119:112]; |
| 1010 | wire[7:0] zcp_data_reg2_byte2 = zcp_data_reg2[111:104]; |
| 1011 | wire[7:0] zcp_data_reg2_byte3 = zcp_data_reg2[103:96]; |
| 1012 | wire[7:0] zcp_data_reg2_byte4 = zcp_data_reg2[95:88]; |
| 1013 | wire[7:0] zcp_data_reg2_byte5 = zcp_data_reg2[87:80]; |
| 1014 | wire[7:0] zcp_data_reg2_byte6 = zcp_data_reg2[79:72]; |
| 1015 | wire[7:0] zcp_data_reg2_byte7 = zcp_data_reg2[71:64]; |
| 1016 | wire[7:0] zcp_data_reg2_byte8 = zcp_data_reg2[63:56]; |
| 1017 | wire[7:0] zcp_data_reg2_byte9 = zcp_data_reg2[55:48]; |
| 1018 | wire[7:0] zcp_data_reg2_byte10 = zcp_data_reg2[47:40]; |
| 1019 | wire[7:0] zcp_data_reg2_byte11 = zcp_data_reg2[39:32]; |
| 1020 | wire[7:0] zcp_data_reg2_byte12 = zcp_data_reg2[31:24]; |
| 1021 | wire[7:0] zcp_data_reg2_byte13 = zcp_data_reg2[23:16]; |
| 1022 | wire[7:0] zcp_data_reg2_byte14 = zcp_data_reg2[15:8]; |
| 1023 | wire[7:0] zcp_data_reg2_byte15 = zcp_data_reg2[7:0]; |
| 1024 | |
| 1025 | wire[7:0] zcp_data_reg3_byte0 = zcp_data_reg3[127:120]; |
| 1026 | wire[7:0] zcp_data_reg3_byte1 = zcp_data_reg3[119:112]; |
| 1027 | wire[7:0] zcp_data_reg3_byte2 = zcp_data_reg3[111:104]; |
| 1028 | wire[7:0] zcp_data_reg3_byte3 = zcp_data_reg3[103:96]; |
| 1029 | wire[7:0] zcp_data_reg3_byte4 = zcp_data_reg3[95:88]; |
| 1030 | wire[7:0] zcp_data_reg3_byte5 = zcp_data_reg3[87:80]; |
| 1031 | wire[7:0] zcp_data_reg3_byte6 = zcp_data_reg3[79:72]; |
| 1032 | wire[7:0] zcp_data_reg3_byte7 = zcp_data_reg3[71:64]; |
| 1033 | wire[7:0] zcp_data_reg3_byte8 = zcp_data_reg3[63:56]; |
| 1034 | wire[7:0] zcp_data_reg3_byte9 = zcp_data_reg3[55:48]; |
| 1035 | wire[7:0] zcp_data_reg3_byte10 = zcp_data_reg3[47:40]; |
| 1036 | wire[7:0] zcp_data_reg3_byte11 = zcp_data_reg3[39:32]; |
| 1037 | wire[7:0] zcp_data_reg3_byte12 = zcp_data_reg3[31:24]; |
| 1038 | wire[7:0] zcp_data_reg3_byte13 = zcp_data_reg3[23:16]; |
| 1039 | wire[7:0] zcp_data_reg3_byte14 = zcp_data_reg3[15:8]; |
| 1040 | wire[7:0] zcp_data_reg3_byte15 = zcp_data_reg3[7:0]; |
| 1041 | |
| 1042 | assign zcp_rdc_num = zcp_data_reg1_byte3[4:0]; |
| 1043 | assign zcp_type = zcp_data_reg1_byte3[6:5]; |
| 1044 | assign zcp_pkt_id = zcp_data_reg1_byte2[5:2]; |
| 1045 | |
| 1046 | assign zcp_vaddr0_tmp = {zcp_data_reg2_byte0[3:0], zcp_data_reg2_byte1, zcp_data_reg2_byte2, |
| 1047 | zcp_data_reg2_byte3, zcp_data_reg2_byte4, zcp_data_reg2_byte5}; |
| 1048 | assign zcp_len0 = {zcp_data_reg2_byte6[5:0], zcp_data_reg2_byte7}; |
| 1049 | |
| 1050 | assign zcp_vaddr1_tmp = {zcp_data_reg2_byte8[3:0], zcp_data_reg2_byte9, zcp_data_reg2_byte10, |
| 1051 | zcp_data_reg2_byte11, zcp_data_reg2_byte12, zcp_data_reg2_byte13}; |
| 1052 | assign zcp_len1 = {zcp_data_reg2_byte14[5:0],zcp_data_reg2_byte15}; |
| 1053 | |
| 1054 | assign zcp_vaddr2_tmp = {zcp_data_reg3_byte0[3:0], zcp_data_reg3_byte1, zcp_data_reg3_byte2, |
| 1055 | zcp_data_reg3_byte3, zcp_data_reg3_byte4, zcp_data_reg3_byte5}; |
| 1056 | assign zcp_len2 = {zcp_data_reg3_byte6[5:0], zcp_data_reg3_byte7}; |
| 1057 | |
| 1058 | assign zcp_vaddr3_tmp = {zcp_data_reg3_byte8[3:0], zcp_data_reg3_byte9, zcp_data_reg3_byte10, |
| 1059 | zcp_data_reg3_byte11, zcp_data_reg3_byte12, zcp_data_reg3_byte13}; |
| 1060 | assign zcp_len3 = {zcp_data_reg3_byte14[5:0],zcp_data_reg3_byte15}; |
| 1061 | |
| 1062 | assign zcp_vaddr0 = {zcp_data_reg1_lo[21:2], zcp_vaddr0_tmp[43:0]}; |
| 1063 | assign zcp_vaddr1 = {zcp_data_reg1_lo[21:2], zcp_vaddr1_tmp[43:0]}; |
| 1064 | assign zcp_vaddr2 = {zcp_data_reg1_lo[21:2], zcp_vaddr2_tmp[43:0]}; |
| 1065 | assign zcp_vaddr3 = {zcp_data_reg1_lo[21:2], zcp_vaddr3_tmp[43:0]}; |
| 1066 | |
| 1067 | assign zcp_func_num = zcp_data_reg1_lo[1:0]; |
| 1068 | |
| 1069 | |
| 1070 | /********************/ |
| 1071 | //IPP Req and Data |
| 1072 | /********************/ |
| 1073 | |
| 1074 | /********************/ |
| 1075 | //Drop Packet Logic |
| 1076 | /********************/ |
| 1077 | assign drop_pkt_len_leftover = |muxed_l2_len_r[3:0]; |
| 1078 | assign drop_pkt_word_cnt_tmp = drop_pkt_len_leftover ? muxed_l2_len_r[13:4] : (muxed_l2_len_r[13:4] - 10'd1); |
| 1079 | assign drop_pkt_done = drop_pkt_en & (drop_pkt_word_cnt == 10'b0); |
| 1080 | |
| 1081 | always @ (posedge clk) |
| 1082 | if (reset) |
| 1083 | drop_pkt_word_cnt <= 10'b0; |
| 1084 | else if (drop_pkt_en_sm) |
| 1085 | drop_pkt_word_cnt <= drop_pkt_word_cnt_tmp; |
| 1086 | else if (drop_pkt_en & !drop_pkt_done) |
| 1087 | drop_pkt_word_cnt <= drop_pkt_word_cnt - 10'd1; |
| 1088 | else |
| 1089 | drop_pkt_word_cnt <= drop_pkt_word_cnt; |
| 1090 | |
| 1091 | always @ (posedge clk) |
| 1092 | if (reset) |
| 1093 | drop_pkt_en_dly <= 4'b0; |
| 1094 | else |
| 1095 | drop_pkt_en_dly <= {4{drop_pkt_en}} & drop_pkt_port_gnt; |
| 1096 | |
| 1097 | |
| 1098 | /*********************/ |
| 1099 | /*********************/ |
| 1100 | assign is_zcp_wr_req = is_zcp0_wr_req | is_zcp1_wr_req | is_zcp2_wr_req | is_zcp3_wr_req; |
| 1101 | |
| 1102 | assign rdmc_wr_req_accept_zcp = rdmc_wr_req_accept_zcp0 | rdmc_wr_req_accept_zcp1 | |
| 1103 | rdmc_wr_req_accept_zcp2 | rdmc_wr_req_accept_zcp3; |
| 1104 | |
| 1105 | assign rdmc_wr_req_accept_all = rdmc_wr_req_accept_hdr | rdmc_wr_req_accept_zcp | |
| 1106 | rdmc_wr_req_accept_jmb; |
| 1107 | |
| 1108 | assign rdmc_wr_req_accept_data = rdmc_wr_req_accept_zcp | rdmc_wr_req_accept_jmb; |
| 1109 | |
| 1110 | |
| 1111 | assign zcp_data_len = is_zcp0_wr_req ? zcp_len0 : |
| 1112 | is_zcp1_wr_req ? zcp_len1 : |
| 1113 | is_zcp2_wr_req ? zcp_len2 : |
| 1114 | zcp_len3 ; |
| 1115 | |
| 1116 | assign zcp_has_ipp_data_req = (|zcp_data_len[13:4]) | (zcp_data_len[3:0] > next_data_offset_reg[3:0]); |
| 1117 | assign new_zcp_data_len_tmp = zcp_data_len - {10'b0, next_data_offset_reg}; |
| 1118 | assign new_zcp_data_len = zcp_has_ipp_data_req ? new_zcp_data_len_tmp : 14'b0; |
| 1119 | |
| 1120 | assign ipp_pkt_len = is_zcp_wr_req ? new_zcp_data_len_r : muxed_pkt_len_r; |
| 1121 | |
| 1122 | assign ipp_pkt_len_left_over = |ipp_pkt_len[3:0]; |
| 1123 | |
| 1124 | assign ipp_pkt_len_word_cnt_tmp = ipp_pkt_len_left_over ? ({1'b0, ipp_pkt_len[13:4]} + 11'd1) : {1'b0, ipp_pkt_len[13:4]}; |
| 1125 | assign rdmc_wr_data_req_p = full_hdr_r1 & is_first_accept & rdmc_wr_data_req & !rdmc_wr_data_req_dly; |
| 1126 | assign rdmc_wr_data_req_mod = rdmc_wr_data_req & !rdmc_wr_data_req_p; |
| 1127 | assign ipp_data_req_en = rdmc_wr_data_req_mod & (|ipp_pkt_len_word_cnt); |
| 1128 | |
| 1129 | always @ (posedge clk) |
| 1130 | if (reset) |
| 1131 | rdmc_wr_data_req_dly <= 1'b0; |
| 1132 | else |
| 1133 | rdmc_wr_data_req_dly <= rdmc_wr_data_req; |
| 1134 | |
| 1135 | always @ (posedge clk) |
| 1136 | if (reset) |
| 1137 | new_zcp_data_len_r <= 14'b0; |
| 1138 | else |
| 1139 | new_zcp_data_len_r <= new_zcp_data_len; |
| 1140 | |
| 1141 | |
| 1142 | always @ (posedge clk) |
| 1143 | if (reset) |
| 1144 | ipp_pkt_len_word_cnt <= 11'b0; |
| 1145 | else if (rdmc_wr_req_accept_zcp | rdmc_wr_req_accept_hdr) |
| 1146 | ipp_pkt_len_word_cnt <= ipp_pkt_len_word_cnt_tmp; |
| 1147 | else if (ipp_data_req_en) |
| 1148 | ipp_pkt_len_word_cnt <= ipp_pkt_len_word_cnt - 11'd1; |
| 1149 | else |
| 1150 | ipp_pkt_len_word_cnt <= ipp_pkt_len_word_cnt; |
| 1151 | |
| 1152 | |
| 1153 | wire ipp_data_req_en1 = ipp_data_req_en | drop_pad_data; |
| 1154 | |
| 1155 | always @ (posedge clk) |
| 1156 | if (reset) |
| 1157 | begin |
| 1158 | ipp_dat_req0_data <= 1'b0; |
| 1159 | ipp_dat_req1_data <= 1'b0; |
| 1160 | ipp_dat_req2_data <= 1'b0; |
| 1161 | ipp_dat_req3_data <= 1'b0; |
| 1162 | end |
| 1163 | else |
| 1164 | begin |
| 1165 | ipp_dat_req0_data <= ipp_data_req_en1 & port_gnt_r1[0] | drop_pkt_en & drop_pkt_port_gnt[0]; |
| 1166 | ipp_dat_req1_data <= ipp_data_req_en1 & port_gnt_r1[1] | drop_pkt_en & drop_pkt_port_gnt[1]; |
| 1167 | ipp_dat_req2_data <= ipp_data_req_en1 & port_gnt_r1[2] | drop_pkt_en & drop_pkt_port_gnt[2]; |
| 1168 | ipp_dat_req3_data <= ipp_data_req_en1 & port_gnt_r1[3] | drop_pkt_en & drop_pkt_port_gnt[3]; |
| 1169 | end |
| 1170 | |
| 1171 | always @ (posedge clk) |
| 1172 | if (reset) |
| 1173 | begin |
| 1174 | dmc_ipp_dat_req0 <= 1'b0; |
| 1175 | dmc_ipp_dat_req1 <= 1'b0; |
| 1176 | dmc_ipp_dat_req2 <= 1'b0; |
| 1177 | dmc_ipp_dat_req3 <= 1'b0; |
| 1178 | rdmc_wr_data_req <= 1'b0; |
| 1179 | end |
| 1180 | else |
| 1181 | begin |
| 1182 | dmc_ipp_dat_req0 <= stage0_en & port_gnt[0] | ipp_data_req_en1 & port_gnt_r1[0] | drop_pkt_en & drop_pkt_port_gnt[0]; |
| 1183 | dmc_ipp_dat_req1 <= stage0_en & port_gnt[1] | ipp_data_req_en1 & port_gnt_r1[1] | drop_pkt_en & drop_pkt_port_gnt[1]; |
| 1184 | dmc_ipp_dat_req2 <= stage0_en & port_gnt[2] | ipp_data_req_en1 & port_gnt_r1[2] | drop_pkt_en & drop_pkt_port_gnt[2]; |
| 1185 | dmc_ipp_dat_req3 <= stage0_en & port_gnt[3] | ipp_data_req_en1 & port_gnt_r1[3] | drop_pkt_en & drop_pkt_port_gnt[3]; |
| 1186 | rdmc_wr_data_req <= meta0_rdmc_wr_data_req; |
| 1187 | end |
| 1188 | |
| 1189 | always @ (posedge clk) |
| 1190 | if (reset) |
| 1191 | stage0_en_r <= 1'b0; |
| 1192 | else |
| 1193 | stage0_en_r <= stage0_en; |
| 1194 | |
| 1195 | always @ (posedge clk) |
| 1196 | if (reset) |
| 1197 | drop_pad_data_r <= 1'b0; |
| 1198 | else |
| 1199 | drop_pad_data_r <= drop_pad_data; |
| 1200 | |
| 1201 | assign ipp_data_req_maskout = {4{stage0_en_r}} & port_gnt | drop_pkt_en_dly | {4{drop_pad_data_r}} & port_gnt_r1; |
| 1202 | |
| 1203 | always @ (posedge clk) |
| 1204 | if (reset) |
| 1205 | begin |
| 1206 | ipp_data_req0_dly <= 1'b0; |
| 1207 | ipp_data_req1_dly <= 1'b0; |
| 1208 | ipp_data_req2_dly <= 1'b0; |
| 1209 | ipp_data_req3_dly <= 1'b0; |
| 1210 | end |
| 1211 | else |
| 1212 | begin |
| 1213 | ipp_data_req0_dly <= dmc_ipp_dat_req0 & !ipp_data_req_maskout[0]; |
| 1214 | ipp_data_req1_dly <= dmc_ipp_dat_req1 & !ipp_data_req_maskout[1]; |
| 1215 | ipp_data_req2_dly <= dmc_ipp_dat_req2 & !ipp_data_req_maskout[2]; |
| 1216 | ipp_data_req3_dly <= dmc_ipp_dat_req3 & !ipp_data_req_maskout[3]; |
| 1217 | end |
| 1218 | |
| 1219 | assign ipp_data_req0_p = dmc_ipp_dat_req0 & !ipp_data_req0_dly & !ipp_data_req_maskout[0]; |
| 1220 | assign ipp_data_req1_p = dmc_ipp_dat_req1 & !ipp_data_req1_dly & !ipp_data_req_maskout[1]; |
| 1221 | assign ipp_data_req2_p = dmc_ipp_dat_req2 & !ipp_data_req2_dly & !ipp_data_req_maskout[2]; |
| 1222 | assign ipp_data_req3_p = dmc_ipp_dat_req3 & !ipp_data_req3_dly & !ipp_data_req_maskout[3]; |
| 1223 | |
| 1224 | assign ipp_data_req_p = ipp_data_req0_p | ipp_data_req1_p | ipp_data_req2_p | ipp_data_req3_p; |
| 1225 | assign ipp_data_req_dly = ipp_data_req0_dly | ipp_data_req1_dly | ipp_data_req2_dly | ipp_data_req3_dly; |
| 1226 | |
| 1227 | |
| 1228 | assign muxed_ipp_data = {128{port_gnt_r2[0] & ipp_data_ack0}} & ipp_data0[127:0] | |
| 1229 | {128{port_gnt_r2[1] & ipp_data_ack1}} & ipp_data1[127:0] | |
| 1230 | {128{port_gnt_r2[2] & ipp_data_ack2}} & ipp_data2[127:0] | |
| 1231 | {128{port_gnt_r2[3] & ipp_data_ack3}} & ipp_data3[127:0] ; |
| 1232 | |
| 1233 | assign muxed_ipp_data_eop = port_gnt_r2[0] & ipp_data_ack0 & ipp_data0[129] | |
| 1234 | port_gnt_r2[1] & ipp_data_ack1 & ipp_data1[129] | |
| 1235 | port_gnt_r2[2] & ipp_data_ack2 & ipp_data2[129] | |
| 1236 | port_gnt_r2[3] & ipp_data_ack3 & ipp_data3[129]; |
| 1237 | |
| 1238 | assign muxed_ipp_data_ack = port_gnt_r2[0] & ipp_data_ack0 | |
| 1239 | port_gnt_r2[1] & ipp_data_ack1 | |
| 1240 | port_gnt_r2[2] & ipp_data_ack2 | |
| 1241 | port_gnt_r2[3] & ipp_data_ack3; |
| 1242 | |
| 1243 | assign ipp_data_req_in = dmc_ipp_dat_req0 & !ipp_data_req_maskout[0] | |
| 1244 | dmc_ipp_dat_req1 & !ipp_data_req_maskout[1] | |
| 1245 | dmc_ipp_dat_req2 & !ipp_data_req_maskout[2] | |
| 1246 | dmc_ipp_dat_req3 & !ipp_data_req_maskout[3]; |
| 1247 | |
| 1248 | assign ipp_fzcp_eop_in = !(|ipp_pkt_len_word_cnt) & ipp_data_req_in; |
| 1249 | |
| 1250 | assign ipp_next_eop = !(|ipp_pkt_len[13:0]); //at accept cycle |
| 1251 | |
| 1252 | always @ (posedge clk) |
| 1253 | if (reset) |
| 1254 | begin |
| 1255 | ipp_data_req_dly1 <= 1'b0; |
| 1256 | ipp_data_req_dly2 <= 1'b0; |
| 1257 | end |
| 1258 | else |
| 1259 | begin |
| 1260 | ipp_data_req_dly1 <= ipp_data_req_dly; |
| 1261 | ipp_data_req_dly2 <= ipp_data_req_dly1; |
| 1262 | end |
| 1263 | |
| 1264 | always @ (posedge clk) |
| 1265 | if (reset) |
| 1266 | begin |
| 1267 | ipp_fzcp_eop_tmp <= 1'b0; |
| 1268 | ipp_fzcp_eop_tmp1 <= 1'b0; |
| 1269 | ipp_fzcp_eop_tmp2 <= 1'b0; |
| 1270 | ipp_fzcp_eop <= 1'b0; |
| 1271 | end |
| 1272 | else |
| 1273 | begin |
| 1274 | ipp_fzcp_eop_tmp <= ipp_fzcp_eop_in; |
| 1275 | ipp_fzcp_eop_tmp1 <= ipp_fzcp_eop_tmp; |
| 1276 | ipp_fzcp_eop_tmp2 <= ipp_fzcp_eop_tmp1; |
| 1277 | ipp_fzcp_eop <= ipp_fzcp_eop_tmp2; |
| 1278 | end |
| 1279 | |
| 1280 | /**************************************************************/ |
| 1281 | //rdmc req counter in 16byte, this is used to generate pkt done |
| 1282 | /**************************************************************/ |
| 1283 | assign pkt_len_left_over = |pkt_trans_len_r[3:0]; |
| 1284 | assign pkt_len_word_cnt_tmp = pkt_len_left_over ? pkt_trans_len_r[13:4] : (pkt_trans_len_r[13:4] - 10'd1); |
| 1285 | assign pkt_req_cnt_done_tmp = (data_req_cnt == pkt_len_word_cnt) & rdmc_wr_data_req; |
| 1286 | |
| 1287 | assign pkt_req_cnt_e_done_mod = pkt_req_cnt_e_done_r & jmb_wr_cycle_sm; |
| 1288 | |
| 1289 | always @ (posedge clk) |
| 1290 | if (reset) |
| 1291 | pkt_len_word_cnt <= 10'd0; |
| 1292 | else if (rdmc_wr_req_accept_all) |
| 1293 | pkt_len_word_cnt <= pkt_len_word_cnt_tmp; |
| 1294 | else |
| 1295 | pkt_len_word_cnt <= pkt_len_word_cnt; |
| 1296 | |
| 1297 | always @ (posedge clk) |
| 1298 | if (reset) |
| 1299 | data_req_cnt <= 10'd0; |
| 1300 | else if (pkt_req_cnt_done_tmp) |
| 1301 | data_req_cnt <= 10'd0; |
| 1302 | else if (rdmc_wr_data_req) |
| 1303 | data_req_cnt <= data_req_cnt + 10'd1; |
| 1304 | else |
| 1305 | data_req_cnt <= data_req_cnt; |
| 1306 | |
| 1307 | always @ (posedge clk) |
| 1308 | if (reset) |
| 1309 | begin |
| 1310 | pkt_req_cnt_pre_done <= 1'b0; |
| 1311 | pkt_req_cnt_done <= 1'b0; |
| 1312 | pkt_req_cnt_done_r <= 1'b0; |
| 1313 | pkt_req_cnt_done_r1 <= 1'b0; |
| 1314 | pkt_req_cnt_done_r2 <= 1'b0; |
| 1315 | pkt_req_cnt_e_done_r <= 1'b0; |
| 1316 | end |
| 1317 | else |
| 1318 | begin |
| 1319 | pkt_req_cnt_pre_done <= pkt_req_cnt_done_tmp; |
| 1320 | pkt_req_cnt_done <= pkt_req_cnt_pre_done; |
| 1321 | pkt_req_cnt_done_r <= pkt_req_cnt_done; |
| 1322 | pkt_req_cnt_done_r1 <= pkt_req_cnt_done_r; |
| 1323 | pkt_req_cnt_done_r2 <= pkt_req_cnt_done_r1; |
| 1324 | pkt_req_cnt_e_done_r <= pkt_req_cnt_done_tmp; //same as pkt_req_cnt_pre_done after added 2 cycles delay of ipp ack |
| 1325 | end |
| 1326 | |
| 1327 | always @ (posedge clk) |
| 1328 | if (reset) |
| 1329 | wr_len_last_bits <= 4'b0; |
| 1330 | else if (rdmc_wr_req_accept_all) |
| 1331 | wr_len_last_bits <= pkt_trans_len_r[3:0]; |
| 1332 | else |
| 1333 | wr_len_last_bits <= wr_len_last_bits; |
| 1334 | |
| 1335 | always @ (posedge clk) |
| 1336 | if (reset) |
| 1337 | wr_len_last_bits_r <= 4'b0; |
| 1338 | else if (ipp_data_req_p_r2) |
| 1339 | wr_len_last_bits_r <= wr_len_last_bits[3:0]; |
| 1340 | else if (rdmc_wr_req_accept_data) |
| 1341 | wr_len_last_bits_r <= pkt_trans_len_r[3:0]; //for jumbo pkt and zcp pkt |
| 1342 | else |
| 1343 | wr_len_last_bits_r <= wr_len_last_bits_r; |
| 1344 | |
| 1345 | |
| 1346 | always @ (wr_len_last_bits_r) |
| 1347 | case (wr_len_last_bits_r) //synopsys parallel_case full_case |
| 1348 | |
| 1349 | 4'd0: wr_data_byte_dec = 16'b1111_1111_1111_1111; |
| 1350 | 4'd1: wr_data_byte_dec = 16'b0000_0000_0000_0001; |
| 1351 | 4'd2: wr_data_byte_dec = 16'b0000_0000_0000_0011; |
| 1352 | 4'd3: wr_data_byte_dec = 16'b0000_0000_0000_0111; |
| 1353 | 4'd4: wr_data_byte_dec = 16'b0000_0000_0000_1111; |
| 1354 | 4'd5: wr_data_byte_dec = 16'b0000_0000_0001_1111; |
| 1355 | 4'd6: wr_data_byte_dec = 16'b0000_0000_0011_1111; |
| 1356 | 4'd7: wr_data_byte_dec = 16'b0000_0000_0111_1111; |
| 1357 | 4'd8: wr_data_byte_dec = 16'b0000_0000_1111_1111; |
| 1358 | 4'd9: wr_data_byte_dec = 16'b0000_0001_1111_1111; |
| 1359 | 4'd10: wr_data_byte_dec = 16'b0000_0011_1111_1111; |
| 1360 | 4'd11: wr_data_byte_dec = 16'b0000_0111_1111_1111; |
| 1361 | 4'd12: wr_data_byte_dec = 16'b0000_1111_1111_1111; |
| 1362 | 4'd13: wr_data_byte_dec = 16'b0001_1111_1111_1111; |
| 1363 | 4'd14: wr_data_byte_dec = 16'b0011_1111_1111_1111; |
| 1364 | 4'd15: wr_data_byte_dec = 16'b0111_1111_1111_1111; |
| 1365 | default:wr_data_byte_dec = 16'b0; |
| 1366 | |
| 1367 | endcase |
| 1368 | |
| 1369 | assign wr_data_byte_en = rdmc_wr_data_comp_sm ? wr_data_byte_dec : 16'hffff; |
| 1370 | |
| 1371 | /************************************/ |
| 1372 | //Packet Alignement |
| 1373 | /************************************/ |
| 1374 | assign next_data_offset_tmp1 = (~ipp_pkt_len[3:0]) + 4'd1; |
| 1375 | assign next_data_offset_tmp2 = next_data_offset_reg - ipp_pkt_len[3:0]; |
| 1376 | assign next_data_offset_tmp = zcp_has_ipp_data_req ? next_data_offset_tmp1 : next_data_offset_tmp2; |
| 1377 | |
| 1378 | always @ (posedge clk) |
| 1379 | if (reset) |
| 1380 | next_data_offset_reg <= 4'b0; |
| 1381 | else if (rdmc_wr_req_accept_all) |
| 1382 | next_data_offset_reg <= next_data_offset_tmp; |
| 1383 | else |
| 1384 | next_data_offset_reg <= next_data_offset_reg; |
| 1385 | |
| 1386 | always @ (posedge clk) |
| 1387 | if (reset) |
| 1388 | data_offset_reg <= 4'd0; |
| 1389 | else if (offset_reg_en & (offset_sel == 2'b00)) |
| 1390 | data_offset_reg <= 4'd2; |
| 1391 | else if (offset_reg_en) |
| 1392 | data_offset_reg <= next_data_offset_reg; |
| 1393 | else |
| 1394 | data_offset_reg <= data_offset_reg; |
| 1395 | |
| 1396 | |
| 1397 | always @ (data_offset_reg or data_save_reg) |
| 1398 | case (data_offset_reg) //synopsys parallel_case full_case |
| 1399 | |
| 1400 | 4'd0: save_reg_trans = data_save_reg[127:0]; |
| 1401 | 4'd1: save_reg_trans = {data_save_reg[7:0], 120'b0}; |
| 1402 | 4'd2: save_reg_trans = {data_save_reg[15:0], 112'b0}; |
| 1403 | 4'd3: save_reg_trans = {data_save_reg[23:0], 104'b0}; |
| 1404 | 4'd4: save_reg_trans = {data_save_reg[31:0], 96'b0}; |
| 1405 | 4'd5: save_reg_trans = {data_save_reg[39:0], 88'b0}; |
| 1406 | 4'd6: save_reg_trans = {data_save_reg[47:0], 80'b0}; |
| 1407 | 4'd7: save_reg_trans = {data_save_reg[55:0], 72'b0}; |
| 1408 | 4'd8: save_reg_trans = {data_save_reg[63:0], 64'b0}; |
| 1409 | 4'd9: save_reg_trans = {data_save_reg[71:0], 56'b0}; |
| 1410 | 4'd10: save_reg_trans = {data_save_reg[79:0], 48'b0}; |
| 1411 | 4'd11: save_reg_trans = {data_save_reg[87:0], 40'b0}; |
| 1412 | 4'd12: save_reg_trans = {data_save_reg[95:0], 32'b0}; |
| 1413 | 4'd13: save_reg_trans = {data_save_reg[103:0], 24'b0}; |
| 1414 | 4'd14: save_reg_trans = {data_save_reg[111:0], 16'b0}; |
| 1415 | 4'd15: save_reg_trans = {data_save_reg[119:0], 8'b0}; |
| 1416 | |
| 1417 | endcase |
| 1418 | |
| 1419 | always @ (posedge clk) |
| 1420 | if (reset) |
| 1421 | date_save_reg_trans <= 128'b0; |
| 1422 | else |
| 1423 | date_save_reg_trans <= save_reg_trans; |
| 1424 | |
| 1425 | wire[119:0] data_last_save = muxed_ipp_data_ack ? muxed_ipp_data[127:8] : date_save_reg_trans[127:8]; |
| 1426 | wire[3:0] data_offset_in = offset_reg_en ? next_data_offset_reg[3:0] : data_offset_reg[3:0]; |
| 1427 | |
| 1428 | always @ (data_offset_in[3:0] or data_last_save) |
| 1429 | case (data_offset_in[3:0]) //synopsys parallel_case full_case |
| 1430 | |
| 1431 | 4'd0: data_save_reg_tmp = 128'b0; |
| 1432 | 4'd1: data_save_reg_tmp = {120'b0, data_last_save[119:112]}; |
| 1433 | 4'd2: data_save_reg_tmp = {112'b0, data_last_save[119:104]}; |
| 1434 | 4'd3: data_save_reg_tmp = {104'b0, data_last_save[119:96]}; |
| 1435 | 4'd4: data_save_reg_tmp = {96'b0, data_last_save[119:88]}; |
| 1436 | 4'd5: data_save_reg_tmp = {88'b0, data_last_save[119:80]}; |
| 1437 | 4'd6: data_save_reg_tmp = {80'b0, data_last_save[119:72]}; |
| 1438 | 4'd7: data_save_reg_tmp = {72'b0, data_last_save[119:64]}; |
| 1439 | 4'd8: data_save_reg_tmp = {64'b0, data_last_save[119:56]}; |
| 1440 | 4'd9: data_save_reg_tmp = {56'b0, data_last_save[119:48]}; |
| 1441 | 4'd10: data_save_reg_tmp = {48'b0, data_last_save[119:40]}; |
| 1442 | 4'd11: data_save_reg_tmp = {40'b0, data_last_save[119:32]}; |
| 1443 | 4'd12: data_save_reg_tmp = {32'b0, data_last_save[119:24]}; |
| 1444 | 4'd13: data_save_reg_tmp = {24'b0, data_last_save[119:16]}; |
| 1445 | 4'd14: data_save_reg_tmp = {16'b0, data_last_save[119:8]}; |
| 1446 | 4'd15: data_save_reg_tmp = {8'b0, data_last_save[119:0]}; |
| 1447 | endcase |
| 1448 | |
| 1449 | |
| 1450 | always @ (posedge clk) |
| 1451 | if (reset) |
| 1452 | data_save_reg <= 128'b0; |
| 1453 | else if (rdmc_wr_data_valid_sm) |
| 1454 | data_save_reg <= data_save_reg_tmp; |
| 1455 | else |
| 1456 | data_save_reg <= data_save_reg; |
| 1457 | |
| 1458 | |
| 1459 | always @ (data_offset_reg or muxed_ipp_data or data_save_reg) |
| 1460 | case (data_offset_reg) //synopsys parallel_case full_case |
| 1461 | |
| 1462 | 4'd0: rdmc_wr_data_tmp = {muxed_ipp_data[127:0]}; |
| 1463 | 4'd1: rdmc_wr_data_tmp = {muxed_ipp_data[119:0], data_save_reg[7:0]}; |
| 1464 | 4'd2: rdmc_wr_data_tmp = {muxed_ipp_data[111:0], data_save_reg[15:0]}; |
| 1465 | 4'd3: rdmc_wr_data_tmp = {muxed_ipp_data[103:0], data_save_reg[23:0]}; |
| 1466 | 4'd4: rdmc_wr_data_tmp = {muxed_ipp_data[95:0], data_save_reg[31:0]}; |
| 1467 | 4'd5: rdmc_wr_data_tmp = {muxed_ipp_data[87:0], data_save_reg[39:0]}; |
| 1468 | 4'd6: rdmc_wr_data_tmp = {muxed_ipp_data[79:0], data_save_reg[47:0]}; |
| 1469 | 4'd7: rdmc_wr_data_tmp = {muxed_ipp_data[71:0], data_save_reg[55:0]}; |
| 1470 | 4'd8: rdmc_wr_data_tmp = {muxed_ipp_data[63:0], data_save_reg[63:0]}; |
| 1471 | 4'd9: rdmc_wr_data_tmp = {muxed_ipp_data[55:0], data_save_reg[71:0]}; |
| 1472 | 4'd10: rdmc_wr_data_tmp = {muxed_ipp_data[47:0], data_save_reg[79:0]}; |
| 1473 | 4'd11: rdmc_wr_data_tmp = {muxed_ipp_data[39:0], data_save_reg[87:0]}; |
| 1474 | 4'd12: rdmc_wr_data_tmp = {muxed_ipp_data[31:0], data_save_reg[95:0]}; |
| 1475 | 4'd13: rdmc_wr_data_tmp = {muxed_ipp_data[23:0], data_save_reg[103:0]}; |
| 1476 | 4'd14: rdmc_wr_data_tmp = {muxed_ipp_data[15:0], data_save_reg[111:0]}; |
| 1477 | 4'd15: rdmc_wr_data_tmp = {muxed_ipp_data[7:0], data_save_reg[119:0]}; |
| 1478 | |
| 1479 | endcase |
| 1480 | |
| 1481 | |
| 1482 | wire[127:0] hdr_data1 = {muxed_ipp_data[111:0], zcp_data_reg0_byte1, zcp_data_reg0_byte0}; |
| 1483 | wire[127:0] hdr_data2 = {zcp_data_reg1_byte1, zcp_data_reg1_byte0, zcp_data_reg0_byte15, zcp_data_reg0_byte14, |
| 1484 | zcp_data_reg0_byte13, zcp_data_reg0_byte12, zcp_data_reg0_byte11, zcp_data_reg0_byte10, |
| 1485 | zcp_data_reg0_byte9, zcp_data_reg0_byte8, zcp_data_reg0_byte7, zcp_data_reg0_byte6, |
| 1486 | zcp_data_reg0_byte5, zcp_data_reg0_byte4, zcp_data_reg0_byte3, zcp_data_reg0_byte2}; |
| 1487 | |
| 1488 | wire[127:0] rdmc_wr_data_in = (rdmc_wr_data_sel == 2'b00) ? hdr_data2 : |
| 1489 | (rdmc_wr_data_sel == 2'b01) ? hdr_data1 : rdmc_wr_data_tmp; |
| 1490 | |
| 1491 | |
| 1492 | /****************************/ |
| 1493 | //ECC ERROR |
| 1494 | /****************************/ |
| 1495 | wire[3:0] ipp_data_err = {ipp_data_err3, ipp_data_err2, ipp_data_err1, ipp_data_err0}; |
| 1496 | wire[3:0] zcp_data_err = {zcp_data_err3, zcp_data_err2, zcp_data_err1, zcp_data_err0}; |
| 1497 | |
| 1498 | wire[3:0] ipp_ack_array= {ipp_data_ack3, ipp_data_ack2, ipp_data_ack1, ipp_data_ack0}; |
| 1499 | wire[3:0] zcp_ack_array= {zcp_data_ack3, zcp_data_ack2, zcp_data_ack1, zcp_data_ack0}; |
| 1500 | |
| 1501 | wire muxed_ipp_ctrl_err = |(port_gnt & ipp_ack_array & ipp_data_err); //first read |
| 1502 | wire muxed_zcp_data_err = |(port_gnt_r & zcp_ack_array & zcp_data_err); //control phase |
| 1503 | assign muxed_ipp_data_err = |(port_gnt_r2 & ipp_ack_array & ipp_data_err); //data phase |
| 1504 | |
| 1505 | always @ (posedge clk) |
| 1506 | if (reset) |
| 1507 | wait_drop_pkt_eop <= 1'b0; |
| 1508 | else if (drop_pkt_done) |
| 1509 | wait_drop_pkt_eop <= 1'b1; |
| 1510 | else if (rdmc_cal_eop_r) |
| 1511 | wait_drop_pkt_eop <= 1'b0; |
| 1512 | else |
| 1513 | wait_drop_pkt_eop <= wait_drop_pkt_eop; |
| 1514 | |
| 1515 | always @ (posedge clk) |
| 1516 | if (reset) |
| 1517 | muxed_data_err <= 1'b0; |
| 1518 | else if (muxed_ipp_ctrl_err) |
| 1519 | muxed_data_err <= 1'b1; |
| 1520 | else if (rdmc_wr_req_accept_hdr | wait_drop_pkt_eop) |
| 1521 | muxed_data_err <= 1'b0; |
| 1522 | else |
| 1523 | muxed_data_err <= muxed_data_err; |
| 1524 | |
| 1525 | always @ (posedge clk) |
| 1526 | if (reset) |
| 1527 | muxed_data_err_r1 <= 1'b0; |
| 1528 | else if (rdmc_wr_req_accept_hdr & muxed_data_err | muxed_zcp_data_err | (|port_zcp_eop_err)) |
| 1529 | muxed_data_err_r1 <= 1'b1; |
| 1530 | else if (ipp_data_req_p_r2 | wait_drop_pkt_eop) |
| 1531 | muxed_data_err_r1 <= 1'b0; |
| 1532 | else |
| 1533 | muxed_data_err_r1 <= muxed_data_err_r1; |
| 1534 | |
| 1535 | |
| 1536 | always @ (posedge clk) |
| 1537 | if (reset) |
| 1538 | muxed_data_err_r2 <= 1'b0; |
| 1539 | else if (ipp_data_req_p_r1) |
| 1540 | muxed_data_err_r2 <= 1'b0; |
| 1541 | else if (muxed_ipp_data_err & !wr_idle_state | ipp_data_req_p_r2 & muxed_data_err_r1 | (|port_ipp_eop_err)) |
| 1542 | muxed_data_err_r2 <= 1'b1; |
| 1543 | else if (rdmc_wr_last_comp | wait_drop_pkt_eop) |
| 1544 | muxed_data_err_r2 <= 1'b0; |
| 1545 | else |
| 1546 | muxed_data_err_r2 <= muxed_data_err_r2; |
| 1547 | |
| 1548 | |
| 1549 | /**********************************************/ |
| 1550 | //calculate eop & sop |
| 1551 | /**********************************************/ |
| 1552 | wire muxed_ipp_data_req = dmc_ipp_dat_req0 & (port_gnt_r1[0] | drop_pkt_en_dly[0]) | |
| 1553 | dmc_ipp_dat_req1 & (port_gnt_r1[1] | drop_pkt_en_dly[1]) | |
| 1554 | dmc_ipp_dat_req2 & (port_gnt_r1[2] | drop_pkt_en_dly[2]) | |
| 1555 | dmc_ipp_dat_req3 & (port_gnt_r1[3] | drop_pkt_en_dly[3]); |
| 1556 | wire rdmc_eop_cnt_done = muxed_ipp_data_req & (rdmc_eop_cnt == 10'b0); |
| 1557 | wire rdmc_eop_for_padding = rdmc_eop_cnt_done; |
| 1558 | |
| 1559 | always @ (posedge clk) |
| 1560 | if (reset) |
| 1561 | rdmc_eop_cnt <= 10'b11_1111_1111; |
| 1562 | else if (rdmc_wr_req_accept_hdr | drop_pkt_en_sm) |
| 1563 | rdmc_eop_cnt <= drop_pkt_word_cnt_tmp[9:0]; |
| 1564 | else if (muxed_ipp_data_req & (|rdmc_eop_cnt)) |
| 1565 | rdmc_eop_cnt <= rdmc_eop_cnt - 10'd1; |
| 1566 | else if (rdmc_eop_cnt_done) |
| 1567 | rdmc_eop_cnt <= 10'b11_1111_1111; |
| 1568 | else |
| 1569 | rdmc_eop_cnt <= rdmc_eop_cnt; |
| 1570 | |
| 1571 | always @ (posedge clk) |
| 1572 | if (reset) |
| 1573 | begin |
| 1574 | rdmc_cal_eop_tmp <= 1'b0; |
| 1575 | rdmc_cal_eop_tmp1 <= 1'b0; |
| 1576 | rdmc_cal_eop <= 1'b0; |
| 1577 | rdmc_cal_eop_r <= 1'b0; |
| 1578 | end |
| 1579 | else |
| 1580 | begin |
| 1581 | rdmc_cal_eop_tmp <= rdmc_eop_cnt_done; |
| 1582 | rdmc_cal_eop_tmp1 <= rdmc_cal_eop_tmp; |
| 1583 | rdmc_cal_eop <= rdmc_cal_eop_tmp1; |
| 1584 | rdmc_cal_eop_r <= rdmc_cal_eop; |
| 1585 | end |
| 1586 | |
| 1587 | |
| 1588 | always @ (posedge clk) |
| 1589 | if (reset) |
| 1590 | muxed_orig_zcopy_mode_r1 <= 1'b0; |
| 1591 | else if (zcp_req_cnt_done) |
| 1592 | muxed_orig_zcopy_mode_r1 <= muxed_orig_zcopy_mode_r; |
| 1593 | else |
| 1594 | muxed_orig_zcopy_mode_r1 <= muxed_orig_zcopy_mode_r1; |
| 1595 | |
| 1596 | wire rdmc_cal_zcp_eop = muxed_orig_zcopy_mode_r1 ? zcp_data_ack & (zcp_ack_cnt == 2'b11) : |
| 1597 | zcp_data_ack & (zcp_ack_cnt == 2'b01); |
| 1598 | |
| 1599 | /*******************/ |
| 1600 | //Port Error |
| 1601 | /*******************/ |
| 1602 | always @ (posedge clk) |
| 1603 | if (reset) |
| 1604 | zcp_second_data_ack_dly <= 1'b0; |
| 1605 | else if (zcp_data_ack & (zcp_ack_cnt == 2'b01)) |
| 1606 | zcp_second_data_ack_dly <= 1'b1; |
| 1607 | else |
| 1608 | zcp_second_data_ack_dly <= 1'b0; |
| 1609 | |
| 1610 | wire pkt_id_err = !(zcp_pkt_id == muxed_ipp_pkt_id_r) & zcp_second_data_ack_dly; |
| 1611 | wire ipp_eop_err = !(rdmc_cal_eop_r == muxed_ipp_data_eop); |
| 1612 | wire zcp_eop_err = !(rdmc_cal_zcp_eop == muxed_zcp_data_eop); |
| 1613 | |
| 1614 | assign port_ipp_eop_err = {4{ipp_eop_err}} & port_gnt_r2; |
| 1615 | assign port_zcp_eop_err = {4{zcp_eop_err}} & port_gnt_r; |
| 1616 | assign port_err_event = {pkt_id_err, port_zcp_eop_err, port_ipp_eop_err}; |
| 1617 | |
| 1618 | |
| 1619 | /**********************/ |
| 1620 | //SOP calculation |
| 1621 | /**********************/ |
| 1622 | always @ (posedge clk) |
| 1623 | if (reset) |
| 1624 | zcp_sop_reg0 <= 1'b1; |
| 1625 | else if (stage0_en_r & port_gnt[0]) |
| 1626 | zcp_sop_reg0 <= 1'b0; |
| 1627 | else if (rdmc_cal_zcp_eop & port_gnt_r[0]) |
| 1628 | zcp_sop_reg0 <= 1'b1; |
| 1629 | else |
| 1630 | zcp_sop_reg0 <= zcp_sop_reg0; |
| 1631 | |
| 1632 | |
| 1633 | always @ (posedge clk) |
| 1634 | if (reset) |
| 1635 | zcp_sop_reg1 <= 1'b1; |
| 1636 | else if (stage0_en_r & port_gnt[1]) |
| 1637 | zcp_sop_reg1 <= 1'b0; |
| 1638 | else if (rdmc_cal_zcp_eop & port_gnt_r[1]) |
| 1639 | zcp_sop_reg1 <= 1'b1; |
| 1640 | else |
| 1641 | zcp_sop_reg1 <= zcp_sop_reg1; |
| 1642 | |
| 1643 | always @ (posedge clk) |
| 1644 | if (reset) |
| 1645 | zcp_sop_reg2 <= 1'b1; |
| 1646 | else if (stage0_en_r & port_gnt[2]) |
| 1647 | zcp_sop_reg2 <= 1'b0; |
| 1648 | else if (rdmc_cal_zcp_eop & port_gnt_r[2]) |
| 1649 | zcp_sop_reg2 <= 1'b1; |
| 1650 | else |
| 1651 | zcp_sop_reg2 <= zcp_sop_reg2; |
| 1652 | |
| 1653 | always @ (posedge clk) |
| 1654 | if (reset) |
| 1655 | zcp_sop_reg3 <= 1'b1; |
| 1656 | else if (stage0_en_r & port_gnt[3]) |
| 1657 | zcp_sop_reg3 <= 1'b0; |
| 1658 | else if (rdmc_cal_zcp_eop & port_gnt_r[3]) |
| 1659 | zcp_sop_reg3 <= 1'b1; |
| 1660 | else |
| 1661 | zcp_sop_reg3 <= zcp_sop_reg3; |
| 1662 | |
| 1663 | |
| 1664 | always @ (posedge clk) |
| 1665 | if (reset) |
| 1666 | ipp_sop_reg0 <= 1'b1; |
| 1667 | else if (stage0_en_r & port_gnt[0]) |
| 1668 | ipp_sop_reg0 <= 1'b0; |
| 1669 | else if (rdmc_cal_eop_r & port_gnt_r2[0]) |
| 1670 | ipp_sop_reg0 <= 1'b1; |
| 1671 | else |
| 1672 | ipp_sop_reg0 <= ipp_sop_reg0; |
| 1673 | |
| 1674 | always @ (posedge clk) |
| 1675 | if (reset) |
| 1676 | ipp_sop_reg1 <= 1'b1; |
| 1677 | else if (stage0_en_r & port_gnt[1]) |
| 1678 | ipp_sop_reg1 <= 1'b0; |
| 1679 | else if (rdmc_cal_eop_r & port_gnt_r2[1]) |
| 1680 | ipp_sop_reg1 <= 1'b1; |
| 1681 | else |
| 1682 | ipp_sop_reg1 <= ipp_sop_reg1; |
| 1683 | |
| 1684 | always @ (posedge clk) |
| 1685 | if (reset) |
| 1686 | ipp_sop_reg2 <= 1'b1; |
| 1687 | else if (stage0_en_r & port_gnt[2]) |
| 1688 | ipp_sop_reg2 <= 1'b0; |
| 1689 | else if (rdmc_cal_eop_r & port_gnt_r2[2]) |
| 1690 | ipp_sop_reg2 <= 1'b1; |
| 1691 | else |
| 1692 | ipp_sop_reg2 <= ipp_sop_reg2; |
| 1693 | |
| 1694 | always @ (posedge clk) |
| 1695 | if (reset) |
| 1696 | ipp_sop_reg3 <= 1'b1; |
| 1697 | else if (stage0_en_r & port_gnt[3]) |
| 1698 | ipp_sop_reg3 <= 1'b0; |
| 1699 | else if (rdmc_cal_eop_r & port_gnt_r2[3]) |
| 1700 | ipp_sop_reg3 <= 1'b1; |
| 1701 | else |
| 1702 | ipp_sop_reg3 <= ipp_sop_reg3; |
| 1703 | |
| 1704 | |
| 1705 | /****************************/ |
| 1706 | //rdmc-meta0 write interface |
| 1707 | /****************************/ |
| 1708 | wire[3:0] rdmc_meta0_wr_status = 4'b0; |
| 1709 | |
| 1710 | always @ (posedge clk) |
| 1711 | if (reset) |
| 1712 | rdmc_meta0_wr_data <= 128'b0; |
| 1713 | else |
| 1714 | rdmc_meta0_wr_data <= rdmc_wr_data_in; |
| 1715 | |
| 1716 | always @ (posedge clk) |
| 1717 | if (reset) |
| 1718 | rdmc_meta0_wr_data_valid <= 1'b0; |
| 1719 | else |
| 1720 | rdmc_meta0_wr_data_valid <= rdmc_wr_data_valid_sm; |
| 1721 | |
| 1722 | always @ (posedge clk) |
| 1723 | if (reset) |
| 1724 | rdmc_meta0_wr_transfer_comp <= 1'b0; |
| 1725 | else |
| 1726 | rdmc_meta0_wr_transfer_comp <= rdmc_wr_data_comp_sm; |
| 1727 | |
| 1728 | always @ (posedge clk) |
| 1729 | if (reset) |
| 1730 | rdmc_meta0_wr_transfer_comp_int <= 1'b0; //for output timing |
| 1731 | else |
| 1732 | rdmc_meta0_wr_transfer_comp_int <= rdmc_wr_data_comp_sm; |
| 1733 | |
| 1734 | |
| 1735 | always @ (posedge clk) |
| 1736 | if (reset) |
| 1737 | rdmc_meta0_wr_req_byteenable <= 16'b0; |
| 1738 | else if (rdmc_wr_data_valid_sm) |
| 1739 | rdmc_meta0_wr_req_byteenable <= wr_data_byte_en; |
| 1740 | else |
| 1741 | rdmc_meta0_wr_req_byteenable <= 16'b0; |
| 1742 | |
| 1743 | always @ (posedge clk) |
| 1744 | if (reset) |
| 1745 | rdmc_wr_last_comp <= 1'b0; |
| 1746 | else |
| 1747 | rdmc_wr_last_comp <= rdmc_wr_last_comp_sm; |
| 1748 | |
| 1749 | |
| 1750 | niu_rdmc_wr_dp_sm niu_rdmc_wr_dp_sm_inst0 ( |
| 1751 | .clk (clk), |
| 1752 | .reset (reset), |
| 1753 | .full_hdr_r1 (full_hdr_r1), |
| 1754 | .ipp_data_req_dly2 (ipp_data_req_dly2), |
| 1755 | .rdmc_wr_req_accept_hdr (rdmc_wr_req_accept_hdr), |
| 1756 | .rdmc_wr_req_accept_zcp (rdmc_wr_req_accept_zcp), |
| 1757 | .muxed_ipp_data_ack (muxed_ipp_data_ack), |
| 1758 | .rdmc_cal_eop_r (rdmc_cal_eop_r), |
| 1759 | .ipp_next_eop (ipp_next_eop), |
| 1760 | .ipp_fzcp_eop (ipp_fzcp_eop), |
| 1761 | .pkt_req_cnt_done (pkt_req_cnt_done), |
| 1762 | .pkt_req_cnt_done_r (pkt_req_cnt_done_r), |
| 1763 | .pkt_req_cnt_done_r1 (pkt_req_cnt_done_r1), |
| 1764 | .pkt_req_cnt_done_r2 (pkt_req_cnt_done_r2), |
| 1765 | .jmb_pkt_type (jmb_pkt_type), |
| 1766 | .zcopy_mode (zcopy_mode), |
| 1767 | .zcp_wr_type (zcp_wr_type), |
| 1768 | |
| 1769 | .offset_reg_en (offset_reg_en), |
| 1770 | .offset_sel (offset_sel), |
| 1771 | .wr_idle_state (wr_idle_state), |
| 1772 | .rdmc_wr_data_sel (rdmc_wr_data_sel), |
| 1773 | .rdmc_wr_data_valid_sm (rdmc_wr_data_valid_sm), |
| 1774 | .rdmc_wr_data_comp_sm (rdmc_wr_data_comp_sm), |
| 1775 | .rdmc_wr_last_comp_sm (rdmc_wr_last_comp_sm), |
| 1776 | .jmb_wr_cycle_sm (jmb_wr_cycle_sm), |
| 1777 | .wr_dp_sm_state (wr_dp_sm_state) |
| 1778 | |
| 1779 | ); |
| 1780 | |
| 1781 | endmodule |
| 1782 | |
| 1783 | |
| 1784 | |
| 1785 | |
| 1786 | |
| 1787 | |
| 1788 | |
| 1789 | |