| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_smx_regfl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | module niu_smx_regfl( |
| 37 | clk, |
| 38 | reset_l, |
| 39 | wr, |
| 40 | addr_wr, |
| 41 | data_wr, |
| 42 | rd, |
| 43 | addr_rd, |
| 44 | data_rd |
| 45 | ); |
| 46 | |
| 47 | // synopsys template |
| 48 | |
| 49 | parameter DATA_WIDTH= 100; |
| 50 | parameter ADDR_WIDTH= 5; |
| 51 | parameter ENTRY_SIZE= 1<<ADDR_WIDTH; |
| 52 | input reset_l; |
| 53 | input clk; |
| 54 | input wr; |
| 55 | input [ADDR_WIDTH-1:0] addr_wr; |
| 56 | input [ADDR_WIDTH-1:0] addr_rd; |
| 57 | input rd; |
| 58 | input [DATA_WIDTH-1:0] data_wr; |
| 59 | output [DATA_WIDTH-1:0] data_rd; |
| 60 | |
| 61 | reg [DATA_WIDTH-1:0] data_rd; |
| 62 | reg [DATA_WIDTH-1:0] data[0:ENTRY_SIZE-1]; |
| 63 | integer i; |
| 64 | |
| 65 | always @(posedge clk) begin |
| 66 | if(!reset_l) begin |
| 67 | for(i=0; i<ENTRY_SIZE; i=i+1) |
| 68 | data[i]<= `SMX_PD {DATA_WIDTH{1'b0}}; |
| 69 | end |
| 70 | else begin |
| 71 | if(wr)begin |
| 72 | data[addr_wr]<= `SMX_PD data_wr; |
| 73 | end |
| 74 | end |
| 75 | end |
| 76 | |
| 77 | always @(posedge clk) begin |
| 78 | if(rd) begin |
| 79 | data_rd<= `SMX_PD data[addr_rd]; |
| 80 | end |
| 81 | end |
| 82 | |
| 83 | endmodule |
| 84 | |
| 85 | |
| 86 | /* |
| 87 | // not use; to be removed |
| 88 | module niu_smx_regfl_nfo( // non flop out |
| 89 | clk, |
| 90 | reset_l, |
| 91 | wr, |
| 92 | addr_wr, |
| 93 | data_wr, |
| 94 | addr_rd, |
| 95 | data_rd |
| 96 | ); |
| 97 | |
| 98 | |
| 99 | parameter DATA_WIDTH= 100; |
| 100 | parameter ADDR_WIDTH= 5; |
| 101 | parameter ENTRY_SIZE= 1<<ADDR_WIDTH; |
| 102 | input reset_l; |
| 103 | input clk; |
| 104 | input wr; |
| 105 | input [ADDR_WIDTH-1:0] addr_wr; |
| 106 | input [ADDR_WIDTH-1:0] addr_rd; |
| 107 | input [DATA_WIDTH-1:0] data_wr; |
| 108 | output [DATA_WIDTH-1:0] data_rd; |
| 109 | |
| 110 | reg [DATA_WIDTH-1:0] data[0:ENTRY_SIZE-1]; |
| 111 | integer i; |
| 112 | |
| 113 | always @(posedge clk) begin |
| 114 | if(!reset_l) begin |
| 115 | for(i=0; i<ENTRY_SIZE; i=i+1) |
| 116 | data[i]<= `SMX_PD {DATA_WIDTH{1'b0}}; |
| 117 | end |
| 118 | else begin |
| 119 | if(wr)begin |
| 120 | data[addr_wr]<= `SMX_PD data_wr; |
| 121 | end |
| 122 | end |
| 123 | end |
| 124 | |
| 125 | wire [DATA_WIDTH-1:0] data_rd_n= data[addr_rd]; |
| 126 | wire [DATA_WIDTH-1:0] data_rd= data_rd_n; |
| 127 | |
| 128 | endmodule |
| 129 | */ |
| 130 | |
| 131 | |