| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_tdmc_cachefetch.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | |
| 37 | `include "txc_defines.h" |
| 38 | `include "niu_dmc_reg_defines.h" |
| 39 | |
| 40 | module niu_tdmc_cachefetch ( /*AUTOARG*/ |
| 41 | // Outputs |
| 42 | choose_available_dmas, updateCacheContext, DMC_TxCache_SMX_Req, |
| 43 | DMC_TxCache_SMX_Req_Port_Num, DMC_TxCache_SMX_Req_Address, |
| 44 | DMA_UpdateAddress, DMC_TxCache_SMX_Req_Length, |
| 45 | tdmc_arb1_req_func_num, DMC_TxCache_SMX_Req_Cmd, |
| 46 | DMC_TxCache_SMX_Req_DMA_Num, LatchDMAPtrs, DMANumToReq, |
| 47 | NoOfCacheWritesDispatched, DMAs_AvailableFor_Fetch, |
| 48 | TxCacheFetchState, |
| 49 | // Inputs |
| 50 | SysClk, Reset_L, DMA0_AvailableFor_Fetch, DMA1_AvailableFor_Fetch, |
| 51 | DMA2_AvailableFor_Fetch, DMA3_AvailableFor_Fetch, |
| 52 | DMA4_AvailableFor_Fetch, DMA5_AvailableFor_Fetch, |
| 53 | DMA6_AvailableFor_Fetch, DMA7_AvailableFor_Fetch, |
| 54 | DMA8_AvailableFor_Fetch, DMA9_AvailableFor_Fetch, |
| 55 | DMA10_AvailableFor_Fetch, DMA11_AvailableFor_Fetch, |
| 56 | DMA12_AvailableFor_Fetch, DMA13_AvailableFor_Fetch, |
| 57 | DMA14_AvailableFor_Fetch, DMA15_AvailableFor_Fetch, |
| 58 | DMA16_AvailableFor_Fetch, DMA17_AvailableFor_Fetch, |
| 59 | DMA18_AvailableFor_Fetch, DMA19_AvailableFor_Fetch, |
| 60 | DMA20_AvailableFor_Fetch, DMA21_AvailableFor_Fetch, |
| 61 | DMA22_AvailableFor_Fetch, DMA23_AvailableFor_Fetch, |
| 62 | DMA0_ReqPending, DMA1_ReqPending, DMA2_ReqPending, |
| 63 | DMA3_ReqPending, DMA4_ReqPending, DMA5_ReqPending, |
| 64 | DMA6_ReqPending, DMA7_ReqPending, DMA8_ReqPending, |
| 65 | DMA9_ReqPending, DMA10_ReqPending, DMA11_ReqPending, |
| 66 | DMA12_ReqPending, DMA13_ReqPending, DMA14_ReqPending, |
| 67 | DMA15_ReqPending, DMA16_ReqPending, DMA17_ReqPending, |
| 68 | DMA18_ReqPending, DMA19_ReqPending, DMA20_ReqPending, |
| 69 | DMA21_ReqPending, DMA22_ReqPending, DMA23_ReqPending, ArbDone, |
| 70 | DMANumToReqArbOut, DMANumToUpdate, SMX_DMC_TxCache_Req_Ack, |
| 71 | NoOfFreeSpaceInCache, ShadowRingWrap, DMA_AddressToReq_ff, |
| 72 | dmc_txc_tx_addr_md, NoOfDescInMem, NoOfDescLeft, |
| 73 | dmc_txc_dma0_func_num, dmc_txc_dma1_func_num, |
| 74 | dmc_txc_dma2_func_num, dmc_txc_dma3_func_num, |
| 75 | dmc_txc_dma4_func_num, dmc_txc_dma5_func_num, |
| 76 | dmc_txc_dma6_func_num, dmc_txc_dma7_func_num, |
| 77 | dmc_txc_dma8_func_num, dmc_txc_dma9_func_num, |
| 78 | dmc_txc_dma10_func_num, dmc_txc_dma11_func_num, |
| 79 | dmc_txc_dma12_func_num, dmc_txc_dma13_func_num, |
| 80 | dmc_txc_dma14_func_num, dmc_txc_dma15_func_num, |
| 81 | dmc_txc_dma16_func_num, dmc_txc_dma17_func_num, |
| 82 | dmc_txc_dma18_func_num, dmc_txc_dma19_func_num, |
| 83 | dmc_txc_dma20_func_num, dmc_txc_dma21_func_num, |
| 84 | dmc_txc_dma22_func_num, dmc_txc_dma23_func_num |
| 85 | ); |
| 86 | |
| 87 | input SysClk; |
| 88 | input Reset_L; |
| 89 | |
| 90 | |
| 91 | input DMA0_AvailableFor_Fetch; |
| 92 | input DMA1_AvailableFor_Fetch; |
| 93 | input DMA2_AvailableFor_Fetch; |
| 94 | input DMA3_AvailableFor_Fetch; |
| 95 | input DMA4_AvailableFor_Fetch; |
| 96 | input DMA5_AvailableFor_Fetch; |
| 97 | input DMA6_AvailableFor_Fetch; |
| 98 | input DMA7_AvailableFor_Fetch; |
| 99 | input DMA8_AvailableFor_Fetch; |
| 100 | input DMA9_AvailableFor_Fetch; |
| 101 | input DMA10_AvailableFor_Fetch; |
| 102 | input DMA11_AvailableFor_Fetch; |
| 103 | input DMA12_AvailableFor_Fetch; |
| 104 | input DMA13_AvailableFor_Fetch; |
| 105 | input DMA14_AvailableFor_Fetch; |
| 106 | input DMA15_AvailableFor_Fetch; |
| 107 | input DMA16_AvailableFor_Fetch; |
| 108 | input DMA17_AvailableFor_Fetch; |
| 109 | input DMA18_AvailableFor_Fetch; |
| 110 | input DMA19_AvailableFor_Fetch; |
| 111 | input DMA20_AvailableFor_Fetch; |
| 112 | input DMA21_AvailableFor_Fetch; |
| 113 | input DMA22_AvailableFor_Fetch; |
| 114 | input DMA23_AvailableFor_Fetch; |
| 115 | |
| 116 | |
| 117 | input DMA0_ReqPending; |
| 118 | input DMA1_ReqPending; |
| 119 | input DMA2_ReqPending; |
| 120 | input DMA3_ReqPending; |
| 121 | input DMA4_ReqPending; |
| 122 | input DMA5_ReqPending; |
| 123 | input DMA6_ReqPending; |
| 124 | input DMA7_ReqPending; |
| 125 | input DMA8_ReqPending; |
| 126 | input DMA9_ReqPending; |
| 127 | input DMA10_ReqPending; |
| 128 | input DMA11_ReqPending; |
| 129 | input DMA12_ReqPending; |
| 130 | input DMA13_ReqPending; |
| 131 | input DMA14_ReqPending; |
| 132 | input DMA15_ReqPending; |
| 133 | input DMA16_ReqPending; |
| 134 | input DMA17_ReqPending; |
| 135 | input DMA18_ReqPending; |
| 136 | input DMA19_ReqPending; |
| 137 | input DMA20_ReqPending; |
| 138 | input DMA21_ReqPending; |
| 139 | input DMA22_ReqPending; |
| 140 | input DMA23_ReqPending; |
| 141 | |
| 142 | |
| 143 | |
| 144 | input ArbDone; |
| 145 | input [4:0] DMANumToReqArbOut; |
| 146 | input [31 :0] DMANumToUpdate; |
| 147 | input SMX_DMC_TxCache_Req_Ack; |
| 148 | |
| 149 | input [4:0] NoOfFreeSpaceInCache; |
| 150 | input ShadowRingWrap; |
| 151 | input [63:0] DMA_AddressToReq_ff; |
| 152 | input dmc_txc_tx_addr_md; |
| 153 | |
| 154 | input [`PTR_WIDTH - 1 :0] NoOfDescInMem; |
| 155 | input [`PTR_WIDTH - 1 :0] NoOfDescLeft; |
| 156 | |
| 157 | output choose_available_dmas; |
| 158 | output [`NO_OF_DMAS -1 :0] updateCacheContext; |
| 159 | output DMC_TxCache_SMX_Req; |
| 160 | output [1:0] DMC_TxCache_SMX_Req_Port_Num ; |
| 161 | output [63:0] DMC_TxCache_SMX_Req_Address; |
| 162 | output [43:0] DMA_UpdateAddress; |
| 163 | output [13:0] DMC_TxCache_SMX_Req_Length ; |
| 164 | output [1:0] tdmc_arb1_req_func_num; |
| 165 | output [7:0] DMC_TxCache_SMX_Req_Cmd; |
| 166 | output [4:0] DMC_TxCache_SMX_Req_DMA_Num ; |
| 167 | output LatchDMAPtrs; |
| 168 | output [4:0] DMANumToReq; |
| 169 | output [3:0] NoOfCacheWritesDispatched; |
| 170 | output [31:0] DMAs_AvailableFor_Fetch; |
| 171 | |
| 172 | |
| 173 | output [3:0] TxCacheFetchState; |
| 174 | |
| 175 | |
| 176 | // function numbers for requests to meta |
| 177 | |
| 178 | input [1:0] dmc_txc_dma0_func_num; |
| 179 | input [1:0] dmc_txc_dma1_func_num; |
| 180 | input [1:0] dmc_txc_dma2_func_num; |
| 181 | input [1:0] dmc_txc_dma3_func_num; |
| 182 | input [1:0] dmc_txc_dma4_func_num; |
| 183 | input [1:0] dmc_txc_dma5_func_num; |
| 184 | input [1:0] dmc_txc_dma6_func_num; |
| 185 | input [1:0] dmc_txc_dma7_func_num; |
| 186 | input [1:0] dmc_txc_dma8_func_num; |
| 187 | input [1:0] dmc_txc_dma9_func_num; |
| 188 | input [1:0] dmc_txc_dma10_func_num; |
| 189 | input [1:0] dmc_txc_dma11_func_num; |
| 190 | input [1:0] dmc_txc_dma12_func_num; |
| 191 | input [1:0] dmc_txc_dma13_func_num; |
| 192 | input [1:0] dmc_txc_dma14_func_num; |
| 193 | input [1:0] dmc_txc_dma15_func_num; |
| 194 | input [1:0] dmc_txc_dma16_func_num; |
| 195 | input [1:0] dmc_txc_dma17_func_num; |
| 196 | input [1:0] dmc_txc_dma18_func_num; |
| 197 | input [1:0] dmc_txc_dma19_func_num; |
| 198 | input [1:0] dmc_txc_dma20_func_num; |
| 199 | input [1:0] dmc_txc_dma21_func_num; |
| 200 | input [1:0] dmc_txc_dma22_func_num; |
| 201 | input [1:0] dmc_txc_dma23_func_num; |
| 202 | |
| 203 | |
| 204 | reg choose_available_dmas; |
| 205 | reg [`NO_OF_DMAS -1 :0] updateCacheContext; |
| 206 | reg DMC_TxCache_SMX_Req; |
| 207 | reg [1:0] DMC_TxCache_SMX_Req_Port_Num ; |
| 208 | reg [63:0] DMC_TxCache_SMX_Req_Address; |
| 209 | reg [13:0] DMC_TxCache_SMX_Req_Length ; |
| 210 | reg [7:0] DMC_TxCache_SMX_Req_Cmd; |
| 211 | reg [4:0] DMC_TxCache_SMX_Req_DMA_Num ; |
| 212 | reg LatchDMAPtrs; |
| 213 | reg CheckDMAReqSize; |
| 214 | reg [4:0] DMANumToReq; |
| 215 | reg [43:0] DMA_UpdateAddress; |
| 216 | |
| 217 | reg dma_req_pending; |
| 218 | reg [3:0] NoOfCacheWritesDispatched; |
| 219 | |
| 220 | |
| 221 | |
| 222 | reg [13:0] DMA_BytesToReq; |
| 223 | reg [63:0] DMA_AddressToReq; |
| 224 | reg [3:0] TxCacheFetchState; |
| 225 | reg UpdateTxCache; |
| 226 | reg [31:0] DMAs_AvailableFor_Fetch; |
| 227 | wire [31:0] DMAs_AvailableFor_Fetch_pre; |
| 228 | reg [`NO_OF_DMAS -1:0] UpdateDMAs; |
| 229 | |
| 230 | reg [1:0] func_num; |
| 231 | reg [1:0] tdmc_arb1_req_func_num; |
| 232 | |
| 233 | /*--------------------------------------------------------------*/ |
| 234 | // Parameters and Defines |
| 235 | /*--------------------------------------------------------------*/ |
| 236 | parameter TXCACHE_FETCH_IDLE = 4'h0, |
| 237 | ARB_FOR_DMAS = 4'h1, |
| 238 | CHECK_PENDING_REQS = 4'h2, |
| 239 | LATCH_PTRS = 4'h3, |
| 240 | EVAL_REQ_SIZE = 4'h4, |
| 241 | REQ_TX_CACHE = 4'h5, |
| 242 | WAIT_FOR_REQ_ACCEPT = 4'h6, |
| 243 | TXCACHE_UPDATE_STATE = 4'h7; |
| 244 | |
| 245 | //VCS coverage off |
| 246 | |
| 247 | // synopsys translate_off |
| 248 | reg [192:1] CACHE_DATA_FETCH_STATE; |
| 249 | |
| 250 | always @(TxCacheFetchState) |
| 251 | begin |
| 252 | case(TxCacheFetchState) |
| 253 | TXCACHE_FETCH_IDLE : CACHE_DATA_FETCH_STATE = "TXCACHE_FETCH_IDLE"; |
| 254 | ARB_FOR_DMAS: CACHE_DATA_FETCH_STATE = "ARB_FOR_DMAS"; |
| 255 | CHECK_PENDING_REQS: CACHE_DATA_FETCH_STATE = "CHECK_PENDING_REQS"; |
| 256 | LATCH_PTRS: CACHE_DATA_FETCH_STATE = "LATCH_PTRS"; |
| 257 | EVAL_REQ_SIZE: CACHE_DATA_FETCH_STATE = "EVAL_REQ_SIZE"; |
| 258 | REQ_TX_CACHE : CACHE_DATA_FETCH_STATE = "REQ_TX_CACHE"; |
| 259 | WAIT_FOR_REQ_ACCEPT : CACHE_DATA_FETCH_STATE = "WAIT_FOR_REQ_ACCEPT"; |
| 260 | TXCACHE_UPDATE_STATE : CACHE_DATA_FETCH_STATE = "TXCACHE_UPDATE_STATE"; |
| 261 | default : CACHE_DATA_FETCH_STATE = "UNKNOWN"; |
| 262 | endcase |
| 263 | end |
| 264 | // synopsys translate_on |
| 265 | //VCS coverage on |
| 266 | |
| 267 | // New pointer manipulation logic |
| 268 | function [13:0] minimum ; |
| 269 | input [18:0] A; |
| 270 | input [18:0] B; |
| 271 | begin |
| 272 | if(A >= B) |
| 273 | minimum = B[13:0] ; |
| 274 | else minimum = A[13:0] ; |
| 275 | end |
| 276 | endfunction // minimum |
| 277 | |
| 278 | // Determine if this request address is 8bytes aligned |
| 279 | // if so the response would need one additional entry in the |
| 280 | // cache. So take care of this additional entry |
| 281 | wire [4:0] AlignedFreeSpaceInCache = ( DMA_AddressToReq_ff[3] & ( NoOfFreeSpaceInCache> 5'h1)) ? |
| 282 | ( NoOfFreeSpaceInCache - 5'h1) : NoOfFreeSpaceInCache; |
| 283 | always@(posedge SysClk ) |
| 284 | if (!Reset_L) begin |
| 285 | DMA_BytesToReq <= 14'h0; |
| 286 | DMA_AddressToReq<= 64'h0; |
| 287 | end else begin |
| 288 | if(CheckDMAReqSize) begin // ??? |
| 289 | if(ShadowRingWrap ) begin |
| 290 | DMA_BytesToReq <= minimum ( {NoOfDescLeft[15:0],3'h0}, { 11'h0, AlignedFreeSpaceInCache, 3'h0} ); |
| 291 | end else begin |
| 292 | DMA_BytesToReq <= minimum ( {NoOfDescInMem[15:0] ,3'h0}, { 11'h0, AlignedFreeSpaceInCache,3'h0} ); |
| 293 | end // else: !if(ShadowRingWrap ) |
| 294 | DMA_AddressToReq<= DMA_AddressToReq_ff; |
| 295 | end |
| 296 | end // else: !if(!Reset_L) |
| 297 | |
| 298 | |
| 299 | |
| 300 | /* -----\/----- EXCLUDED -----\/----- |
| 301 | assign DMAs_AvailableFor_Fetch = {DMA31_AvailableFor_Fetch, DMA30_AvailableFor_Fetch, DMA29_AvailableFor_Fetch, DMA28_AvailableFor_Fetch, |
| 302 | DMA27_AvailableFor_Fetch, DMA26_AvailableFor_Fetch, DMA25_AvailableFor_Fetch, DMA24_AvailableFor_Fetch, |
| 303 | DMA23_AvailableFor_Fetch, DMA22_AvailableFor_Fetch, DMA21_AvailableFor_Fetch, DMA20_AvailableFor_Fetch, |
| 304 | DMA19_AvailableFor_Fetch, DMA18_AvailableFor_Fetch, DMA17_AvailableFor_Fetch, DMA16_AvailableFor_Fetch, |
| 305 | DMA15_AvailableFor_Fetch, DMA14_AvailableFor_Fetch, DMA13_AvailableFor_Fetch, DMA12_AvailableFor_Fetch, |
| 306 | DMA11_AvailableFor_Fetch, DMA10_AvailableFor_Fetch, DMA9_AvailableFor_Fetch, DMA8_AvailableFor_Fetch, |
| 307 | DMA7_AvailableFor_Fetch, DMA6_AvailableFor_Fetch, DMA5_AvailableFor_Fetch, DMA4_AvailableFor_Fetch, |
| 308 | DMA3_AvailableFor_Fetch, DMA2_AvailableFor_Fetch, DMA1_AvailableFor_Fetch, DMA0_AvailableFor_Fetch }; |
| 309 | -----/\----- EXCLUDED -----/\----- */ |
| 310 | assign DMAs_AvailableFor_Fetch_pre = {8'h0, |
| 311 | DMA23_AvailableFor_Fetch, DMA22_AvailableFor_Fetch, DMA21_AvailableFor_Fetch, DMA20_AvailableFor_Fetch, |
| 312 | DMA19_AvailableFor_Fetch, DMA18_AvailableFor_Fetch, DMA17_AvailableFor_Fetch, DMA16_AvailableFor_Fetch, |
| 313 | DMA15_AvailableFor_Fetch, DMA14_AvailableFor_Fetch, DMA13_AvailableFor_Fetch, DMA12_AvailableFor_Fetch, |
| 314 | DMA11_AvailableFor_Fetch, DMA10_AvailableFor_Fetch, DMA9_AvailableFor_Fetch, DMA8_AvailableFor_Fetch, |
| 315 | DMA7_AvailableFor_Fetch, DMA6_AvailableFor_Fetch, DMA5_AvailableFor_Fetch, DMA4_AvailableFor_Fetch, |
| 316 | DMA3_AvailableFor_Fetch, DMA2_AvailableFor_Fetch, DMA1_AvailableFor_Fetch, DMA0_AvailableFor_Fetch }; |
| 317 | |
| 318 | |
| 319 | |
| 320 | always@(posedge SysClk ) |
| 321 | if(!Reset_L) |
| 322 | UpdateTxCache <= 1'b0; |
| 323 | else |
| 324 | UpdateTxCache <= |DMAs_AvailableFor_Fetch_pre; |
| 325 | |
| 326 | |
| 327 | |
| 328 | |
| 329 | |
| 330 | always@(posedge SysClk ) |
| 331 | if (!Reset_L) begin |
| 332 | TxCacheFetchState <= TXCACHE_FETCH_IDLE; |
| 333 | choose_available_dmas <= 1'b0; |
| 334 | updateCacheContext <= `NO_OF_DMAS'b0; |
| 335 | DMC_TxCache_SMX_Req <= 1'b0; |
| 336 | DMC_TxCache_SMX_Req_Port_Num <= 2'b0; |
| 337 | DMC_TxCache_SMX_Req_Address <= 64'b0; |
| 338 | DMA_UpdateAddress <= 44'b0; |
| 339 | DMC_TxCache_SMX_Req_Length <= 14'b0; |
| 340 | DMC_TxCache_SMX_Req_Cmd <= 8'b0; |
| 341 | DMC_TxCache_SMX_Req_DMA_Num <= 5'b0; |
| 342 | tdmc_arb1_req_func_num <= 2'h0; |
| 343 | LatchDMAPtrs <= 1'b0; |
| 344 | CheckDMAReqSize <= 1'b0; |
| 345 | DMANumToReq <= 5'h0; |
| 346 | NoOfCacheWritesDispatched <= 4'h0; |
| 347 | DMAs_AvailableFor_Fetch <= 32'h0; |
| 348 | |
| 349 | end else begin |
| 350 | case(TxCacheFetchState) // synopsys full_case parallel_case |
| 351 | TXCACHE_FETCH_IDLE: begin |
| 352 | updateCacheContext <= `NO_OF_DMAS'b0; |
| 353 | DMANumToReq <= 5'h0; |
| 354 | DMA_UpdateAddress <= 44'b0; |
| 355 | DMC_TxCache_SMX_Req_Length <= 14'b0; |
| 356 | if(UpdateTxCache) begin |
| 357 | DMAs_AvailableFor_Fetch <= DMAs_AvailableFor_Fetch_pre; |
| 358 | TxCacheFetchState <= ARB_FOR_DMAS; |
| 359 | choose_available_dmas <= 1'b1; |
| 360 | end else begin // if (UpdateTxCache) |
| 361 | TxCacheFetchState <= TXCACHE_FETCH_IDLE; |
| 362 | choose_available_dmas <= 1'b0; |
| 363 | end // else: !if(UpdateTxCache) |
| 364 | end // case: TXCACHE_FETCH_IDLE |
| 365 | ARB_FOR_DMAS: begin |
| 366 | if(ArbDone) begin |
| 367 | // Need another signal here to indicated DMA has been scheduled |
| 368 | // This will be used by the reset state machine -- TOADS |
| 369 | |
| 370 | DMANumToReq <= DMANumToReqArbOut; |
| 371 | UpdateDMAs <= DMANumToUpdate[`NO_OF_DMAS -1 :0]; |
| 372 | DMAs_AvailableFor_Fetch <= 32'h0; |
| 373 | choose_available_dmas <= 1'b0; |
| 374 | TxCacheFetchState <= CHECK_PENDING_REQS; |
| 375 | end // if (ArbDone) |
| 376 | else begin |
| 377 | TxCacheFetchState <= ARB_FOR_DMAS; |
| 378 | end // else: !if(ArbDone) |
| 379 | end // case: ARB_FOR_DMAS |
| 380 | CHECK_PENDING_REQS: begin |
| 381 | if(dma_req_pending) begin |
| 382 | TxCacheFetchState <= TXCACHE_FETCH_IDLE; |
| 383 | // go back and rearbitrate |
| 384 | end else begin |
| 385 | TxCacheFetchState <= LATCH_PTRS; |
| 386 | LatchDMAPtrs <= 1'b1; |
| 387 | end |
| 388 | end |
| 389 | LATCH_PTRS: begin |
| 390 | LatchDMAPtrs <= 1'b0; |
| 391 | TxCacheFetchState <= EVAL_REQ_SIZE; |
| 392 | CheckDMAReqSize <= 1'b1; |
| 393 | end |
| 394 | EVAL_REQ_SIZE: begin |
| 395 | CheckDMAReqSize <= 1'b0; |
| 396 | TxCacheFetchState <= REQ_TX_CACHE; |
| 397 | end |
| 398 | REQ_TX_CACHE: begin |
| 399 | DMC_TxCache_SMX_Req <= 1'b1; |
| 400 | tdmc_arb1_req_func_num <= func_num; |
| 401 | DMC_TxCache_SMX_Req_Address <= DMA_AddressToReq; |
| 402 | // added-- |
| 403 | DMA_UpdateAddress <= DMA_AddressToReq[43:0] + {30'h0,DMA_BytesToReq}; |
| 404 | // DMC_TxCache_SMX_Req_Length <= 14'd64; |
| 405 | DMC_TxCache_SMX_Req_Length <= DMA_BytesToReq; |
| 406 | |
| 407 | NoOfCacheWritesDispatched <= (DMA_AddressToReq[3 ] | DMA_BytesToReq[3] ) ? |
| 408 | ( {1'b0,DMA_BytesToReq[6:4]} +4'b1): |
| 409 | DMA_BytesToReq[7:4] ; |
| 410 | |
| 411 | DMC_TxCache_SMX_Req_Cmd <= dmc_txc_tx_addr_md ? `TXC_MEM_READ_BYPASS_32 : `TXC_MEM_READ_BYPASS_64; |
| 412 | DMC_TxCache_SMX_Req_DMA_Num <= DMANumToReq; |
| 413 | choose_available_dmas <= 1'b0; |
| 414 | TxCacheFetchState <= WAIT_FOR_REQ_ACCEPT; |
| 415 | updateCacheContext <= UpdateDMAs [ `NO_OF_DMAS -1: 0]; |
| 416 | end |
| 417 | WAIT_FOR_REQ_ACCEPT: begin |
| 418 | updateCacheContext <= `NO_OF_DMAS'b0; |
| 419 | if (SMX_DMC_TxCache_Req_Ack) begin |
| 420 | DMC_TxCache_SMX_Req <= 1'b0; |
| 421 | TxCacheFetchState <= TXCACHE_UPDATE_STATE; |
| 422 | end |
| 423 | end // case: WAIT_FOR_REQ_ACCEPT |
| 424 | TXCACHE_UPDATE_STATE: begin |
| 425 | TxCacheFetchState <= TXCACHE_FETCH_IDLE; |
| 426 | updateCacheContext <= `NO_OF_DMAS'b0; |
| 427 | end // case: TXCACHE_UPDATE_STATE |
| 428 | default: begin |
| 429 | TxCacheFetchState <= TXCACHE_FETCH_IDLE; |
| 430 | choose_available_dmas <= 1'b0; |
| 431 | updateCacheContext <= `NO_OF_DMAS'b0; |
| 432 | DMC_TxCache_SMX_Req <= 1'b0; |
| 433 | DMC_TxCache_SMX_Req_Port_Num <= 2'b0; |
| 434 | DMC_TxCache_SMX_Req_Address <= 64'b0; |
| 435 | DMA_UpdateAddress <= 44'b0; |
| 436 | DMC_TxCache_SMX_Req_Length <= 14'b0; |
| 437 | DMC_TxCache_SMX_Req_Cmd <= 8'b0; |
| 438 | DMC_TxCache_SMX_Req_DMA_Num <= 5'b0; |
| 439 | tdmc_arb1_req_func_num <= 2'h0; |
| 440 | LatchDMAPtrs <= 1'b0; |
| 441 | CheckDMAReqSize <= 1'b0; |
| 442 | DMANumToReq <= 5'h0; |
| 443 | NoOfCacheWritesDispatched <= 4'h0; |
| 444 | DMAs_AvailableFor_Fetch <= 32'h0; |
| 445 | end |
| 446 | endcase // case(TxCacheFetchState) |
| 447 | end // else: !if(!Reset_L) |
| 448 | |
| 449 | // move this to a common module which interfaces all the dmas |
| 450 | // Q? Will this meet timing? |
| 451 | |
| 452 | always@(/*AUTOJUNK*/DMA0_ReqPending or DMA10_ReqPending |
| 453 | or DMA11_ReqPending or DMA12_ReqPending or DMA13_ReqPending |
| 454 | or DMA14_ReqPending or DMA15_ReqPending or DMA16_ReqPending |
| 455 | or DMA17_ReqPending or DMA18_ReqPending or DMA19_ReqPending |
| 456 | or DMA1_ReqPending or DMA20_ReqPending or DMA21_ReqPending |
| 457 | or DMA22_ReqPending or DMA23_ReqPending |
| 458 | or DMA3_ReqPending or DMA2_ReqPending |
| 459 | or DMA4_ReqPending or DMA5_ReqPending or DMA6_ReqPending |
| 460 | or DMA7_ReqPending or DMA8_ReqPending or DMA9_ReqPending |
| 461 | or DMANumToReq ) begin |
| 462 | case(DMANumToReq) // synopsys full_case parallel_case |
| 463 | `DMA_CHANNEL_ZERO: dma_req_pending = DMA0_ReqPending; |
| 464 | `DMA_CHANNEL_ONE: dma_req_pending = DMA1_ReqPending; |
| 465 | `DMA_CHANNEL_TWO: dma_req_pending = DMA2_ReqPending; |
| 466 | `DMA_CHANNEL_THREE: dma_req_pending = DMA3_ReqPending; |
| 467 | `DMA_CHANNEL_FOUR: dma_req_pending = DMA4_ReqPending; |
| 468 | `DMA_CHANNEL_FIVE: dma_req_pending = DMA5_ReqPending; |
| 469 | `DMA_CHANNEL_SIX: dma_req_pending = DMA6_ReqPending; |
| 470 | `DMA_CHANNEL_SEVEN: dma_req_pending = DMA7_ReqPending; |
| 471 | `DMA_CHANNEL_EIGHT: dma_req_pending = DMA8_ReqPending; |
| 472 | `DMA_CHANNEL_NINE: dma_req_pending = DMA9_ReqPending; |
| 473 | `DMA_CHANNEL_TEN: dma_req_pending = DMA10_ReqPending; |
| 474 | `DMA_CHANNEL_ELEVEN: dma_req_pending = DMA11_ReqPending; |
| 475 | `DMA_CHANNEL_TWELVE: dma_req_pending = DMA12_ReqPending; |
| 476 | `DMA_CHANNEL_THIRTEEN: dma_req_pending = DMA13_ReqPending; |
| 477 | `DMA_CHANNEL_FOURTEEN: dma_req_pending = DMA14_ReqPending; |
| 478 | `DMA_CHANNEL_FIFTEEN: dma_req_pending = DMA15_ReqPending; |
| 479 | `DMA_CHANNEL_SIXTEEN: dma_req_pending = DMA16_ReqPending; |
| 480 | `DMA_CHANNEL_SEVENTEEN: dma_req_pending = DMA17_ReqPending; |
| 481 | `DMA_CHANNEL_EIGHTEEN: dma_req_pending = DMA18_ReqPending; |
| 482 | `DMA_CHANNEL_NINETEEN: dma_req_pending = DMA19_ReqPending; |
| 483 | `DMA_CHANNEL_TWENTY: dma_req_pending = DMA20_ReqPending; |
| 484 | `DMA_CHANNEL_TWENTYONE: dma_req_pending = DMA21_ReqPending; |
| 485 | `DMA_CHANNEL_TWENTYTWO: dma_req_pending = DMA22_ReqPending; |
| 486 | `DMA_CHANNEL_TWENTYTHREE: dma_req_pending = DMA23_ReqPending; |
| 487 | |
| 488 | default: dma_req_pending = 1'b0; |
| 489 | endcase |
| 490 | end // always@ (... |
| 491 | |
| 492 | always@(/*AUTOJUNK*/DMANumToReq or dmc_txc_dma0_func_num |
| 493 | or dmc_txc_dma10_func_num or dmc_txc_dma11_func_num |
| 494 | or dmc_txc_dma12_func_num or dmc_txc_dma13_func_num |
| 495 | or dmc_txc_dma14_func_num or dmc_txc_dma15_func_num |
| 496 | or dmc_txc_dma16_func_num or dmc_txc_dma17_func_num |
| 497 | or dmc_txc_dma18_func_num or dmc_txc_dma19_func_num |
| 498 | or dmc_txc_dma1_func_num or dmc_txc_dma20_func_num |
| 499 | or dmc_txc_dma21_func_num or dmc_txc_dma22_func_num |
| 500 | or dmc_txc_dma23_func_num or dmc_txc_dma2_func_num |
| 501 | or dmc_txc_dma3_func_num or dmc_txc_dma4_func_num |
| 502 | or dmc_txc_dma5_func_num or dmc_txc_dma6_func_num |
| 503 | or dmc_txc_dma7_func_num or dmc_txc_dma8_func_num |
| 504 | or dmc_txc_dma9_func_num) begin |
| 505 | case(DMANumToReq) // synopsys full_case parallel_case |
| 506 | `DMA_CHANNEL_TWENTYTHREE: func_num = dmc_txc_dma23_func_num; |
| 507 | `DMA_CHANNEL_TWENTYTWO: func_num = dmc_txc_dma22_func_num; |
| 508 | `DMA_CHANNEL_TWENTYONE: func_num = dmc_txc_dma21_func_num; |
| 509 | `DMA_CHANNEL_TWENTY: func_num = dmc_txc_dma20_func_num; |
| 510 | `DMA_CHANNEL_NINETEEN: func_num = dmc_txc_dma19_func_num; |
| 511 | `DMA_CHANNEL_EIGHTEEN: func_num = dmc_txc_dma18_func_num; |
| 512 | `DMA_CHANNEL_SEVENTEEN: func_num = dmc_txc_dma17_func_num; |
| 513 | `DMA_CHANNEL_SIXTEEN: func_num = dmc_txc_dma16_func_num; |
| 514 | `DMA_CHANNEL_FIFTEEN: func_num = dmc_txc_dma15_func_num; |
| 515 | `DMA_CHANNEL_FOURTEEN: func_num = dmc_txc_dma14_func_num; |
| 516 | `DMA_CHANNEL_THIRTEEN: func_num = dmc_txc_dma13_func_num; |
| 517 | `DMA_CHANNEL_TWELVE: func_num = dmc_txc_dma12_func_num; |
| 518 | `DMA_CHANNEL_ELEVEN: func_num = dmc_txc_dma11_func_num; |
| 519 | `DMA_CHANNEL_TEN: func_num = dmc_txc_dma10_func_num; |
| 520 | `DMA_CHANNEL_NINE: func_num = dmc_txc_dma9_func_num; |
| 521 | `DMA_CHANNEL_EIGHT: func_num = dmc_txc_dma8_func_num; |
| 522 | `DMA_CHANNEL_SEVEN: func_num = dmc_txc_dma7_func_num; |
| 523 | `DMA_CHANNEL_SIX: func_num = dmc_txc_dma6_func_num; |
| 524 | `DMA_CHANNEL_FIVE: func_num = dmc_txc_dma5_func_num; |
| 525 | `DMA_CHANNEL_FOUR: func_num = dmc_txc_dma4_func_num; |
| 526 | `DMA_CHANNEL_THREE: func_num = dmc_txc_dma3_func_num; |
| 527 | `DMA_CHANNEL_TWO: func_num = dmc_txc_dma2_func_num; |
| 528 | `DMA_CHANNEL_ONE: func_num = dmc_txc_dma1_func_num; |
| 529 | `DMA_CHANNEL_ZERO: func_num = dmc_txc_dma0_func_num; |
| 530 | |
| 531 | default: func_num = 2'h0; |
| 532 | endcase // case(DMANumToReq) |
| 533 | end // always@ (... |
| 534 | endmodule // niu_tdmc_cachefetch |
| 535 | |
| 536 | |