| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_zcp_tt.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /*************************************************************** |
| 38 | * |
| 39 | * File Name : niu_zcp_tt.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : |
| 42 | * Parent Module: |
| 43 | * Child Module: |
| 44 | * Interface Mod: |
| 45 | * Date Created : 5/6/04 |
| 46 | * |
| 47 | * Copyright (c) 2020, Sun Microsystems, Inc. |
| 48 | * Sun Proprietary and Confidential |
| 49 | * |
| 50 | * Modification : |
| 51 | * |
| 52 | * Synthesis Notes: |
| 53 | * |
| 54 | * Design Notes: |
| 55 | * |
| 56 | * |
| 57 | **************************************************************/ |
| 58 | |
| 59 | `include "niu_zcp.h" |
| 60 | |
| 61 | module niu_zcp_tt ( |
| 62 | `ifdef NEPTUNE |
| 63 | dmaw_threshold, |
| 64 | // error handling |
| 65 | va_ram_perr, |
| 66 | dn_ram_perr, |
| 67 | st_ram_perr, |
| 68 | // tt intf |
| 69 | va_dout, |
| 70 | st_dout, |
| 71 | dn_dout, |
| 72 | tt_index_4va, |
| 73 | tt_index_4dn, |
| 74 | tt_index_4st, |
| 75 | // req ptr intf |
| 76 | credit_ok, |
| 77 | zcp_tt_index_err_lv, |
| 78 | tt_index, |
| 79 | buf_req, |
| 80 | wptr_HoQ_reg, |
| 81 | cross_q_end_reg, |
| 82 | cross_4KB_reg, |
| 83 | ring_size_reg, |
| 84 | ring_base_addr_reg, |
| 85 | reach_buf_end_reg, |
| 86 | total_num_buf_requested_reg, |
| 87 | // wb |
| 88 | wb_dn_reg, |
| 89 | wb_tt0, |
| 90 | wb_tt1, |
| 91 | // |
| 92 | tt_rd_en0, |
| 93 | tt_rd_en1, |
| 94 | tt_rd_en2, |
| 95 | tt_rd_en3, |
| 96 | tt_active, |
| 97 | tt_sm_rw, |
| 98 | // debug |
| 99 | tcp_payld_len, |
| 100 | l2_hdr_len, |
| 101 | l3_hdr_len, |
| 102 | header_len, |
| 103 | tt_ok_reg7, |
| 104 | buf_req_ok, |
| 105 | // MCP debug |
| 106 | TL, |
| 107 | S, |
| 108 | payload_len, // registered output. |
| 109 | header_delta, // registered output. |
| 110 | UE, |
| 111 | TL_bt_UE, |
| 112 | TL_eq_UE, |
| 113 | qual_ulp_end_fail_reg, |
| 114 | running_anchor_seq, |
| 115 | first_byte_buf, |
| 116 | last_byte_buf, |
| 117 | index0, |
| 118 | index1, |
| 119 | index2, |
| 120 | index3, |
| 121 | win_ok, |
| 122 | ulp_end_fail, |
| 123 | mapped_in_fail, |
| 124 | dmaw_threshold_fail, |
| 125 | unmap_on_left_oc, |
| 126 | last_line2, |
| 127 | second_line2, |
| 128 | first_line2, |
| 129 | last_line3, |
| 130 | second_line3, |
| 131 | first_line3, |
| 132 | `else // N2 |
| 133 | `endif |
| 134 | last_line0, |
| 135 | second_line0, |
| 136 | first_line0, |
| 137 | last_line1, |
| 138 | second_line1, |
| 139 | first_line1, |
| 140 | clk, |
| 141 | reset, |
| 142 | kickoff_tt_reg, |
| 143 | set_tt_program_err, |
| 144 | fflp_data, |
| 145 | // zcp_slv intf |
| 146 | tt_en, |
| 147 | fn, |
| 148 | handle, |
| 149 | // fflp wr intf |
| 150 | ififo_ren, |
| 151 | ififo_dout, |
| 152 | // rx dmc stuff |
| 153 | decode_default_rdc, |
| 154 | decode_table_rdc, |
| 155 | decode_zc_rdc, |
| 156 | tt_rdc_reg, |
| 157 | fflp_rdc, |
| 158 | default_rdc, |
| 159 | table_rdc, |
| 160 | zc_rdc, |
| 161 | wr_data, |
| 162 | wr_en0, |
| 163 | wr_en1, |
| 164 | wr_en2, |
| 165 | wr_en3, |
| 166 | tt_state |
| 167 | ); |
| 168 | |
| 169 | `ifdef NEPTUNE |
| 170 | input [10:0] dmaw_threshold; |
| 171 | // error handling |
| 172 | input va_ram_perr; |
| 173 | input dn_ram_perr; |
| 174 | input st_ram_perr; |
| 175 | // tt intf |
| 176 | input [1023:0] va_dout; |
| 177 | input [`ST_R] st_dout; |
| 178 | input [`DN_R] dn_dout; |
| 179 | output [11:0] tt_index_4va; |
| 180 | output [11:0] tt_index_4dn; |
| 181 | output [11:0] tt_index_4st; |
| 182 | // req ptr intf |
| 183 | input credit_ok; |
| 184 | input zcp_tt_index_err_lv; |
| 185 | output [11:0] tt_index ; |
| 186 | output buf_req ; |
| 187 | output [15:0] wptr_HoQ_reg ; |
| 188 | output cross_q_end_reg ; |
| 189 | output cross_4KB_reg ; |
| 190 | output [3:0] ring_size_reg ; |
| 191 | output [38:0] ring_base_addr_reg ; |
| 192 | output reach_buf_end_reg ; |
| 193 | output [5:0] total_num_buf_requested_reg; |
| 194 | // wb |
| 195 | output [`DN_R] wb_dn_reg; |
| 196 | output wb_tt0; |
| 197 | output wb_tt1; |
| 198 | // |
| 199 | output tt_rd_en0; |
| 200 | output tt_rd_en1; |
| 201 | output tt_rd_en2; |
| 202 | output tt_rd_en3; |
| 203 | output tt_active; |
| 204 | output tt_sm_rw; |
| 205 | // debug |
| 206 | output [15:0] tcp_payld_len; |
| 207 | output [9:0] l2_hdr_len; |
| 208 | output [9:0] l3_hdr_len; |
| 209 | output [9:0] header_len; |
| 210 | output tt_ok_reg7; |
| 211 | output buf_req_ok; |
| 212 | // MCP debug |
| 213 | output [`XPAN_TCP_SEQ_SPACE]TL; |
| 214 | output [`XPAN_TCP_SEQ_SPACE]S; |
| 215 | output [`PKT_LEN_R] payload_len; // registered output. |
| 216 | output [`PKT_LEN_R] header_delta; // registered output. |
| 217 | output [`XPAN_TCP_SEQ_SPACE]UE; |
| 218 | output TL_bt_UE; |
| 219 | output TL_eq_UE; |
| 220 | output qual_ulp_end_fail_reg; |
| 221 | output [`TCP_SEQ_SPACE] running_anchor_seq; |
| 222 | output [5:0] first_byte_buf; |
| 223 | output [20:0] last_byte_buf; |
| 224 | output [5:0] index0; |
| 225 | output [5:0] index1; |
| 226 | output [5:0] index2; |
| 227 | output [5:0] index3; |
| 228 | output win_ok; |
| 229 | output ulp_end_fail; |
| 230 | output mapped_in_fail; |
| 231 | output dmaw_threshold_fail; |
| 232 | output unmap_on_left_oc; |
| 233 | // |
| 234 | output last_line2; |
| 235 | output second_line2; |
| 236 | output first_line2; |
| 237 | output last_line3; |
| 238 | output second_line3; |
| 239 | output first_line3; |
| 240 | `else // N2 |
| 241 | `endif |
| 242 | output last_line0; |
| 243 | output second_line0; |
| 244 | output first_line0; |
| 245 | output last_line1; |
| 246 | output second_line1; |
| 247 | output first_line1; |
| 248 | input clk; |
| 249 | // vlint flag_input_port_not_connected off |
| 250 | input [10:0] reset; |
| 251 | // vlint flag_input_port_not_connected on |
| 252 | output kickoff_tt_reg; |
| 253 | output set_tt_program_err ; // zcp_slv.v |
| 254 | output [`IFIFO_W_R] fflp_data; |
| 255 | // zcp_slv intf |
| 256 | input tt_en; |
| 257 | input [1:0] fn; |
| 258 | input [19:0] handle; |
| 259 | // fflp wr intf |
| 260 | // vlint flag_input_port_not_connected off |
| 261 | input [2:0] ififo_ren; |
| 262 | // vlint flag_input_port_not_connected on |
| 263 | input [`IFIFO_W_R] ififo_dout; |
| 264 | // rx dmc stuff |
| 265 | output decode_default_rdc; |
| 266 | output decode_table_rdc; |
| 267 | output decode_zc_rdc; |
| 268 | output [7:0] tt_rdc_reg; |
| 269 | output [7:0] fflp_rdc; |
| 270 | input [4:0] default_rdc; |
| 271 | input [4:0] table_rdc; |
| 272 | input [4:0] zc_rdc; |
| 273 | output [`CFIFO_W_R] wr_data; |
| 274 | output wr_en0; |
| 275 | output wr_en1; |
| 276 | output wr_en2; |
| 277 | output wr_en3; |
| 278 | output [3:0] tt_state; |
| 279 | |
| 280 | /*AUTOWIRE*/ |
| 281 | // Beginning of automatic wires (for undeclared instantiated-module outputs) |
| 282 | // End of automatics |
| 283 | |
| 284 | // manually created by loj |
| 285 | wire [1:0] dmaw_type_reg; |
| 286 | wire [23:0] first_byte_offset_reg; |
| 287 | wire [`PKT_LEN_R] tt_dmaw_len0_reg; |
| 288 | wire [`PKT_LEN_R] tt_dmaw_len1_reg; |
| 289 | wire [`PKT_LEN_R] tt_dmaw_len2_reg; |
| 290 | wire [`PKT_LEN_R] tt_dmaw_len3_reg; |
| 291 | wire [`DMA_R] tt_dmaw_va0_reg; |
| 292 | wire [`DMA_R] tt_dmaw_va1_reg; |
| 293 | wire [`DMA_R] tt_dmaw_va2_reg; |
| 294 | wire [`DMA_R] tt_dmaw_va3_reg; |
| 295 | wire [`PKT_LEN_R] tt_hdr_len_reg; |
| 296 | wire wr_2words; |
| 297 | wire wr_4words; |
| 298 | wire zc_mode; |
| 299 | wire kickoff_tt; |
| 300 | wire [1:0] mac_port; |
| 301 | wire wr_en0; |
| 302 | wire wr_en1; |
| 303 | wire wr_en2; |
| 304 | wire wr_en3; |
| 305 | wire wr_2words0; |
| 306 | wire wr_2words1; |
| 307 | wire [`IFIFO_W_R] fflp_data; |
| 308 | wire va_ram_perr; |
| 309 | wire dn_ram_perr; |
| 310 | wire st_ram_perr; |
| 311 | wire tt_err = va_ram_perr | dn_ram_perr | st_ram_perr; |
| 312 | |
| 313 | // vlint flag_dangling_net_within_module off |
| 314 | // vlint flag_net_has_no_load off |
| 315 | wire [10:0] reset; |
| 316 | wire reset9 = reset[9]; // for niu_zcp_tt_dpath |
| 317 | wire reset10= reset[10]; // for niu_zcp_tt_sm |
| 318 | wire wb_tt0; |
| 319 | wire wb_tt1; |
| 320 | wire tt_rd_en0; |
| 321 | wire tt_rd_en1; |
| 322 | wire tt_rd_en2; |
| 323 | wire tt_rd_en3; |
| 324 | wire tt_rd_en4; |
| 325 | wire tt_active; |
| 326 | wire tt_sm_rw; |
| 327 | wire [7:0] tt_rdc_reg ; |
| 328 | wire buf_req ; |
| 329 | wire [15:0] wptr_HoQ_reg ; |
| 330 | wire [15:0] HoQ_reg ; |
| 331 | wire cross_q_end_reg ; |
| 332 | wire cross_4KB_reg ; |
| 333 | wire [3:0] ring_size_reg ; |
| 334 | wire [38:0] ring_base_addr_reg ; |
| 335 | wire reach_buf_end_reg ; |
| 336 | wire [5:0] total_num_buf_requested_reg ; // total number of buffer requested |
| 337 | wire [`DN_R] wb_dn_reg ; |
| 338 | wire wr_4words0; |
| 339 | wire wr_4words1; |
| 340 | wire wr_4words2; |
| 341 | wire wr_4words3; |
| 342 | wire set_tt_program_err; |
| 343 | wire [7:0] tt_ok_reg; |
| 344 | wire tt_ok_reg6 = tt_ok_reg[6]; |
| 345 | wire tt_ok_reg7 = tt_ok_reg[7]; |
| 346 | wire buf_req_ok; |
| 347 | wire [`PKT_LEN_R] payload_len; // registered output. |
| 348 | wire neptune_signature; |
| 349 | wire [5:0] first_byte_buf_reg; |
| 350 | wire [31:0] ld_cal_results; |
| 351 | wire tt_fail; |
| 352 | wire [2:0] ififo_ren; |
| 353 | // vlint flag_net_has_no_load on |
| 354 | // vlint flag_dangling_net_within_module on |
| 355 | |
| 356 | |
| 357 | /* ----------------- start of fflp load ------------------ */ |
| 358 | // This is the first pipeline register after ififo. |
| 359 | dffre #(`IFIFO_W) fflp_data_dffre (.clk(clk), |
| 360 | .reset(reset[0]), |
| 361 | .en(ififo_ren[0]), |
| 362 | .d(ififo_dout[`IFIFO_W_R]), |
| 363 | .q(fflp_data[`IFIFO_W_R])); |
| 364 | |
| 365 | df1 #(1) kickoff_tt_df1 (.clk(clk), |
| 366 | .d(ififo_ren[1]), |
| 367 | .q(kickoff_tt)); |
| 368 | |
| 369 | df1 #(1) kickoff_tt_reg_df1 (.clk(clk), |
| 370 | .d(kickoff_tt), |
| 371 | .q(kickoff_tt_reg)); |
| 372 | |
| 373 | |
| 374 | // vlint flag_dangling_net_within_module off |
| 375 | // vlint flag_net_has_no_load off |
| 376 | wire [7:0] B0 = fflp_data[`BBYTE0]; |
| 377 | wire [7:0] B1 = fflp_data[`BBYTE1]; |
| 378 | wire [7:0] B4 = fflp_data[`BBYTE4]; |
| 379 | wire [7:0] B6 = fflp_data[`BBYTE6]; |
| 380 | wire [7:0] B18 = fflp_data[`BBYTE18]; |
| 381 | wire [7:0] B2 = fflp_data[`BBYTE2]; |
| 382 | wire [7:0] B7 = fflp_data[`BBYTE7]; |
| 383 | wire [7:0] B20 = fflp_data[`BBYTE20]; |
| 384 | wire [7:0] B21 = fflp_data[`BBYTE21]; |
| 385 | wire [7:0] B22 = fflp_data[`BBYTE22]; |
| 386 | wire [7:0] B23 = fflp_data[`BBYTE23]; |
| 387 | wire [7:0] B24 = fflp_data[`BBYTE24]; |
| 388 | wire [7:0] B25 = fflp_data[`BBYTE25]; |
| 389 | wire [7:0] B26 = fflp_data[`BBYTE26]; |
| 390 | // aliasing |
| 391 | wire vlan = B1[7]; // 4 bytes |
| 392 | wire llc_snap = B1[6]; // 8 bytes |
| 393 | wire tzfvld = B1[0]; |
| 394 | wire [7:0] fflp_rdc = B2; // will be replaced by default_RDC, and table_RDC after RDC table lookup. |
| 395 | wire hzfvld = B4[3]; |
| 396 | wire [11:0] tt_index ={B6[3:0],B7}; |
| 397 | wire ip_ver = B18[6]; |
| 398 | wire [1:0] tt_index_hi = tt_index[11:10]; |
| 399 | wire [15:0] ip_pkt_len ={B20,B21}; // IPv4 pkt len or IPv6 payload len |
| 400 | wire [3:0] ip_hdr_len = B22[7:4]; // IPv4 header only |
| 401 | wire [3:0] tcp_hdr_len = B22[3:0]; |
| 402 | wire [`TCP_SEQ_SPACE]tcp_seq_num ={B23,B24,B25,B26}; |
| 403 | // vlint flag_dangling_net_within_module on |
| 404 | // vlint flag_net_has_no_load on |
| 405 | |
| 406 | assign zc_mode = tzfvld | hzfvld; // un register version |
| 407 | |
| 408 | /* ----------------- end of fflp load -------------------- */ |
| 409 | |
| 410 | /* ******* translation algorithm is happening here ******* */ |
| 411 | |
| 412 | /* ----------------- post TT to cfifo -------------------- */ |
| 413 | |
| 414 | // latch data from zero copy processing results |
| 415 | // and prepare for writing to cfifo |
| 416 | |
| 417 | // latch the first 20 bytes from fflp for posting to rdmc |
| 418 | // wire [151:0] fflp_cword; |
| 419 | // vlint flag_dangling_net_within_module off |
| 420 | // vlint flag_net_has_no_load off |
| 421 | wire [`IFIFO_W_R] fflp_cword; |
| 422 | // vlint flag_dangling_net_within_module on |
| 423 | // vlint flag_net_has_no_load on |
| 424 | |
| 425 | assign fflp_cword[63:0] = 0; |
| 426 | zcp_xREG #(32) fflp_cword0_xREG(.clk(clk),.reset(reset[1]),.en(ld_cal_results[26]),.din(fflp_data[95:64] ),.qout(fflp_cword[95:64] )); |
| 427 | zcp_xREG #(32) fflp_cword1_xREG(.clk(clk),.reset(reset[2]),.en(ld_cal_results[27]),.din(fflp_data[127:96] ),.qout(fflp_cword[127:96] )); |
| 428 | zcp_xREG #(32) fflp_cword2_xREG(.clk(clk),.reset(reset[3]),.en(ld_cal_results[28]),.din(fflp_data[159:128]),.qout(fflp_cword[159:128])); |
| 429 | zcp_xREG #(32) fflp_cword3_xREG(.clk(clk),.reset(reset[4]),.en(ld_cal_results[29]),.din(fflp_data[191:160]),.qout(fflp_cword[191:160])); |
| 430 | zcp_xREG #(24) fflp_cword4_xREG(.clk(clk),.reset(reset[5]),.en(ld_cal_results[31]),.din(fflp_data[215:192]),.qout(fflp_cword[215:192])); |
| 431 | |
| 432 | /* vlint change by Shimon --- this is not used anywhere |
| 433 | wire [7:0] CC2 = fflp_cword[`BBYTE2]; |
| 434 | wire [7:0] CC5 = fflp_cword[`BBYTE5]; |
| 435 | */ |
| 436 | // The following data will stay for 8 clocks |
| 437 | // until another ld_cal_results happens. |
| 438 | // These CC/fflp_cword data are valid at the same time |
| 439 | // as tt_ok_reg, wb_tt, wr_2words, wr_4words. |
| 440 | wire [7:0] CC0 = fflp_cword[`BBYTE0]; |
| 441 | wire [7:0] CC1 = fflp_cword[`BBYTE1]; |
| 442 | wire [7:0] CC3 = fflp_cword[`BBYTE3]; |
| 443 | wire [7:0] CC6 = fflp_cword[`BBYTE6]; |
| 444 | wire [7:0] CC7 = fflp_cword[`BBYTE7]; |
| 445 | wire [7:0] CC8 = fflp_cword[`BBYTE8]; |
| 446 | wire [7:0] CC9 = fflp_cword[`BBYTE9]; |
| 447 | wire [7:0] CC10 = fflp_cword[`BBYTE10]; |
| 448 | wire [7:0] CC11 = fflp_cword[`BBYTE11]; |
| 449 | wire [7:0] CC12 = fflp_cword[`BBYTE12]; |
| 450 | wire [7:0] CC13 = fflp_cword[`BBYTE13]; |
| 451 | wire [7:0] CC14 = fflp_cword[`BBYTE14]; |
| 452 | wire [7:0] CC15 = fflp_cword[`BBYTE15]; |
| 453 | wire [7:0] CC16 = fflp_cword[`BBYTE16]; |
| 454 | wire [7:0] CC17 = fflp_cword[`BBYTE17]; |
| 455 | wire [7:0] CC18 = fflp_cword[`BBYTE18]; |
| 456 | wire [7:0] CC19 = fflp_cword[`BBYTE19]; |
| 457 | wire [7:0] CC20 = fflp_cword[`BBYTE20]; |
| 458 | wire [7:0] CC21 = fflp_cword[`BBYTE21]; |
| 459 | wire [7:0] CC22 = fflp_cword[`BBYTE22]; |
| 460 | wire [7:0] CC23 = fflp_cword[`BBYTE23]; |
| 461 | wire [7:0] CC24 = fflp_cword[`BBYTE24]; |
| 462 | wire [7:0] CC25 = fflp_cword[`BBYTE25]; |
| 463 | wire [7:0] CC26 = fflp_cword[`BBYTE26]; |
| 464 | wire [7:0] CC27 = 8'b0; // unused field |
| 465 | wire [7:0] CC28 = 8'b0; // unused field |
| 466 | wire [7:0] CC29 = 8'b0; // unused field |
| 467 | wire [7:0] CC30 = 8'b0; // unused field |
| 468 | wire [7:0] CC31 = 8'b0; // unused field |
| 469 | // vlint flag_dangling_net_within_module off |
| 470 | // vlint flag_net_has_no_load off |
| 471 | wire [7:0] CC4 = fflp_cword[`BBYTE4]; |
| 472 | wire [7:0] CC32 = 8'b0; // unused field |
| 473 | wire [7:0] CC40 = 8'b0; // unused field |
| 474 | wire [7:0] CC48 = 8'b0; // unused field |
| 475 | wire [7:0] CC56 = 8'b0; // unused field |
| 476 | // vlint flag_dangling_net_within_module on |
| 477 | // vlint flag_net_has_no_load on |
| 478 | wire [`CFIFO_W_R] full_cword0; |
| 479 | wire [`CFIFO_W_R] full_cword1; |
| 480 | wire [`CFIFO_W_R] full_cword2; |
| 481 | wire [`CFIFO_W_R] full_cword3; |
| 482 | reg [127:0] cword0; |
| 483 | reg [127:0] cword1; |
| 484 | wire [127:0] cword2; |
| 485 | wire [127:0] cword3; |
| 486 | wire rdmc_tzfvld = CC1[0]; |
| 487 | wire rdmc_hzfvld = CC4[3]; |
| 488 | wire rdmc_zc_mode = rdmc_tzfvld | rdmc_hzfvld; |
| 489 | wire rsv = 1'b0; |
| 490 | |
| 491 | always @ (/*AUTOSENSE*/CC0 or CC1 or CC10 or CC11 or CC12 or CC13 |
| 492 | or CC14 or CC15 or CC16 or CC17 or CC18 or CC19 or CC20 |
| 493 | or CC21 or CC22 or CC23 or CC24 or CC25 or CC26 or CC27 |
| 494 | or CC28 or CC29 or CC3 or CC30 or CC31 or CC4 or CC6 |
| 495 | or CC7 or CC8 or CC9 or HoQ_reg or default_rdc |
| 496 | or dmaw_type_reg or first_byte_buf_reg |
| 497 | or first_byte_offset_reg or fn or handle or payload_len |
| 498 | or rdmc_zc_mode or reach_buf_end_reg or rsv or table_rdc |
| 499 | or tt_err or tt_hdr_len_reg or tt_ok_reg6 or zc_rdc) |
| 500 | begin |
| 501 | if (rdmc_zc_mode & tt_ok_reg6) |
| 502 | begin // zcp packet |
| 503 | cword0 = {CC0,CC1,{default_rdc[4:0],table_rdc[4:2]},CC3,{table_rdc[1:0],CC4[5:0]}, |
| 504 | {1'b1,{tt_err,{6{rsv}}}},// <-B5[7] tt_succeed == 1 => zc mode; |
| 505 | CC6,CC7, |
| 506 | tt_hdr_len_reg[15:0],payload_len[15:0],HoQ_reg[15:0],first_byte_offset_reg[23:8]}; |
| 507 | cword1 = {first_byte_offset_reg[7:0], // 17th Byte |
| 508 | {reach_buf_end_reg,dmaw_type_reg[1:0],first_byte_buf_reg[4:0]}, // 18th Byte // win_buf_offset == first_byte_buf_reg |
| 509 | CC18,{CC19[7],dmaw_type_reg[1:0],zc_rdc[4:0]},CC20,CC21,CC22,CC23,CC24,CC25,CC26,CC27,CC28, |
| 510 | handle[19:0],fn[1:0],CC31[1:0]}; //CC29,CC30,CC31 |
| 511 | end |
| 512 | else |
| 513 | begin // bypass packet |
| 514 | cword0 = {CC0,CC1,{default_rdc[4:0],table_rdc[4:2]},CC3,{table_rdc[1:0],CC4[5:0]}, |
| 515 | {1'b0,{1'b0,{6{rsv}}}}, // <-B5[7] tt_succeed == 0 => bypass mode/ B5[6] tt_err == 0 always. |
| 516 | CC6,CC7, |
| 517 | CC8,CC9,CC10,CC11,CC12,CC13,CC14,CC15}; |
| 518 | cword1 = {CC16,CC17, // end of control header |
| 519 | CC18,CC19,CC20,CC21,CC22,CC23,CC24,CC25,CC26,CC27,CC28, |
| 520 | CC29,CC30,CC31}; |
| 521 | end |
| 522 | end // always @ (... |
| 523 | |
| 524 | assign cword2 = {CC32[7:4],tt_dmaw_va0_reg[43:0],tt_dmaw_len0_reg[15:0], |
| 525 | CC40[7:4],tt_dmaw_va1_reg[43:0],tt_dmaw_len1_reg[15:0]}; |
| 526 | assign cword3 = {CC48[7:4],tt_dmaw_va2_reg[43:0],tt_dmaw_len2_reg[15:0], |
| 527 | CC56[7:4],tt_dmaw_va3_reg[43:0],tt_dmaw_len3_reg[15:0]}; |
| 528 | |
| 529 | |
| 530 | |
| 531 | |
| 532 | assign full_cword0[`CFIFO_W_R] = {`CFIFO_SOP, cword0}; // sop = 2'b01, B0~B15 |
| 533 | assign full_cword1[`CFIFO_W_R] = {wr_2words1,1'b0,cword1}; // {eop,,,}; |
| 534 | assign full_cword2[`CFIFO_W_R] = {2'b00, cword2}; |
| 535 | assign full_cword3[`CFIFO_W_R] = {2'b10, cword3}; // {eop,,,}; |
| 536 | assign mac_port = CC0[7:6]; |
| 537 | |
| 538 | // wr_2words and wr_4words happens at the same time as |
| 539 | df1 #(1) wr_2words0_df1(.clk(clk),.d(wr_2words), .q(wr_2words0)); |
| 540 | df1 #(1) wr_2words1_df1(.clk(clk),.d(wr_2words0),.q(wr_2words1)); |
| 541 | |
| 542 | df1 #(1) wr_4words0_df1(.clk(clk),.d(wr_4words), .q(wr_4words0)); |
| 543 | df1 #(1) wr_4words1_df1(.clk(clk),.d(wr_4words0),.q(wr_4words1)); |
| 544 | df1 #(1) wr_4words2_df1(.clk(clk),.d(wr_4words1),.q(wr_4words2)); |
| 545 | df1 #(1) wr_4words3_df1(.clk(clk),.d(wr_4words2),.q(wr_4words3)); |
| 546 | |
| 547 | wire wr_ens = wr_2words0 | wr_2words1 | |
| 548 | wr_4words0 | wr_4words1 | |
| 549 | wr_4words2 | wr_4words3 ; |
| 550 | |
| 551 | wire port0 = mac_port[1:0] == 2'b00; |
| 552 | wire port1 = mac_port[1:0] == 2'b01; |
| 553 | wire port2 = mac_port[1:0] == 2'b10; |
| 554 | wire port3 = mac_port[1:0] == 2'b11; |
| 555 | |
| 556 | assign wr_en0 = (port0 & wr_ens); |
| 557 | assign wr_en1 = (port1 & wr_ens); |
| 558 | assign wr_en2 = (port2 & wr_ens); |
| 559 | assign wr_en3 = (port3 & wr_ens); |
| 560 | |
| 561 | wire [`CFIFO_W_R] wr_data = (wr_4words0 | wr_2words0) ? full_cword0 : |
| 562 | (wr_4words1 | wr_2words1) ? full_cword1 : |
| 563 | (wr_4words2 ) ? full_cword2 : |
| 564 | (wr_4words3 ) ? full_cword3 : |
| 565 | full_cword0 ; |
| 566 | |
| 567 | // ECC error injection logic |
| 568 | wire last_line0 = (port0 & (wr_2words1 | wr_4words3)); |
| 569 | wire second_line0 = (port0 & (wr_2words1 | wr_4words1)); |
| 570 | wire first_line0 = (port0 & (wr_2words0 | wr_4words0)); |
| 571 | wire last_line1 = (port1 & (wr_2words1 | wr_4words3)); |
| 572 | wire second_line1 = (port1 & (wr_2words1 | wr_4words1)); |
| 573 | wire first_line1 = (port1 & (wr_2words0 | wr_4words0)); |
| 574 | |
| 575 | ///////////////////////////////////////////////////////////////// |
| 576 | // ifdef between neptune and n2 |
| 577 | ///////////////////////////////////////////////////////////////// |
| 578 | |
| 579 | `ifdef NEPTUNE |
| 580 | wire last_line2 = (port2 & (wr_2words1 | wr_4words3)); |
| 581 | wire second_line2 = (port2 & (wr_2words1 | wr_4words1)); |
| 582 | wire first_line2 = (port2 & (wr_2words0 | wr_4words0)); |
| 583 | wire last_line3 = (port3 & (wr_2words1 | wr_4words3)); |
| 584 | wire second_line3 = (port3 & (wr_2words1 | wr_4words1)); |
| 585 | wire first_line3 = (port3 & (wr_2words0 | wr_4words0)); |
| 586 | wire [1023:0] va_dout; |
| 587 | wire [`ST_R] st_dout; |
| 588 | wire [`DN_R] dn_dout; |
| 589 | wire [9:0] header_len; |
| 590 | wire [9:0] l3_hdr_len; |
| 591 | // vlint flag_dangling_net_within_module off |
| 592 | // vlint flag_net_has_no_load off |
| 593 | wire [23:0] buf_size; |
| 594 | wire [`XPAN_TCP_SEQ_SPACE]TL; |
| 595 | wire [`XPAN_TCP_SEQ_SPACE]S; |
| 596 | wire [`PKT_LEN_R] header_delta; // registered output. |
| 597 | wire [`XPAN_TCP_SEQ_SPACE]UE; |
| 598 | wire TL_bt_UE; |
| 599 | wire TL_eq_UE; |
| 600 | wire qual_ulp_end_fail_reg; |
| 601 | wire [`TCP_SEQ_SPACE]running_anchor_seq; |
| 602 | wire [5:0] first_byte_buf; |
| 603 | wire [20:0] last_byte_buf; |
| 604 | wire [5:0] index0; |
| 605 | wire [5:0] index1; |
| 606 | wire [5:0] index2; |
| 607 | wire [5:0] index3; |
| 608 | wire win_ok; |
| 609 | wire ulp_end_fail; |
| 610 | wire mapped_in_fail; |
| 611 | wire dmaw_threshold_fail; |
| 612 | wire unmap_on_left_oc; |
| 613 | // vlint flag_dangling_net_within_module on |
| 614 | // vlint flag_net_has_no_load on |
| 615 | wire [10:0] dmaw_threshold; |
| 616 | |
| 617 | assign neptune_signature = 1; |
| 618 | |
| 619 | // tcp_payload_len (tcp_segment_len) calculation: |
| 620 | // |
| 621 | // IPv4: tcp_payld_len = ip_pkt_length (16 bits) - ip_hdr_length x 4 bytes - tcp_hdr_length x 4 bytes; |
| 622 | // |
| 623 | // IPv6: tcp_payld_len = ip_payload_length (16 bits) - tcp_hdr_length x 4 bytes; |
| 624 | // |
| 625 | // Generate pkt_off_set for calculating pkt_length for IBTP |
| 626 | wire [15:0] ipv4_hdr_lenx4 = {10'b0,ip_hdr_len, 2'b0}; |
| 627 | wire [15:0] tcp_hdr_lenx4 = {10'b0,tcp_hdr_len,2'b0}; |
| 628 | |
| 629 | /* ----- Start the tt_index registration which is to resolve timing issues ----- */ |
| 630 | // Every ram got its own tt_index as address |
| 631 | // wire [11:0] tt_index ={B6[3:0],B7}; |
| 632 | |
| 633 | // vlint flag_dangling_net_within_module off |
| 634 | // vlint flag_net_has_no_load off |
| 635 | wire [3:0] fflp_data_4va_rsv; |
| 636 | wire [3:0] fflp_data_4dn_rsv; |
| 637 | wire [3:0] fflp_data_4st_rsv; |
| 638 | // vlint flag_dangling_net_within_module on |
| 639 | // vlint flag_net_has_no_load on |
| 640 | |
| 641 | wire [11:0] tt_index_4va; |
| 642 | |
| 643 | dffre #(16) fflp_data_4va_dffre (.clk(clk), |
| 644 | .reset(reset[6]), |
| 645 | .en(ififo_ren[1]), |
| 646 | .d({ififo_dout[`BBYTE6],ififo_dout[`BBYTE7]}), |
| 647 | .q({fflp_data_4va_rsv[3:0],tt_index_4va[11:0]})); |
| 648 | |
| 649 | wire [11:0] tt_index_4dn; |
| 650 | |
| 651 | dffre #(16) fflp_data_4dn_dffre (.clk(clk), |
| 652 | .reset(reset[7]), |
| 653 | .en(ififo_ren[2]), |
| 654 | .d({ififo_dout[`BBYTE6],ififo_dout[`BBYTE7]}), |
| 655 | .q({fflp_data_4dn_rsv[3:0],tt_index_4dn[11:0]})); |
| 656 | |
| 657 | wire [11:0] tt_index_4st; |
| 658 | dffre #(16) fflp_data_4st_dffre (.clk(clk), |
| 659 | .reset(reset[8]), |
| 660 | .en(ififo_ren[2]), |
| 661 | .d({ififo_dout[`BBYTE6],ififo_dout[`BBYTE7]}), |
| 662 | .q({fflp_data_4st_rsv[3:0],tt_index_4st[11:0]})); |
| 663 | /* ----- end of tt_index registration which is to resolve timing issues ----- */ |
| 664 | |
| 665 | |
| 666 | reg [15:0] tcp_payld_len; |
| 667 | always @ (/*AUTOSENSE*/ip_pkt_len or ip_ver or ipv4_hdr_lenx4 |
| 668 | or tcp_hdr_lenx4) |
| 669 | case(ip_ver) |
| 670 | 1'b0: tcp_payld_len = ip_pkt_len[15:0] - ipv4_hdr_lenx4[15:0] - tcp_hdr_lenx4[15:0]; // IPv4 |
| 671 | 1'b1: tcp_payld_len = ip_pkt_len[15:0] - tcp_hdr_lenx4[15:0]; // IPv6 |
| 672 | default:tcp_payld_len = ip_pkt_len[15:0] - ipv4_hdr_lenx4[15:0] - tcp_hdr_lenx4[15:0]; // IPv4 |
| 673 | endcase |
| 674 | |
| 675 | |
| 676 | reg [9:0] l2_hdr_len; |
| 677 | always @ (/*AUTOSENSE*/llc_snap or vlan) |
| 678 | casex({llc_snap,vlan}) |
| 679 | 2'b00: l2_hdr_len = 10'd14; |
| 680 | 2'b01: l2_hdr_len = 10'd18; |
| 681 | 2'b10: l2_hdr_len = 10'd22; |
| 682 | 2'b11: l2_hdr_len = 10'd26; |
| 683 | default:l2_hdr_len = 10'd14; |
| 684 | endcase |
| 685 | |
| 686 | assign l3_hdr_len = ip_ver ? 10'd40 : ipv4_hdr_lenx4[9:0]; |
| 687 | |
| 688 | assign header_len = tcp_hdr_lenx4[9:0] + l3_hdr_len[9:0] + l2_hdr_len[9:0]; |
| 689 | |
| 690 | |
| 691 | /* ------------ instantiations ------------ */ |
| 692 | niu_zcp_tt_dpath niu_zcp_tt_dpath |
| 693 | (/*AUTOINST*/ |
| 694 | // Outputs |
| 695 | .tt_rdc_reg (tt_rdc_reg[7:0]), |
| 696 | .tt_ok_reg (tt_ok_reg[7:0]), |
| 697 | .dmaw_type_reg (dmaw_type_reg[1:0]), |
| 698 | .tt_dmaw_va0_reg (tt_dmaw_va0_reg[`DMA_R]), |
| 699 | .tt_dmaw_len0_reg (tt_dmaw_len0_reg[`PKT_LEN_R]), |
| 700 | .tt_dmaw_va1_reg (tt_dmaw_va1_reg[`DMA_R]), |
| 701 | .tt_dmaw_len1_reg (tt_dmaw_len1_reg[`PKT_LEN_R]), |
| 702 | .tt_dmaw_va2_reg (tt_dmaw_va2_reg[`DMA_R]), |
| 703 | .tt_dmaw_len2_reg (tt_dmaw_len2_reg[`PKT_LEN_R]), |
| 704 | .tt_dmaw_va3_reg (tt_dmaw_va3_reg[`DMA_R]), |
| 705 | .tt_dmaw_len3_reg (tt_dmaw_len3_reg[`PKT_LEN_R]), |
| 706 | .tt_hdr_len_reg (tt_hdr_len_reg[`PKT_LEN_R]), |
| 707 | .first_byte_buf_reg (first_byte_buf_reg[5:0]), |
| 708 | .first_byte_offset_reg (first_byte_offset_reg[23:0]), |
| 709 | .HoQ_reg (HoQ_reg[15:0]), |
| 710 | .wptr_HoQ_reg (wptr_HoQ_reg[15:0]), |
| 711 | .cross_q_end_reg (cross_q_end_reg), |
| 712 | .cross_4KB_reg (cross_4KB_reg), |
| 713 | .ring_size_reg (ring_size_reg[3:0]), |
| 714 | .ring_base_addr_reg (ring_base_addr_reg[38:0]), |
| 715 | .reach_buf_end_reg (reach_buf_end_reg), |
| 716 | .total_num_buf_requested_reg (total_num_buf_requested_reg[5:0]), |
| 717 | .wb_dn_reg (wb_dn_reg[`DN_R]), |
| 718 | .buf_req_ok (buf_req_ok), |
| 719 | .set_tt_program_err (set_tt_program_err), |
| 720 | .buf_size (buf_size[23:0]), |
| 721 | .TL (TL[`XPAN_TCP_SEQ_SPACE]), |
| 722 | .S (S[`XPAN_TCP_SEQ_SPACE]), |
| 723 | .payload_len (payload_len[`PKT_LEN_R]), |
| 724 | .header_delta (header_delta[`PKT_LEN_R]), |
| 725 | .UE (UE[`XPAN_TCP_SEQ_SPACE]), |
| 726 | .TL_bt_UE (TL_bt_UE), |
| 727 | .TL_eq_UE (TL_eq_UE), |
| 728 | .qual_ulp_end_fail_reg (qual_ulp_end_fail_reg), |
| 729 | .running_anchor_seq (running_anchor_seq[`TCP_SEQ_SPACE]), |
| 730 | .first_byte_buf (first_byte_buf[5:0]), |
| 731 | .last_byte_buf (last_byte_buf[20:0]), |
| 732 | .index0 (index0[5:0]), |
| 733 | .index1 (index1[5:0]), |
| 734 | .index2 (index2[5:0]), |
| 735 | .index3 (index3[5:0]), |
| 736 | .win_ok (win_ok), |
| 737 | .ulp_end_fail (ulp_end_fail), |
| 738 | .mapped_in_fail (mapped_in_fail), |
| 739 | .dmaw_threshold_fail (dmaw_threshold_fail), |
| 740 | .unmap_on_left_oc (unmap_on_left_oc), |
| 741 | // Inputs |
| 742 | .clk (clk), |
| 743 | .reset9 (reset9), |
| 744 | .dmaw_threshold (dmaw_threshold[10:0]), |
| 745 | .credit_ok (credit_ok), |
| 746 | .tcp_seq_num (tcp_seq_num[`TCP_SEQ_SPACE]), |
| 747 | .tcp_payld_len (tcp_payld_len[`PKT_LEN_R]), |
| 748 | .header_len (header_len[9:0]), |
| 749 | .tt_index_hi (tt_index_hi[1:0]), |
| 750 | .zcp_tt_index_err_lv (zcp_tt_index_err_lv), |
| 751 | .tt_rd_en4 (tt_rd_en4), |
| 752 | .ld_cal_results (ld_cal_results[21:0]), |
| 753 | .va_dout (va_dout[1023:0]), |
| 754 | .st_dout (st_dout[`ST_R]), |
| 755 | .dn_dout (dn_dout[`DN_R])); |
| 756 | `else // N2 mode |
| 757 | // Unused niu_zcp_tt_dpath signals are driven to 0. |
| 758 | |
| 759 | assign dmaw_type_reg = 0; |
| 760 | assign first_byte_offset_reg = 0; |
| 761 | assign tt_dmaw_len0_reg = 0; |
| 762 | assign tt_dmaw_len1_reg = 0; |
| 763 | assign tt_dmaw_len2_reg = 0; |
| 764 | assign tt_dmaw_len3_reg = 0; |
| 765 | assign tt_dmaw_va0_reg = 0; |
| 766 | assign tt_dmaw_va1_reg = 0; |
| 767 | assign tt_dmaw_va2_reg = 0; |
| 768 | assign tt_dmaw_va3_reg = 0; |
| 769 | assign tt_hdr_len_reg = 0; |
| 770 | assign va_ram_perr = 0; |
| 771 | assign dn_ram_perr = 0; |
| 772 | assign st_ram_perr = 0; |
| 773 | |
| 774 | assign neptune_signature = 0; |
| 775 | assign tt_ok_reg = 0; |
| 776 | assign buf_req_ok = 0; |
| 777 | // error handling |
| 778 | assign wptr_HoQ_reg = 0; |
| 779 | assign HoQ_reg = 0; |
| 780 | assign cross_q_end_reg = 0; |
| 781 | assign cross_4KB_reg = 0; |
| 782 | assign ring_size_reg = 0; |
| 783 | assign ring_base_addr_reg = 0; |
| 784 | assign reach_buf_end_reg = 0; |
| 785 | assign total_num_buf_requested_reg = 0; |
| 786 | assign wb_dn_reg = 0; |
| 787 | // |
| 788 | assign tt_rdc_reg = 0; |
| 789 | assign first_byte_buf_reg = 0; |
| 790 | assign set_tt_program_err = 0; |
| 791 | assign payload_len = 0; |
| 792 | |
| 793 | `endif |
| 794 | |
| 795 | niu_zcp_tt_sm niu_zcp_tt_sm |
| 796 | (/*AUTOINST*/ |
| 797 | // Outputs |
| 798 | .tt_rd_en0 (tt_rd_en0), |
| 799 | .tt_rd_en1 (tt_rd_en1), |
| 800 | .tt_rd_en2 (tt_rd_en2), |
| 801 | .tt_rd_en3 (tt_rd_en3), |
| 802 | .tt_rd_en4 (tt_rd_en4), |
| 803 | .wb_tt0 (wb_tt0), |
| 804 | .wb_tt1 (wb_tt1), |
| 805 | .decode_default_rdc (decode_default_rdc), |
| 806 | .decode_table_rdc (decode_table_rdc), |
| 807 | .decode_zc_rdc (decode_zc_rdc), |
| 808 | .tt_active (tt_active), |
| 809 | .tt_sm_rw (tt_sm_rw), |
| 810 | .ld_cal_results (ld_cal_results[31:0]), |
| 811 | .tt_fail (tt_fail), |
| 812 | .buf_req (buf_req), |
| 813 | .wr_2words (wr_2words), |
| 814 | .wr_4words (wr_4words), |
| 815 | .tt_state (tt_state[3:0]), |
| 816 | // Inputs |
| 817 | .clk (clk), |
| 818 | .reset10 (reset10), |
| 819 | .kickoff_tt (kickoff_tt), |
| 820 | .tt_ok_reg (tt_ok_reg[5:0]), |
| 821 | .tt_en (tt_en), |
| 822 | .zc_mode (zc_mode), |
| 823 | .buf_req_ok (buf_req_ok)); |
| 824 | |
| 825 | /* --------------- spare gates --------------- */ |
| 826 | `ifdef NEPTUNE |
| 827 | wire [3:0] do_nad; |
| 828 | wire [3:0] do_nor; |
| 829 | wire [3:0] do_inv; |
| 830 | wire [3:0] do_mux; |
| 831 | wire [3:0] do_q; |
| 832 | wire so; |
| 833 | |
| 834 | zcp_spare_gates zcp_tt_spare_gates ( |
| 835 | .di_nd3 ({1'h1, 1'h1, do_q[3]}), |
| 836 | .di_nd2 ({1'h1, 1'h1, do_q[2]}), |
| 837 | .di_nd1 ({1'h1, 1'h1, do_q[1]}), |
| 838 | .di_nd0 ({1'h1, 1'h1, do_q[0]}), |
| 839 | .di_nr3 ({1'h0, 1'h0}), |
| 840 | .di_nr2 ({1'h0, 1'h0}), |
| 841 | .di_nr1 ({1'h0, 1'h0}), |
| 842 | .di_nr0 ({1'h0, 1'h0}), |
| 843 | .di_inv (do_nad[3:0]), |
| 844 | .di_mx3 ({1'h0, 1'h0}), |
| 845 | .di_mx2 ({1'h0, 1'h0}), |
| 846 | .di_mx1 ({1'h0, 1'h0}), |
| 847 | .di_mx0 ({1'h0, 1'h0}), |
| 848 | .mx_sel (do_nor[3:0]), |
| 849 | .di_reg (do_inv[3:0]), |
| 850 | .wt_ena (do_mux[3:0]), |
| 851 | .rst (reset[10:7]), |
| 852 | .si (1'h0), |
| 853 | .se (1'h0), |
| 854 | .clk (clk), |
| 855 | .do_nad (do_nad[3:0]), |
| 856 | .do_nor (do_nor[3:0]), |
| 857 | .do_inv (do_inv[3:0]), |
| 858 | .do_mux (do_mux[3:0]), |
| 859 | .do_q (do_q[3:0]), |
| 860 | .so (so) |
| 861 | ); |
| 862 | |
| 863 | `else |
| 864 | `endif |
| 865 | |
| 866 | |
| 867 | endmodule // niu_zcp_tt |
| 868 | |