| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: rgmii_clk_gen.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /************************************************************************* |
| 38 | * |
| 39 | * File Name : rgmii_clk_gen.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : Use 250Mhz ref clk to generate |
| 42 | * 125Mhz, 25Mhz and 2.5Mhz clocks. |
| 43 | * To generate 50% duty cycle, the ref clk has to be 250Mhz. |
| 44 | * |
| 45 | * Parent Module: xmac_2pcs_clk_mux or bmcac_pcs_clk_mux |
| 46 | * Child Module: |
| 47 | * Interface Mod: |
| 48 | * Date Created : 1-1-2003 |
| 49 | * |
| 50 | * Copyright (c) 2008, Sun Microsystems, Inc. |
| 51 | * Sun Proprietary and Confidential |
| 52 | * |
| 53 | * Modification : |
| 54 | * |
| 55 | * Synthesis Notes: |
| 56 | * |
| 57 | *************************************************************************/ |
| 58 | |
| 59 | |
| 60 | |
| 61 | module rgmii_clk_gen ( |
| 62 | ref_clk_250mhz, |
| 63 | reset, |
| 64 | gmii_mode, |
| 65 | sel_clk_25mhz, |
| 66 | // output |
| 67 | tclk_int, |
| 68 | // for observation |
| 69 | toggle, |
| 70 | cnt3, |
| 71 | cnt4, |
| 72 | cnt49 |
| 73 | ); |
| 74 | |
| 75 | input ref_clk_250mhz; |
| 76 | input reset; |
| 77 | input gmii_mode; |
| 78 | input sel_clk_25mhz; |
| 79 | // output |
| 80 | output tclk_int; |
| 81 | // for observation |
| 82 | output toggle; |
| 83 | output cnt3; |
| 84 | output cnt4; |
| 85 | output cnt49; |
| 86 | |
| 87 | wire tclk_int; |
| 88 | wire hw_reset_tclk; |
| 89 | wire d_hw_reset_tclk; |
| 90 | |
| 91 | /* --------------- tx_rgmii_timer -------------------- */ |
| 92 | |
| 93 | SYNC_CELL hw_reset_tclk_SYNC_CELL(.D(reset),.CP(ref_clk_250mhz),.Q(hw_reset_tclk)); |
| 94 | |
| 95 | FD1 d_hw_reset_tclk_FD1(.D(hw_reset_tclk), |
| 96 | .CP(ref_clk_250mhz), |
| 97 | .Q(d_hw_reset_tclk)); |
| 98 | |
| 99 | wire hw_reset_tclk_lead = hw_reset_tclk & ~d_hw_reset_tclk; |
| 100 | // ----------------------------------------------------------------- |
| 101 | // 250Mhz period is 4ns. |
| 102 | // ----------------------------------------------------------------- |
| 103 | |
| 104 | // ----------------------------------------------------------------- |
| 105 | // 25Mhz perios is 40ns. It needs 10, 250Mhz clocks to make 40ns. |
| 106 | // 5 250Mhz clocks for each edge. -> cnt4 |
| 107 | // ----------------------------------------------------------------- |
| 108 | |
| 109 | // ----------------------------------------------------------------- |
| 110 | // 2.5Mhz period is 400ns. It needs 100, 250Mhz clocks to make 400ns. |
| 111 | // 50 250Mhz clocks for each edge. -> cnt49 |
| 112 | // ----------------------------------------------------------------- |
| 113 | |
| 114 | wire [5:0] tx_rgmii_timer; |
| 115 | wire cnt3 = tx_rgmii_timer == 6'd03; |
| 116 | wire cnt4 = tx_rgmii_timer == 6'd04; |
| 117 | wire cnt49 = tx_rgmii_timer == 6'd49; |
| 118 | reg toggle; |
| 119 | |
| 120 | always @ (gmii_mode or sel_clk_25mhz or |
| 121 | cnt4 or cnt49) |
| 122 | begin |
| 123 | if (gmii_mode) |
| 124 | toggle = 1'b1; // 1G mode freq = 125mhz |
| 125 | else if (sel_clk_25mhz) |
| 126 | toggle = cnt4; // 100Mhz freq = 25mhz |
| 127 | else |
| 128 | toggle = cnt49; // 10Mhz freq = 2.5mhz |
| 129 | end |
| 130 | |
| 131 | Counter #(6) tx_rgmii_timer_Counter (.reset(hw_reset_tclk_lead | toggle), |
| 132 | .clk(ref_clk_250mhz), |
| 133 | .ce(1'b1), |
| 134 | .count(tx_rgmii_timer)); |
| 135 | |
| 136 | TFF tclk_int_TFF (.toggle(toggle), |
| 137 | .clk(ref_clk_250mhz), |
| 138 | .reset(hw_reset_tclk_lead), |
| 139 | .qout(tclk_int)); |
| 140 | |
| 141 | |
| 142 | endmodule // rgmii_clk_gen |
| 143 | |