| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: rxfifo_unload.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /************************************************************************* |
| 38 | * |
| 39 | * File Name : rxfifo_unload.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : It contains system clock domain read/write pointer |
| 42 | * management logic and rxmac_ipp_ack, ipp_rxmac_req logic. |
| 43 | * Parent Module: xmac_core |
| 44 | * Child Module: |
| 45 | * Interface Mod: many. |
| 46 | * Date Created : 5/9/00 |
| 47 | * |
| 48 | * Copyright (c) 2002, Sun Microsystems, Inc. |
| 49 | * Sun Proprietary and Confidential |
| 50 | * |
| 51 | * Modification : |
| 52 | * |
| 53 | * Synthesis Notes: |
| 54 | * |
| 55 | *************************************************************************/ |
| 56 | |
| 57 | `include "xmac.h" |
| 58 | |
| 59 | module rxfifo_unload ( |
| 60 | clk, |
| 61 | rx_reset_clk, |
| 62 | // rxfifo stuff |
| 63 | srfifo_g_wr_ptr_sync, |
| 64 | rxfifo_g_wr_ptr_sync, // from rx_clk |
| 65 | rxfifo_dout, |
| 66 | ipp_rxmac_req, |
| 67 | srfifo_dout, |
| 68 | // outputs |
| 69 | // Rx DMA Interface |
| 70 | rxmac_ipp_ack, |
| 71 | rxmac_ipp_tag, |
| 72 | rxmac_ipp_data, |
| 73 | rxmac_ipp_ctrl, |
| 74 | rxmac_ipp_stat, |
| 75 | // rxfifo stuff |
| 76 | rxfifo_g_rd_ptr_clk, // to xmac_sync.v |
| 77 | rxfifo_rd_ptr_clk, |
| 78 | rxfifo_wr_ptr_clk, |
| 79 | rxfifo_underrun_clk, |
| 80 | // srfifo stuff |
| 81 | srfifo_rd_ptr_clk, |
| 82 | // rmon |
| 83 | inc_histo_cntr1, |
| 84 | inc_histo_cntr2, |
| 85 | inc_histo_cntr3, |
| 86 | inc_histo_cntr4, |
| 87 | inc_histo_cntr5, |
| 88 | inc_histo_cntr6, |
| 89 | inc_histo_cntr7, |
| 90 | // for signal observation |
| 91 | rxfifo_full_clk_reg, |
| 92 | rxfifo_empty_clk_reg, |
| 93 | rxfifo_full_space_clk |
| 94 | ); |
| 95 | |
| 96 | |
| 97 | input clk; |
| 98 | input rx_reset_clk; |
| 99 | // rxfifo stuff |
| 100 | input [4:0] srfifo_g_wr_ptr_sync; |
| 101 | input [4:0] rxfifo_g_wr_ptr_sync; // from rx_clk |
| 102 | input [65:0] rxfifo_dout; |
| 103 | input ipp_rxmac_req; |
| 104 | input [`TBITS] srfifo_dout; |
| 105 | // outputs |
| 106 | // Rx DMA Interface |
| 107 | output rxmac_ipp_ack; |
| 108 | output rxmac_ipp_tag; |
| 109 | output [63:0] rxmac_ipp_data; |
| 110 | output rxmac_ipp_ctrl; |
| 111 | output [`TBITS] rxmac_ipp_stat; |
| 112 | // rxfifo stuff |
| 113 | output [4:0] rxfifo_g_rd_ptr_clk; // to xmac_sync.v |
| 114 | output [4:0] rxfifo_rd_ptr_clk; |
| 115 | output [4:0] rxfifo_wr_ptr_clk; |
| 116 | output rxfifo_underrun_clk; |
| 117 | // srfifo stuff |
| 118 | output [4:0] srfifo_rd_ptr_clk; |
| 119 | // rmon |
| 120 | output inc_histo_cntr1; |
| 121 | output inc_histo_cntr2; |
| 122 | output inc_histo_cntr3; |
| 123 | output inc_histo_cntr4; |
| 124 | output inc_histo_cntr5; |
| 125 | output inc_histo_cntr6; |
| 126 | output inc_histo_cntr7; |
| 127 | // for signal observation |
| 128 | output rxfifo_full_clk_reg; |
| 129 | output rxfifo_empty_clk_reg; |
| 130 | output [4:0] rxfifo_full_space_clk; |
| 131 | |
| 132 | wire rxmac_ipp_ack; |
| 133 | wire ipp_rxmac_req; |
| 134 | wire ipp_req; |
| 135 | wire [4:0] srfifo_g_wr_ptr_sync; |
| 136 | wire [4:0] rxfifo_wr_ptr_clk; |
| 137 | wire [4:0] rxfifo_g_rd_ptr_clk,rxfifo_rd_ptr_clk; |
| 138 | wire srfifo_rd_en; |
| 139 | wire new_inc_histo_cntr1,new_inc_histo_cntr2, |
| 140 | new_inc_histo_cntr3,new_inc_histo_cntr4, |
| 141 | new_inc_histo_cntr5,new_inc_histo_cntr6, |
| 142 | new_inc_histo_cntr7; |
| 143 | // alias |
| 144 | wire ctrl_out = rxfifo_dout[65]; |
| 145 | wire tag_out = rxfifo_dout[64]; |
| 146 | wire filterred_ctrl_out; |
| 147 | wire filterred_tag_out; |
| 148 | |
| 149 | // internal signal |
| 150 | wire rxfifo_full_clk; |
| 151 | wire rxfifo_empty_clk; |
| 152 | wire rxfifo_full_clk_reg; |
| 153 | wire rxfifo_empty_clk_reg; |
| 154 | wire rxfifo_rd_en; |
| 155 | wire [4:0] srfifo_rd_ptr_clk; |
| 156 | wire rxmac_ipp_tag_pls; |
| 157 | wire rxmac_ipp_tag_pls_d; |
| 158 | wire rxmac_ipp_tag_pls_d2; |
| 159 | // vlint flag_dangling_net_within_module off |
| 160 | // vlint flag_net_has_no_load off |
| 161 | wire [4:0] srfifo_wr_ptr_clk; |
| 162 | // vlint flag_net_has_no_load on |
| 163 | // vlint flag_dangling_net_within_module on |
| 164 | |
| 165 | /* ----------------------- Rx Burst I/F ----------------------------- */ |
| 166 | // register output signals |
| 167 | RegRst #(1) rxmac_ipp_ack_RegRst (.reset(rx_reset_clk), |
| 168 | .din(rxfifo_rd_en),.clk(clk), |
| 169 | .qout(rxmac_ipp_ack)); |
| 170 | |
| 171 | RegRst #(1) rxmac_ipp_ctrl_RegDff (.reset(rx_reset_clk), |
| 172 | .din(filterred_ctrl_out),.clk(clk), |
| 173 | .qout(rxmac_ipp_ctrl)); |
| 174 | |
| 175 | RegRst #(1) rxmac_ipp_tag_RegDff (.reset(rx_reset_clk), |
| 176 | .din(filterred_tag_out),.clk(clk), |
| 177 | .qout(rxmac_ipp_tag)); |
| 178 | |
| 179 | RegDff #(64) rxmac_ipp_data_RegDff ( |
| 180 | .din(rxfifo_dout[63:0]),.clk(clk), |
| 181 | .qout(rxmac_ipp_data[63:0])); |
| 182 | |
| 183 | // 1st bubble |
| 184 | PlsGen rxmac_ipp_tag_pls_PlsGen(.reset(rx_reset_clk), |
| 185 | .clk(clk), |
| 186 | .iSigIn(rxmac_ipp_tag), |
| 187 | .oPlsOut(rxmac_ipp_tag_pls)); |
| 188 | // 2nd bubble |
| 189 | RegDff #(1) rxmac_ipp_tag_pls_d_RegDff ( |
| 190 | .din(rxmac_ipp_tag_pls),.clk(clk), |
| 191 | .qout(rxmac_ipp_tag_pls_d)); |
| 192 | |
| 193 | // loj eco 3-8-06 |
| 194 | // The following flop will help to create the 3rd bubble |
| 195 | // such that the total bubble is 3 cycles between |
| 196 | // tag de-assertion and next ctl assertion. |
| 197 | RegDff #(1) rxmac_ipp_tag_pls_d2_RegDff ( |
| 198 | .din (rxmac_ipp_tag_pls_d),.clk(clk), |
| 199 | .qout(rxmac_ipp_tag_pls_d2)); |
| 200 | |
| 201 | RegDff #(`TBITS_WIDTH) rxmac_ipp_stat_RegDff ( |
| 202 | .din(srfifo_dout[`TBITS]),.clk(clk), |
| 203 | .qout(rxmac_ipp_stat[`TBITS])); |
| 204 | |
| 205 | /* ------------------------------------------------------------------ */ |
| 206 | |
| 207 | /* --------------- start rxfifo pointer Management ------------------ */ |
| 208 | // It is possible that the rxfifo underrun_clk when ipp is not following rules. |
| 209 | RegDff #(1) ipp_req_RegDff (.din(ipp_rxmac_req),.clk(clk), |
| 210 | .qout(ipp_req)); |
| 211 | |
| 212 | assign rxfifo_underrun_clk = rxfifo_rd_en & rxfifo_empty_clk; |
| 213 | |
| 214 | // loj eco 3-8-06 |
| 215 | assign rxfifo_rd_en = ipp_req & (~rxfifo_empty_clk) & |
| 216 | (~rxmac_ipp_tag_pls) & (~rxmac_ipp_tag_pls_d) & (~rxmac_ipp_tag_pls_d2); |
| 217 | |
| 218 | // Rxfifo write Pointer, wr_ptr from rx_clk |
| 219 | g2b_5bit rxfifo_wr_ptr_clk_g2b_5bit(.g_cnt(rxfifo_g_wr_ptr_sync), |
| 220 | .b_cnt(rxfifo_wr_ptr_clk)); |
| 221 | |
| 222 | // Rxfifo G read Pointer, g_wr_ptr to sysclk |
| 223 | g_cntr_5bit rxfifo_g_rd_ptr_clk_g_cntr_5bit( |
| 224 | .reset(rx_reset_clk), |
| 225 | .clk(clk), |
| 226 | .ce(rxfifo_rd_en), |
| 227 | .g_cnt(rxfifo_g_rd_ptr_clk)); |
| 228 | |
| 229 | // Rxfifo Read Pointer |
| 230 | g2b_5bit rxfifo_g2b_5bit(.g_cnt(rxfifo_g_rd_ptr_clk), |
| 231 | .b_cnt(rxfifo_rd_ptr_clk)); |
| 232 | |
| 233 | assign rxfifo_full_clk = (rxfifo_wr_ptr_clk[4] == (!rxfifo_rd_ptr_clk[4])) && |
| 234 | (rxfifo_wr_ptr_clk[3:0] == rxfifo_rd_ptr_clk[3:0]); |
| 235 | |
| 236 | FD1 rxfifo_full_clk_reg_FD1 (.D(rxfifo_full_clk), .CP(clk),.Q(rxfifo_full_clk_reg)); |
| 237 | |
| 238 | assign rxfifo_empty_clk = (rxfifo_wr_ptr_clk[4:0] == rxfifo_rd_ptr_clk[4:0]); |
| 239 | |
| 240 | FD1 rxfifo_empty_clk_reg_FD1(.D(rxfifo_empty_clk),.CP(clk),.Q(rxfifo_empty_clk_reg)); |
| 241 | |
| 242 | wire [4:0] rxfifo_full_space_clk = (rxfifo_wr_ptr_clk[4] == rxfifo_rd_ptr_clk[4]) ? |
| 243 | ({1'b0,rxfifo_wr_ptr_clk[3:0]} - {1'b0,rxfifo_rd_ptr_clk[3:0]}) : |
| 244 | (16 - ({1'b0,rxfifo_rd_ptr_clk[3:0]} - {1'b0,rxfifo_wr_ptr_clk[3:0]})); |
| 245 | |
| 246 | // wire [4:0] rxfifo_rd_ptr_plus_1 = rxfifo_rd_ptr_clk + 1; |
| 247 | // wire rxfifo_aempty =(rxfifo_wr_ptr_clk[4:0] == rxfifo_rd_ptr_plus_1[4:0]); |
| 248 | |
| 249 | /* --------------- end of rxfifo pointer Management ----------------- */ |
| 250 | |
| 251 | /* --------------- start srfifo pointer Management ------------------ */ |
| 252 | // srfifo write Pointer, wr_ptr from rx_clk |
| 253 | g2b_5bit srfifo_wr_ptr_g2b_5bit(.g_cnt(srfifo_g_wr_ptr_sync), |
| 254 | .b_cnt(srfifo_wr_ptr_clk)); |
| 255 | |
| 256 | // srfifo Read Pointer |
| 257 | assign filterred_tag_out = rxfifo_rd_en & tag_out; |
| 258 | assign filterred_ctrl_out = rxfifo_rd_en & ctrl_out; |
| 259 | |
| 260 | assign srfifo_rd_en = (filterred_tag_out | filterred_ctrl_out); |
| 261 | |
| 262 | counter_X5 srfifo_rd_ptr_counter_X5(.clk(clk), |
| 263 | .clr(rx_reset_clk), |
| 264 | .enable(srfifo_rd_en), |
| 265 | .count(srfifo_rd_ptr_clk)); |
| 266 | |
| 267 | /* --------------- end of srfifo pointer Management ----------------- */ |
| 268 | |
| 269 | |
| 270 | /* ---------------------------- RMON Support ------------------------ */ |
| 271 | assign new_inc_histo_cntr1 = rxmac_ipp_tag & |
| 272 | (rxmac_ipp_stat[13:0] == 14'h40); |
| 273 | assign new_inc_histo_cntr2 = rxmac_ipp_tag & |
| 274 | (rxmac_ipp_stat[13:0] > 14'h40) & |
| 275 | (rxmac_ipp_stat[13:0] <= 14'h7F); |
| 276 | assign new_inc_histo_cntr3 = rxmac_ipp_tag & |
| 277 | (rxmac_ipp_stat[13:0] > 14'h7F) & |
| 278 | (rxmac_ipp_stat[13:0] <= 14'hFF); |
| 279 | assign new_inc_histo_cntr4 = rxmac_ipp_tag & |
| 280 | (rxmac_ipp_stat[13:0] > 14'hFF) & |
| 281 | (rxmac_ipp_stat[13:0] <= 14'h1FF); |
| 282 | assign new_inc_histo_cntr5 = rxmac_ipp_tag & |
| 283 | (rxmac_ipp_stat[13:0] > 14'h1FF) & |
| 284 | (rxmac_ipp_stat[13:0] <= 14'h3FF); |
| 285 | assign new_inc_histo_cntr6 = rxmac_ipp_tag & |
| 286 | (rxmac_ipp_stat[13:0] > 14'h3FF) & |
| 287 | (rxmac_ipp_stat[13:0] <= 14'h5F2); |
| 288 | assign new_inc_histo_cntr7 = rxmac_ipp_tag & |
| 289 | (rxmac_ipp_stat[13:0] > 14'h5F2); |
| 290 | FD1 INC_HIST_CNTR1_FF(.D(new_inc_histo_cntr1),.CP(clk),.Q(inc_histo_cntr1)); |
| 291 | FD1 INC_HIST_CNTR2_FF(.D(new_inc_histo_cntr2),.CP(clk),.Q(inc_histo_cntr2)); |
| 292 | FD1 INC_HIST_CNTR3_FF(.D(new_inc_histo_cntr3),.CP(clk),.Q(inc_histo_cntr3)); |
| 293 | FD1 INC_HIST_CNTR4_FF(.D(new_inc_histo_cntr4),.CP(clk),.Q(inc_histo_cntr4)); |
| 294 | FD1 INC_HIST_CNTR5_FF(.D(new_inc_histo_cntr5),.CP(clk),.Q(inc_histo_cntr5)); |
| 295 | FD1 INC_HIST_CNTR6_FF(.D(new_inc_histo_cntr6),.CP(clk),.Q(inc_histo_cntr6)); |
| 296 | FD1 INC_HIST_CNTR7_FF(.D(new_inc_histo_cntr7),.CP(clk),.Q(inc_histo_cntr7)); |
| 297 | |
| 298 | |
| 299 | /* ------------------------------------------------------------------------- */ |
| 300 | |
| 301 | |
| 302 | endmodule // rxfifo_unload |
| 303 | |
| 304 | |
| 305 | /********************************************************** |
| 306 | * |
| 307 | * tag ctrl srfifo_rd_ptr |
| 308 | * ---- ---- ------------- |
| 309 | * 0 0 no change |
| 310 | * |
| 311 | * 0 1 inc 1 |
| 312 | * |
| 313 | * 1 0 inc 1 |
| 314 | * |
| 315 | * 1 1 inc 1 |
| 316 | * ------------------------- |
| 317 | * |
| 318 | * rxfifo_rd_en is controlled by ipp_rxmac_req only. |
| 319 | * assign rxfifo_rd_en = ipp_rxmac_req & ~rxfifo_empty_clk; |
| 320 | * |
| 321 | * |
| 322 | * ******************************************************/ |
| 323 | |
| 324 | |
| 325 | |
| 326 | |
| 327 | |
| 328 | |