| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fgu.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module fgu ( |
| 36 | dec_frf_r1_addr_d, |
| 37 | dec_frf_r2_addr_d, |
| 38 | dec_frf_r1_vld_d, |
| 39 | dec_frf_r2_vld_d, |
| 40 | dec_frf_r1_32b_d, |
| 41 | dec_frf_r2_32b_d, |
| 42 | dec_frf_r1_odd32b_d, |
| 43 | dec_frf_r2_odd32b_d, |
| 44 | dec_frf_w_vld_d, |
| 45 | dec_frf_w_addr_d, |
| 46 | dec_frf_w_32b_d, |
| 47 | dec_frf_w_odd32b_d, |
| 48 | dec_spu_grant_d, |
| 49 | dec_exu_src_vld_d, |
| 50 | dec_irf_w_addr_d, |
| 51 | dec_frf_store_d, |
| 52 | dec_fsr_store_d, |
| 53 | dec_valid_e, |
| 54 | dec_fgu_op3_d, |
| 55 | dec_fgu_opf_d, |
| 56 | dec_fgu_fmov_vld_m, |
| 57 | dec_fgu_decode_d, |
| 58 | dec_fgu_valid_e, |
| 59 | dec_fgu_tid_d, |
| 60 | dec_flush_f1, |
| 61 | dec_flush_f2, |
| 62 | fgu_cmp_fcc_fx3, |
| 63 | fgu_cmp_fcc_vld_fx3, |
| 64 | fgu_cmp_fcc_tid_fx2, |
| 65 | fgu_fld_fcc_fx3, |
| 66 | fgu_fld_fcc_vld_fx3, |
| 67 | fgu_fprs_fef, |
| 68 | fgu_fdiv_stall, |
| 69 | fgu_idiv_stall, |
| 70 | fgu_divide_completion, |
| 71 | tlu_flush_fgu_b, |
| 72 | tlu_ceter_pscce, |
| 73 | tlu_cerer_frf, |
| 74 | spc_core_running_status, |
| 75 | fgu_predict_fx2, |
| 76 | fgu_pdist_beat2_fx1, |
| 77 | fgu_cecc_fx2, |
| 78 | fgu_uecc_fx2, |
| 79 | fgu_ecc_addr_fx2, |
| 80 | fgu_ecc_check_fx2, |
| 81 | fgu_fpx_ieee_trap_fw, |
| 82 | fgu_fpd_ieee_trap_fw, |
| 83 | fgu_fpx_unfin_fw, |
| 84 | fgu_fpd_unfin_fw, |
| 85 | fgu_fpd_idiv0_trap_fw, |
| 86 | fgu_fpx_trap_tid_fw, |
| 87 | fgu_fpd_trap_tid_fw, |
| 88 | lsu_fgu_fld_data_b, |
| 89 | lsu_fgu_fld_addr_b, |
| 90 | lsu_fgu_fld_vld_w, |
| 91 | lsu_fgu_fld_b, |
| 92 | lsu_fgu_fld_tid_b, |
| 93 | lsu_fgu_fld_32b_b, |
| 94 | lsu_fgu_fld_odd32b_b, |
| 95 | lsu_fgu_fsr_load_b, |
| 96 | lsu_fgu_exception_w, |
| 97 | lsu_block_store_m, |
| 98 | lsu_asi_error_inject, |
| 99 | lsu_fgu_pmen, |
| 100 | lsu_asi_clken, |
| 101 | fgu_lsu_fst_data_fx1, |
| 102 | fgu_fst_ecc_error_fx2, |
| 103 | exu_fgu_rs1_e, |
| 104 | exu_fgu_rs2_e, |
| 105 | exu_fgu_gsr_m, |
| 106 | exu_fgu_gsr_vld_m, |
| 107 | exu_fgu_flush_m, |
| 108 | fgu_exu_icc_fx5, |
| 109 | fgu_exu_xcc_fx5, |
| 110 | fgu_exu_cc_vld_fx5, |
| 111 | fgu_exu_w_vld_fx5, |
| 112 | fgu_result_tid_fx5, |
| 113 | fgu_irf_w_addr_fx5, |
| 114 | fgu_exu_result_fx5, |
| 115 | spu_fgu_fpy_ctl_d, |
| 116 | spu_fgu_rs1_e, |
| 117 | spu_fgu_rs2_e, |
| 118 | fgu_accum_b0_fx5, |
| 119 | fgu_mul_result_fx5, |
| 120 | l2clk, |
| 121 | scan_in, |
| 122 | spc_aclk_wmr, |
| 123 | wmr_scan_in, |
| 124 | lb_scan_en_wmr, |
| 125 | tcu_pce_ov, |
| 126 | spc_aclk, |
| 127 | spc_bclk, |
| 128 | tcu_muxtest, |
| 129 | tcu_dectest, |
| 130 | tcu_scan_en, |
| 131 | tcu_array_wr_inhibit, |
| 132 | tcu_se_scancollar_in, |
| 133 | tcu_se_scancollar_out, |
| 134 | mbi_frf_read_en, |
| 135 | mbi_frf_write_en, |
| 136 | mbi_addr, |
| 137 | mbi_wdata, |
| 138 | mbi_run, |
| 139 | in_rngl_cdbus, |
| 140 | fgu_mbi_frf_fail, |
| 141 | fgu_rngl_cdbus, |
| 142 | scan_out, |
| 143 | wmr_scan_out); |
| 144 | wire fpf_scanin; |
| 145 | wire fpf_scanout; |
| 146 | wire [4:0] fad_fsr_tem_fx1; |
| 147 | wire fpy_scanin; |
| 148 | wire fpy_scanout; |
| 149 | wire fpe_scanin; |
| 150 | wire fpe_scanout; |
| 151 | wire fpc_wmr_scanin; |
| 152 | wire fpc_wmr_scanout; |
| 153 | wire fpc_scanin; |
| 154 | wire fpc_scanout; |
| 155 | wire [63:0] fad_rs1_fmt_fx1; |
| 156 | wire [63:0] fad_rs2_fmt_fx1; |
| 157 | wire fdc_finish_int_early_rep0; |
| 158 | wire fdc_finish_fltd_early_rep0; |
| 159 | wire fdc_finish_flts_early_rep0; |
| 160 | wire fpf_bze0_fx1; |
| 161 | wire fpf_boe0_fx1; |
| 162 | wire fpf_bzf0_fx1; |
| 163 | wire fpf_aze0_fx1; |
| 164 | wire fpf_aoe0_fx1; |
| 165 | wire fpf_azf0_fx1; |
| 166 | wire main_clken0; |
| 167 | wire fic_scanin; |
| 168 | wire fic_scanout; |
| 169 | wire fgd_wmr_scanin; |
| 170 | wire fgd_wmr_scanout; |
| 171 | wire fgd_scanin; |
| 172 | wire fgd_scanout; |
| 173 | wire fdd_scanin; |
| 174 | wire fdd_scanout; |
| 175 | wire fdc_scanin; |
| 176 | wire fdc_scanout; |
| 177 | wire fpf_hi_bof_fx1_rep0; |
| 178 | wire fpf_lo_bof_fx1_rep0; |
| 179 | wire fpe_rs2_fmt_fx1_b0_rep0; |
| 180 | wire div_clken_rep0; |
| 181 | wire fac_div_valid_fx1_rep0; |
| 182 | wire fac_divq_valid_fx1_rep0; |
| 183 | wire [4:0] fac_div_control_fx1_rep0; |
| 184 | wire fad_wmr_scanin; |
| 185 | wire fad_wmr_scanout; |
| 186 | wire fad_scanin; |
| 187 | wire fad_scanout; |
| 188 | wire fac_wmr_scanin; |
| 189 | wire fac_wmr_scanout; |
| 190 | wire fac_scanin; |
| 191 | wire fac_scanout; |
| 192 | wire fec_scanin; |
| 193 | wire fec_scanout; |
| 194 | wire frf_scanin; |
| 195 | wire frf_scanout; |
| 196 | wire [4:0] fac_w1_addr_fb; |
| 197 | wire [2:0] fac_w1_tid_fb; |
| 198 | wire [1:0] fpc_w1_vld_fb; |
| 199 | wire [4:0] fad_w2_addr_fw; |
| 200 | wire [2:0] fad_w2_tid_fw; |
| 201 | wire [1:0] fad_w2_vld_fw; |
| 202 | wire [63:0] fpf_w1_result_fb; |
| 203 | wire [13:0] fpf_w1_synd_fb; |
| 204 | wire [63:0] fad_w2_result_fw; |
| 205 | wire [13:0] fec_w2_synd_fw; |
| 206 | wire [2:0] fac_tid_d; |
| 207 | wire fac_frf_r1_vld_d; |
| 208 | wire [4:0] fac_frf_r1_addr_d; |
| 209 | wire [63:0] frf_r1_data_e; |
| 210 | wire [13:0] frf_r1_ecc_e; |
| 211 | wire [63:0] frf_r2_data_e; |
| 212 | wire [13:0] frf_r2_ecc_e; |
| 213 | wire [63:0] fad_rs1_fmt_fx1_rep0; |
| 214 | wire [63:0] fad_rs1_fmt_fx1_rep01; |
| 215 | wire [63:0] fad_rs2_fmt_fx1_rep0; |
| 216 | wire [63:0] fad_rs2_fmt_fx1_rep01; |
| 217 | wire [63:0] fad_rs2_fmt_fx1_rep1; |
| 218 | wire [63:0] fdd_result; |
| 219 | wire [62:11] fdd_result_rep0; |
| 220 | wire fpf_hi_bof_fx1; |
| 221 | wire fpf_lo_bof_fx1; |
| 222 | wire [10:0] fpe_rs2_fmt_fx1; |
| 223 | wire mul_clken; |
| 224 | wire div_clken; |
| 225 | wire mul_clken_rep0; |
| 226 | wire mul_clken_rep01; |
| 227 | wire fac_div_valid_fx1; |
| 228 | wire fac_divq_valid_fx1; |
| 229 | wire [4:0] fac_div_control_fx1; |
| 230 | wire fdc_finish_int_early; |
| 231 | wire fdc_finish_fltd_early; |
| 232 | wire fdc_finish_flts_early; |
| 233 | wire [63:0] fad_rs1_fx1; |
| 234 | wire [63:0] fad_rs2_fx1; |
| 235 | wire fad_r1_odd32b_fx1; |
| 236 | wire [63:0] fgd_result_fx5; |
| 237 | wire [5:1] fpc_int_res_sel_fx4; |
| 238 | wire [3:0] fpc_vis_cmp_result_fx5; |
| 239 | wire [5:0] fpc_result_sel_fx5; |
| 240 | wire [1:0] fpc_ovf_if_rcout_fx5; |
| 241 | wire [4:0] fpc_ma_fmt_sel_fx4; |
| 242 | wire [3:0] fpc_int_sel_fx5; |
| 243 | wire [4:0] fpc_fconst_sel_fx5; |
| 244 | wire fpc_fp_cin00_fx2; |
| 245 | wire fpc_cin00_fx2; |
| 246 | wire fpc_cin16_48_fx2; |
| 247 | wire fpc_cin32_fx2; |
| 248 | wire fpc_prop16_48_fx2; |
| 249 | wire fpc_prop32_fx2; |
| 250 | wire fpc_mle_sel_fx2; |
| 251 | wire [2:0] fpc_mse_sel_fx2; |
| 252 | wire fpc_sign_fx5; |
| 253 | wire fpc_sign_fb; |
| 254 | wire fpc_sp_dest_fx4; |
| 255 | wire fpc_fadd_eac_enable_fx2; |
| 256 | wire [3:2] fpc_i2f_sel_fx1; |
| 257 | wire fpc_rinc_sel_fx5; |
| 258 | wire fpc_qthenan_fx4; |
| 259 | wire fpc_den2nor_sp_fb; |
| 260 | wire fpc_den2nor_dp_fb; |
| 261 | wire [3:0] fpf_b_gteq_a_fx2; |
| 262 | wire [3:0] fpf_b_eq_a_fx2; |
| 263 | wire fpf_hi_aof_fx1; |
| 264 | wire fpf_lo_aof_fx1; |
| 265 | wire [63:0] fpf_ma_sum_fx4; |
| 266 | wire fpf_ma_cout_fx4; |
| 267 | wire fpf_cmp_swap_blta_fx2; |
| 268 | wire fpf_align_sticky_fx4_l; |
| 269 | wire [1:0] fpf_byte_unsure_x_sp_fx3; |
| 270 | wire [1:0] fpf_byte_unsure_x_dp_fx3; |
| 271 | wire [5:0] fic_norm_eadj_fx5; |
| 272 | wire [5:0] fic_i2f_align_sel_fx2; |
| 273 | wire [63:0] fpf_rs2_cmp_din_fx1; |
| 274 | wire [38:32] fpf_man_se_byte_fx3_b38_32; |
| 275 | wire [6:0] fpf_man_se_byte_fx3_b6_0; |
| 276 | wire fac_tlu_flush_fx3; |
| 277 | wire fac_fpx_sp_dest_fx1; |
| 278 | wire fac_fpx_sp_src_fx1; |
| 279 | wire [3:0] fac_pre_fcc_vld_fx2; |
| 280 | wire fac_fcmpe_fx1; |
| 281 | wire [4:0] fac_rs2_rotate_sel_e; |
| 282 | wire [1:0] fac_i2f_sel_e; |
| 283 | wire fac_force_swap_blta_fx1; |
| 284 | wire fac_force_noswap_blta_fx1; |
| 285 | wire main_clken; |
| 286 | wire fpy_fp_result_fx4_b63; |
| 287 | wire fpf_sa_xor_sb_fx1; |
| 288 | wire [10:0] fpe_exp_res_fb; |
| 289 | wire [10:0] fpe_align_sel_fx2; |
| 290 | wire fpf_rcout_fx5; |
| 291 | wire fpf_rcout_fb; |
| 292 | wire fpf_implied_bit_fx5; |
| 293 | wire [6:0] fec_w1_ecc_inject_fb; |
| 294 | wire fac_xr_mode_fx1; |
| 295 | wire [4:0] fac_rs1_sel_fx1; |
| 296 | wire [3:0] fac_rs2_sel_fx1; |
| 297 | wire [1:0] fac_8x16_rnd_fx3; |
| 298 | wire [3:0] fac_scff_sel_fx3; |
| 299 | wire [6:0] fac_accum_sel_fx3; |
| 300 | wire [5:0] fac_result_sel_fx4; |
| 301 | wire fac_ma_result_en_fx4; |
| 302 | wire fpy_sticky_dp_fx5; |
| 303 | wire fpy_sticky_sp_fx5; |
| 304 | wire [1:0] fpy_xicc_z_fx5; |
| 305 | wire [9:0] fac_aexp_fmt_sel_e; |
| 306 | wire [7:0] fac_bexp_fmt_sel_e; |
| 307 | wire fac_aux_cin_fx1; |
| 308 | wire fpc_exp_sel_mul_fx5; |
| 309 | wire [3:0] fpc_eintx_sel_fx2; |
| 310 | wire [2:0] fpc_eadjx_sel_fx2; |
| 311 | wire fpc_q_rinc_sel_fx5; |
| 312 | wire fpe_aux_rs2_fmt_fx1_b0; |
| 313 | wire [11:0] fpe_aux_eint_fx1; |
| 314 | wire [10:0] fpe_rs1_fmt_fx1; |
| 315 | wire fpe_einty_adj_cout_fx5; |
| 316 | wire fpe_einty_eq_eadj_fx5; |
| 317 | wire [5:0] fic_i2f_eadj_fx2; |
| 318 | wire fpc_fpd_ieee_trap_fb; |
| 319 | wire fpc_fpx_unfin_fb; |
| 320 | wire fpc_fpd_unfin_fb; |
| 321 | wire [1:0] fad_fsr_rd_fx1; |
| 322 | wire fad_fsr_ns_fx1; |
| 323 | wire [2:0] fad_gsr_imirnd_fx1; |
| 324 | wire fpc_w1_ul_vld_fb; |
| 325 | wire [1:0] fpc_fsr_w1_vld_fx5; |
| 326 | wire [11:0] fpc_fsr_w1_result_fw; |
| 327 | wire [11:0] fpc_fsr_w2_result_fw; |
| 328 | wire [10:0] fpc_fpd_exp_res; |
| 329 | wire fpc_fpd_sign_res; |
| 330 | wire [1:0] fpc_fpd_const_sel; |
| 331 | wire [1:0] fpc_fcc_fw; |
| 332 | wire [1:0] fpc_rd_mode_fx3; |
| 333 | wire fpc_emin_fx3; |
| 334 | wire [2:0] fac_tid_e; |
| 335 | wire fac_dec_valid_fx1; |
| 336 | wire [2:0] fac_fpx_itype_fx1; |
| 337 | wire [2:0] fac_fpx_dtype_fx1; |
| 338 | wire [1:0] fac_fpx_stype_fx1; |
| 339 | wire fac_fpx_sign_instr_fx1; |
| 340 | wire fac_fpx_rnd_trunc_fx1; |
| 341 | wire fac_fpx_mulscc_fx1; |
| 342 | wire fac_fpx_saverestore_fx1; |
| 343 | wire fac_fgx_pdist_fx1; |
| 344 | wire fac_fgx_popc_fx2; |
| 345 | wire fac_fgx_mvcond_fx2; |
| 346 | wire fac_fgx_mvucond_fx2; |
| 347 | wire fac_fgx_abs_fx2; |
| 348 | wire fac_fgx_neg_fx2; |
| 349 | wire fac_fpx_nv_vld_fx1; |
| 350 | wire fac_fpx_of_vld_fx1; |
| 351 | wire fac_fpx_uf_vld_fx1; |
| 352 | wire fac_fpx_dz_vld_fx1; |
| 353 | wire fac_fpx_nx_vld_fx1; |
| 354 | wire fac_fpx_unfin_vld_fx1; |
| 355 | wire fac_fgx_instr_fx4; |
| 356 | wire [1:0] fac_w1_vld_fx1; |
| 357 | wire fac_w1_odd32b_fx1; |
| 358 | wire [4:1] fac_opf_fx2; |
| 359 | wire fac_fgx_siam_fx2; |
| 360 | wire fac_fsr_store_fx2; |
| 361 | wire [2:0] fac_gsr_asr_tid_fx2; |
| 362 | wire fac_rng_wr_gsr_3f; |
| 363 | wire [1:0] fac_gsr_w_vld_fx2; |
| 364 | wire fac_dec_valid_noflush_fx5; |
| 365 | wire fac_exu_src_e; |
| 366 | wire coreon_clken; |
| 367 | wire [3:0] fpc_fcc_vld_fx5; |
| 368 | wire fpc_stfsr_en_fx3to5; |
| 369 | wire fic_mulscc_iccz_fx4; |
| 370 | wire fic_mulscc_xccz_fx4; |
| 371 | wire fic_convert_sticky_fx4; |
| 372 | wire fic_fxtod_sticky_fx4; |
| 373 | wire fic_ftoi_nx_fx4; |
| 374 | wire fic_ftox_nx_fx4; |
| 375 | wire fic_bzf31msb_fx2; |
| 376 | wire fic_bzf32lsb_fx2; |
| 377 | wire fic_bof22msb_fx2; |
| 378 | wire fpc_lzd_override_fx4; |
| 379 | wire fpc_sp_source_fx3; |
| 380 | wire fdc_flt_inexact; |
| 381 | wire [1:0] fdc_xicc_z_early; |
| 382 | wire fdc_icc_v_early; |
| 383 | wire fdc_dec_exp_early; |
| 384 | wire fpc_pre_div_flush_fx2; |
| 385 | wire fpc_div_default_res_fx2; |
| 386 | wire fdd_pte_cla_early_b63; |
| 387 | wire fec_cecc_fx2; |
| 388 | wire fec_uecc_fx2; |
| 389 | wire fpc_frf_store_vld_fx1; |
| 390 | wire [1:0] fpc_gsr0_mask_sel_fx3; |
| 391 | wire [1:0] fpc_gsr1_mask_sel_fx3; |
| 392 | wire [1:0] fpc_gsr2_mask_sel_fx3; |
| 393 | wire [1:0] fpc_gsr3_mask_sel_fx3; |
| 394 | wire [1:0] fpc_gsr4_mask_sel_fx3; |
| 395 | wire [1:0] fpc_gsr5_mask_sel_fx3; |
| 396 | wire [1:0] fpc_gsr6_mask_sel_fx3; |
| 397 | wire [1:0] fpc_gsr7_mask_sel_fx3; |
| 398 | wire [4:0] fpc_gsr_scale_fx4; |
| 399 | wire [2:0] fpc_gsr_align_fx4; |
| 400 | wire [10:0] fpc_gsr_asr_11bits_fx4; |
| 401 | wire [62:0] fgd_rngl_cdbus_3f; |
| 402 | wire vis_clken; |
| 403 | wire fac_fgx_logical_fx2; |
| 404 | wire fac_fgx_expand_fx2; |
| 405 | wire fac_fgx_merge_fx2; |
| 406 | wire fac_fgx_align_fx2; |
| 407 | wire fac_fgx_shuffle_fx2; |
| 408 | wire fac_fgx_pack16_fx2; |
| 409 | wire fac_fgx_pack32_fx2; |
| 410 | wire fac_fgx_packfix_fx2; |
| 411 | wire fac_fgx_pack_sel_fx2; |
| 412 | wire [2:0] fac_tid_fx2; |
| 413 | wire [2:0] fac_rng_fprs; |
| 414 | wire fac_rng_rd_fprs_4f; |
| 415 | wire fac_rng_rd_gsr_4f; |
| 416 | wire [13:0] fec_r1_ecc_fx1; |
| 417 | wire fac_rng_rd_ecc_4f; |
| 418 | wire fac_rng_rd_or_wr_3f; |
| 419 | wire asi_clken; |
| 420 | wire fgd_gsr_asr_mask_fx4_b31; |
| 421 | wire fdc_asign_lth; |
| 422 | wire fdc_bsign_lth; |
| 423 | wire fdc_bsign_lth_; |
| 424 | wire fdc_pe_cycle3; |
| 425 | wire fdc_pe_cmux_sel; |
| 426 | wire [2:0] fdc_pe_smux_sel; |
| 427 | wire [5:0] fdc_pe_xsht_ctl; |
| 428 | wire fdc_ie_fsqrt_valid_even; |
| 429 | wire fdc_ie_fsqrt_valid_even_; |
| 430 | wire fdc_ie_fsqrt_valid_odd; |
| 431 | wire fdc_ie_fsqrt_valid_odd_; |
| 432 | wire [4:0] fdc_ie_rmux_sel; |
| 433 | wire [2:0] fdc_ie_dmux_sel; |
| 434 | wire fdc_flt_increment; |
| 435 | wire [1:0] fdc_pte_clasel; |
| 436 | wire fdc_pte_csa_cin; |
| 437 | wire fdc_pte_cycle2; |
| 438 | wire fdc_emin_lth; |
| 439 | wire [2:0] fdc_pte_qsel; |
| 440 | wire fdc_pte_stall_; |
| 441 | wire [1:0] fdc_flt_round; |
| 442 | wire [4:0] fdc_idiv_ctl; |
| 443 | wire fdc_fdx_cin_in; |
| 444 | wire [2:0] fdc_qsel00; |
| 445 | wire [2:0] fdc_qsel1; |
| 446 | wire [1:0] fdc_q_in; |
| 447 | wire [1:0] fdc_qm1_in; |
| 448 | wire [63:0] fdd_pe_clth; |
| 449 | wire fdd_cla_zero32_; |
| 450 | wire fdd_cla_zero64_; |
| 451 | wire fdd_fdx_din0; |
| 452 | wire fdd_fdx_din1; |
| 453 | wire fdd_fdx_cin64; |
| 454 | wire [4:0] fdd_fdq00_10_sum; |
| 455 | wire [4:0] fdd_fdq00_10_carry; |
| 456 | wire [3:0] fdd_fdq1p_sum; |
| 457 | wire [3:0] fdd_fdq1p_carry; |
| 458 | wire [3:0] fdd_fdq1n_sum; |
| 459 | wire [3:0] fdd_fdq1n_carry; |
| 460 | wire fac_div_flush_fx3; |
| 461 | wire [4:0] fac_frf_r1_addr_e; |
| 462 | wire [4:0] fac_aman_fmt_sel_e; |
| 463 | wire [4:0] fac_bman_fmt_sel_e; |
| 464 | wire [3:0] fac_fst_fmt_sel_fx1; |
| 465 | wire [4:0] fac_fpd_addr_fb; |
| 466 | wire fac_w1_32b_fb; |
| 467 | wire fac_fpd_32b_fb; |
| 468 | wire fac_w1_odd32b_fb; |
| 469 | wire fac_fpd_odd32b_fb; |
| 470 | wire [2:0] fac_fpd_tid_fb; |
| 471 | wire [5:0] fac_fsr0_sel_fw; |
| 472 | wire [5:0] fac_fsr1_sel_fw; |
| 473 | wire [5:0] fac_fsr2_sel_fw; |
| 474 | wire [5:0] fac_fsr3_sel_fw; |
| 475 | wire [5:0] fac_fsr4_sel_fw; |
| 476 | wire [5:0] fac_fsr5_sel_fw; |
| 477 | wire [5:0] fac_fsr6_sel_fw; |
| 478 | wire [5:0] fac_fsr7_sel_fw; |
| 479 | wire fad_w2_addr_fw1_b4; |
| 480 | wire [2:0] fad_w2_tid_fw1; |
| 481 | wire [1:0] fad_w2_vld_fw1; |
| 482 | wire [2:0] fad_w1_tid_fw; |
| 483 | wire [1:0] fad_w1_vld_fw; |
| 484 | wire [63:0] fad_nombi_w2_result_fw; |
| 485 | wire fad_r1_byp_hit_fx1; |
| 486 | wire fad_r2_byp_hit_fx1; |
| 487 | wire fad_i_parity_2e_fx1; |
| 488 | wire fad_i_parity_2o_fx1; |
| 489 | wire fad_i_parity_1e_fx1; |
| 490 | wire fad_i_parity_1o_fx1; |
| 491 | wire [7:0] fac_mbist_addr_1f; |
| 492 | wire [7:0] fec_mbist_wdata_1f; |
| 493 | wire [7:0] fec_mbist_wdata_3f; |
| 494 | wire fad_mbist_cmp64_fx1; |
| 495 | wire [1:0] fac_r1_vld_fx1; |
| 496 | wire [1:0] fac_r2_vld_fx1; |
| 497 | wire fac_ecc_trap_en_fx1; |
| 498 | |
| 499 | |
| 500 | |
| 501 | // ---------------------------------------------------------------------------- |
| 502 | // Interface with DEC |
| 503 | // ---------------------------------------------------------------------------- |
| 504 | |
| 505 | input [4:0] dec_frf_r1_addr_d; // FRF r1 read addr |
| 506 | input [4:0] dec_frf_r2_addr_d; // FRF r2 read addr (incl. STF,STDF) |
| 507 | input dec_frf_r1_vld_d; // FRF r1 read valid |
| 508 | input dec_frf_r2_vld_d; // FRF r2 read valid (incl. STF,STDF) |
| 509 | input dec_frf_r1_32b_d; // FRF r1 is 32-bit source |
| 510 | input dec_frf_r2_32b_d; // FRF r2 is 32-bit source |
| 511 | input dec_frf_r1_odd32b_d; // 0in custom -fire (dec_frf_r1_odd32b_d & ~dec_frf_r1_32b_d) |
| 512 | // FRF r1 is odd 32-bit source (32 LSBs) |
| 513 | input dec_frf_r2_odd32b_d; // 0in custom -fire (dec_frf_r2_odd32b_d & ~dec_frf_r2_32b_d) |
| 514 | // FRF r2 is odd 32-bit source (32 LSBs) (incl. STF,STDF) |
| 515 | |
| 516 | input dec_frf_w_vld_d; // FRF target |
| 517 | input [4:0] dec_frf_w_addr_d; // FRF write addr |
| 518 | input dec_frf_w_32b_d; // FRF write is 32-bit dest |
| 519 | input dec_frf_w_odd32b_d; // 0in custom -fire (dec_frf_w_odd32b_d & ~dec_frf_w_32b_d) |
| 520 | // FRF write is odd 32-bit dest (32 LSBs) |
| 521 | |
| 522 | input dec_spu_grant_d; // 0in custom -fire (($0in_delay(dec_spu_grant_d,1)) & dec_fgu_valid_e) |
| 523 | // SPU sources are valid next cycle (frf/e) |
| 524 | input dec_exu_src_vld_d; // FGU instr issued has EXU{1,0} source(s) |
| 525 | input [4:0] dec_irf_w_addr_d; // IRF write addr for EXU{1,0} |
| 526 | |
| 527 | input dec_frf_store_d; // FGU instr issued is a store of FRF data |
| 528 | input dec_fsr_store_d; // FGU instr issued is a store of FSR data |
| 529 | input [1:0] dec_valid_e; // used by FGU to qual store FSR update of FSR.ftt |
| 530 | |
| 531 | input [5:0] dec_fgu_op3_d; // 6-bit op3 field = instr[24:19] |
| 532 | input [7:0] dec_fgu_opf_d; // 9-bit opf field = instr[13:5] = fpop type (bit 13 is unused) |
| 533 | input dec_fgu_fmov_vld_m; // FMOV condition is true |
| 534 | input dec_fgu_decode_d; // 0in known_driven; assert_leader -leader dec_fgu_decode_d -follower dec_fgu_valid_e -min 1 -max 1 |
| 535 | // FGU instr issue valid (d stage), also asserts for ST(X)FSR |
| 536 | input dec_fgu_valid_e; // 0in known_driven |
| 537 | // FGU instr issue valid (e stage), doesn't assert for ST(X)FSR |
| 538 | input [2:0] dec_fgu_tid_d; // FGU instr TID |
| 539 | |
| 540 | input dec_flush_f1; // flush fx2 (xmit in fx1/m) |
| 541 | input dec_flush_f2; // flush fx3 (xmit in fx2/b) |
| 542 | |
| 543 | output [1:0] fgu_cmp_fcc_fx3; // fcmp fcc data {fccX[1:0]} |
| 544 | output [3:0] fgu_cmp_fcc_vld_fx3; // 0in bits_on -max 1 |
| 545 | // fcmp fcc data valid {fcc3, fcc2, fcc1, fcc0} |
| 546 | output [2:0] fgu_cmp_fcc_tid_fx2; // fcmp fcc data TID |
| 547 | output [7:0] fgu_fld_fcc_fx3; // ldfsr fcc data {fcc3[1:0], fcc2[1:0], fcc1[1:0], fcc0[1:0]} |
| 548 | output [1:0] fgu_fld_fcc_vld_fx3; // 0in value -val 2'b00 2'b01 2'b11 |
| 549 | // ldfsr fcc data valid {fcc3, fcc2, fcc1}, fcc0 |
| 550 | output [7:0] fgu_fprs_fef; // FPRS.fef for each TID |
| 551 | |
| 552 | output fgu_fdiv_stall; // FPD needs bubble to avoid FRF w2 port conflict |
| 553 | output [1:0] fgu_idiv_stall; // 0in bits_on -max 1 |
| 554 | // FPD needs bubble to avoid FGU/IRF result bus conflict |
| 555 | output [7:0] fgu_divide_completion; // 0in bits_on -max 2 |
| 556 | // FPD completion/TID |
| 557 | |
| 558 | // ---------------------------------------------------------------------------- |
| 559 | // Interface with TLU |
| 560 | // ---------------------------------------------------------------------------- |
| 561 | |
| 562 | input tlu_flush_fgu_b; // flush fx3, non-load (xmit in fx2/b) |
| 563 | input [7:0] tlu_ceter_pscce; // core error trap enable reg precise enable |
| 564 | input tlu_cerer_frf; // FRF ecc error trap enable |
| 565 | input [7:0] spc_core_running_status; // thread active |
| 566 | |
| 567 | output fgu_predict_fx2; // exception trap predicted |
| 568 | output fgu_pdist_beat2_fx1; // 2nd beat (bubble) of PDIST instr |
| 569 | output fgu_cecc_fx2; // FRF ECC correctable error |
| 570 | output fgu_uecc_fx2; // FRF ECC uncorrectable error |
| 571 | output [5:0] fgu_ecc_addr_fx2; // FRF cecc/uecc address (6-bit reg number format) |
| 572 | output [13:0] fgu_ecc_check_fx2; // FRF ECC check bits {even[6:0],odd[6:0]} |
| 573 | |
| 574 | output fgu_fpx_ieee_trap_fw; // FPX enabled ieee 754 exception detected |
| 575 | output fgu_fpd_ieee_trap_fw; // FPD enabled ieee 754 exception detected |
| 576 | output fgu_fpx_unfin_fw; // unfinished_FPop |
| 577 | output fgu_fpd_unfin_fw; // unfinished_FPop |
| 578 | output fgu_fpd_idiv0_trap_fw; // integer division by zero detected |
| 579 | output [2:0] fgu_fpx_trap_tid_fw; // FPX trap TID |
| 580 | output [2:0] fgu_fpd_trap_tid_fw; // FPD trap TID |
| 581 | |
| 582 | // ---------------------------------------------------------------------------- |
| 583 | // Interface with LSU |
| 584 | // ---------------------------------------------------------------------------- |
| 585 | |
| 586 | input [63:0] lsu_fgu_fld_data_b; // FRF/FSR load data |
| 587 | input [4:0] lsu_fgu_fld_addr_b; // FRF w2 write addr (fload hit/miss) |
| 588 | input lsu_fgu_fld_vld_w; // 0in custom -fire (lsu_fgu_fld_vld_w & ($0in_delay((~lsu_fgu_fld_b),1))) |
| 589 | // FRF/FSR load data valid (fload hit/miss), LSU qualified with dec_flush_lb, tlu_flush_fld_b, lsu_ldhit_b |
| 590 | input lsu_fgu_fld_b; // FRF/FSR load data (unqualified) |
| 591 | input [2:0] lsu_fgu_fld_tid_b; // FRF/FSR load data TID (fload hit/miss) |
| 592 | input lsu_fgu_fld_32b_b; // FRF/FSR is 32-bit dest (fload hit/miss) |
| 593 | input lsu_fgu_fld_odd32b_b; // 0in custom -fire (lsu_fgu_fld_odd32b_b & ~lsu_fgu_fld_32b_b) |
| 594 | // FRF w2 is odd 32-bit dest (32 LSBs) (fload hit/miss) |
| 595 | input lsu_fgu_fsr_load_b; // FSR is target of the load (not FRF) (unqualified) |
| 596 | input lsu_fgu_exception_w; // store exception detected |
| 597 | input lsu_block_store_m; // block store in progress |
| 598 | |
| 599 | input [31:0] lsu_asi_error_inject; // [31]=global inject en, [24]=FRF inject en, [7:0]=mask |
| 600 | input lsu_fgu_pmen; // FGU global power management enable |
| 601 | input lsu_asi_clken; // ASI ring clk enable |
| 602 | |
| 603 | output [63:0] fgu_lsu_fst_data_fx1; // FRF/FSR store data |
| 604 | output fgu_fst_ecc_error_fx2; // store float FRF ECC correctable/uncorrectable error |
| 605 | |
| 606 | // ---------------------------------------------------------------------------- |
| 607 | // Interface with EXUs |
| 608 | // ---------------------------------------------------------------------------- |
| 609 | |
| 610 | input [63:0] exu_fgu_rs1_e; // rs1 source from EXU{1,0} |
| 611 | // MULScc format: {30'b0,Y[0],1'b0,icc.nXORicc.v,rs1[31:1]} |
| 612 | input [63:0] exu_fgu_rs2_e; // rs2 source from EXU{1,0} |
| 613 | |
| 614 | input [31:0] exu_fgu_gsr_m; // GSR.align data: |
| 615 | // [31:3] = don't care |
| 616 | // [2:0] = GSR.align |
| 617 | // GSR.mask data: |
| 618 | // [31:0] = GSR.mask |
| 619 | input [1:0] exu_fgu_gsr_vld_m; // 0in bits_on -max 1 |
| 620 | // GSR data valid {align,mask} |
| 621 | input exu_fgu_flush_m; // EXU{1,0} src has bad ECC or exception, FGU must flush instr |
| 622 | |
| 623 | output [3:0] fgu_exu_icc_fx5; // int icc cond code {N,Z,V,C} |
| 624 | output [1:0] fgu_exu_xcc_fx5; // int xcc cond code {N,Z} |
| 625 | output fgu_exu_cc_vld_fx5; // int icc/xcc cond code valid |
| 626 | output [1:0] fgu_exu_w_vld_fx5; // 0in bits_on -max 1 |
| 627 | // FGU data result valid for EXU{1,0} w port |
| 628 | output [1:0] fgu_result_tid_fx5; // FGU result TID for EXU{1,0} or SPU |
| 629 | output [4:0] fgu_irf_w_addr_fx5; // IRF w1 write addr |
| 630 | output [63:0] fgu_exu_result_fx5; // FGU result for EXU{1,0} |
| 631 | |
| 632 | // ---------------------------------------------------------------------------- |
| 633 | // Interface with SPU |
| 634 | // ---------------------------------------------------------------------------- |
| 635 | |
| 636 | input [6:0] spu_fgu_fpy_ctl_d; // Mult control |
| 637 | input [63:0] spu_fgu_rs1_e; // rs1 source from SPU |
| 638 | input [63:0] spu_fgu_rs2_e; // rs2 source from SPU |
| 639 | |
| 640 | output fgu_accum_b0_fx5; |
| 641 | output [63:0] fgu_mul_result_fx5; // FGU result for SPU |
| 642 | |
| 643 | // ---------------------------------------------------------------------------- |
| 644 | // Global Signals |
| 645 | // ---------------------------------------------------------------------------- |
| 646 | |
| 647 | input l2clk; // clock input |
| 648 | input scan_in; |
| 649 | input spc_aclk_wmr; |
| 650 | input wmr_scan_in; |
| 651 | input lb_scan_en_wmr; |
| 652 | input tcu_pce_ov; // scan signals |
| 653 | input spc_aclk; |
| 654 | input spc_bclk; |
| 655 | input tcu_muxtest; |
| 656 | input tcu_dectest; |
| 657 | input tcu_scan_en; |
| 658 | input tcu_array_wr_inhibit; |
| 659 | input tcu_se_scancollar_in; |
| 660 | input tcu_se_scancollar_out; |
| 661 | input mbi_frf_read_en; // MBIST |
| 662 | input mbi_frf_write_en; // MBIST |
| 663 | input [7:0] mbi_addr; // MBIST |
| 664 | input [7:0] mbi_wdata; // MBIST |
| 665 | input mbi_run; // MBIST |
| 666 | input [64:0] in_rngl_cdbus; // ASI local ring |
| 667 | |
| 668 | output fgu_mbi_frf_fail; // MBIST |
| 669 | output [64:0] fgu_rngl_cdbus; // ASI local ring |
| 670 | output scan_out; |
| 671 | output wmr_scan_out; |
| 672 | |
| 673 | // ---------------------------------------------------------------------------- |
| 674 | // Instantiate sub-units |
| 675 | // ---------------------------------------------------------------------------- |
| 676 | |
| 677 | fgu_rep_dp rep (.fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]), |
| 678 | .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]), |
| 679 | .fad_rs1_fmt_fx1_rep0(fad_rs1_fmt_fx1_rep0[63:0]), |
| 680 | .fad_rs1_fmt_fx1_rep01(fad_rs1_fmt_fx1_rep01[63:0]), |
| 681 | .fad_rs2_fmt_fx1_rep0(fad_rs2_fmt_fx1_rep0[63:0]), |
| 682 | .fad_rs2_fmt_fx1_rep01(fad_rs2_fmt_fx1_rep01[63:0]), |
| 683 | .fad_rs2_fmt_fx1_rep1(fad_rs2_fmt_fx1_rep1[63:0]), |
| 684 | .fdd_result(fdd_result[62:11]), |
| 685 | .fdd_result_rep0(fdd_result_rep0[62:11]), |
| 686 | .fpf_hi_bof_fx1(fpf_hi_bof_fx1), |
| 687 | .fpf_lo_bof_fx1(fpf_lo_bof_fx1), |
| 688 | .fpf_hi_bof_fx1_rep0(fpf_hi_bof_fx1_rep0), |
| 689 | .fpf_lo_bof_fx1_rep0(fpf_lo_bof_fx1_rep0), |
| 690 | .fpe_rs2_fmt_fx1(fpe_rs2_fmt_fx1[0:0]), |
| 691 | .fpe_rs2_fmt_fx1_b0_rep0(fpe_rs2_fmt_fx1_b0_rep0), |
| 692 | .mul_clken(mul_clken), |
| 693 | .div_clken(div_clken), |
| 694 | .mul_clken_rep0(mul_clken_rep0), |
| 695 | .mul_clken_rep01(mul_clken_rep01), |
| 696 | .div_clken_rep0(div_clken_rep0), |
| 697 | .fac_div_valid_fx1(fac_div_valid_fx1), |
| 698 | .fac_divq_valid_fx1(fac_divq_valid_fx1), |
| 699 | .fac_div_control_fx1(fac_div_control_fx1[4:0]), |
| 700 | .fac_div_valid_fx1_rep0(fac_div_valid_fx1_rep0), |
| 701 | .fac_divq_valid_fx1_rep0(fac_divq_valid_fx1_rep0), |
| 702 | .fac_div_control_fx1_rep0(fac_div_control_fx1_rep0[4:0]), |
| 703 | .fdc_finish_int_early(fdc_finish_int_early), |
| 704 | .fdc_finish_fltd_early(fdc_finish_fltd_early), |
| 705 | .fdc_finish_flts_early(fdc_finish_flts_early), |
| 706 | .fdc_finish_int_early_rep0(fdc_finish_int_early_rep0), |
| 707 | .fdc_finish_fltd_early_rep0(fdc_finish_fltd_early_rep0), |
| 708 | .fdc_finish_flts_early_rep0(fdc_finish_flts_early_rep0) |
| 709 | ); |
| 710 | |
| 711 | fgu_fpf_dp fpf ( |
| 712 | .scan_in(fpf_scanin), |
| 713 | .scan_out(fpf_scanout), |
| 714 | .l2clk(l2clk), |
| 715 | .fad_fsr_tem_fx1_b4 (fad_fsr_tem_fx1[4]), |
| 716 | .fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]), |
| 717 | .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]), |
| 718 | .fad_rs1_fx1(fad_rs1_fx1[63:0]), |
| 719 | .fad_rs2_fx1(fad_rs2_fx1[63:0]), |
| 720 | .fad_r1_odd32b_fx1(fad_r1_odd32b_fx1), |
| 721 | .fpf_w1_result_fb(fpf_w1_result_fb[63:0]), |
| 722 | .fgu_exu_result_fx5(fgu_exu_result_fx5[63:0]), |
| 723 | .fgd_result_fx5(fgd_result_fx5[63:0]), |
| 724 | .fpc_int_res_sel_fx4(fpc_int_res_sel_fx4[5:1]), |
| 725 | .fpc_vis_cmp_result_fx5(fpc_vis_cmp_result_fx5[3:0]), |
| 726 | .fpc_result_sel_fx5(fpc_result_sel_fx5[5:0]), |
| 727 | .fpc_ovf_if_rcout_fx5(fpc_ovf_if_rcout_fx5[1:0]), |
| 728 | .fpc_ma_fmt_sel_fx4(fpc_ma_fmt_sel_fx4[4:0]), |
| 729 | .fpc_int_sel_fx5(fpc_int_sel_fx5[3:0]), |
| 730 | .fpc_fconst_sel_fx5(fpc_fconst_sel_fx5[4:0]), |
| 731 | .fpc_fp_cin00_fx2(fpc_fp_cin00_fx2), |
| 732 | .fpc_cin00_fx2(fpc_cin00_fx2), |
| 733 | .fpc_cin16_48_fx2(fpc_cin16_48_fx2), |
| 734 | .fpc_cin32_fx2(fpc_cin32_fx2), |
| 735 | .fpc_prop16_48_fx2(fpc_prop16_48_fx2), |
| 736 | .fpc_prop32_fx2(fpc_prop32_fx2), |
| 737 | .fpc_mle_sel_fx2(fpc_mle_sel_fx2), |
| 738 | .fpc_mse_sel_fx2(fpc_mse_sel_fx2[2:0]), |
| 739 | .fpc_sign_fx5(fpc_sign_fx5), |
| 740 | .fpc_sign_fb(fpc_sign_fb), |
| 741 | .fpc_sp_dest_fx4(fpc_sp_dest_fx4), |
| 742 | .fpc_fadd_eac_enable_fx2(fpc_fadd_eac_enable_fx2), |
| 743 | .fpc_i2f_sel_fx1(fpc_i2f_sel_fx1[3:2]), |
| 744 | .fpc_rinc_sel_fx5(fpc_rinc_sel_fx5), |
| 745 | .fpc_qthenan_fx4(fpc_qthenan_fx4), |
| 746 | .fpc_den2nor_sp_fb(fpc_den2nor_sp_fb), |
| 747 | .fpc_den2nor_dp_fb(fpc_den2nor_dp_fb), |
| 748 | .fpf_b_gteq_a_fx2(fpf_b_gteq_a_fx2[3:0]), |
| 749 | .fpf_b_eq_a_fx2(fpf_b_eq_a_fx2[3:0]), |
| 750 | .fpf_hi_aof_fx1(fpf_hi_aof_fx1), |
| 751 | .fpf_hi_bof_fx1(fpf_hi_bof_fx1), |
| 752 | .fpf_lo_aof_fx1(fpf_lo_aof_fx1), |
| 753 | .fpf_lo_bof_fx1(fpf_lo_bof_fx1), |
| 754 | .fpf_azf0_fx1(fpf_azf0_fx1), |
| 755 | .fpf_bzf0_fx1(fpf_bzf0_fx1), |
| 756 | .fpf_aoe0_fx1(fpf_aoe0_fx1), |
| 757 | .fpf_boe0_fx1(fpf_boe0_fx1), |
| 758 | .fpf_aze0_fx1(fpf_aze0_fx1), |
| 759 | .fpf_bze0_fx1(fpf_bze0_fx1), |
| 760 | .fpf_ma_sum_fx4(fpf_ma_sum_fx4[63:0]), |
| 761 | .fpf_ma_cout_fx4(fpf_ma_cout_fx4), |
| 762 | .fpf_cmp_swap_blta_fx2(fpf_cmp_swap_blta_fx2), |
| 763 | .fpf_align_sticky_fx4_l(fpf_align_sticky_fx4_l), |
| 764 | .fpf_byte_unsure_x_sp_fx3(fpf_byte_unsure_x_sp_fx3[1:0]), |
| 765 | .fpf_byte_unsure_x_dp_fx3(fpf_byte_unsure_x_dp_fx3[1:0]), |
| 766 | .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]), |
| 767 | .fic_i2f_align_sel_fx2(fic_i2f_align_sel_fx2[5:0]), |
| 768 | .fpf_rs2_cmp_din_fx1(fpf_rs2_cmp_din_fx1[63:0]), |
| 769 | .fpf_man_se_byte_fx3_b38_32(fpf_man_se_byte_fx3_b38_32[38:32]), |
| 770 | .fpf_man_se_byte_fx3_b6_0(fpf_man_se_byte_fx3_b6_0[6:0]), |
| 771 | .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]), |
| 772 | .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0]), |
| 773 | .fac_tlu_flush_fx3(fac_tlu_flush_fx3), |
| 774 | .fac_fpx_sp_dest_fx1(fac_fpx_sp_dest_fx1), |
| 775 | .fac_fpx_sp_src_fx1(fac_fpx_sp_src_fx1), |
| 776 | .fac_pre_fcc_vld_fx2(fac_pre_fcc_vld_fx2[3:0]), |
| 777 | .fac_fcmpe_fx1(fac_fcmpe_fx1), |
| 778 | .fac_rs2_rotate_sel_e(fac_rs2_rotate_sel_e[4:0]), |
| 779 | .fac_i2f_sel_e(fac_i2f_sel_e[1:0]), |
| 780 | .fac_force_swap_blta_fx1(fac_force_swap_blta_fx1), |
| 781 | .fac_force_noswap_blta_fx1(fac_force_noswap_blta_fx1), |
| 782 | .main_clken(main_clken), |
| 783 | .fgu_mul_result_fx5(fgu_mul_result_fx5[63:0]), |
| 784 | .fpy_fp_result_fx4_b63(fpy_fp_result_fx4_b63), |
| 785 | .fdc_finish_int_early(fdc_finish_int_early), |
| 786 | .fdd_result(fdd_result[63:0]), |
| 787 | .fpf_sa_xor_sb_fx1(fpf_sa_xor_sb_fx1), |
| 788 | .fpe_exp_res_fb(fpe_exp_res_fb[10:0]), |
| 789 | .fpe_align_sel_fx2(fpe_align_sel_fx2[5:0]), |
| 790 | .fpf_rcout_fx5(fpf_rcout_fx5), |
| 791 | .fpf_rcout_fb(fpf_rcout_fb), |
| 792 | .fpf_implied_bit_fx5(fpf_implied_bit_fx5), |
| 793 | .fec_w1_ecc_inject_fb(fec_w1_ecc_inject_fb[6:0]), |
| 794 | .fpf_w1_synd_fb(fpf_w1_synd_fb[13:0]), |
| 795 | .tcu_pce_ov(tcu_pce_ov), |
| 796 | .spc_aclk(spc_aclk), |
| 797 | .spc_bclk(spc_bclk), |
| 798 | .tcu_dectest(tcu_dectest), |
| 799 | .tcu_muxtest(tcu_muxtest), |
| 800 | .tcu_scan_en(tcu_scan_en) |
| 801 | ); |
| 802 | |
| 803 | fgu_fpy_dp fpy ( |
| 804 | .scan_in(fpy_scanin), |
| 805 | .scan_out(fpy_scanout), |
| 806 | .l2clk(l2clk), |
| 807 | .tcu_pce_ov(tcu_pce_ov), |
| 808 | .spc_aclk(spc_aclk), |
| 809 | .spc_bclk(spc_bclk), |
| 810 | .tcu_scan_en(tcu_scan_en), |
| 811 | .tcu_dectest(tcu_dectest), |
| 812 | .tcu_muxtest(tcu_muxtest), |
| 813 | .mul_clken_rep0(mul_clken_rep0), |
| 814 | .mul_clken_rep01(mul_clken_rep01), |
| 815 | .spu_fgu_rs1_e(spu_fgu_rs1_e[63:0]), |
| 816 | .spu_fgu_rs2_e(spu_fgu_rs2_e[63:0]), |
| 817 | .fad_rs1_fmt_fx1_rep0(fad_rs1_fmt_fx1_rep0[63:0]), |
| 818 | .fad_rs2_fmt_fx1_rep0(fad_rs2_fmt_fx1_rep0[63:0]), |
| 819 | .fad_rs2_fmt_fx1_rep1(fad_rs2_fmt_fx1_rep1[63:0]), |
| 820 | .fac_xr_mode_fx1(fac_xr_mode_fx1), |
| 821 | .fac_rs1_sel_fx1(fac_rs1_sel_fx1[4:0]), |
| 822 | .fac_rs2_sel_fx1(fac_rs2_sel_fx1[3:0]), |
| 823 | .fac_8x16_rnd_fx3(fac_8x16_rnd_fx3[1:0]), |
| 824 | .fac_scff_sel_fx3(fac_scff_sel_fx3[3:0]), |
| 825 | .fac_accum_sel_fx3(fac_accum_sel_fx3[6:0]), |
| 826 | .fac_result_sel_fx4(fac_result_sel_fx4[5:0]), |
| 827 | .fac_ma_result_en_fx4(fac_ma_result_en_fx4), |
| 828 | .fgu_mul_result_fx5(fgu_mul_result_fx5[63:0]), |
| 829 | .fpy_sticky_dp_fx5(fpy_sticky_dp_fx5), |
| 830 | .fpy_sticky_sp_fx5(fpy_sticky_sp_fx5), |
| 831 | .fpy_fp_result_fx4_b63(fpy_fp_result_fx4_b63), |
| 832 | .fpy_xicc_z_fx5(fpy_xicc_z_fx5[1:0]), |
| 833 | .fgu_accum_b0_fx5(fgu_accum_b0_fx5) |
| 834 | ); |
| 835 | |
| 836 | fgu_fpe_dp fpe ( |
| 837 | .scan_in(fpe_scanin), |
| 838 | .scan_out(fpe_scanout), |
| 839 | .l2clk(l2clk), |
| 840 | .fgu_mul_result_fx5_b63(fgu_mul_result_fx5[63]), |
| 841 | .fad_rs1_fx1(fad_rs1_fx1[62:23]), |
| 842 | .fad_rs2_fx1(fad_rs2_fx1[62:23]), |
| 843 | .fac_aexp_fmt_sel_e(fac_aexp_fmt_sel_e[9:0]), |
| 844 | .fac_bexp_fmt_sel_e(fac_bexp_fmt_sel_e[7:0]), |
| 845 | .fac_aux_cin_fx1(fac_aux_cin_fx1), |
| 846 | .main_clken(main_clken), |
| 847 | .fpc_exp_sel_mul_fx5(fpc_exp_sel_mul_fx5), |
| 848 | .fpc_eintx_sel_fx2(fpc_eintx_sel_fx2[3:0]), |
| 849 | .fpc_eadjx_sel_fx2(fpc_eadjx_sel_fx2[2:0]), |
| 850 | .fpc_ma_fmt_sel_fx4(fpc_ma_fmt_sel_fx4[1:0]), |
| 851 | .fpc_rinc_sel_fx5(fpc_rinc_sel_fx5), |
| 852 | .fpc_q_rinc_sel_fx5(fpc_q_rinc_sel_fx5), |
| 853 | .fpe_aux_rs2_fmt_fx1_b0(fpe_aux_rs2_fmt_fx1_b0), |
| 854 | .fpe_aux_eint_fx1(fpe_aux_eint_fx1[11:0]), |
| 855 | .fpe_rs1_fmt_fx1(fpe_rs1_fmt_fx1[10:0]), |
| 856 | .fpe_rs2_fmt_fx1(fpe_rs2_fmt_fx1[10:0]), |
| 857 | .fpe_einty_adj_cout_fx5(fpe_einty_adj_cout_fx5), |
| 858 | .fpe_einty_eq_eadj_fx5(fpe_einty_eq_eadj_fx5), |
| 859 | .fpf_rcout_fx5(fpf_rcout_fx5), |
| 860 | .fpe_exp_res_fb(fpe_exp_res_fb[10:0]), |
| 861 | .fpe_align_sel_fx2(fpe_align_sel_fx2[10:0]), |
| 862 | .fic_i2f_eadj_fx2(fic_i2f_eadj_fx2[5:0]), |
| 863 | .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]), |
| 864 | .tcu_pce_ov(tcu_pce_ov), |
| 865 | .spc_aclk(spc_aclk), |
| 866 | .spc_bclk(spc_bclk), |
| 867 | .tcu_dectest(tcu_dectest), |
| 868 | .tcu_muxtest(tcu_muxtest), |
| 869 | .tcu_scan_en(tcu_scan_en) |
| 870 | ); |
| 871 | |
| 872 | fgu_fpc_ctl fpc ( // FS:wmr_protect |
| 873 | .wmr_scan_in(fpc_wmr_scanin), |
| 874 | .wmr_scan_out(fpc_wmr_scanout), |
| 875 | .scan_in(fpc_scanin), |
| 876 | .scan_out(fpc_scanout), |
| 877 | .l2clk(l2clk), |
| 878 | .fad_rs1_fmt_fx1_b62 (fad_rs1_fmt_fx1[62]), |
| 879 | .fad_rs2_fmt_fx1_b62 (fad_rs2_fmt_fx1[62]), |
| 880 | .fdc_finish_int_early (fdc_finish_int_early_rep0), // fgu global buff rename |
| 881 | .fdc_finish_fltd_early (fdc_finish_fltd_early_rep0), // fgu global buff rename |
| 882 | .fdc_finish_flts_early (fdc_finish_flts_early_rep0), // fgu global buff rename |
| 883 | .fpf_bze_fx1 (fpf_bze0_fx1), // fgu global buff rename |
| 884 | .fpf_boe_fx1 (fpf_boe0_fx1), // fgu global buff rename |
| 885 | .fpf_bzf_fx1 (fpf_bzf0_fx1), // fgu global buff rename |
| 886 | .fpf_aze_fx1 (fpf_aze0_fx1), // fgu global buff rename |
| 887 | .fpf_aoe_fx1 (fpf_aoe0_fx1), // fgu global buff rename |
| 888 | .fpf_azf_fx1 (fpf_azf0_fx1), // fgu global buff rename |
| 889 | .main_clken (main_clken0), |
| 890 | .fpc_fpd_ieee_trap_fb(fpc_fpd_ieee_trap_fb), |
| 891 | .fpc_fpx_unfin_fb(fpc_fpx_unfin_fb), |
| 892 | .fpc_fpd_unfin_fb(fpc_fpd_unfin_fb), |
| 893 | .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw), |
| 894 | .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw), |
| 895 | .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw), |
| 896 | .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw), |
| 897 | .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw), |
| 898 | .fgu_predict_fx2(fgu_predict_fx2), |
| 899 | .lsu_fgu_exception_w(lsu_fgu_exception_w), |
| 900 | .lsu_block_store_m(lsu_block_store_m), |
| 901 | .exu_fgu_flush_m(exu_fgu_flush_m), |
| 902 | .exu_fgu_gsr_m(exu_fgu_gsr_m[2:0]), |
| 903 | .fgu_exu_icc_fx5(fgu_exu_icc_fx5[3:0]), |
| 904 | .fgu_exu_xcc_fx5(fgu_exu_xcc_fx5[1:0]), |
| 905 | .fad_rs1_fx1(fad_rs1_fx1[63:15]), |
| 906 | .fad_rs2_fx1(fad_rs2_fx1[63:15]), |
| 907 | .fad_fsr_rd_fx1(fad_fsr_rd_fx1[1:0]), |
| 908 | .fad_fsr_tem_fx1(fad_fsr_tem_fx1[4:0]), |
| 909 | .fad_fsr_ns_fx1(fad_fsr_ns_fx1), |
| 910 | .fad_gsr_imirnd_fx1(fad_gsr_imirnd_fx1[2:0]), |
| 911 | .fpc_w1_vld_fb(fpc_w1_vld_fb[1:0]), |
| 912 | .fpc_w1_ul_vld_fb(fpc_w1_ul_vld_fb), |
| 913 | .fpc_fsr_w1_vld_fx5(fpc_fsr_w1_vld_fx5[1:0]), |
| 914 | .fpc_fsr_w1_result_fw(fpc_fsr_w1_result_fw[11:0]), |
| 915 | .fpc_fsr_w2_result_fw(fpc_fsr_w2_result_fw[11:0]), |
| 916 | .fpc_fpd_exp_res(fpc_fpd_exp_res[10:0]), |
| 917 | .fpc_fpd_sign_res(fpc_fpd_sign_res), |
| 918 | .fpc_fpd_const_sel(fpc_fpd_const_sel[1:0]), |
| 919 | .fpc_fcc_fw(fpc_fcc_fw[1:0]), |
| 920 | .fpf_b_gteq_a_fx2(fpf_b_gteq_a_fx2[3:0]), |
| 921 | .fpf_b_eq_a_fx2(fpf_b_eq_a_fx2[3:0]), |
| 922 | .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]), |
| 923 | .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0]), |
| 924 | .fpf_hi_aof_fx1(fpf_hi_aof_fx1), |
| 925 | .fpf_lo_aof_fx1(fpf_lo_aof_fx1), |
| 926 | .fpf_ma_sum_fx4(fpf_ma_sum_fx4[63:9]), |
| 927 | .fpf_ma_cout_fx4(fpf_ma_cout_fx4), |
| 928 | .fpf_cmp_swap_blta_fx2(fpf_cmp_swap_blta_fx2), |
| 929 | .fpf_align_sticky_fx4_l(fpf_align_sticky_fx4_l), |
| 930 | .fpf_byte_unsure_x_sp_fx3(fpf_byte_unsure_x_sp_fx3[1:0]), |
| 931 | .fpf_byte_unsure_x_dp_fx3(fpf_byte_unsure_x_dp_fx3[1:0]), |
| 932 | .fpf_rcout_fb(fpf_rcout_fb), |
| 933 | .fpf_implied_bit_fx5(fpf_implied_bit_fx5), |
| 934 | .fpc_result_sel_fx5(fpc_result_sel_fx5[5:0]), |
| 935 | .fpc_ovf_if_rcout_fx5(fpc_ovf_if_rcout_fx5[1:0]), |
| 936 | .fpc_vis_cmp_result_fx5(fpc_vis_cmp_result_fx5[3:0]), |
| 937 | .fpc_int_res_sel_fx4(fpc_int_res_sel_fx4[5:1]), |
| 938 | .fpc_ma_fmt_sel_fx4(fpc_ma_fmt_sel_fx4[4:0]), |
| 939 | .fpc_int_sel_fx5(fpc_int_sel_fx5[3:0]), |
| 940 | .fpc_fconst_sel_fx5(fpc_fconst_sel_fx5[4:0]), |
| 941 | .fpc_fp_cin00_fx2(fpc_fp_cin00_fx2), |
| 942 | .fpc_cin00_fx2(fpc_cin00_fx2), |
| 943 | .fpc_cin16_48_fx2(fpc_cin16_48_fx2), |
| 944 | .fpc_cin32_fx2(fpc_cin32_fx2), |
| 945 | .fpc_prop16_48_fx2(fpc_prop16_48_fx2), |
| 946 | .fpc_prop32_fx2(fpc_prop32_fx2), |
| 947 | .fpc_mle_sel_fx2(fpc_mle_sel_fx2), |
| 948 | .fpc_mse_sel_fx2(fpc_mse_sel_fx2[2:0]), |
| 949 | .fpc_sign_fx5(fpc_sign_fx5), |
| 950 | .fpc_sign_fb(fpc_sign_fb), |
| 951 | .fpc_rd_mode_fx3(fpc_rd_mode_fx3[1:0]), |
| 952 | .fpc_emin_fx3(fpc_emin_fx3), |
| 953 | .fpc_sp_dest_fx4(fpc_sp_dest_fx4), |
| 954 | .fpc_fadd_eac_enable_fx2(fpc_fadd_eac_enable_fx2), |
| 955 | .fpc_i2f_sel_fx1(fpc_i2f_sel_fx1[3:2]), |
| 956 | .fpc_rinc_sel_fx5(fpc_rinc_sel_fx5), |
| 957 | .fpc_qthenan_fx4(fpc_qthenan_fx4), |
| 958 | .fpc_den2nor_sp_fb(fpc_den2nor_sp_fb), |
| 959 | .fpc_den2nor_dp_fb(fpc_den2nor_dp_fb), |
| 960 | .fpe_aux_rs2_fmt_fx1_b0(fpe_aux_rs2_fmt_fx1_b0), |
| 961 | .fpe_aux_eint_fx1(fpe_aux_eint_fx1[11:0]), |
| 962 | .fpe_align_sel_fx2(fpe_align_sel_fx2[10:0]), |
| 963 | .fpe_rs1_fmt_fx1(fpe_rs1_fmt_fx1[10:0]), |
| 964 | .fpe_rs2_fmt_fx1(fpe_rs2_fmt_fx1[10:0]), |
| 965 | .fpe_einty_adj_cout_fx5(fpe_einty_adj_cout_fx5), |
| 966 | .fpe_einty_eq_eadj_fx5(fpe_einty_eq_eadj_fx5), |
| 967 | .fpc_exp_sel_mul_fx5(fpc_exp_sel_mul_fx5), |
| 968 | .fpc_eintx_sel_fx2(fpc_eintx_sel_fx2[3:0]), |
| 969 | .fpc_eadjx_sel_fx2(fpc_eadjx_sel_fx2[2:0]), |
| 970 | .fpc_q_rinc_sel_fx5(fpc_q_rinc_sel_fx5), |
| 971 | .fac_tlu_flush_fx3(fac_tlu_flush_fx3), |
| 972 | .fac_tid_e(fac_tid_e[2:0]), |
| 973 | .fac_dec_valid_fx1(fac_dec_valid_fx1), |
| 974 | .fac_fpx_itype_fx1(fac_fpx_itype_fx1[2:0]), |
| 975 | .fac_fpx_dtype_fx1(fac_fpx_dtype_fx1[2:0]), |
| 976 | .fac_fpx_stype_fx1(fac_fpx_stype_fx1[1:0]), |
| 977 | .fac_fpx_sign_instr_fx1(fac_fpx_sign_instr_fx1), |
| 978 | .fac_fpx_rnd_trunc_fx1(fac_fpx_rnd_trunc_fx1), |
| 979 | .fac_fcmpe_fx1(fac_fcmpe_fx1), |
| 980 | .fac_fpx_mulscc_fx1(fac_fpx_mulscc_fx1), |
| 981 | .fac_fpx_saverestore_fx1(fac_fpx_saverestore_fx1), |
| 982 | .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1), |
| 983 | .fac_fgx_popc_fx2(fac_fgx_popc_fx2), |
| 984 | .fac_fgx_mvcond_fx2(fac_fgx_mvcond_fx2), |
| 985 | .fac_fgx_mvucond_fx2(fac_fgx_mvucond_fx2), |
| 986 | .fac_fgx_abs_fx2(fac_fgx_abs_fx2), |
| 987 | .fac_fgx_neg_fx2(fac_fgx_neg_fx2), |
| 988 | .fac_fpx_nv_vld_fx1(fac_fpx_nv_vld_fx1), |
| 989 | .fac_fpx_of_vld_fx1(fac_fpx_of_vld_fx1), |
| 990 | .fac_fpx_uf_vld_fx1(fac_fpx_uf_vld_fx1), |
| 991 | .fac_fpx_dz_vld_fx1(fac_fpx_dz_vld_fx1), |
| 992 | .fac_fpx_nx_vld_fx1(fac_fpx_nx_vld_fx1), |
| 993 | .fac_fpx_unfin_vld_fx1(fac_fpx_unfin_vld_fx1), |
| 994 | .fac_fgx_instr_fx4(fac_fgx_instr_fx4), |
| 995 | .fac_w1_vld_fx1(fac_w1_vld_fx1[1:0]), |
| 996 | .fac_w1_odd32b_fx1(fac_w1_odd32b_fx1), |
| 997 | .fac_opf_fx2(fac_opf_fx2[3:1]), |
| 998 | .fac_fgx_siam_fx2(fac_fgx_siam_fx2), |
| 999 | .fac_div_valid_fx1(fac_div_valid_fx1), |
| 1000 | .fac_divq_valid_fx1(fac_divq_valid_fx1), |
| 1001 | .fac_fsr_store_fx2(fac_fsr_store_fx2), |
| 1002 | .fac_gsr_asr_tid_fx2(fac_gsr_asr_tid_fx2[2:0]), |
| 1003 | .fac_rng_wr_gsr_3f(fac_rng_wr_gsr_3f), |
| 1004 | .fac_gsr_w_vld_fx2(fac_gsr_w_vld_fx2[1:0]), |
| 1005 | .fac_dec_valid_noflush_fx5(fac_dec_valid_noflush_fx5), |
| 1006 | .fac_exu_src_e(fac_exu_src_e), |
| 1007 | .coreon_clken(coreon_clken), |
| 1008 | .fpc_fcc_vld_fx5(fpc_fcc_vld_fx5[3:0]), |
| 1009 | .fpc_stfsr_en_fx3to5(fpc_stfsr_en_fx3to5), |
| 1010 | .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]), |
| 1011 | .fic_mulscc_iccz_fx4(fic_mulscc_iccz_fx4), |
| 1012 | .fic_mulscc_xccz_fx4(fic_mulscc_xccz_fx4), |
| 1013 | .fic_convert_sticky_fx4(fic_convert_sticky_fx4), |
| 1014 | .fic_fxtod_sticky_fx4(fic_fxtod_sticky_fx4), |
| 1015 | .fic_ftoi_nx_fx4(fic_ftoi_nx_fx4), |
| 1016 | .fic_ftox_nx_fx4(fic_ftox_nx_fx4), |
| 1017 | .fic_bzf31msb_fx2(fic_bzf31msb_fx2), |
| 1018 | .fic_bzf32lsb_fx2(fic_bzf32lsb_fx2), |
| 1019 | .fic_bof22msb_fx2(fic_bof22msb_fx2), |
| 1020 | .fpc_lzd_override_fx4(fpc_lzd_override_fx4), |
| 1021 | .fpc_sp_source_fx3(fpc_sp_source_fx3), |
| 1022 | .fdc_flt_inexact(fdc_flt_inexact), |
| 1023 | .fdc_xicc_z_early(fdc_xicc_z_early[1:0]), |
| 1024 | .fdc_icc_v_early(fdc_icc_v_early), |
| 1025 | .fdc_dec_exp_early(fdc_dec_exp_early), |
| 1026 | .fpc_pre_div_flush_fx2(fpc_pre_div_flush_fx2), |
| 1027 | .fpc_div_default_res_fx2(fpc_div_default_res_fx2), |
| 1028 | .fdd_result(fdd_result[63:31]), |
| 1029 | .fdd_pte_cla_early_b63(fdd_pte_cla_early_b63), |
| 1030 | .fgu_mul_result_fx5(fgu_mul_result_fx5[63:9]), |
| 1031 | .fpy_sticky_dp_fx5(fpy_sticky_dp_fx5), |
| 1032 | .fpy_sticky_sp_fx5(fpy_sticky_sp_fx5), |
| 1033 | .fpy_xicc_z_fx5(fpy_xicc_z_fx5[1:0]), |
| 1034 | .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d), |
| 1035 | .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d), |
| 1036 | .dec_flush_f1(dec_flush_f1), |
| 1037 | .dec_flush_f2(dec_flush_f2), |
| 1038 | .dec_fgu_fmov_vld_m(dec_fgu_fmov_vld_m), |
| 1039 | .dec_valid_e(dec_valid_e[1:0]), |
| 1040 | .dec_frf_store_d(dec_frf_store_d), |
| 1041 | .fec_cecc_fx2(fec_cecc_fx2), |
| 1042 | .fec_uecc_fx2(fec_uecc_fx2), |
| 1043 | .fpc_frf_store_vld_fx1(fpc_frf_store_vld_fx1), |
| 1044 | .fpc_gsr0_mask_sel_fx3(fpc_gsr0_mask_sel_fx3[1:0]), |
| 1045 | .fpc_gsr1_mask_sel_fx3(fpc_gsr1_mask_sel_fx3[1:0]), |
| 1046 | .fpc_gsr2_mask_sel_fx3(fpc_gsr2_mask_sel_fx3[1:0]), |
| 1047 | .fpc_gsr3_mask_sel_fx3(fpc_gsr3_mask_sel_fx3[1:0]), |
| 1048 | .fpc_gsr4_mask_sel_fx3(fpc_gsr4_mask_sel_fx3[1:0]), |
| 1049 | .fpc_gsr5_mask_sel_fx3(fpc_gsr5_mask_sel_fx3[1:0]), |
| 1050 | .fpc_gsr6_mask_sel_fx3(fpc_gsr6_mask_sel_fx3[1:0]), |
| 1051 | .fpc_gsr7_mask_sel_fx3(fpc_gsr7_mask_sel_fx3[1:0]), |
| 1052 | .fpc_gsr_scale_fx4(fpc_gsr_scale_fx4[4:0]), |
| 1053 | .fpc_gsr_align_fx4(fpc_gsr_align_fx4[2:0]), |
| 1054 | .fpc_gsr_asr_11bits_fx4(fpc_gsr_asr_11bits_fx4[10:0]), |
| 1055 | .spc_aclk_wmr(spc_aclk_wmr), |
| 1056 | .tcu_pce_ov(tcu_pce_ov), |
| 1057 | .spc_aclk(spc_aclk), |
| 1058 | .spc_bclk(spc_bclk), |
| 1059 | .tcu_scan_en(tcu_scan_en), |
| 1060 | .mbi_run(mbi_run), |
| 1061 | .in_rngl_cdbus(in_rngl_cdbus[27:0]) |
| 1062 | ); |
| 1063 | |
| 1064 | fgu_fic_ctl fic ( |
| 1065 | .scan_in(fic_scanin), |
| 1066 | .scan_out(fic_scanout), |
| 1067 | .l2clk(l2clk), |
| 1068 | .fpf_rs2_cmp_din_fx1(fpf_rs2_cmp_din_fx1[63:0]), |
| 1069 | .fpf_ma_sum_fx4(fpf_ma_sum_fx4[63:0]), |
| 1070 | .fpf_man_se_byte_fx3_b38_32(fpf_man_se_byte_fx3_b38_32[38:32]), |
| 1071 | .fpf_man_se_byte_fx3_b6_0(fpf_man_se_byte_fx3_b6_0[6:0]), |
| 1072 | .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]), |
| 1073 | .fic_i2f_align_sel_fx2(fic_i2f_align_sel_fx2[5:0]), |
| 1074 | .fpe_align_sel_fx2(fpe_align_sel_fx2[5:0]), |
| 1075 | .fic_i2f_eadj_fx2(fic_i2f_eadj_fx2[5:0]), |
| 1076 | .fpc_lzd_override_fx4(fpc_lzd_override_fx4), |
| 1077 | .fpc_sp_source_fx3(fpc_sp_source_fx3), |
| 1078 | .fic_mulscc_iccz_fx4(fic_mulscc_iccz_fx4), |
| 1079 | .fic_mulscc_xccz_fx4(fic_mulscc_xccz_fx4), |
| 1080 | .fic_convert_sticky_fx4(fic_convert_sticky_fx4), |
| 1081 | .fic_fxtod_sticky_fx4(fic_fxtod_sticky_fx4), |
| 1082 | .fic_ftoi_nx_fx4(fic_ftoi_nx_fx4), |
| 1083 | .fic_ftox_nx_fx4(fic_ftox_nx_fx4), |
| 1084 | .fic_bzf31msb_fx2(fic_bzf31msb_fx2), |
| 1085 | .fic_bzf32lsb_fx2(fic_bzf32lsb_fx2), |
| 1086 | .fic_bof22msb_fx2(fic_bof22msb_fx2), |
| 1087 | .main_clken(main_clken), |
| 1088 | .tcu_pce_ov(tcu_pce_ov), |
| 1089 | .spc_aclk(spc_aclk), |
| 1090 | .spc_bclk(spc_bclk), |
| 1091 | .tcu_scan_en(tcu_scan_en) |
| 1092 | ); |
| 1093 | |
| 1094 | fgu_fgd_dp fgd ( // FS:wmr_protect |
| 1095 | .wmr_scan_in(fgd_wmr_scanin), |
| 1096 | .wmr_scan_out(fgd_wmr_scanout), |
| 1097 | .scan_in(fgd_scanin), |
| 1098 | .scan_out(fgd_scanout), |
| 1099 | .l2clk(l2clk), |
| 1100 | .fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]), |
| 1101 | .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]), |
| 1102 | .fgd_rngl_cdbus_3f(fgd_rngl_cdbus_3f[62:0]), |
| 1103 | .fgd_result_fx5(fgd_result_fx5[63:0]), |
| 1104 | .vis_clken(vis_clken), |
| 1105 | .coreon_clken(coreon_clken), |
| 1106 | .fac_fgx_abs_fx2(fac_fgx_abs_fx2), |
| 1107 | .fac_fgx_neg_fx2(fac_fgx_neg_fx2), |
| 1108 | .fac_fgx_logical_fx2(fac_fgx_logical_fx2), |
| 1109 | .fac_fgx_expand_fx2(fac_fgx_expand_fx2), |
| 1110 | .fac_fgx_merge_fx2(fac_fgx_merge_fx2), |
| 1111 | .fac_fgx_align_fx2(fac_fgx_align_fx2), |
| 1112 | .fac_fgx_shuffle_fx2(fac_fgx_shuffle_fx2), |
| 1113 | .fac_fgx_pack16_fx2(fac_fgx_pack16_fx2), |
| 1114 | .fac_fgx_pack32_fx2(fac_fgx_pack32_fx2), |
| 1115 | .fac_fgx_packfix_fx2(fac_fgx_packfix_fx2), |
| 1116 | .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1), |
| 1117 | .fac_fgx_popc_fx2(fac_fgx_popc_fx2), |
| 1118 | .fac_fgx_pack_sel_fx2(fac_fgx_pack_sel_fx2), |
| 1119 | .fac_opf_fx2(fac_opf_fx2[4:1]), |
| 1120 | .fac_gsr_asr_tid_fx2(fac_gsr_asr_tid_fx2[2:0]), |
| 1121 | .fac_tid_fx2(fac_tid_fx2[2:0]), |
| 1122 | .fac_rng_fprs(fac_rng_fprs[2:0]), |
| 1123 | .fac_rng_rd_fprs_4f(fac_rng_rd_fprs_4f), |
| 1124 | .fac_rng_rd_gsr_4f(fac_rng_rd_gsr_4f), |
| 1125 | .fec_r1_ecc_fx1(fec_r1_ecc_fx1[13:0]), |
| 1126 | .fac_rng_rd_ecc_4f(fac_rng_rd_ecc_4f), |
| 1127 | .fac_rng_rd_or_wr_3f(fac_rng_rd_or_wr_3f), |
| 1128 | .asi_clken(asi_clken), |
| 1129 | .fgd_gsr_asr_mask_fx4_b31(fgd_gsr_asr_mask_fx4_b31), |
| 1130 | .fpc_gsr0_mask_sel_fx3(fpc_gsr0_mask_sel_fx3[1:0]), |
| 1131 | .fpc_gsr1_mask_sel_fx3(fpc_gsr1_mask_sel_fx3[1:0]), |
| 1132 | .fpc_gsr2_mask_sel_fx3(fpc_gsr2_mask_sel_fx3[1:0]), |
| 1133 | .fpc_gsr3_mask_sel_fx3(fpc_gsr3_mask_sel_fx3[1:0]), |
| 1134 | .fpc_gsr4_mask_sel_fx3(fpc_gsr4_mask_sel_fx3[1:0]), |
| 1135 | .fpc_gsr5_mask_sel_fx3(fpc_gsr5_mask_sel_fx3[1:0]), |
| 1136 | .fpc_gsr6_mask_sel_fx3(fpc_gsr6_mask_sel_fx3[1:0]), |
| 1137 | .fpc_gsr7_mask_sel_fx3(fpc_gsr7_mask_sel_fx3[1:0]), |
| 1138 | .fpc_gsr_scale_fx4(fpc_gsr_scale_fx4[4:0]), |
| 1139 | .fpc_gsr_align_fx4(fpc_gsr_align_fx4[2:0]), |
| 1140 | .fpc_gsr_asr_11bits_fx4(fpc_gsr_asr_11bits_fx4[10:0]), |
| 1141 | .exu_fgu_gsr_m(exu_fgu_gsr_m[31:0]), |
| 1142 | .spc_aclk_wmr(spc_aclk_wmr), |
| 1143 | .lb_scan_en_wmr(lb_scan_en_wmr), |
| 1144 | .tcu_pce_ov(tcu_pce_ov), |
| 1145 | .spc_aclk(spc_aclk), |
| 1146 | .spc_bclk(spc_bclk), |
| 1147 | .tcu_dectest(tcu_dectest), |
| 1148 | .tcu_muxtest(tcu_muxtest), |
| 1149 | .tcu_scan_en(tcu_scan_en), |
| 1150 | .in_rngl_cdbus(in_rngl_cdbus[63:0]) |
| 1151 | ); |
| 1152 | |
| 1153 | fgu_fdd_dp fdd ( |
| 1154 | .scan_in(fdd_scanin), |
| 1155 | .scan_out(fdd_scanout), |
| 1156 | .l2clk(l2clk), |
| 1157 | .tcu_pce_ov(tcu_pce_ov), |
| 1158 | .spc_aclk(spc_aclk), |
| 1159 | .spc_bclk(spc_bclk), |
| 1160 | .tcu_scan_en(tcu_scan_en), |
| 1161 | .div_clken_rep0(div_clken_rep0), |
| 1162 | .fad_rs1_fmt_fx1_rep01(fad_rs1_fmt_fx1_rep01[63:0]), |
| 1163 | .fad_rs2_fmt_fx1_rep01(fad_rs2_fmt_fx1_rep01[63:0]), |
| 1164 | .fac_div_valid_fx1_rep0(fac_div_valid_fx1_rep0), |
| 1165 | .fac_divq_valid_fx1_rep0(fac_divq_valid_fx1_rep0), |
| 1166 | .fdc_asign_lth(fdc_asign_lth), |
| 1167 | .fdc_bsign_lth(fdc_bsign_lth), |
| 1168 | .fdc_bsign_lth_(fdc_bsign_lth_), |
| 1169 | .fdc_pe_cycle3(fdc_pe_cycle3), |
| 1170 | .fdc_pe_cmux_sel(fdc_pe_cmux_sel), |
| 1171 | .fdc_pe_smux_sel(fdc_pe_smux_sel[2:0]), |
| 1172 | .fdc_pe_xsht_ctl(fdc_pe_xsht_ctl[5:0]), |
| 1173 | .fdc_ie_fsqrt_valid_even(fdc_ie_fsqrt_valid_even), |
| 1174 | .fdc_ie_fsqrt_valid_even_(fdc_ie_fsqrt_valid_even_), |
| 1175 | .fdc_ie_fsqrt_valid_odd(fdc_ie_fsqrt_valid_odd), |
| 1176 | .fdc_ie_fsqrt_valid_odd_(fdc_ie_fsqrt_valid_odd_), |
| 1177 | .fdc_ie_rmux_sel(fdc_ie_rmux_sel[4:0]), |
| 1178 | .fdc_ie_dmux_sel(fdc_ie_dmux_sel[2:0]), |
| 1179 | .fdc_flt_increment(fdc_flt_increment), |
| 1180 | .fdc_pte_clasel(fdc_pte_clasel[1:0]), |
| 1181 | .fdc_pte_csa_cin(fdc_pte_csa_cin), |
| 1182 | .fdc_pte_cycle2(fdc_pte_cycle2), |
| 1183 | .fdc_emin_lth(fdc_emin_lth), |
| 1184 | .fdc_pte_qsel(fdc_pte_qsel[2:0]), |
| 1185 | .fdc_pte_stall_(fdc_pte_stall_), |
| 1186 | .fdc_flt_round(fdc_flt_round[1:0]), |
| 1187 | .fdc_idiv_ctl(fdc_idiv_ctl[4:0]), |
| 1188 | .fdc_fdx_cin_in(fdc_fdx_cin_in), |
| 1189 | .fdc_qsel00(fdc_qsel00[2:0]), |
| 1190 | .fdc_qsel1(fdc_qsel1[2:0]), |
| 1191 | .fdc_q_in(fdc_q_in[1:0]), |
| 1192 | .fdc_qm1_in(fdc_qm1_in[1:0]), |
| 1193 | .fdd_result(fdd_result[63:0]), |
| 1194 | .fdd_pte_cla_early_b63(fdd_pte_cla_early_b63), |
| 1195 | .fdd_pe_clth(fdd_pe_clth[63:0]), |
| 1196 | .fdd_cla_zero32_(fdd_cla_zero32_), |
| 1197 | .fdd_cla_zero64_(fdd_cla_zero64_), |
| 1198 | .fdd_fdx_din0(fdd_fdx_din0), |
| 1199 | .fdd_fdx_din1(fdd_fdx_din1), |
| 1200 | .fdd_fdx_cin64(fdd_fdx_cin64), |
| 1201 | .fdd_fdq00_10_sum(fdd_fdq00_10_sum[4:0]), |
| 1202 | .fdd_fdq00_10_carry(fdd_fdq00_10_carry[4:0]), |
| 1203 | .fdd_fdq1p_sum(fdd_fdq1p_sum[3:0]), |
| 1204 | .fdd_fdq1p_carry(fdd_fdq1p_carry[3:0]), |
| 1205 | .fdd_fdq1n_sum(fdd_fdq1n_sum[3:0]), |
| 1206 | .fdd_fdq1n_carry(fdd_fdq1n_carry[3:0]) |
| 1207 | ); |
| 1208 | |
| 1209 | fgu_fdc_ctl fdc ( |
| 1210 | .scan_in(fdc_scanin), |
| 1211 | .scan_out(fdc_scanout), |
| 1212 | .l2clk(l2clk), |
| 1213 | .fpf_hi_bof_fx1 (fpf_hi_bof_fx1_rep0), // fgu global buff rename |
| 1214 | .fpf_lo_bof_fx1 (fpf_lo_bof_fx1_rep0), // fgu global buff rename |
| 1215 | .fpe_rs2_fmt_fx1_b0 (fpe_rs2_fmt_fx1_b0_rep0), // fgu global buff rename |
| 1216 | .div_clken (div_clken_rep0), // fgu global buff rename |
| 1217 | .fac_div_valid_fx1 (fac_div_valid_fx1_rep0), // fgu global buff rename |
| 1218 | .fac_divq_valid_fx1 (fac_divq_valid_fx1_rep0), // fgu global buff rename |
| 1219 | .fac_div_control_fx1 (fac_div_control_fx1_rep0[4:0]), |
| 1220 | .tcu_pce_ov(tcu_pce_ov), |
| 1221 | .spc_aclk(spc_aclk), |
| 1222 | .spc_bclk(spc_bclk), |
| 1223 | .tcu_scan_en(tcu_scan_en), |
| 1224 | .fac_div_flush_fx3(fac_div_flush_fx3), |
| 1225 | .fpf_sa_xor_sb_fx1(fpf_sa_xor_sb_fx1), |
| 1226 | .fpc_rd_mode_fx3(fpc_rd_mode_fx3[1:0]), |
| 1227 | .fpc_emin_fx3(fpc_emin_fx3), |
| 1228 | .fdd_pe_clth(fdd_pe_clth[63:0]), |
| 1229 | .fdd_cla_zero32_(fdd_cla_zero32_), |
| 1230 | .fdd_cla_zero64_(fdd_cla_zero64_), |
| 1231 | .fdd_result(fdd_result[63:9]), |
| 1232 | .fdd_fdx_din0(fdd_fdx_din0), |
| 1233 | .fdd_fdx_din1(fdd_fdx_din1), |
| 1234 | .fdd_fdx_cin64(fdd_fdx_cin64), |
| 1235 | .fdd_fdq00_10_sum(fdd_fdq00_10_sum[4:0]), |
| 1236 | .fdd_fdq00_10_carry(fdd_fdq00_10_carry[4:0]), |
| 1237 | .fdd_fdq1p_sum(fdd_fdq1p_sum[3:0]), |
| 1238 | .fdd_fdq1p_carry(fdd_fdq1p_carry[3:0]), |
| 1239 | .fdd_fdq1n_sum(fdd_fdq1n_sum[3:0]), |
| 1240 | .fdd_fdq1n_carry(fdd_fdq1n_carry[3:0]), |
| 1241 | .fgu_fdiv_stall(fgu_fdiv_stall), |
| 1242 | .fgu_idiv_stall(fgu_idiv_stall[1:0]), |
| 1243 | .fdc_dec_exp_early(fdc_dec_exp_early), |
| 1244 | .fdc_icc_v_early(fdc_icc_v_early), |
| 1245 | .fdc_xicc_z_early(fdc_xicc_z_early[1:0]), |
| 1246 | .fdc_finish_int_early(fdc_finish_int_early), |
| 1247 | .fdc_finish_fltd_early(fdc_finish_fltd_early), |
| 1248 | .fdc_finish_flts_early(fdc_finish_flts_early), |
| 1249 | .fdc_flt_inexact(fdc_flt_inexact), |
| 1250 | .fdc_asign_lth(fdc_asign_lth), |
| 1251 | .fdc_bsign_lth(fdc_bsign_lth), |
| 1252 | .fdc_bsign_lth_(fdc_bsign_lth_), |
| 1253 | .fdc_pe_cycle3(fdc_pe_cycle3), |
| 1254 | .fdc_pe_cmux_sel(fdc_pe_cmux_sel), |
| 1255 | .fdc_pe_smux_sel(fdc_pe_smux_sel[2:0]), |
| 1256 | .fdc_pe_xsht_ctl(fdc_pe_xsht_ctl[5:0]), |
| 1257 | .fdc_ie_fsqrt_valid_even(fdc_ie_fsqrt_valid_even), |
| 1258 | .fdc_ie_fsqrt_valid_even_(fdc_ie_fsqrt_valid_even_), |
| 1259 | .fdc_ie_fsqrt_valid_odd(fdc_ie_fsqrt_valid_odd), |
| 1260 | .fdc_ie_fsqrt_valid_odd_(fdc_ie_fsqrt_valid_odd_), |
| 1261 | .fdc_ie_rmux_sel(fdc_ie_rmux_sel[4:0]), |
| 1262 | .fdc_ie_dmux_sel(fdc_ie_dmux_sel[2:0]), |
| 1263 | .fdc_flt_increment(fdc_flt_increment), |
| 1264 | .fdc_pte_clasel(fdc_pte_clasel[1:0]), |
| 1265 | .fdc_pte_csa_cin(fdc_pte_csa_cin), |
| 1266 | .fdc_pte_cycle2(fdc_pte_cycle2), |
| 1267 | .fdc_emin_lth(fdc_emin_lth), |
| 1268 | .fdc_pte_qsel(fdc_pte_qsel[2:0]), |
| 1269 | .fdc_pte_stall_(fdc_pte_stall_), |
| 1270 | .fdc_flt_round(fdc_flt_round[1:0]), |
| 1271 | .fdc_idiv_ctl(fdc_idiv_ctl[4:0]), |
| 1272 | .fdc_fdx_cin_in(fdc_fdx_cin_in), |
| 1273 | .fdc_qsel00(fdc_qsel00[2:0]), |
| 1274 | .fdc_qsel1(fdc_qsel1[2:0]), |
| 1275 | .fdc_q_in(fdc_q_in[1:0]), |
| 1276 | .fdc_qm1_in(fdc_qm1_in[1:0]) // fgu global buff rename |
| 1277 | ); |
| 1278 | |
| 1279 | fgu_fad_dp fad ( // FS:wmr_protect |
| 1280 | .wmr_scan_in(fad_wmr_scanin), |
| 1281 | .wmr_scan_out(fad_wmr_scanout), |
| 1282 | .scan_in(fad_scanin), |
| 1283 | .scan_out(fad_scanout), |
| 1284 | .l2clk(l2clk), |
| 1285 | .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]), |
| 1286 | .dec_frf_r1_32b_d(dec_frf_r1_32b_d), |
| 1287 | .dec_frf_r2_32b_d(dec_frf_r2_32b_d), |
| 1288 | .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d), |
| 1289 | .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d), |
| 1290 | .fgu_fld_fcc_fx3(fgu_fld_fcc_fx3[7:0]), |
| 1291 | .lsu_fgu_fld_data_b(lsu_fgu_fld_data_b[63:0]), |
| 1292 | .lsu_fgu_fld_addr_b(lsu_fgu_fld_addr_b[4:0]), |
| 1293 | .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w), |
| 1294 | .lsu_fgu_fld_b(lsu_fgu_fld_b), |
| 1295 | .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]), |
| 1296 | .lsu_fgu_fld_32b_b(lsu_fgu_fld_32b_b), |
| 1297 | .lsu_fgu_fld_odd32b_b(lsu_fgu_fld_odd32b_b), |
| 1298 | .lsu_fgu_fsr_load_b(lsu_fgu_fsr_load_b), |
| 1299 | .fgu_lsu_fst_data_fx1(fgu_lsu_fst_data_fx1[63:0]), |
| 1300 | .exu_fgu_rs1_e(exu_fgu_rs1_e[63:0]), |
| 1301 | .exu_fgu_rs2_e(exu_fgu_rs2_e[63:0]), |
| 1302 | .fac_frf_r1_addr_e(fac_frf_r1_addr_e[4:0]), |
| 1303 | .fac_tid_e(fac_tid_e[2:0]), |
| 1304 | .fac_aman_fmt_sel_e(fac_aman_fmt_sel_e[4:0]), |
| 1305 | .fac_bman_fmt_sel_e(fac_bman_fmt_sel_e[4:0]), |
| 1306 | .fac_fst_fmt_sel_fx1(fac_fst_fmt_sel_fx1[3:0]), |
| 1307 | .fac_exu_src_e(fac_exu_src_e), |
| 1308 | .fac_w1_addr_fb(fac_w1_addr_fb[4:0]), |
| 1309 | .fac_fpd_addr_fb(fac_fpd_addr_fb[4:0]), |
| 1310 | .fac_w1_32b_fb(fac_w1_32b_fb), |
| 1311 | .fac_fpd_32b_fb(fac_fpd_32b_fb), |
| 1312 | .fac_w1_odd32b_fb(fac_w1_odd32b_fb), |
| 1313 | .fac_fpd_odd32b_fb(fac_fpd_odd32b_fb), |
| 1314 | .fac_w1_tid_fb(fac_w1_tid_fb[2:0]), |
| 1315 | .fac_fpd_tid_fb(fac_fpd_tid_fb[2:0]), |
| 1316 | .fac_fsr0_sel_fw(fac_fsr0_sel_fw[5:0]), |
| 1317 | .fac_fsr1_sel_fw(fac_fsr1_sel_fw[5:0]), |
| 1318 | .fac_fsr2_sel_fw(fac_fsr2_sel_fw[5:0]), |
| 1319 | .fac_fsr3_sel_fw(fac_fsr3_sel_fw[5:0]), |
| 1320 | .fac_fsr4_sel_fw(fac_fsr4_sel_fw[5:0]), |
| 1321 | .fac_fsr5_sel_fw(fac_fsr5_sel_fw[5:0]), |
| 1322 | .fac_fsr6_sel_fw(fac_fsr6_sel_fw[5:0]), |
| 1323 | .fac_fsr7_sel_fw(fac_fsr7_sel_fw[5:0]), |
| 1324 | .main_clken(main_clken), |
| 1325 | .asi_clken(asi_clken), |
| 1326 | .coreon_clken(coreon_clken), |
| 1327 | .fad_w2_addr_fw1_b4(fad_w2_addr_fw1_b4), |
| 1328 | .fad_w2_tid_fw1(fad_w2_tid_fw1[2:0]), |
| 1329 | .fad_w2_vld_fw1(fad_w2_vld_fw1[1:0]), |
| 1330 | .fpc_w1_vld_fb(fpc_w1_vld_fb[1:0]), |
| 1331 | .fpc_w1_ul_vld_fb(fpc_w1_ul_vld_fb), |
| 1332 | .fpc_fsr_w1_result_fw(fpc_fsr_w1_result_fw[11:0]), |
| 1333 | .fpc_fsr_w2_result_fw(fpc_fsr_w2_result_fw[11:0]), |
| 1334 | .fpc_fpd_exp_res(fpc_fpd_exp_res[10:0]), |
| 1335 | .fpc_fpd_sign_res(fpc_fpd_sign_res), |
| 1336 | .fpc_fpd_const_sel(fpc_fpd_const_sel[1:0]), |
| 1337 | .fpc_fcc_fw(fpc_fcc_fw[1:0]), |
| 1338 | .fpc_fpd_ieee_trap_fb(fpc_fpd_ieee_trap_fb), |
| 1339 | .fpc_fpd_unfin_fb(fpc_fpd_unfin_fb), |
| 1340 | .fad_gsr_imirnd_fx1(fad_gsr_imirnd_fx1[2:0]), |
| 1341 | .frf_r1_data_e(frf_r1_data_e[63:0]), |
| 1342 | .frf_r2_data_e(frf_r2_data_e[63:0]), |
| 1343 | .fad_w1_tid_fw(fad_w1_tid_fw[2:0]), |
| 1344 | .fad_w1_vld_fw(fad_w1_vld_fw[1:0]), |
| 1345 | .fad_w2_result_fw(fad_w2_result_fw[63:0]), |
| 1346 | .fad_w2_addr_fw(fad_w2_addr_fw[4:0]), |
| 1347 | .fad_w2_tid_fw(fad_w2_tid_fw[2:0]), |
| 1348 | .fad_w2_vld_fw(fad_w2_vld_fw[1:0]), |
| 1349 | .fad_nombi_w2_result_fw(fad_nombi_w2_result_fw[63:0]), |
| 1350 | .fad_r1_byp_hit_fx1(fad_r1_byp_hit_fx1), |
| 1351 | .fad_r2_byp_hit_fx1(fad_r2_byp_hit_fx1), |
| 1352 | .fad_i_parity_2e_fx1(fad_i_parity_2e_fx1), |
| 1353 | .fad_i_parity_2o_fx1(fad_i_parity_2o_fx1), |
| 1354 | .fad_i_parity_1e_fx1(fad_i_parity_1e_fx1), |
| 1355 | .fad_i_parity_1o_fx1(fad_i_parity_1o_fx1), |
| 1356 | .fpf_w1_result_fb(fpf_w1_result_fb[63:0]), |
| 1357 | .fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]), |
| 1358 | .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]), |
| 1359 | .fad_rs1_fx1(fad_rs1_fx1[63:0]), |
| 1360 | .fad_rs2_fx1(fad_rs2_fx1[63:0]), |
| 1361 | .fad_r1_odd32b_fx1(fad_r1_odd32b_fx1), |
| 1362 | .fad_fsr_rd_fx1(fad_fsr_rd_fx1[1:0]), |
| 1363 | .fad_fsr_tem_fx1(fad_fsr_tem_fx1[4:0]), |
| 1364 | .fad_fsr_ns_fx1(fad_fsr_ns_fx1), |
| 1365 | .fdd_result_rep0(fdd_result_rep0[62:11]), |
| 1366 | .fdc_finish_fltd_early_rep0(fdc_finish_fltd_early_rep0), |
| 1367 | .fdc_finish_flts_early_rep0(fdc_finish_flts_early_rep0), |
| 1368 | .fgd_rngl_cdbus_3f(fgd_rngl_cdbus_3f[62:0]), |
| 1369 | .spc_aclk_wmr(spc_aclk_wmr), |
| 1370 | .lb_scan_en_wmr(lb_scan_en_wmr), |
| 1371 | .tcu_pce_ov(tcu_pce_ov), |
| 1372 | .spc_aclk(spc_aclk), |
| 1373 | .spc_bclk(spc_bclk), |
| 1374 | .tcu_scan_en(tcu_scan_en), |
| 1375 | .tcu_se_scancollar_out(tcu_se_scancollar_out), |
| 1376 | .mbi_run(mbi_run), |
| 1377 | .mbi_frf_write_en(mbi_frf_write_en), |
| 1378 | .fac_mbist_addr_1f(fac_mbist_addr_1f[7:0]), |
| 1379 | .fec_mbist_wdata_1f(fec_mbist_wdata_1f[7:0]), |
| 1380 | .fec_mbist_wdata_3f(fec_mbist_wdata_3f[7:0]), |
| 1381 | .fad_mbist_cmp64_fx1(fad_mbist_cmp64_fx1), |
| 1382 | .fgu_rngl_cdbus(fgu_rngl_cdbus[62:0]) |
| 1383 | ); |
| 1384 | |
| 1385 | fgu_fac_ctl fac ( // FS:wmr_protect |
| 1386 | .wmr_scan_in(fac_wmr_scanin), |
| 1387 | .wmr_scan_out(fac_wmr_scanout), |
| 1388 | .scan_in(fac_scanin), |
| 1389 | .scan_out(fac_scanout), |
| 1390 | .l2clk(l2clk), |
| 1391 | .fdc_finish_int_early (fdc_finish_int_early_rep0), // fgu global buff rename |
| 1392 | .fdc_finish_fltd_early (fdc_finish_fltd_early_rep0), // fgu global buff rename |
| 1393 | .fdc_finish_flts_early (fdc_finish_flts_early_rep0), // fgu global buff rename |
| 1394 | .fgu_rngl_cdbus_b64 (fgu_rngl_cdbus[64]), |
| 1395 | .fgu_rngl_cdbus_b63 (fgu_rngl_cdbus[63]), |
| 1396 | .dec_frf_r1_addr_d(dec_frf_r1_addr_d[4:0]), |
| 1397 | .dec_frf_r1_vld_d(dec_frf_r1_vld_d), |
| 1398 | .dec_frf_r2_vld_d(dec_frf_r2_vld_d), |
| 1399 | .dec_frf_r1_32b_d(dec_frf_r1_32b_d), |
| 1400 | .dec_frf_r2_32b_d(dec_frf_r2_32b_d), |
| 1401 | .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d), |
| 1402 | .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d), |
| 1403 | .dec_frf_w_vld_d(dec_frf_w_vld_d), |
| 1404 | .dec_frf_w_addr_d(dec_frf_w_addr_d[4:0]), |
| 1405 | .dec_frf_w_32b_d(dec_frf_w_32b_d), |
| 1406 | .dec_frf_w_odd32b_d(dec_frf_w_odd32b_d), |
| 1407 | .dec_fgu_valid_e(dec_fgu_valid_e), |
| 1408 | .dec_exu_src_vld_d(dec_exu_src_vld_d), |
| 1409 | .dec_irf_w_addr_d(dec_irf_w_addr_d[4:0]), |
| 1410 | .dec_spu_grant_d(dec_spu_grant_d), |
| 1411 | .dec_frf_store_d(dec_frf_store_d), |
| 1412 | .dec_fsr_store_d(dec_fsr_store_d), |
| 1413 | .dec_flush_f1(dec_flush_f1), |
| 1414 | .dec_flush_f2(dec_flush_f2), |
| 1415 | .dec_fgu_op3_d(dec_fgu_op3_d[5:0]), |
| 1416 | .dec_fgu_opf_d(dec_fgu_opf_d[7:0]), |
| 1417 | .dec_fgu_decode_d(dec_fgu_decode_d), |
| 1418 | .dec_fgu_tid_d(dec_fgu_tid_d[2:0]), |
| 1419 | .fgu_cmp_fcc_tid_fx2(fgu_cmp_fcc_tid_fx2[2:0]), |
| 1420 | .fgu_fld_fcc_vld_fx3(fgu_fld_fcc_vld_fx3[1:0]), |
| 1421 | .fgu_fprs_fef(fgu_fprs_fef[7:0]), |
| 1422 | .fgu_divide_completion(fgu_divide_completion[7:0]), |
| 1423 | .tlu_flush_fgu_b(tlu_flush_fgu_b), |
| 1424 | .tlu_ceter_pscce(tlu_ceter_pscce[7:0]), |
| 1425 | .tlu_cerer_frf(tlu_cerer_frf), |
| 1426 | .spc_core_running_status(spc_core_running_status[7:0]), |
| 1427 | .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]), |
| 1428 | .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]), |
| 1429 | .fpc_pre_div_flush_fx2(fpc_pre_div_flush_fx2), |
| 1430 | .fpc_div_default_res_fx2(fpc_div_default_res_fx2), |
| 1431 | .fpc_fsr_w1_vld_fx5(fpc_fsr_w1_vld_fx5[1:0]), |
| 1432 | .fpc_fcc_vld_fx5(fpc_fcc_vld_fx5[3:0]), |
| 1433 | .fpc_fpx_unfin_fb(fpc_fpx_unfin_fb), |
| 1434 | .fpc_fpd_unfin_fb(fpc_fpd_unfin_fb), |
| 1435 | .fpc_stfsr_en_fx3to5(fpc_stfsr_en_fx3to5), |
| 1436 | .fac_tlu_flush_fx3(fac_tlu_flush_fx3), |
| 1437 | .fac_dec_valid_fx1(fac_dec_valid_fx1), |
| 1438 | .fac_fpx_itype_fx1(fac_fpx_itype_fx1[2:0]), |
| 1439 | .fac_fpx_dtype_fx1(fac_fpx_dtype_fx1[2:0]), |
| 1440 | .fac_fpx_stype_fx1(fac_fpx_stype_fx1[1:0]), |
| 1441 | .fac_fpx_sign_instr_fx1(fac_fpx_sign_instr_fx1), |
| 1442 | .fac_fpx_rnd_trunc_fx1(fac_fpx_rnd_trunc_fx1), |
| 1443 | .fac_fpx_mulscc_fx1(fac_fpx_mulscc_fx1), |
| 1444 | .fac_fpx_saverestore_fx1(fac_fpx_saverestore_fx1), |
| 1445 | .fac_fpx_nv_vld_fx1(fac_fpx_nv_vld_fx1), |
| 1446 | .fac_fpx_of_vld_fx1(fac_fpx_of_vld_fx1), |
| 1447 | .fac_fpx_uf_vld_fx1(fac_fpx_uf_vld_fx1), |
| 1448 | .fac_fpx_dz_vld_fx1(fac_fpx_dz_vld_fx1), |
| 1449 | .fac_fpx_nx_vld_fx1(fac_fpx_nx_vld_fx1), |
| 1450 | .fac_fpx_unfin_vld_fx1(fac_fpx_unfin_vld_fx1), |
| 1451 | .fac_fpx_sp_dest_fx1(fac_fpx_sp_dest_fx1), |
| 1452 | .fac_fpx_sp_src_fx1(fac_fpx_sp_src_fx1), |
| 1453 | .fac_fgx_instr_fx4(fac_fgx_instr_fx4), |
| 1454 | .fac_w1_vld_fx1(fac_w1_vld_fx1[1:0]), |
| 1455 | .fac_w1_odd32b_fx1(fac_w1_odd32b_fx1), |
| 1456 | .fac_gsr_w_vld_fx2(fac_gsr_w_vld_fx2[1:0]), |
| 1457 | .fac_dec_valid_noflush_fx5(fac_dec_valid_noflush_fx5), |
| 1458 | .fgd_gsr_asr_mask_fx4_b31(fgd_gsr_asr_mask_fx4_b31), |
| 1459 | .fac_fgx_mvcond_fx2(fac_fgx_mvcond_fx2), |
| 1460 | .fac_fgx_mvucond_fx2(fac_fgx_mvucond_fx2), |
| 1461 | .fac_fgx_abs_fx2(fac_fgx_abs_fx2), |
| 1462 | .fac_fgx_neg_fx2(fac_fgx_neg_fx2), |
| 1463 | .fac_fgx_logical_fx2(fac_fgx_logical_fx2), |
| 1464 | .fac_fgx_expand_fx2(fac_fgx_expand_fx2), |
| 1465 | .fac_fgx_merge_fx2(fac_fgx_merge_fx2), |
| 1466 | .fac_fgx_align_fx2(fac_fgx_align_fx2), |
| 1467 | .fac_fgx_shuffle_fx2(fac_fgx_shuffle_fx2), |
| 1468 | .fac_fgx_pack16_fx2(fac_fgx_pack16_fx2), |
| 1469 | .fac_fgx_pack32_fx2(fac_fgx_pack32_fx2), |
| 1470 | .fac_fgx_packfix_fx2(fac_fgx_packfix_fx2), |
| 1471 | .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1), |
| 1472 | .fac_fgx_popc_fx2(fac_fgx_popc_fx2), |
| 1473 | .fac_fgx_siam_fx2(fac_fgx_siam_fx2), |
| 1474 | .fac_fgx_pack_sel_fx2(fac_fgx_pack_sel_fx2), |
| 1475 | .fac_opf_fx2(fac_opf_fx2[4:1]), |
| 1476 | .fac_gsr_asr_tid_fx2(fac_gsr_asr_tid_fx2[2:0]), |
| 1477 | .fac_tid_fx2(fac_tid_fx2[2:0]), |
| 1478 | .fac_rng_fprs(fac_rng_fprs[2:0]), |
| 1479 | .fac_rng_rd_fprs_4f(fac_rng_rd_fprs_4f), |
| 1480 | .fac_rng_wr_gsr_3f(fac_rng_wr_gsr_3f), |
| 1481 | .fac_rng_rd_gsr_4f(fac_rng_rd_gsr_4f), |
| 1482 | .fac_rng_rd_ecc_4f(fac_rng_rd_ecc_4f), |
| 1483 | .fac_rng_rd_or_wr_3f(fac_rng_rd_or_wr_3f), |
| 1484 | .fad_w1_tid_fw(fad_w1_tid_fw[2:0]), |
| 1485 | .fad_w1_vld_fw(fad_w1_vld_fw[1:0]), |
| 1486 | .fad_w2_addr_fw1_b4(fad_w2_addr_fw1_b4), |
| 1487 | .fad_w2_tid_fw1(fad_w2_tid_fw1[2:0]), |
| 1488 | .fad_w2_vld_fw1(fad_w2_vld_fw1[1:0]), |
| 1489 | .fac_frf_r1_addr_e(fac_frf_r1_addr_e[4:0]), |
| 1490 | .fac_tid_e(fac_tid_e[2:0]), |
| 1491 | .fac_aman_fmt_sel_e(fac_aman_fmt_sel_e[4:0]), |
| 1492 | .fac_bman_fmt_sel_e(fac_bman_fmt_sel_e[4:0]), |
| 1493 | .fac_fst_fmt_sel_fx1(fac_fst_fmt_sel_fx1[3:0]), |
| 1494 | .fac_w1_addr_fb(fac_w1_addr_fb[4:0]), |
| 1495 | .fac_fpd_addr_fb(fac_fpd_addr_fb[4:0]), |
| 1496 | .fac_w1_32b_fb(fac_w1_32b_fb), |
| 1497 | .fac_fpd_32b_fb(fac_fpd_32b_fb), |
| 1498 | .fac_w1_odd32b_fb(fac_w1_odd32b_fb), |
| 1499 | .fac_fpd_odd32b_fb(fac_fpd_odd32b_fb), |
| 1500 | .fac_w1_tid_fb(fac_w1_tid_fb[2:0]), |
| 1501 | .fac_fpd_tid_fb(fac_fpd_tid_fb[2:0]), |
| 1502 | .fac_fsr_store_fx2(fac_fsr_store_fx2), |
| 1503 | .fac_exu_src_e(fac_exu_src_e), |
| 1504 | .fac_fsr0_sel_fw(fac_fsr0_sel_fw[5:0]), |
| 1505 | .fac_fsr1_sel_fw(fac_fsr1_sel_fw[5:0]), |
| 1506 | .fac_fsr2_sel_fw(fac_fsr2_sel_fw[5:0]), |
| 1507 | .fac_fsr3_sel_fw(fac_fsr3_sel_fw[5:0]), |
| 1508 | .fac_fsr4_sel_fw(fac_fsr4_sel_fw[5:0]), |
| 1509 | .fac_fsr5_sel_fw(fac_fsr5_sel_fw[5:0]), |
| 1510 | .fac_fsr6_sel_fw(fac_fsr6_sel_fw[5:0]), |
| 1511 | .fac_fsr7_sel_fw(fac_fsr7_sel_fw[5:0]), |
| 1512 | .fac_pre_fcc_vld_fx2(fac_pre_fcc_vld_fx2[3:0]), |
| 1513 | .fac_fcmpe_fx1(fac_fcmpe_fx1), |
| 1514 | .fac_rs2_rotate_sel_e(fac_rs2_rotate_sel_e[4:0]), |
| 1515 | .fac_i2f_sel_e(fac_i2f_sel_e[1:0]), |
| 1516 | .fac_force_swap_blta_fx1(fac_force_swap_blta_fx1), |
| 1517 | .fac_force_noswap_blta_fx1(fac_force_noswap_blta_fx1), |
| 1518 | .fac_xr_mode_fx1(fac_xr_mode_fx1), |
| 1519 | .fac_rs1_sel_fx1(fac_rs1_sel_fx1[4:0]), |
| 1520 | .fac_rs2_sel_fx1(fac_rs2_sel_fx1[3:0]), |
| 1521 | .fac_8x16_rnd_fx3(fac_8x16_rnd_fx3[1:0]), |
| 1522 | .fac_scff_sel_fx3(fac_scff_sel_fx3[3:0]), |
| 1523 | .fac_accum_sel_fx3(fac_accum_sel_fx3[6:0]), |
| 1524 | .fac_result_sel_fx4(fac_result_sel_fx4[5:0]), |
| 1525 | .fac_ma_result_en_fx4(fac_ma_result_en_fx4), |
| 1526 | .fac_div_flush_fx3(fac_div_flush_fx3), |
| 1527 | .fac_div_valid_fx1(fac_div_valid_fx1), |
| 1528 | .fac_divq_valid_fx1(fac_divq_valid_fx1), |
| 1529 | .fac_div_control_fx1(fac_div_control_fx1[4:0]), |
| 1530 | .fac_aexp_fmt_sel_e(fac_aexp_fmt_sel_e[9:0]), |
| 1531 | .fac_bexp_fmt_sel_e(fac_bexp_fmt_sel_e[7:0]), |
| 1532 | .fac_aux_cin_fx1(fac_aux_cin_fx1), |
| 1533 | .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w), |
| 1534 | .lsu_fgu_fld_b(lsu_fgu_fld_b), |
| 1535 | .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]), |
| 1536 | .lsu_fgu_fld_32b_b(lsu_fgu_fld_32b_b), |
| 1537 | .lsu_fgu_fsr_load_b(lsu_fgu_fsr_load_b), |
| 1538 | .lsu_fgu_pmen(lsu_fgu_pmen), |
| 1539 | .lsu_asi_clken(lsu_asi_clken), |
| 1540 | .exu_fgu_gsr_vld_m(exu_fgu_gsr_vld_m[1:0]), |
| 1541 | .exu_fgu_flush_m(exu_fgu_flush_m), |
| 1542 | .fgu_result_tid_fx5(fgu_result_tid_fx5[1:0]), |
| 1543 | .fgu_irf_w_addr_fx5(fgu_irf_w_addr_fx5[4:0]), |
| 1544 | .fgu_exu_cc_vld_fx5(fgu_exu_cc_vld_fx5), |
| 1545 | .fgu_exu_w_vld_fx5(fgu_exu_w_vld_fx5[1:0]), |
| 1546 | .fec_cecc_fx2(fec_cecc_fx2), |
| 1547 | .fec_uecc_fx2(fec_uecc_fx2), |
| 1548 | .fac_r1_vld_fx1(fac_r1_vld_fx1[1:0]), |
| 1549 | .fac_r2_vld_fx1(fac_r2_vld_fx1[1:0]), |
| 1550 | .fac_ecc_trap_en_fx1(fac_ecc_trap_en_fx1), |
| 1551 | .fac_tid_d(fac_tid_d[2:0]), |
| 1552 | .fac_frf_r1_addr_d(fac_frf_r1_addr_d[4:0]), |
| 1553 | .fac_frf_r1_vld_d(fac_frf_r1_vld_d), |
| 1554 | .spu_fgu_fpy_ctl_d(spu_fgu_fpy_ctl_d[6:0]), |
| 1555 | .main_clken(main_clken), |
| 1556 | .main_clken0(main_clken0), |
| 1557 | .mul_clken(mul_clken), |
| 1558 | .div_clken(div_clken), |
| 1559 | .vis_clken(vis_clken), |
| 1560 | .asi_clken(asi_clken), |
| 1561 | .coreon_clken(coreon_clken), |
| 1562 | .spc_aclk_wmr(spc_aclk_wmr), |
| 1563 | .tcu_pce_ov(tcu_pce_ov), |
| 1564 | .spc_aclk(spc_aclk), |
| 1565 | .spc_bclk(spc_bclk), |
| 1566 | .tcu_scan_en(tcu_scan_en), |
| 1567 | .mbi_frf_read_en(mbi_frf_read_en), |
| 1568 | .mbi_addr(mbi_addr[7:0]), |
| 1569 | .mbi_run(mbi_run), |
| 1570 | .in_rngl_cdbus(in_rngl_cdbus[64:0]), |
| 1571 | .fac_mbist_addr_1f(fac_mbist_addr_1f[7:0]) |
| 1572 | ); |
| 1573 | |
| 1574 | fgu_fec_ctl fec ( |
| 1575 | .scan_in(fec_scanin), |
| 1576 | .scan_out(fec_scanout), |
| 1577 | .l2clk(l2clk), |
| 1578 | .tcu_pce_ov(tcu_pce_ov), |
| 1579 | .spc_aclk(spc_aclk), |
| 1580 | .spc_bclk(spc_bclk), |
| 1581 | .tcu_scan_en(tcu_scan_en), |
| 1582 | .tcu_se_scancollar_out(tcu_se_scancollar_out), |
| 1583 | .mbi_frf_read_en(mbi_frf_read_en), |
| 1584 | .mbi_wdata(mbi_wdata[7:0]), |
| 1585 | .mbi_run(mbi_run), |
| 1586 | .fad_mbist_cmp64_fx1(fad_mbist_cmp64_fx1), |
| 1587 | .lsu_asi_error_inject(lsu_asi_error_inject[31:0]), |
| 1588 | .fad_nombi_w2_result_fw(fad_nombi_w2_result_fw[63:0]), |
| 1589 | .fec_w1_ecc_inject_fb(fec_w1_ecc_inject_fb[6:0]), |
| 1590 | .fec_w2_synd_fw(fec_w2_synd_fw[13:0]), |
| 1591 | .fec_r1_ecc_fx1(fec_r1_ecc_fx1[13:0]), |
| 1592 | .fec_mbist_wdata_1f(fec_mbist_wdata_1f[7:0]), |
| 1593 | .fec_mbist_wdata_3f(fec_mbist_wdata_3f[7:0]), |
| 1594 | .main_clken(main_clken), |
| 1595 | .coreon_clken(coreon_clken), |
| 1596 | .fac_frf_r1_addr_e(fac_frf_r1_addr_e[4:0]), |
| 1597 | .fac_dec_valid_fx1(fac_dec_valid_fx1), |
| 1598 | .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1), |
| 1599 | .fac_ecc_trap_en_fx1(fac_ecc_trap_en_fx1), |
| 1600 | .fac_r1_vld_fx1(fac_r1_vld_fx1[1:0]), |
| 1601 | .fac_r2_vld_fx1(fac_r2_vld_fx1[1:0]), |
| 1602 | .fad_r1_byp_hit_fx1(fad_r1_byp_hit_fx1), |
| 1603 | .fad_r2_byp_hit_fx1(fad_r2_byp_hit_fx1), |
| 1604 | .fpc_frf_store_vld_fx1(fpc_frf_store_vld_fx1), |
| 1605 | .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]), |
| 1606 | .dec_frf_r1_32b_d(dec_frf_r1_32b_d), |
| 1607 | .dec_frf_r2_32b_d(dec_frf_r2_32b_d), |
| 1608 | .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d), |
| 1609 | .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d), |
| 1610 | .dec_flush_f1(dec_flush_f1), |
| 1611 | .dec_flush_f2(dec_flush_f2), |
| 1612 | .tlu_flush_fgu_b(tlu_flush_fgu_b), |
| 1613 | .fad_rs1_fx1(fad_rs1_fx1[63:0]), |
| 1614 | .fad_rs2_fx1(fad_rs2_fx1[63:0]), |
| 1615 | .fad_i_parity_2e_fx1(fad_i_parity_2e_fx1), |
| 1616 | .fad_i_parity_2o_fx1(fad_i_parity_2o_fx1), |
| 1617 | .fad_i_parity_1e_fx1(fad_i_parity_1e_fx1), |
| 1618 | .fad_i_parity_1o_fx1(fad_i_parity_1o_fx1), |
| 1619 | .frf_r1_ecc_e(frf_r1_ecc_e[13:0]), |
| 1620 | .frf_r2_ecc_e(frf_r2_ecc_e[13:0]), |
| 1621 | .fgu_pdist_beat2_fx1(fgu_pdist_beat2_fx1), |
| 1622 | .fgu_ecc_addr_fx2(fgu_ecc_addr_fx2[5:0]), |
| 1623 | .fgu_ecc_check_fx2(fgu_ecc_check_fx2[13:0]), |
| 1624 | .fgu_cecc_fx2(fgu_cecc_fx2), |
| 1625 | .fec_cecc_fx2(fec_cecc_fx2), |
| 1626 | .fgu_uecc_fx2(fgu_uecc_fx2), |
| 1627 | .fec_uecc_fx2(fec_uecc_fx2), |
| 1628 | .fgu_fst_ecc_error_fx2(fgu_fst_ecc_error_fx2), |
| 1629 | .fgu_mbi_frf_fail(fgu_mbi_frf_fail) |
| 1630 | ); |
| 1631 | |
| 1632 | // ------------------------------------ |
| 1633 | // floating point regfile |
| 1634 | // ------------------------------------ |
| 1635 | |
| 1636 | |
| 1637 | |
| 1638 | // 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[0] & fac_frf_r1_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e & ~fad.r1_odd32b_e))) -message "FRF w1[0] = r1 without bypass" -group core_array |
| 1639 | |
| 1640 | // 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[1] & fac_frf_r1_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e & fad.r1_odd32b_e))) -message "FRF w1[1] = r1 without bypass" -group core_array |
| 1641 | |
| 1642 | // 0in custom -fire ( $0in_delay((fad_w2_vld_fw[0] & fac_frf_r1_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e & ~fad.r1_odd32b_e))) -message "FRF w2[0] = r1 without bypass" -group core_array |
| 1643 | |
| 1644 | // 0in custom -fire ( $0in_delay((fad_w2_vld_fw[1] & fac_frf_r1_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e & fad.r1_odd32b_e))) -message "FRF w2[1] = r1 without bypass" -group core_array |
| 1645 | |
| 1646 | |
| 1647 | // 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[0] & dec_frf_r2_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e & ~fad.r2_odd32b_e))) -message "FRF w1[0] = r2 without bypass" -group core_array |
| 1648 | |
| 1649 | // 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[1] & dec_frf_r2_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e & fad.r2_odd32b_e))) -message "FRF w1[1] = r2 without bypass" -group core_array |
| 1650 | |
| 1651 | // 0in custom -fire ( $0in_delay((fad_w2_vld_fw[0] & dec_frf_r2_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e & ~fad.r2_odd32b_e))) -message "FRF w2[0] = r2 without bypass" -group core_array |
| 1652 | |
| 1653 | // 0in custom -fire ( $0in_delay((fad_w2_vld_fw[1] & dec_frf_r2_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e & fad.r2_odd32b_e))) -message "FRF w2[1] = r2 without bypass" -group core_array |
| 1654 | |
| 1655 | |
| 1656 | n2_frf_mp_256x78_cust frf ( |
| 1657 | |
| 1658 | .scan_in(frf_scanin), |
| 1659 | .scan_out(frf_scanout), |
| 1660 | .l2clk ( l2clk ), |
| 1661 | .pce ( 1'b1 ), |
| 1662 | |
| 1663 | .tcu_aclk ( spc_aclk ), |
| 1664 | .tcu_bclk ( spc_bclk ), |
| 1665 | |
| 1666 | .w1_addr ( fac_w1_addr_fb[4:0] ), |
| 1667 | .w1_tid ( fac_w1_tid_fb [2:0] ), |
| 1668 | .w1_valid ( fpc_w1_vld_fb [1:0] ), |
| 1669 | .w2_addr ( fad_w2_addr_fw[4:0] ), |
| 1670 | .w2_tid ( fad_w2_tid_fw[2:0] ), |
| 1671 | .w2_valid ( fad_w2_vld_fw[1:0] ), |
| 1672 | |
| 1673 | .w1_data ( fpf_w1_result_fb[63:0] ), |
| 1674 | .w1_ecc ( fpf_w1_synd_fb[13:0] ), |
| 1675 | .w2_data ( fad_w2_result_fw[63:0] ), |
| 1676 | .w2_ecc ( fec_w2_synd_fw[13:0] ), |
| 1677 | |
| 1678 | .r_tid ( fac_tid_d[2:0] ), |
| 1679 | .r1_valid ( fac_frf_r1_vld_d ), |
| 1680 | .r1_addr ( fac_frf_r1_addr_d[4:0] ), |
| 1681 | .r2_valid ( dec_frf_r2_vld_d ), |
| 1682 | .r2_addr ( dec_frf_r2_addr_d[4:0] ), |
| 1683 | |
| 1684 | |
| 1685 | .frf_r1_data ( frf_r1_data_e[63:0] ), |
| 1686 | .frf_r1_ecc ( frf_r1_ecc_e[13:0] ), |
| 1687 | .frf_r2_data ( frf_r2_data_e[63:0] ), |
| 1688 | .frf_r2_ecc ( frf_r2_ecc_e[13:0] ), |
| 1689 | .tcu_pce_ov(tcu_pce_ov), |
| 1690 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), |
| 1691 | .tcu_scan_en(tcu_scan_en), |
| 1692 | .tcu_se_scancollar_in(tcu_se_scancollar_in), |
| 1693 | .main_clken(main_clken) |
| 1694 | |
| 1695 | ); |
| 1696 | |
| 1697 | |
| 1698 | // fixscan start: |
| 1699 | assign fpf_scanin = scan_in ; |
| 1700 | assign fpy_scanin = fpf_scanout ; |
| 1701 | assign fpe_scanin = fpy_scanout ; |
| 1702 | assign fpc_scanin = fpe_scanout ; |
| 1703 | assign fic_scanin = fpc_scanout ; |
| 1704 | assign fgd_scanin = fic_scanout ; |
| 1705 | assign fdd_scanin = fgd_scanout ; |
| 1706 | assign fdc_scanin = fdd_scanout ; |
| 1707 | assign fad_scanin = fdc_scanout ; |
| 1708 | assign fac_scanin = fad_scanout ; |
| 1709 | assign fec_scanin = fac_scanout ; |
| 1710 | assign frf_scanin = fec_scanout ; |
| 1711 | assign scan_out = frf_scanout ; |
| 1712 | |
| 1713 | assign fpc_wmr_scanin = wmr_scan_in ; |
| 1714 | assign fgd_wmr_scanin = fpc_wmr_scanout ; |
| 1715 | assign fad_wmr_scanin = fgd_wmr_scanout ; |
| 1716 | assign fac_wmr_scanin = fad_wmr_scanout ; |
| 1717 | assign wmr_scan_out = fac_wmr_scanout ; |
| 1718 | // fixscan end: |
| 1719 | endmodule // fgu |