| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lsu_pic_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module lsu_pic_ctl ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | tcu_scan_en, |
| 40 | spc_aclk, |
| 41 | spc_bclk, |
| 42 | scan_out, |
| 43 | lmc_pcx_rq_vld, |
| 44 | lmc_asi_rq_vld, |
| 45 | lmc_ld_rq_p3, |
| 46 | lmc_ld_no_req_p4, |
| 47 | tlb_cache_hit_b, |
| 48 | dcc_early_ld_b, |
| 49 | sbc_asi_rq_p3, |
| 50 | sbc_pcx_rq_p3, |
| 51 | sbc_st_atomic_p2, |
| 52 | sbc_st_rq_p2, |
| 53 | sbc_pic_kill_store_p4_, |
| 54 | sbc_indet_block_p3, |
| 55 | sbs_stb_full, |
| 56 | asc_pid_ack, |
| 57 | dcc_asi_rtn_vld, |
| 58 | lsu_ring_ctl, |
| 59 | lsu_misc_pmen, |
| 60 | pic_ld_pcx_sel_p4, |
| 61 | pic_st_pcx_sel_p3, |
| 62 | pic_st_pcx_sel_p4, |
| 63 | pic_st_asi_sel_p3, |
| 64 | pic_st_asi_p4, |
| 65 | pic_ld_asi_p4, |
| 66 | pic_st_sel_p3, |
| 67 | pic_asi_sel_p4, |
| 68 | pic_asi_req, |
| 69 | pic_casa_squash_req, |
| 70 | pic_early_ld_b_sel_p3, |
| 71 | pic_no_load_p3, |
| 72 | pic_asi_busy, |
| 73 | l15_lsu_grant, |
| 74 | lsu_l15_valid, |
| 75 | lsu_l15_lock, |
| 76 | lsu_asi_clken); |
| 77 | wire se; |
| 78 | wire pce_ov; |
| 79 | wire stop; |
| 80 | wire siclk; |
| 81 | wire soclk; |
| 82 | wire l1clk; |
| 83 | wire stb_full_in; |
| 84 | wire dff_stb_full_scanin; |
| 85 | wire dff_stb_full_scanout; |
| 86 | wire stb_full; |
| 87 | wire [1:0] favor_count_inc; |
| 88 | wire [1:0] favor_count; |
| 89 | wire inc_count; |
| 90 | wire st_rq_p3; |
| 91 | wire no_ldst_p3; |
| 92 | wire asi_busy; |
| 93 | wire cancel_store_req_p3; |
| 94 | wire ld_pcx_sel_p3; |
| 95 | wire ld_asi_sel_p3; |
| 96 | wire clear_count; |
| 97 | wire [1:0] favor_count_in; |
| 98 | wire dff_st_favor_scanin; |
| 99 | wire dff_st_favor_scanout; |
| 100 | wire st_favor_p2; |
| 101 | wire st_block_ld_p2; |
| 102 | wire st_favor_p3; |
| 103 | wire st_block_ld_p3; |
| 104 | wire cancel_store_req_p2; |
| 105 | wire unqual_no_load_p2; |
| 106 | wire pcx_atm_p3; |
| 107 | wire block_casa_p3; |
| 108 | wire dff_pic_p2_scanin; |
| 109 | wire dff_pic_p2_scanout; |
| 110 | wire st_atomic_p3; |
| 111 | wire unqual_no_load_p3; |
| 112 | wire early_ld_miss_b; |
| 113 | wire pipe_load_req; |
| 114 | wire fifo_empty; |
| 115 | wire fifo_full; |
| 116 | wire pcx_atm_p4; |
| 117 | wire block_casa_p4; |
| 118 | wire ld_sel_p3; |
| 119 | wire st_sel_p3; |
| 120 | wire early_ld_b_sel_p3; |
| 121 | wire st_pcx_sel_p3; |
| 122 | wire st_asi_sel_p3; |
| 123 | wire any_pcx_sel_p3; |
| 124 | wire dff_pcx_p4_scanin; |
| 125 | wire dff_pcx_p4_scanout; |
| 126 | wire ld_pcx_sel_p4; |
| 127 | wire st_pcx_sel_p4; |
| 128 | wire early_ld_b_sel_pa; |
| 129 | wire cas2_select_p4; |
| 130 | wire cas2_select_p3; |
| 131 | wire dff_cas_select_scanin; |
| 132 | wire dff_cas_select_scanout; |
| 133 | wire last_early_inv; |
| 134 | wire [1:0] fifo_count_next; |
| 135 | wire [1:0] fifo_count; |
| 136 | wire dff_fifo_count_scanin; |
| 137 | wire dff_fifo_count_scanout; |
| 138 | wire dff_asi_ack_scanin; |
| 139 | wire dff_asi_ack_scanout; |
| 140 | wire asi_ack; |
| 141 | wire dff_asi_sel_pa_scanin; |
| 142 | wire dff_asi_sel_pa_scanout; |
| 143 | wire asi_req_ax; |
| 144 | wire kill_asi_st_p5; |
| 145 | wire asi_req_ax_next; |
| 146 | wire kill_asi_st_p4; |
| 147 | wire dff_asi_req_scanin; |
| 148 | wire dff_asi_req_scanout; |
| 149 | wire kill_store_p5_; |
| 150 | wire kill_store_p5__unused; |
| 151 | wire [1:0] asi_dec; |
| 152 | wire [4:0] asi_count_dec; |
| 153 | wire [4:0] asi_count; |
| 154 | wire [4:0] asi_count_in; |
| 155 | wire asi_clken_next; |
| 156 | wire dff_asi_pm_scanin; |
| 157 | wire dff_asi_pm_scanout; |
| 158 | wire spares_scanin; |
| 159 | wire spares_scanout; |
| 160 | |
| 161 | |
| 162 | input l2clk; |
| 163 | input scan_in; |
| 164 | input tcu_pce_ov; // scan signals |
| 165 | input tcu_scan_en; |
| 166 | input spc_aclk; |
| 167 | input spc_bclk; |
| 168 | output scan_out; |
| 169 | |
| 170 | input lmc_pcx_rq_vld; // LMQ needs access to PCX |
| 171 | input lmc_asi_rq_vld; // LMQ needs access to PCX |
| 172 | input lmc_ld_rq_p3; |
| 173 | input lmc_ld_no_req_p4; |
| 174 | |
| 175 | input tlb_cache_hit_b; |
| 176 | input dcc_early_ld_b; |
| 177 | |
| 178 | input sbc_asi_rq_p3; // STB needs access to PCX |
| 179 | input sbc_pcx_rq_p3; // STB needs access to PCX |
| 180 | input sbc_st_atomic_p2; |
| 181 | input sbc_st_rq_p2; |
| 182 | input sbc_pic_kill_store_p4_; |
| 183 | input sbc_indet_block_p3; |
| 184 | |
| 185 | input [7:0] sbs_stb_full; |
| 186 | |
| 187 | input asc_pid_ack; |
| 188 | input [7:0] dcc_asi_rtn_vld; |
| 189 | |
| 190 | input lsu_ring_ctl; |
| 191 | input lsu_misc_pmen; |
| 192 | |
| 193 | output pic_ld_pcx_sel_p4; |
| 194 | output pic_st_pcx_sel_p3; // store port has access |
| 195 | output pic_st_pcx_sel_p4; |
| 196 | output pic_st_asi_sel_p3; |
| 197 | output pic_st_asi_p4; |
| 198 | output pic_ld_asi_p4; |
| 199 | output pic_st_sel_p3; |
| 200 | output pic_asi_sel_p4; |
| 201 | output pic_asi_req; |
| 202 | output pic_casa_squash_req; |
| 203 | output pic_early_ld_b_sel_p3; |
| 204 | output pic_no_load_p3; // load cannot issue |
| 205 | output pic_asi_busy; |
| 206 | |
| 207 | input l15_lsu_grant; |
| 208 | output lsu_l15_valid; |
| 209 | output lsu_l15_lock; |
| 210 | output lsu_asi_clken; |
| 211 | |
| 212 | // scan renames |
| 213 | assign se = tcu_scan_en; |
| 214 | assign pce_ov = tcu_pce_ov; |
| 215 | assign stop = 1'b0; |
| 216 | assign siclk = spc_aclk; |
| 217 | assign soclk = spc_bclk; |
| 218 | // end scan |
| 219 | |
| 220 | ////////////////////////////// |
| 221 | // Clock header |
| 222 | ////////////////////////////// |
| 223 | lsu_pic_ctl_l1clkhdr_ctl_macro clkgen ( |
| 224 | .l2clk (l2clk ), |
| 225 | .l1en (1'b1 ), |
| 226 | .l1clk (l1clk ), |
| 227 | .pce_ov(pce_ov), |
| 228 | .stop(stop), |
| 229 | .se(se) |
| 230 | ); |
| 231 | |
| 232 | assign stb_full_in = |(sbs_stb_full[7:0]); |
| 233 | |
| 234 | lsu_pic_ctl_msff_ctl_macro__width_1 dff_stb_full ( |
| 235 | .scan_in(dff_stb_full_scanin), |
| 236 | .scan_out(dff_stb_full_scanout), |
| 237 | .din (stb_full_in), |
| 238 | .dout (stb_full), |
| 239 | .l1clk(l1clk), |
| 240 | .siclk(siclk), |
| 241 | .soclk(soclk) |
| 242 | ); |
| 243 | |
| 244 | //////////////////////////////////////////////////////////////////////////////// |
| 245 | // Source arbitration |
| 246 | // Loads and stores must arbitrate against each other for pcx/asi access |
| 247 | // Loads are generally favored over stores unless |
| 248 | // (i) stores get favor every 4 cycles if they've been waiting |
| 249 | // (ii) stores get favor every 2 cycles if they've been waiting and a store |
| 250 | // buffer is full |
| 251 | // * - CAS second packet (from LMQ) must always follow the first packet |
| 252 | // * - when a CAS is pending, ALL requests must wait until the FIFO is empty |
| 253 | // to avoid starving the CAS |
| 254 | // * - to avoid various potential store livelock cases, if a store request |
| 255 | // is rejected while the st_favor condition is true, loads requests will |
| 256 | // be suppressed until the store can be issued |
| 257 | //////////////////////////////////////////////////////////////////////////////// |
| 258 | |
| 259 | assign favor_count_inc[1:0] = favor_count[1:0] + 2'b01; |
| 260 | assign inc_count = (st_rq_p3 & ~pic_st_sel_p3 & ~no_ldst_p3 & ~(sbc_asi_rq_p3 & asi_busy & (pic_st_asi_p4 | lmc_asi_rq_vld))) | |
| 261 | (cancel_store_req_p3 & (ld_pcx_sel_p3 | ld_asi_sel_p3)); |
| 262 | assign clear_count = st_rq_p3 & pic_st_sel_p3; |
| 263 | assign favor_count_in[1:0] = {2{~clear_count}} & (inc_count ? favor_count_inc[1:0] : favor_count[1:0]); |
| 264 | |
| 265 | lsu_pic_ctl_msff_ctl_macro__width_4 dff_st_favor ( |
| 266 | .scan_in(dff_st_favor_scanin), |
| 267 | .scan_out(dff_st_favor_scanout), |
| 268 | .din ({st_favor_p2,st_block_ld_p2,favor_count_in[1:0]}), |
| 269 | .dout ({st_favor_p3,st_block_ld_p3,favor_count[1:0]}), |
| 270 | .l1clk(l1clk), |
| 271 | .siclk(siclk), |
| 272 | .soclk(soclk) |
| 273 | ); |
| 274 | |
| 275 | assign st_favor_p2 = ((&favor_count[1:0] | (favor_count[0] & (stb_full | sbc_st_atomic_p2))) & inc_count) | |
| 276 | (st_favor_p3 & ~pic_st_sel_p3); |
| 277 | |
| 278 | assign st_block_ld_p2 = (st_favor_p3 & st_rq_p3 & ~pic_st_sel_p3) | (st_block_ld_p3 & ~pic_st_sel_p3); |
| 279 | |
| 280 | ////////// |
| 281 | // P2 - early signals for ld/st arb |
| 282 | ////////// |
| 283 | |
| 284 | // Still must be qualified with fifo_full in P3 |
| 285 | // Loads never win when |
| 286 | // Stores have favor and are requesting OR |
| 287 | // CASA was picked last cycle OR |
| 288 | // CASA was blocked last cycle |
| 289 | |
| 290 | // If a store requests but doesn't win arbitration, then stores can't win in the next |
| 291 | // cycle either. Otherwise, we create a livelock possibility where ST0 wins thread arb |
| 292 | // in p2, but loses ld/st arb in P3. Meanwhile, ST1 wins thread arb in the next P2, and |
| 293 | // wins ld/st arb in it's P3. This can continue indefinitely. |
| 294 | |
| 295 | assign cancel_store_req_p2 = st_rq_p3 & ~pic_st_sel_p3 & ~cancel_store_req_p3; |
| 296 | |
| 297 | assign unqual_no_load_p2 = (st_favor_p2 & sbc_st_rq_p2 & ~cancel_store_req_p2) | |
| 298 | st_block_ld_p2 | pcx_atm_p3 | block_casa_p3; |
| 299 | |
| 300 | lsu_pic_ctl_msff_ctl_macro__width_4 dff_pic_p2 ( |
| 301 | .scan_in(dff_pic_p2_scanin), |
| 302 | .scan_out(dff_pic_p2_scanout), |
| 303 | .din ({sbc_st_atomic_p2,unqual_no_load_p2,sbc_st_rq_p2,cancel_store_req_p2}), |
| 304 | .dout ({ st_atomic_p3,unqual_no_load_p3, st_rq_p3,cancel_store_req_p3}), |
| 305 | .l1clk(l1clk), |
| 306 | .siclk(siclk), |
| 307 | .soclk(soclk) |
| 308 | ); |
| 309 | |
| 310 | ////////// |
| 311 | // P3 - ld/st arb |
| 312 | ////////// |
| 313 | |
| 314 | assign early_ld_miss_b = dcc_early_ld_b & ~tlb_cache_hit_b; |
| 315 | |
| 316 | assign pipe_load_req = early_ld_miss_b & ~lmc_ld_rq_p3; |
| 317 | assign block_casa_p3 = st_atomic_p3 & ~cancel_store_req_p3 & ~fifo_empty; |
| 318 | assign pic_no_load_p3 = unqual_no_load_p3 | fifo_full | block_casa_p3 | sbc_indet_block_p3; |
| 319 | |
| 320 | |
| 321 | // Don't select anything if CASA selected last cycle (CAS2 must go) or fifo is full |
| 322 | assign no_ldst_p3 = pcx_atm_p4 | fifo_full | block_casa_p4 | sbc_indet_block_p3; |
| 323 | |
| 324 | assign ld_sel_p3 = (lmc_ld_rq_p3 | early_ld_miss_b) & ~pic_no_load_p3; |
| 325 | assign st_sel_p3 = st_rq_p3 & (st_favor_p3 | ~(lmc_ld_rq_p3 | early_ld_miss_b)) & ~block_casa_p3 & |
| 326 | ~no_ldst_p3 & ~cancel_store_req_p3; |
| 327 | |
| 328 | // 0in bits_on -var {st_sel_p3,ld_sel_p3} -max 1 -message "load and store selected for pcx" |
| 329 | |
| 330 | assign early_ld_b_sel_p3 = ld_sel_p3 & ~lmc_ld_rq_p3 & early_ld_miss_b; |
| 331 | |
| 332 | // 0in bits_on -var {ld_pcx_sel_p3,ld_asi_sel_p3} -max 1 -message "asi and pcx loads selected" |
| 333 | // 0in bits_on -var {st_pcx_sel_p3,st_asi_sel_p3} -max 1 -message "asi and pcx stores selected" |
| 334 | |
| 335 | assign ld_pcx_sel_p3 = ld_sel_p3 & (lmc_pcx_rq_vld | pipe_load_req); |
| 336 | assign st_pcx_sel_p3 = st_sel_p3 & sbc_pcx_rq_p3; |
| 337 | |
| 338 | assign ld_asi_sel_p3 = ld_sel_p3 & lmc_asi_rq_vld & ~asi_busy; |
| 339 | assign st_asi_sel_p3 = st_sel_p3 & sbc_asi_rq_p3 & ~asi_busy; |
| 340 | |
| 341 | assign pic_st_asi_sel_p3 = st_asi_sel_p3; |
| 342 | |
| 343 | assign pic_st_sel_p3 = st_pcx_sel_p3 | st_asi_sel_p3; |
| 344 | |
| 345 | assign pic_st_pcx_sel_p3 = st_pcx_sel_p3; |
| 346 | assign pic_early_ld_b_sel_p3 = early_ld_b_sel_p3; // to lmc |
| 347 | |
| 348 | |
| 349 | assign any_pcx_sel_p3 = ld_pcx_sel_p3 | st_pcx_sel_p3 | pcx_atm_p4; |
| 350 | |
| 351 | assign pcx_atm_p3 = st_pcx_sel_p3 & st_atomic_p3; |
| 352 | |
| 353 | |
| 354 | |
| 355 | lsu_pic_ctl_msff_ctl_macro__width_5 dff_pcx_p4 ( |
| 356 | .scan_in(dff_pcx_p4_scanin), |
| 357 | .scan_out(dff_pcx_p4_scanout), |
| 358 | .din ({ld_pcx_sel_p3,st_pcx_sel_p3,early_ld_b_sel_p3,pcx_atm_p3,block_casa_p3}), |
| 359 | .dout ({ld_pcx_sel_p4,st_pcx_sel_p4,early_ld_b_sel_pa,pcx_atm_p4,block_casa_p4}), |
| 360 | .l1clk(l1clk), |
| 361 | .siclk(siclk), |
| 362 | .soclk(soclk) |
| 363 | ); |
| 364 | |
| 365 | ////////// |
| 366 | // P4 - drive packets to l1g |
| 367 | ////////// |
| 368 | |
| 369 | assign pic_ld_pcx_sel_p4 = ld_pcx_sel_p4 | cas2_select_p4; |
| 370 | assign pic_st_pcx_sel_p4 = st_pcx_sel_p4; |
| 371 | |
| 372 | assign lsu_l15_valid = (ld_pcx_sel_p4 & ~lmc_ld_no_req_p4) | cas2_select_p4 | pic_st_pcx_sel_p4; |
| 373 | |
| 374 | assign pic_casa_squash_req = pcx_atm_p4; |
| 375 | |
| 376 | assign lsu_l15_lock = pcx_atm_p4; // lock for atomic packets |
| 377 | |
| 378 | // CAS2 packet comes from LMQ. |
| 379 | assign cas2_select_p3 = pcx_atm_p4; |
| 380 | |
| 381 | lsu_pic_ctl_msff_ctl_macro__width_1 dff_cas_select ( |
| 382 | .scan_in(dff_cas_select_scanin), |
| 383 | .scan_out(dff_cas_select_scanout), |
| 384 | .din (cas2_select_p3), |
| 385 | .dout (cas2_select_p4), |
| 386 | .l1clk(l1clk), |
| 387 | .siclk(siclk), |
| 388 | .soclk(soclk) |
| 389 | ); |
| 390 | |
| 391 | //////////////////////////////////////////////////////////////////////////////// |
| 392 | // Gasket FIFO Queue Tracking |
| 393 | // The gasket contains a two-entry FIFO. It's the LSU's responsibility to not |
| 394 | // overflow this fifo. Keep track of requests and grants to maintain the count. |
| 395 | // This count needs to be maintained based on the P3 cycle so that arbitration |
| 396 | // is halted if the FIFO is full. |
| 397 | // Increment the count for each ld/st sent (any_pcx_sel_p3) |
| 398 | // Decrement the count for each grant received (l15_lsu_grant) |
| 399 | // Decrement the count for a load sent, but invalidated in P4 (last_early_inv) |
| 400 | //////////////////////////////////////////////////////////////////////////////// |
| 401 | |
| 402 | //assign fifo_count_inc[1:0] = fifo_count[1:0] + 2'b01; |
| 403 | //assign fifo_count_dec[1:0] = fifo_count[1:0] - 2'b01; |
| 404 | //assign fifo_count_dec2[1:0] = fifo_count[1:0] - 2'b10; |
| 405 | |
| 406 | assign last_early_inv = early_ld_b_sel_pa & ~lsu_l15_valid; |
| 407 | |
| 408 | assign fifo_count_next[1] = (fifo_count[1] & ~last_early_inv & (any_pcx_sel_p3 | ~l15_lsu_grant)) | |
| 409 | (fifo_count[0] & any_pcx_sel_p3 & ~l15_lsu_grant & ~last_early_inv) ; |
| 410 | |
| 411 | assign fifo_count_next[0] = (fifo_count[0] & ~last_early_inv & (any_pcx_sel_p3 ~^ l15_lsu_grant)) | // 1->1 |
| 412 | (~fifo_count[0] & any_pcx_sel_p3 & ~l15_lsu_grant) | // 0->1 |
| 413 | (~fifo_count[0] & last_early_inv & (~l15_lsu_grant | any_pcx_sel_p3)) | // 2->1 |
| 414 | (~fifo_count[0] & ~any_pcx_sel_p3 & l15_lsu_grant & ~last_early_inv) | // 2->1 |
| 415 | (any_pcx_sel_p3 & ~l15_lsu_grant & last_early_inv); // 1->1 |
| 416 | |
| 417 | lsu_pic_ctl_msff_ctl_macro__width_2 dff_fifo_count ( |
| 418 | .scan_in(dff_fifo_count_scanin), |
| 419 | .scan_out(dff_fifo_count_scanout), |
| 420 | .din (fifo_count_next[1:0]), |
| 421 | .dout (fifo_count[1:0]), |
| 422 | .l1clk(l1clk), |
| 423 | .siclk(siclk), |
| 424 | .soclk(soclk) |
| 425 | ); |
| 426 | |
| 427 | // 0in underflow -var fifo_count[1:0] |
| 428 | // 0in maximum 2 -var fifo_count[1:0] |
| 429 | |
| 430 | assign fifo_full = fifo_count[1] & ~l15_lsu_grant; |
| 431 | assign fifo_empty = ~fifo_count[1] & (~fifo_count[0] | l15_lsu_grant); |
| 432 | |
| 433 | //////// |
| 434 | // P4 - ASI |
| 435 | //////// |
| 436 | |
| 437 | // asc_pid_ack returns (best case) on the same cycle as the packet is sent |
| 438 | lsu_pic_ctl_msff_ctl_macro__width_1 dff_asi_ack ( |
| 439 | .scan_in(dff_asi_ack_scanin), |
| 440 | .scan_out(dff_asi_ack_scanout), |
| 441 | .din (asc_pid_ack), |
| 442 | .dout (asi_ack), |
| 443 | .l1clk(l1clk), |
| 444 | .siclk(siclk), |
| 445 | .soclk(soclk) |
| 446 | ); |
| 447 | |
| 448 | lsu_pic_ctl_msff_ctl_macro__width_2 dff_asi_sel_pa ( |
| 449 | .scan_in(dff_asi_sel_pa_scanin), |
| 450 | .scan_out(dff_asi_sel_pa_scanout), |
| 451 | .din ({ld_asi_sel_p3,st_asi_sel_p3}), |
| 452 | .dout ({pic_ld_asi_p4,pic_st_asi_p4}), |
| 453 | .l1clk(l1clk), |
| 454 | .siclk(siclk), |
| 455 | .soclk(soclk) |
| 456 | ); |
| 457 | |
| 458 | assign pic_asi_sel_p4 = pic_ld_asi_p4 | pic_st_asi_p4; |
| 459 | |
| 460 | assign pic_asi_req = (pic_asi_sel_p4 | asi_req_ax) & ~kill_asi_st_p5; |
| 461 | |
| 462 | assign asi_req_ax_next = (pic_asi_sel_p4 | (asi_req_ax & ~asi_ack)) & ~kill_asi_st_p5; |
| 463 | |
| 464 | assign kill_asi_st_p4 = pic_st_asi_p4 & ~sbc_pic_kill_store_p4_; |
| 465 | |
| 466 | lsu_pic_ctl_msff_ctl_macro__width_3 dff_asi_req ( |
| 467 | .scan_in(dff_asi_req_scanin), |
| 468 | .scan_out(dff_asi_req_scanout), |
| 469 | .din ({asi_req_ax_next,sbc_pic_kill_store_p4_,kill_asi_st_p4}), |
| 470 | .dout ({asi_req_ax, kill_store_p5_, kill_asi_st_p5}), |
| 471 | .l1clk(l1clk), |
| 472 | .siclk(siclk), |
| 473 | .soclk(soclk) |
| 474 | ); |
| 475 | assign kill_store_p5__unused = kill_store_p5_; |
| 476 | |
| 477 | // ASI interface will be busy in the cycle following a request until the request is acked |
| 478 | assign asi_busy = (pic_asi_sel_p4 | asi_req_ax) & ~asi_ack; |
| 479 | assign pic_asi_busy = asi_busy; |
| 480 | |
| 481 | //////////////////////////////////////////////////////////////////////////////// |
| 482 | // ASI ring power management |
| 483 | // Keep count of number of ring transactions outstanding. If >0, enable the ring. |
| 484 | // Increment each time an ASI request is selected (watch for errors) |
| 485 | // Decrement each time it returns from the ring |
| 486 | // Shut down the ring so that bit[64] is held low. |
| 487 | //////////////////////////////////////////////////////////////////////////////// |
| 488 | |
| 489 | assign asi_dec[1:0] = {1'b0,|(dcc_asi_rtn_vld[7:0])} + {1'b0,kill_asi_st_p5}; |
| 490 | assign asi_count_dec[4:0] = asi_count[4:0] - {3'b000,asi_dec[1:0]}; |
| 491 | |
| 492 | assign asi_count_in[4:0] = asi_count_dec[4:0] + {4'b0000,(ld_asi_sel_p3 | st_asi_sel_p3)}; |
| 493 | |
| 494 | assign asi_clken_next = ~lsu_misc_pmen | ld_asi_sel_p3 | st_asi_sel_p3 | (|(asi_count[4:0])) | |
| 495 | (lsu_asi_clken & ~lsu_ring_ctl); |
| 496 | |
| 497 | lsu_pic_ctl_msff_ctl_macro__width_6 dff_asi_pm ( |
| 498 | .scan_in(dff_asi_pm_scanin), |
| 499 | .scan_out(dff_asi_pm_scanout), |
| 500 | .din ({asi_clken_next,asi_count_in[4:0]}), |
| 501 | .dout ({lsu_asi_clken, asi_count[4:0]}), |
| 502 | .l1clk(l1clk), |
| 503 | .siclk(siclk), |
| 504 | .soclk(soclk) |
| 505 | ); |
| 506 | // 0in underflow -var asi_count[4:0] |
| 507 | // 0in overflow -var asi_count[4:0] |
| 508 | |
| 509 | |
| 510 | lsu_pic_ctl_spare_ctl_macro__num_1 spares ( |
| 511 | .scan_in(spares_scanin), |
| 512 | .scan_out(spares_scanout), |
| 513 | .l1clk (l1clk), |
| 514 | .siclk(siclk), |
| 515 | .soclk(soclk) |
| 516 | ); |
| 517 | |
| 518 | supply0 vss; |
| 519 | supply1 vdd; |
| 520 | // fixscan start: |
| 521 | assign dff_stb_full_scanin = scan_in ; |
| 522 | assign dff_st_favor_scanin = dff_stb_full_scanout ; |
| 523 | assign dff_pic_p2_scanin = dff_st_favor_scanout ; |
| 524 | assign dff_pcx_p4_scanin = dff_pic_p2_scanout ; |
| 525 | assign dff_cas_select_scanin = dff_pcx_p4_scanout ; |
| 526 | assign dff_fifo_count_scanin = dff_cas_select_scanout ; |
| 527 | assign dff_asi_ack_scanin = dff_fifo_count_scanout ; |
| 528 | assign dff_asi_sel_pa_scanin = dff_asi_ack_scanout ; |
| 529 | assign dff_asi_req_scanin = dff_asi_sel_pa_scanout ; |
| 530 | assign dff_asi_pm_scanin = dff_asi_req_scanout ; |
| 531 | assign spares_scanin = dff_asi_pm_scanout ; |
| 532 | assign scan_out = spares_scanout ; |
| 533 | // fixscan end: |
| 534 | endmodule |
| 535 | |
| 536 | |
| 537 | |
| 538 | |
| 539 | |
| 540 | |
| 541 | // any PARAMS parms go into naming of macro |
| 542 | |
| 543 | module lsu_pic_ctl_l1clkhdr_ctl_macro ( |
| 544 | l2clk, |
| 545 | l1en, |
| 546 | pce_ov, |
| 547 | stop, |
| 548 | se, |
| 549 | l1clk); |
| 550 | |
| 551 | |
| 552 | input l2clk; |
| 553 | input l1en; |
| 554 | input pce_ov; |
| 555 | input stop; |
| 556 | input se; |
| 557 | output l1clk; |
| 558 | |
| 559 | |
| 560 | |
| 561 | |
| 562 | |
| 563 | cl_sc1_l1hdr_8x c_0 ( |
| 564 | |
| 565 | |
| 566 | .l2clk(l2clk), |
| 567 | .pce(l1en), |
| 568 | .l1clk(l1clk), |
| 569 | .se(se), |
| 570 | .pce_ov(pce_ov), |
| 571 | .stop(stop) |
| 572 | ); |
| 573 | |
| 574 | |
| 575 | |
| 576 | endmodule |
| 577 | |
| 578 | |
| 579 | |
| 580 | |
| 581 | |
| 582 | |
| 583 | |
| 584 | |
| 585 | |
| 586 | |
| 587 | |
| 588 | |
| 589 | |
| 590 | // any PARAMS parms go into naming of macro |
| 591 | |
| 592 | module lsu_pic_ctl_msff_ctl_macro__width_1 ( |
| 593 | din, |
| 594 | l1clk, |
| 595 | scan_in, |
| 596 | siclk, |
| 597 | soclk, |
| 598 | dout, |
| 599 | scan_out); |
| 600 | wire [0:0] fdin; |
| 601 | |
| 602 | input [0:0] din; |
| 603 | input l1clk; |
| 604 | input scan_in; |
| 605 | |
| 606 | |
| 607 | input siclk; |
| 608 | input soclk; |
| 609 | |
| 610 | output [0:0] dout; |
| 611 | output scan_out; |
| 612 | assign fdin[0:0] = din[0:0]; |
| 613 | |
| 614 | |
| 615 | |
| 616 | |
| 617 | |
| 618 | |
| 619 | dff #(1) d0_0 ( |
| 620 | .l1clk(l1clk), |
| 621 | .siclk(siclk), |
| 622 | .soclk(soclk), |
| 623 | .d(fdin[0:0]), |
| 624 | .si(scan_in), |
| 625 | .so(scan_out), |
| 626 | .q(dout[0:0]) |
| 627 | ); |
| 628 | |
| 629 | |
| 630 | |
| 631 | |
| 632 | |
| 633 | |
| 634 | |
| 635 | |
| 636 | |
| 637 | |
| 638 | |
| 639 | |
| 640 | endmodule |
| 641 | |
| 642 | |
| 643 | |
| 644 | |
| 645 | |
| 646 | |
| 647 | |
| 648 | |
| 649 | |
| 650 | |
| 651 | |
| 652 | |
| 653 | |
| 654 | // any PARAMS parms go into naming of macro |
| 655 | |
| 656 | module lsu_pic_ctl_msff_ctl_macro__width_4 ( |
| 657 | din, |
| 658 | l1clk, |
| 659 | scan_in, |
| 660 | siclk, |
| 661 | soclk, |
| 662 | dout, |
| 663 | scan_out); |
| 664 | wire [3:0] fdin; |
| 665 | wire [2:0] so; |
| 666 | |
| 667 | input [3:0] din; |
| 668 | input l1clk; |
| 669 | input scan_in; |
| 670 | |
| 671 | |
| 672 | input siclk; |
| 673 | input soclk; |
| 674 | |
| 675 | output [3:0] dout; |
| 676 | output scan_out; |
| 677 | assign fdin[3:0] = din[3:0]; |
| 678 | |
| 679 | |
| 680 | |
| 681 | |
| 682 | |
| 683 | |
| 684 | dff #(4) d0_0 ( |
| 685 | .l1clk(l1clk), |
| 686 | .siclk(siclk), |
| 687 | .soclk(soclk), |
| 688 | .d(fdin[3:0]), |
| 689 | .si({scan_in,so[2:0]}), |
| 690 | .so({so[2:0],scan_out}), |
| 691 | .q(dout[3:0]) |
| 692 | ); |
| 693 | |
| 694 | |
| 695 | |
| 696 | |
| 697 | |
| 698 | |
| 699 | |
| 700 | |
| 701 | |
| 702 | |
| 703 | |
| 704 | |
| 705 | endmodule |
| 706 | |
| 707 | |
| 708 | |
| 709 | |
| 710 | |
| 711 | |
| 712 | |
| 713 | |
| 714 | |
| 715 | |
| 716 | |
| 717 | |
| 718 | |
| 719 | // any PARAMS parms go into naming of macro |
| 720 | |
| 721 | module lsu_pic_ctl_msff_ctl_macro__width_5 ( |
| 722 | din, |
| 723 | l1clk, |
| 724 | scan_in, |
| 725 | siclk, |
| 726 | soclk, |
| 727 | dout, |
| 728 | scan_out); |
| 729 | wire [4:0] fdin; |
| 730 | wire [3:0] so; |
| 731 | |
| 732 | input [4:0] din; |
| 733 | input l1clk; |
| 734 | input scan_in; |
| 735 | |
| 736 | |
| 737 | input siclk; |
| 738 | input soclk; |
| 739 | |
| 740 | output [4:0] dout; |
| 741 | output scan_out; |
| 742 | assign fdin[4:0] = din[4:0]; |
| 743 | |
| 744 | |
| 745 | |
| 746 | |
| 747 | |
| 748 | |
| 749 | dff #(5) d0_0 ( |
| 750 | .l1clk(l1clk), |
| 751 | .siclk(siclk), |
| 752 | .soclk(soclk), |
| 753 | .d(fdin[4:0]), |
| 754 | .si({scan_in,so[3:0]}), |
| 755 | .so({so[3:0],scan_out}), |
| 756 | .q(dout[4:0]) |
| 757 | ); |
| 758 | |
| 759 | |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | |
| 766 | |
| 767 | |
| 768 | |
| 769 | |
| 770 | endmodule |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | |
| 778 | |
| 779 | |
| 780 | |
| 781 | |
| 782 | |
| 783 | |
| 784 | // any PARAMS parms go into naming of macro |
| 785 | |
| 786 | module lsu_pic_ctl_msff_ctl_macro__width_2 ( |
| 787 | din, |
| 788 | l1clk, |
| 789 | scan_in, |
| 790 | siclk, |
| 791 | soclk, |
| 792 | dout, |
| 793 | scan_out); |
| 794 | wire [1:0] fdin; |
| 795 | wire [0:0] so; |
| 796 | |
| 797 | input [1:0] din; |
| 798 | input l1clk; |
| 799 | input scan_in; |
| 800 | |
| 801 | |
| 802 | input siclk; |
| 803 | input soclk; |
| 804 | |
| 805 | output [1:0] dout; |
| 806 | output scan_out; |
| 807 | assign fdin[1:0] = din[1:0]; |
| 808 | |
| 809 | |
| 810 | |
| 811 | |
| 812 | |
| 813 | |
| 814 | dff #(2) d0_0 ( |
| 815 | .l1clk(l1clk), |
| 816 | .siclk(siclk), |
| 817 | .soclk(soclk), |
| 818 | .d(fdin[1:0]), |
| 819 | .si({scan_in,so[0:0]}), |
| 820 | .so({so[0:0],scan_out}), |
| 821 | .q(dout[1:0]) |
| 822 | ); |
| 823 | |
| 824 | |
| 825 | |
| 826 | |
| 827 | |
| 828 | |
| 829 | |
| 830 | |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | endmodule |
| 836 | |
| 837 | |
| 838 | |
| 839 | |
| 840 | |
| 841 | |
| 842 | |
| 843 | |
| 844 | |
| 845 | |
| 846 | |
| 847 | |
| 848 | |
| 849 | // any PARAMS parms go into naming of macro |
| 850 | |
| 851 | module lsu_pic_ctl_msff_ctl_macro__width_3 ( |
| 852 | din, |
| 853 | l1clk, |
| 854 | scan_in, |
| 855 | siclk, |
| 856 | soclk, |
| 857 | dout, |
| 858 | scan_out); |
| 859 | wire [2:0] fdin; |
| 860 | wire [1:0] so; |
| 861 | |
| 862 | input [2:0] din; |
| 863 | input l1clk; |
| 864 | input scan_in; |
| 865 | |
| 866 | |
| 867 | input siclk; |
| 868 | input soclk; |
| 869 | |
| 870 | output [2:0] dout; |
| 871 | output scan_out; |
| 872 | assign fdin[2:0] = din[2:0]; |
| 873 | |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | dff #(3) d0_0 ( |
| 880 | .l1clk(l1clk), |
| 881 | .siclk(siclk), |
| 882 | .soclk(soclk), |
| 883 | .d(fdin[2:0]), |
| 884 | .si({scan_in,so[1:0]}), |
| 885 | .so({so[1:0],scan_out}), |
| 886 | .q(dout[2:0]) |
| 887 | ); |
| 888 | |
| 889 | |
| 890 | |
| 891 | |
| 892 | |
| 893 | |
| 894 | |
| 895 | |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | endmodule |
| 901 | |
| 902 | |
| 903 | |
| 904 | |
| 905 | |
| 906 | |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | |
| 914 | // any PARAMS parms go into naming of macro |
| 915 | |
| 916 | module lsu_pic_ctl_msff_ctl_macro__width_6 ( |
| 917 | din, |
| 918 | l1clk, |
| 919 | scan_in, |
| 920 | siclk, |
| 921 | soclk, |
| 922 | dout, |
| 923 | scan_out); |
| 924 | wire [5:0] fdin; |
| 925 | wire [4:0] so; |
| 926 | |
| 927 | input [5:0] din; |
| 928 | input l1clk; |
| 929 | input scan_in; |
| 930 | |
| 931 | |
| 932 | input siclk; |
| 933 | input soclk; |
| 934 | |
| 935 | output [5:0] dout; |
| 936 | output scan_out; |
| 937 | assign fdin[5:0] = din[5:0]; |
| 938 | |
| 939 | |
| 940 | |
| 941 | |
| 942 | |
| 943 | |
| 944 | dff #(6) d0_0 ( |
| 945 | .l1clk(l1clk), |
| 946 | .siclk(siclk), |
| 947 | .soclk(soclk), |
| 948 | .d(fdin[5:0]), |
| 949 | .si({scan_in,so[4:0]}), |
| 950 | .so({so[4:0],scan_out}), |
| 951 | .q(dout[5:0]) |
| 952 | ); |
| 953 | |
| 954 | |
| 955 | |
| 956 | |
| 957 | |
| 958 | |
| 959 | |
| 960 | |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | endmodule |
| 966 | |
| 967 | |
| 968 | |
| 969 | |
| 970 | |
| 971 | |
| 972 | |
| 973 | |
| 974 | |
| 975 | // Description: Spare gate macro for control blocks |
| 976 | // |
| 977 | // Param num controls the number of times the macro is added |
| 978 | // flops=0 can be used to use only combination spare logic |
| 979 | |
| 980 | |
| 981 | module lsu_pic_ctl_spare_ctl_macro__num_1 ( |
| 982 | l1clk, |
| 983 | scan_in, |
| 984 | siclk, |
| 985 | soclk, |
| 986 | scan_out); |
| 987 | wire si_0; |
| 988 | wire so_0; |
| 989 | wire spare0_flop_unused; |
| 990 | wire spare0_buf_32x_unused; |
| 991 | wire spare0_nand3_8x_unused; |
| 992 | wire spare0_inv_8x_unused; |
| 993 | wire spare0_aoi22_4x_unused; |
| 994 | wire spare0_buf_8x_unused; |
| 995 | wire spare0_oai22_4x_unused; |
| 996 | wire spare0_inv_16x_unused; |
| 997 | wire spare0_nand2_16x_unused; |
| 998 | wire spare0_nor3_4x_unused; |
| 999 | wire spare0_nand2_8x_unused; |
| 1000 | wire spare0_buf_16x_unused; |
| 1001 | wire spare0_nor2_16x_unused; |
| 1002 | wire spare0_inv_32x_unused; |
| 1003 | |
| 1004 | |
| 1005 | input l1clk; |
| 1006 | input scan_in; |
| 1007 | input siclk; |
| 1008 | input soclk; |
| 1009 | output scan_out; |
| 1010 | |
| 1011 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 1012 | .siclk(siclk), |
| 1013 | .soclk(soclk), |
| 1014 | .si(si_0), |
| 1015 | .so(so_0), |
| 1016 | .d(1'b0), |
| 1017 | .q(spare0_flop_unused)); |
| 1018 | assign si_0 = scan_in; |
| 1019 | |
| 1020 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 1021 | .out(spare0_buf_32x_unused)); |
| 1022 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 1023 | .in1(1'b1), |
| 1024 | .in2(1'b1), |
| 1025 | .out(spare0_nand3_8x_unused)); |
| 1026 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 1027 | .out(spare0_inv_8x_unused)); |
| 1028 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 1029 | .in01(1'b1), |
| 1030 | .in10(1'b1), |
| 1031 | .in11(1'b1), |
| 1032 | .out(spare0_aoi22_4x_unused)); |
| 1033 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 1034 | .out(spare0_buf_8x_unused)); |
| 1035 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 1036 | .in01(1'b1), |
| 1037 | .in10(1'b1), |
| 1038 | .in11(1'b1), |
| 1039 | .out(spare0_oai22_4x_unused)); |
| 1040 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 1041 | .out(spare0_inv_16x_unused)); |
| 1042 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 1043 | .in1(1'b1), |
| 1044 | .out(spare0_nand2_16x_unused)); |
| 1045 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 1046 | .in1(1'b0), |
| 1047 | .in2(1'b0), |
| 1048 | .out(spare0_nor3_4x_unused)); |
| 1049 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 1050 | .in1(1'b1), |
| 1051 | .out(spare0_nand2_8x_unused)); |
| 1052 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 1053 | .out(spare0_buf_16x_unused)); |
| 1054 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 1055 | .in1(1'b0), |
| 1056 | .out(spare0_nor2_16x_unused)); |
| 1057 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 1058 | .out(spare0_inv_32x_unused)); |
| 1059 | assign scan_out = so_0; |
| 1060 | |
| 1061 | |
| 1062 | |
| 1063 | endmodule |
| 1064 | |