| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mmu_mel_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mmu_mel_dp ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | spc_aclk, |
| 40 | spc_bclk, |
| 41 | tcu_scan_en, |
| 42 | tlu_cerer_mrau, |
| 43 | tlu_cerer_hwtwmu, |
| 44 | mra_parity, |
| 45 | med0_parity_err, |
| 46 | med1_parity_err, |
| 47 | scan_out, |
| 48 | mel_crit_parity, |
| 49 | mel_parity, |
| 50 | mel_parity_err, |
| 51 | mel_htc_parity_err); |
| 52 | wire pce_ov; |
| 53 | wire clk; |
| 54 | wire stop; |
| 55 | wire siclk; |
| 56 | wire soclk; |
| 57 | wire se; |
| 58 | wire en; |
| 59 | wire ecc_lat_scanin; |
| 60 | wire ecc_lat_scanout; |
| 61 | wire parity_err_in; |
| 62 | wire parity_err_for_htc_in; |
| 63 | wire [1:0] rd_parity; |
| 64 | wire parity_err; |
| 65 | wire parity_err_for_htc; |
| 66 | wire cerer_mrau_; |
| 67 | wire cerer_hwtwmu_; |
| 68 | wire pparity_err_; |
| 69 | |
| 70 | |
| 71 | |
| 72 | |
| 73 | input l2clk; |
| 74 | input scan_in; |
| 75 | input tcu_pce_ov; |
| 76 | input spc_aclk; |
| 77 | input spc_bclk; |
| 78 | input tcu_scan_en; |
| 79 | |
| 80 | input tlu_cerer_mrau; |
| 81 | input tlu_cerer_hwtwmu; |
| 82 | |
| 83 | input [1:0] mra_parity; |
| 84 | |
| 85 | input med0_parity_err; |
| 86 | input med1_parity_err; |
| 87 | |
| 88 | |
| 89 | output scan_out; |
| 90 | |
| 91 | output [1:0] mel_crit_parity; |
| 92 | output [1:0] mel_parity; |
| 93 | |
| 94 | output mel_parity_err; |
| 95 | output mel_htc_parity_err; |
| 96 | |
| 97 | |
| 98 | |
| 99 | //////////////////////////////////////////////////////////////////////////////// |
| 100 | |
| 101 | assign pce_ov = tcu_pce_ov; |
| 102 | assign clk = l2clk; |
| 103 | assign stop = 1'b0; |
| 104 | assign siclk = spc_aclk; |
| 105 | assign soclk = spc_bclk; |
| 106 | assign se = tcu_scan_en; |
| 107 | assign en = 1'b1; |
| 108 | |
| 109 | |
| 110 | |
| 111 | // Data is flopped, but parity is not... so flop here |
| 112 | |
| 113 | mmu_mel_dp_msff_macro__width_4 ecc_lat ( |
| 114 | .scan_in(ecc_lat_scanin), |
| 115 | .scan_out(ecc_lat_scanout), |
| 116 | .din ({mra_parity [1:0], |
| 117 | parity_err_in , |
| 118 | parity_err_for_htc_in }), |
| 119 | .dout ({rd_parity [1:0], |
| 120 | parity_err , |
| 121 | parity_err_for_htc }), |
| 122 | .clk(clk), |
| 123 | .en(en), |
| 124 | .se(se), |
| 125 | .siclk(siclk), |
| 126 | .soclk(soclk), |
| 127 | .pce_ov(pce_ov), |
| 128 | .stop(stop) |
| 129 | ); |
| 130 | |
| 131 | assign mel_crit_parity[1:0] = |
| 132 | rd_parity[1:0]; |
| 133 | |
| 134 | mmu_mel_dp_buff_macro__rep_1__width_2 parity_buf ( |
| 135 | .din (rd_parity [1:0] ), |
| 136 | .dout (mel_parity [1:0] ) |
| 137 | ); |
| 138 | |
| 139 | // Qualify error signals |
| 140 | |
| 141 | |
| 142 | mmu_mel_dp_inv_macro__width_1 cerer_mrau_inv ( |
| 143 | .din (tlu_cerer_mrau ), |
| 144 | .dout (cerer_mrau_ ) |
| 145 | ); |
| 146 | |
| 147 | mmu_mel_dp_inv_macro__width_1 cerer_hwtwmu_inv ( |
| 148 | .din (tlu_cerer_hwtwmu ), |
| 149 | .dout (cerer_hwtwmu_ ) |
| 150 | ); |
| 151 | |
| 152 | mmu_mel_dp_nor_macro__ports_2__width_1 parity_err_inv_nor ( |
| 153 | .din0 (med0_parity_err ), |
| 154 | .din1 (med1_parity_err ), |
| 155 | .dout (pparity_err_ ) |
| 156 | ); |
| 157 | |
| 158 | mmu_mel_dp_nor_macro__ports_2__width_1 mrau_in_nor ( |
| 159 | .din0 (pparity_err_ ), |
| 160 | .din1 (cerer_mrau_ ), |
| 161 | .dout (parity_err_in ) |
| 162 | ); |
| 163 | |
| 164 | mmu_mel_dp_nor_macro__ports_2__width_1 parity_err_for_htc_in_nor ( |
| 165 | .din0 (pparity_err_ ), |
| 166 | .din1 (cerer_hwtwmu_ ), |
| 167 | .dout (parity_err_for_htc_in ) |
| 168 | ); |
| 169 | |
| 170 | assign mel_parity_err = |
| 171 | parity_err; |
| 172 | |
| 173 | assign mel_htc_parity_err = |
| 174 | parity_err_for_htc; |
| 175 | |
| 176 | |
| 177 | |
| 178 | supply0 vss; // <- port for ground |
| 179 | supply1 vdd; // <- port for power |
| 180 | |
| 181 | // fixscan start: |
| 182 | assign ecc_lat_scanin = scan_in ; |
| 183 | assign scan_out = ecc_lat_scanout ; |
| 184 | // fixscan end: |
| 185 | endmodule |
| 186 | |
| 187 | |
| 188 | |
| 189 | |
| 190 | |
| 191 | |
| 192 | |
| 193 | // any PARAMS parms go into naming of macro |
| 194 | |
| 195 | module mmu_mel_dp_msff_macro__width_4 ( |
| 196 | din, |
| 197 | clk, |
| 198 | en, |
| 199 | se, |
| 200 | scan_in, |
| 201 | siclk, |
| 202 | soclk, |
| 203 | pce_ov, |
| 204 | stop, |
| 205 | dout, |
| 206 | scan_out); |
| 207 | wire l1clk; |
| 208 | wire siclk_out; |
| 209 | wire soclk_out; |
| 210 | wire [2:0] so; |
| 211 | |
| 212 | input [3:0] din; |
| 213 | |
| 214 | |
| 215 | input clk; |
| 216 | input en; |
| 217 | input se; |
| 218 | input scan_in; |
| 219 | input siclk; |
| 220 | input soclk; |
| 221 | input pce_ov; |
| 222 | input stop; |
| 223 | |
| 224 | |
| 225 | |
| 226 | output [3:0] dout; |
| 227 | |
| 228 | |
| 229 | output scan_out; |
| 230 | |
| 231 | |
| 232 | |
| 233 | |
| 234 | cl_dp1_l1hdr_8x c0_0 ( |
| 235 | .l2clk(clk), |
| 236 | .pce(en), |
| 237 | .aclk(siclk), |
| 238 | .bclk(soclk), |
| 239 | .l1clk(l1clk), |
| 240 | .se(se), |
| 241 | .pce_ov(pce_ov), |
| 242 | .stop(stop), |
| 243 | .siclk_out(siclk_out), |
| 244 | .soclk_out(soclk_out) |
| 245 | ); |
| 246 | dff #(4) d0_0 ( |
| 247 | .l1clk(l1clk), |
| 248 | .siclk(siclk_out), |
| 249 | .soclk(soclk_out), |
| 250 | .d(din[3:0]), |
| 251 | .si({scan_in,so[2:0]}), |
| 252 | .so({so[2:0],scan_out}), |
| 253 | .q(dout[3:0]) |
| 254 | ); |
| 255 | |
| 256 | |
| 257 | |
| 258 | |
| 259 | |
| 260 | |
| 261 | |
| 262 | |
| 263 | |
| 264 | |
| 265 | |
| 266 | |
| 267 | |
| 268 | |
| 269 | |
| 270 | |
| 271 | |
| 272 | |
| 273 | |
| 274 | |
| 275 | endmodule |
| 276 | |
| 277 | |
| 278 | |
| 279 | |
| 280 | |
| 281 | |
| 282 | |
| 283 | |
| 284 | |
| 285 | // |
| 286 | // buff macro |
| 287 | // |
| 288 | // |
| 289 | |
| 290 | |
| 291 | |
| 292 | |
| 293 | |
| 294 | module mmu_mel_dp_buff_macro__rep_1__width_2 ( |
| 295 | din, |
| 296 | dout); |
| 297 | input [1:0] din; |
| 298 | output [1:0] dout; |
| 299 | |
| 300 | |
| 301 | |
| 302 | |
| 303 | |
| 304 | |
| 305 | buff #(2) d0_0 ( |
| 306 | .in(din[1:0]), |
| 307 | .out(dout[1:0]) |
| 308 | ); |
| 309 | |
| 310 | |
| 311 | |
| 312 | |
| 313 | |
| 314 | |
| 315 | |
| 316 | |
| 317 | endmodule |
| 318 | |
| 319 | |
| 320 | |
| 321 | |
| 322 | |
| 323 | // |
| 324 | // invert macro |
| 325 | // |
| 326 | // |
| 327 | |
| 328 | |
| 329 | |
| 330 | |
| 331 | |
| 332 | module mmu_mel_dp_inv_macro__width_1 ( |
| 333 | din, |
| 334 | dout); |
| 335 | input [0:0] din; |
| 336 | output [0:0] dout; |
| 337 | |
| 338 | |
| 339 | |
| 340 | |
| 341 | |
| 342 | |
| 343 | inv #(1) d0_0 ( |
| 344 | .in(din[0:0]), |
| 345 | .out(dout[0:0]) |
| 346 | ); |
| 347 | |
| 348 | |
| 349 | |
| 350 | |
| 351 | |
| 352 | |
| 353 | |
| 354 | |
| 355 | |
| 356 | endmodule |
| 357 | |
| 358 | |
| 359 | |
| 360 | |
| 361 | |
| 362 | // |
| 363 | // nor macro for ports = 2,3 |
| 364 | // |
| 365 | // |
| 366 | |
| 367 | |
| 368 | |
| 369 | |
| 370 | |
| 371 | module mmu_mel_dp_nor_macro__ports_2__width_1 ( |
| 372 | din0, |
| 373 | din1, |
| 374 | dout); |
| 375 | input [0:0] din0; |
| 376 | input [0:0] din1; |
| 377 | output [0:0] dout; |
| 378 | |
| 379 | |
| 380 | |
| 381 | |
| 382 | |
| 383 | |
| 384 | nor2 #(1) d0_0 ( |
| 385 | .in0(din0[0:0]), |
| 386 | .in1(din1[0:0]), |
| 387 | .out(dout[0:0]) |
| 388 | ); |
| 389 | |
| 390 | |
| 391 | |
| 392 | |
| 393 | |
| 394 | |
| 395 | |
| 396 | endmodule |
| 397 | |
| 398 | |
| 399 | |
| 400 | |