| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: cl_a1.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module cl_a1_msffmin_fp_16x ( q, so, d, l1clk, si, siclk, soclk ); |
| 36 | // RFM 05-14-2004 |
| 37 | // Level sensitive in SCAN_MODE |
| 38 | // Edge triggered when not in SCAN_MODE |
| 39 | |
| 40 | |
| 41 | parameter SIZE = 1; |
| 42 | |
| 43 | output q; |
| 44 | output so; |
| 45 | |
| 46 | input d; |
| 47 | input l1clk; |
| 48 | input si; |
| 49 | input siclk; |
| 50 | input soclk; |
| 51 | |
| 52 | reg q; |
| 53 | wire so; |
| 54 | wire l1clk, siclk, soclk; |
| 55 | |
| 56 | `ifdef SCAN_MODE |
| 57 | |
| 58 | reg l1; |
| 59 | `ifdef FAST_FLUSH |
| 60 | always @(posedge l1clk or posedge siclk ) begin |
| 61 | if (siclk) begin |
| 62 | q <= 1'b0; //pseudo flush reset |
| 63 | end else begin |
| 64 | q <= d; |
| 65 | end |
| 66 | end |
| 67 | `else |
| 68 | always @(l1clk or siclk or soclk or d or si) |
| 69 | begin |
| 70 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 71 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 72 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 73 | |
| 74 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 75 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 76 | end |
| 77 | `endif |
| 78 | `else |
| 79 | wire si_unused; |
| 80 | wire siclk_unused; |
| 81 | wire soclk_unused; |
| 82 | assign si_unused = si; |
| 83 | assign siclk_unused = siclk; |
| 84 | assign soclk_unused = soclk; |
| 85 | |
| 86 | |
| 87 | `ifdef INITLATZERO |
| 88 | initial q = 1'b0; |
| 89 | `endif |
| 90 | |
| 91 | always @(posedge l1clk) |
| 92 | begin |
| 93 | if (!siclk && !soclk) q <= d; |
| 94 | else q <= 1'bx; |
| 95 | end |
| 96 | `endif |
| 97 | |
| 98 | assign so = q; |
| 99 | |
| 100 | endmodule // dff |
| 101 | |
| 102 | |
| 103 | |
| 104 | |
| 105 | module cl_a1_msffmin_fp_8x ( q, so, d, l1clk, si, siclk, soclk ); |
| 106 | // RFM 05-14-2004 |
| 107 | // Level sensitive in SCAN_MODE |
| 108 | // Edge triggered when not in SCAN_MODE |
| 109 | |
| 110 | |
| 111 | parameter SIZE = 1; |
| 112 | |
| 113 | output q; |
| 114 | output so; |
| 115 | |
| 116 | input d; |
| 117 | input l1clk; |
| 118 | input si; |
| 119 | input siclk; |
| 120 | input soclk; |
| 121 | |
| 122 | reg q; |
| 123 | wire so; |
| 124 | wire l1clk, siclk, soclk; |
| 125 | |
| 126 | `ifdef SCAN_MODE |
| 127 | `ifdef FAST_FLUSH |
| 128 | always @(posedge l1clk or posedge siclk ) begin |
| 129 | if (siclk) begin |
| 130 | q <= 1'b0; //pseudo flush reset |
| 131 | end else begin |
| 132 | q <= d; |
| 133 | end |
| 134 | end |
| 135 | `else |
| 136 | reg l1; |
| 137 | |
| 138 | always @(l1clk or siclk or soclk or d or si) |
| 139 | begin |
| 140 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 141 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 142 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 143 | |
| 144 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 145 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 146 | end |
| 147 | `endif |
| 148 | `else |
| 149 | wire si_unused; |
| 150 | wire siclk_unused; |
| 151 | wire soclk_unused; |
| 152 | assign si_unused = si; |
| 153 | assign siclk_unused = siclk; |
| 154 | assign soclk_unused = soclk; |
| 155 | |
| 156 | |
| 157 | `ifdef INITLATZERO |
| 158 | initial q = 1'b0; |
| 159 | `endif |
| 160 | |
| 161 | always @(posedge l1clk) |
| 162 | begin |
| 163 | if (!siclk && !soclk) q <= d; |
| 164 | else q <= 1'bx; |
| 165 | end |
| 166 | `endif |
| 167 | |
| 168 | assign so = q; |
| 169 | |
| 170 | endmodule // dff |
| 171 | module cl_a1_msffmin_fp_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 172 | // RFM 05-14-2004 |
| 173 | // Level sensitive in SCAN_MODE |
| 174 | // Edge triggered when not in SCAN_MODE |
| 175 | |
| 176 | |
| 177 | parameter SIZE = 1; |
| 178 | |
| 179 | output q; |
| 180 | output so; |
| 181 | |
| 182 | input d; |
| 183 | input l1clk; |
| 184 | input si; |
| 185 | input siclk; |
| 186 | input soclk; |
| 187 | |
| 188 | reg q; |
| 189 | wire so; |
| 190 | wire l1clk, siclk, soclk; |
| 191 | |
| 192 | `ifdef SCAN_MODE |
| 193 | |
| 194 | reg l1; |
| 195 | `ifdef FAST_FLUSH |
| 196 | always @(posedge l1clk or posedge siclk ) begin |
| 197 | if (siclk) begin |
| 198 | q <= 1'b0; //pseudo flush reset |
| 199 | end else begin |
| 200 | q <= d; |
| 201 | end |
| 202 | end |
| 203 | `else |
| 204 | always @(l1clk or siclk or soclk or d or si) |
| 205 | begin |
| 206 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 207 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 208 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 209 | |
| 210 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 211 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 212 | end |
| 213 | `endif |
| 214 | `else |
| 215 | wire si_unused; |
| 216 | wire siclk_unused; |
| 217 | wire soclk_unused; |
| 218 | assign si_unused = si; |
| 219 | assign siclk_unused = siclk; |
| 220 | assign soclk_unused = soclk; |
| 221 | |
| 222 | |
| 223 | `ifdef INITLATZERO |
| 224 | initial q = 1'b0; |
| 225 | `endif |
| 226 | |
| 227 | always @(posedge l1clk) |
| 228 | begin |
| 229 | if (!siclk && !soclk) q <= d; |
| 230 | else q <= 1'bx; |
| 231 | end |
| 232 | `endif |
| 233 | |
| 234 | assign so = q; |
| 235 | |
| 236 | endmodule // dff |
| 237 | module cl_a1_msffmin_fp_32x ( q, so, d, l1clk, si, siclk, soclk ); |
| 238 | // RFM 05-14-2004 |
| 239 | // Level sensitive in SCAN_MODE |
| 240 | // Edge triggered when not in SCAN_MODE |
| 241 | |
| 242 | |
| 243 | parameter SIZE = 1; |
| 244 | |
| 245 | output q; |
| 246 | output so; |
| 247 | |
| 248 | input d; |
| 249 | input l1clk; |
| 250 | input si; |
| 251 | input siclk; |
| 252 | input soclk; |
| 253 | |
| 254 | reg q; |
| 255 | wire so; |
| 256 | wire l1clk, siclk, soclk; |
| 257 | |
| 258 | `ifdef SCAN_MODE |
| 259 | |
| 260 | reg l1; |
| 261 | `ifdef FAST_FLUSH |
| 262 | always @(posedge l1clk or posedge siclk ) begin |
| 263 | if (siclk) begin |
| 264 | q <= 1'b0; //pseudo flush reset |
| 265 | end else begin |
| 266 | q <= d; |
| 267 | end |
| 268 | end |
| 269 | `else |
| 270 | always @(l1clk or siclk or soclk or d or si) |
| 271 | begin |
| 272 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 273 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 274 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 275 | |
| 276 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 277 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 278 | end |
| 279 | `endif |
| 280 | `else |
| 281 | wire si_unused; |
| 282 | wire siclk_unused; |
| 283 | wire soclk_unused; |
| 284 | assign si_unused = si; |
| 285 | assign siclk_unused = siclk; |
| 286 | assign soclk_unused = soclk; |
| 287 | |
| 288 | |
| 289 | `ifdef INITLATZERO |
| 290 | initial q = 1'b0; |
| 291 | `endif |
| 292 | |
| 293 | always @(posedge l1clk) |
| 294 | begin |
| 295 | if (!siclk && !soclk) q <= d; |
| 296 | else q <= 1'bx; |
| 297 | end |
| 298 | `endif |
| 299 | |
| 300 | assign so = q; |
| 301 | |
| 302 | endmodule // dff |
| 303 | module cl_a1_msffmin_fp_1x ( q, so, d, l1clk, si, siclk, soclk ); |
| 304 | // RFM 05-14-2004 |
| 305 | // Level sensitive in SCAN_MODE |
| 306 | // Edge triggered when not in SCAN_MODE |
| 307 | |
| 308 | |
| 309 | parameter SIZE = 1; |
| 310 | |
| 311 | output q; |
| 312 | output so; |
| 313 | |
| 314 | input d; |
| 315 | input l1clk; |
| 316 | input si; |
| 317 | input siclk; |
| 318 | input soclk; |
| 319 | |
| 320 | reg q; |
| 321 | wire so; |
| 322 | wire l1clk, siclk, soclk; |
| 323 | |
| 324 | `ifdef SCAN_MODE |
| 325 | |
| 326 | reg l1; |
| 327 | `ifdef FAST_FLUSH |
| 328 | always @(posedge l1clk or posedge siclk ) begin |
| 329 | if (siclk) begin |
| 330 | q <= 1'b0; //pseudo flush reset |
| 331 | end else begin |
| 332 | q <= d; |
| 333 | end |
| 334 | end |
| 335 | `else |
| 336 | always @(l1clk or siclk or soclk or d or si) |
| 337 | begin |
| 338 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 339 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 340 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 341 | |
| 342 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 343 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 344 | end |
| 345 | `endif |
| 346 | `else |
| 347 | wire si_unused; |
| 348 | wire siclk_unused; |
| 349 | wire soclk_unused; |
| 350 | assign si_unused = si; |
| 351 | assign siclk_unused = siclk; |
| 352 | assign soclk_unused = soclk; |
| 353 | |
| 354 | |
| 355 | `ifdef INITLATZERO |
| 356 | initial q = 1'b0; |
| 357 | `endif |
| 358 | |
| 359 | always @(posedge l1clk) |
| 360 | begin |
| 361 | if (!siclk && !soclk) q <= d; |
| 362 | else q <= 1'bx; |
| 363 | end |
| 364 | `endif |
| 365 | |
| 366 | assign so = q; |
| 367 | |
| 368 | endmodule // dff |
| 369 | module cl_a1_msffmin_fp_30ps_16x ( q, so, d, l1clk, si, siclk, soclk ); |
| 370 | // RFM 05-14-2004 |
| 371 | // Level sensitive in SCAN_MODE |
| 372 | // Edge triggered when not in SCAN_MODE |
| 373 | |
| 374 | |
| 375 | parameter SIZE = 1; |
| 376 | |
| 377 | output q; |
| 378 | output so; |
| 379 | |
| 380 | input d; |
| 381 | input l1clk; |
| 382 | input si; |
| 383 | input siclk; |
| 384 | input soclk; |
| 385 | |
| 386 | reg q; |
| 387 | wire so; |
| 388 | wire l1clk, siclk, soclk; |
| 389 | |
| 390 | `ifdef SCAN_MODE |
| 391 | |
| 392 | reg l1; |
| 393 | `ifdef FAST_FLUSH |
| 394 | always @(posedge l1clk or posedge siclk ) begin |
| 395 | if (siclk) begin |
| 396 | q <= 1'b0; //pseudo flush reset |
| 397 | end else begin |
| 398 | q <= d; |
| 399 | end |
| 400 | end |
| 401 | `else |
| 402 | |
| 403 | always @(l1clk or siclk or soclk or d or si) |
| 404 | begin |
| 405 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 406 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 407 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 408 | |
| 409 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 410 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 411 | end |
| 412 | `endif |
| 413 | `else |
| 414 | wire si_unused; |
| 415 | wire siclk_unused; |
| 416 | wire soclk_unused; |
| 417 | assign si_unused = si; |
| 418 | assign siclk_unused = siclk; |
| 419 | assign soclk_unused = soclk; |
| 420 | |
| 421 | |
| 422 | `ifdef INITLATZERO |
| 423 | initial q = 1'b0; |
| 424 | `endif |
| 425 | |
| 426 | always @(posedge l1clk) |
| 427 | begin |
| 428 | if (!siclk && !soclk) q <= d; |
| 429 | else q <= 1'bx; |
| 430 | end |
| 431 | `endif |
| 432 | |
| 433 | assign so = q; |
| 434 | |
| 435 | endmodule // dff |
| 436 | |
| 437 | |
| 438 | |
| 439 | |
| 440 | module cl_a1_msffmin_fp_30ps_8x ( q, so, d, l1clk, si, siclk, soclk ); |
| 441 | // RFM 05-14-2004 |
| 442 | // Level sensitive in SCAN_MODE |
| 443 | // Edge triggered when not in SCAN_MODE |
| 444 | |
| 445 | |
| 446 | parameter SIZE = 1; |
| 447 | |
| 448 | output q; |
| 449 | output so; |
| 450 | |
| 451 | input d; |
| 452 | input l1clk; |
| 453 | input si; |
| 454 | input siclk; |
| 455 | input soclk; |
| 456 | |
| 457 | reg q; |
| 458 | wire so; |
| 459 | wire l1clk, siclk, soclk; |
| 460 | |
| 461 | `ifdef SCAN_MODE |
| 462 | |
| 463 | reg l1; |
| 464 | `ifdef FAST_FLUSH |
| 465 | always @(posedge l1clk or posedge siclk ) begin |
| 466 | if (siclk) begin |
| 467 | q <= 1'b0; //pseudo flush reset |
| 468 | end else begin |
| 469 | q <= d; |
| 470 | end |
| 471 | end |
| 472 | `else |
| 473 | always @(l1clk or siclk or soclk or d or si) |
| 474 | begin |
| 475 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 476 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 477 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 478 | |
| 479 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 480 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 481 | end |
| 482 | `endif |
| 483 | `else |
| 484 | wire si_unused; |
| 485 | wire siclk_unused; |
| 486 | wire soclk_unused; |
| 487 | assign si_unused = si; |
| 488 | assign siclk_unused = siclk; |
| 489 | assign soclk_unused = soclk; |
| 490 | |
| 491 | |
| 492 | `ifdef INITLATZERO |
| 493 | initial q = 1'b0; |
| 494 | `endif |
| 495 | |
| 496 | always @(posedge l1clk) |
| 497 | begin |
| 498 | if (!siclk && !soclk) q <= d; |
| 499 | else q <= 1'bx; |
| 500 | end |
| 501 | `endif |
| 502 | |
| 503 | assign so = q; |
| 504 | |
| 505 | endmodule // dff |
| 506 | module cl_a1_msffmin_fp_30ps_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 507 | // RFM 05-14-2004 |
| 508 | // Level sensitive in SCAN_MODE |
| 509 | // Edge triggered when not in SCAN_MODE |
| 510 | |
| 511 | |
| 512 | parameter SIZE = 1; |
| 513 | |
| 514 | output q; |
| 515 | output so; |
| 516 | |
| 517 | input d; |
| 518 | input l1clk; |
| 519 | input si; |
| 520 | input siclk; |
| 521 | input soclk; |
| 522 | |
| 523 | reg q; |
| 524 | wire so; |
| 525 | wire l1clk, siclk, soclk; |
| 526 | |
| 527 | `ifdef SCAN_MODE |
| 528 | |
| 529 | reg l1; |
| 530 | `ifdef FAST_FLUSH |
| 531 | always @(posedge l1clk or posedge siclk ) begin |
| 532 | if (siclk) begin |
| 533 | q <= 1'b0; //pseudo flush reset |
| 534 | end else begin |
| 535 | q <= d; |
| 536 | end |
| 537 | end |
| 538 | `else |
| 539 | always @(l1clk or siclk or soclk or d or si) |
| 540 | begin |
| 541 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 542 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 543 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 544 | |
| 545 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 546 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 547 | end |
| 548 | `endif |
| 549 | `else |
| 550 | wire si_unused; |
| 551 | wire siclk_unused; |
| 552 | wire soclk_unused; |
| 553 | assign si_unused = si; |
| 554 | assign siclk_unused = siclk; |
| 555 | assign soclk_unused = soclk; |
| 556 | |
| 557 | |
| 558 | `ifdef INITLATZERO |
| 559 | initial q = 1'b0; |
| 560 | `endif |
| 561 | |
| 562 | always @(posedge l1clk) |
| 563 | begin |
| 564 | if (!siclk && !soclk) q <= d; |
| 565 | else q <= 1'bx; |
| 566 | end |
| 567 | `endif |
| 568 | |
| 569 | assign so = q; |
| 570 | |
| 571 | endmodule // dff |
| 572 | module cl_a1_msffmin_fp_30ps_32x ( q, so, d, l1clk, si, siclk, soclk ); |
| 573 | // RFM 05-14-2004 |
| 574 | // Level sensitive in SCAN_MODE |
| 575 | // Edge triggered when not in SCAN_MODE |
| 576 | |
| 577 | |
| 578 | parameter SIZE = 1; |
| 579 | |
| 580 | output q; |
| 581 | output so; |
| 582 | |
| 583 | input d; |
| 584 | input l1clk; |
| 585 | input si; |
| 586 | input siclk; |
| 587 | input soclk; |
| 588 | |
| 589 | reg q; |
| 590 | wire so; |
| 591 | wire l1clk, siclk, soclk; |
| 592 | |
| 593 | `ifdef SCAN_MODE |
| 594 | |
| 595 | reg l1; |
| 596 | `ifdef FAST_FLUSH |
| 597 | always @(posedge l1clk or posedge siclk ) begin |
| 598 | if (siclk) begin |
| 599 | q <= 1'b0; //pseudo flush reset |
| 600 | end else begin |
| 601 | q <= d; |
| 602 | end |
| 603 | end |
| 604 | `else |
| 605 | always @(l1clk or siclk or soclk or d or si) |
| 606 | begin |
| 607 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 608 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 609 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 610 | |
| 611 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 612 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 613 | end |
| 614 | `endif |
| 615 | `else |
| 616 | wire si_unused; |
| 617 | wire siclk_unused; |
| 618 | wire soclk_unused; |
| 619 | assign si_unused = si; |
| 620 | assign siclk_unused = siclk; |
| 621 | assign soclk_unused = soclk; |
| 622 | |
| 623 | |
| 624 | `ifdef INITLATZERO |
| 625 | initial q = 1'b0; |
| 626 | `endif |
| 627 | |
| 628 | always @(posedge l1clk) |
| 629 | begin |
| 630 | if (!siclk && !soclk) q <= d; |
| 631 | else q <= 1'bx; |
| 632 | end |
| 633 | `endif |
| 634 | |
| 635 | assign so = q; |
| 636 | |
| 637 | endmodule // dff |
| 638 | module cl_a1_msffmin_fp_30ps_1x ( q, so, d, l1clk, si, siclk, soclk ); |
| 639 | // RFM 05-14-2004 |
| 640 | // Level sensitive in SCAN_MODE |
| 641 | // Edge triggered when not in SCAN_MODE |
| 642 | |
| 643 | |
| 644 | parameter SIZE = 1; |
| 645 | |
| 646 | output q; |
| 647 | output so; |
| 648 | |
| 649 | input d; |
| 650 | input l1clk; |
| 651 | input si; |
| 652 | input siclk; |
| 653 | input soclk; |
| 654 | |
| 655 | reg q; |
| 656 | wire so; |
| 657 | wire l1clk, siclk, soclk; |
| 658 | |
| 659 | `ifdef SCAN_MODE |
| 660 | |
| 661 | reg l1; |
| 662 | `ifdef FAST_FLUSH |
| 663 | always @(posedge l1clk or posedge siclk ) begin |
| 664 | if (siclk) begin |
| 665 | q <= 1'b0; //pseudo flush reset |
| 666 | end else begin |
| 667 | q <= d; |
| 668 | end |
| 669 | end |
| 670 | `else |
| 671 | always @(l1clk or siclk or soclk or d or si) |
| 672 | begin |
| 673 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 674 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 675 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 676 | |
| 677 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 678 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 679 | end |
| 680 | `endif |
| 681 | `else |
| 682 | wire si_unused; |
| 683 | wire siclk_unused; |
| 684 | wire soclk_unused; |
| 685 | assign si_unused = si; |
| 686 | assign siclk_unused = siclk; |
| 687 | assign soclk_unused = soclk; |
| 688 | |
| 689 | |
| 690 | `ifdef INITLATZERO |
| 691 | initial q = 1'b0; |
| 692 | `endif |
| 693 | |
| 694 | always @(posedge l1clk) |
| 695 | begin |
| 696 | if (!siclk && !soclk) q <= d; |
| 697 | else q <= 1'bx; |
| 698 | end |
| 699 | `endif |
| 700 | |
| 701 | assign so = q; |
| 702 | |
| 703 | endmodule // dff |
| 704 | |
| 705 | module cl_a1_msffmin_fp_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 706 | // RFM 05-14-2004 |
| 707 | // Level sensitive in SCAN_MODE |
| 708 | // Edge triggered when not in SCAN_MODE |
| 709 | |
| 710 | |
| 711 | parameter SIZE = 1; |
| 712 | |
| 713 | output q; |
| 714 | output so; |
| 715 | |
| 716 | input d; |
| 717 | input l1clk; |
| 718 | input si; |
| 719 | input siclk; |
| 720 | input soclk; |
| 721 | input reset; |
| 722 | reg q; |
| 723 | wire so; |
| 724 | wire l1clk, siclk, soclk; |
| 725 | |
| 726 | `ifdef SCAN_MODE |
| 727 | |
| 728 | reg l1; |
| 729 | `ifdef FAST_FLUSH |
| 730 | always @(l1clk or siclk or d ) // vcs optimized code |
| 731 | begin |
| 732 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 733 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 734 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 735 | l1 <= 1'b0; |
| 736 | q <= 1'b0; |
| 737 | end |
| 738 | end |
| 739 | `else |
| 740 | always @(l1clk or siclk or soclk or d or si) |
| 741 | begin |
| 742 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 743 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 744 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 745 | |
| 746 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 747 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 748 | end |
| 749 | `endif |
| 750 | `else |
| 751 | wire si_unused; |
| 752 | wire siclk_unused; |
| 753 | wire soclk_unused; |
| 754 | assign si_unused = si; |
| 755 | assign siclk_unused = siclk; |
| 756 | assign soclk_unused = soclk; |
| 757 | |
| 758 | |
| 759 | `ifdef INITLATZERO |
| 760 | initial q = 1'b0; |
| 761 | `endif |
| 762 | |
| 763 | always @(posedge l1clk) |
| 764 | begin |
| 765 | if (!siclk && !soclk) q <= (d&reset); |
| 766 | else q <= 1'bx; |
| 767 | end |
| 768 | `endif |
| 769 | |
| 770 | assign so = q; |
| 771 | |
| 772 | endmodule // dff |
| 773 | module cl_a1_msffmin_fp_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 774 | // RFM 05-14-2004 |
| 775 | // Level sensitive in SCAN_MODE |
| 776 | // Edge triggered when not in SCAN_MODE |
| 777 | |
| 778 | |
| 779 | parameter SIZE = 1; |
| 780 | |
| 781 | output q; |
| 782 | output so; |
| 783 | |
| 784 | input d; |
| 785 | input l1clk; |
| 786 | input si; |
| 787 | input siclk; |
| 788 | input soclk; |
| 789 | input reset; |
| 790 | reg q; |
| 791 | wire so; |
| 792 | wire l1clk, siclk, soclk; |
| 793 | |
| 794 | `ifdef SCAN_MODE |
| 795 | |
| 796 | reg l1; |
| 797 | `ifdef FAST_FLUSH |
| 798 | always @(l1clk or siclk or d ) // vcs optimized code |
| 799 | begin |
| 800 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 801 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 802 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 803 | l1 <= 1'b0; |
| 804 | q <= 1'b0; |
| 805 | end |
| 806 | end |
| 807 | `else |
| 808 | always @(l1clk or siclk or soclk or d or si) |
| 809 | begin |
| 810 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 811 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 812 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 813 | |
| 814 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 815 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 816 | end |
| 817 | `endif |
| 818 | `else |
| 819 | wire si_unused; |
| 820 | wire siclk_unused; |
| 821 | wire soclk_unused; |
| 822 | assign si_unused = si; |
| 823 | assign siclk_unused = siclk; |
| 824 | assign soclk_unused = soclk; |
| 825 | |
| 826 | |
| 827 | `ifdef INITLATZERO |
| 828 | initial q = 1'b0; |
| 829 | `endif |
| 830 | |
| 831 | always @(posedge l1clk) |
| 832 | begin |
| 833 | if (!siclk && !soclk) q <= (d&reset); |
| 834 | else q <= 1'bx; |
| 835 | end |
| 836 | `endif |
| 837 | |
| 838 | assign so = q; |
| 839 | |
| 840 | endmodule // dff |
| 841 | module cl_a1_msffmin_fp_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 842 | // RFM 05-14-2004 |
| 843 | // Level sensitive in SCAN_MODE |
| 844 | // Edge triggered when not in SCAN_MODE |
| 845 | |
| 846 | |
| 847 | parameter SIZE = 1; |
| 848 | |
| 849 | output q; |
| 850 | output so; |
| 851 | |
| 852 | input d; |
| 853 | input l1clk; |
| 854 | input si; |
| 855 | input siclk; |
| 856 | input soclk; |
| 857 | input reset; |
| 858 | reg q; |
| 859 | wire so; |
| 860 | wire l1clk, siclk, soclk; |
| 861 | |
| 862 | `ifdef SCAN_MODE |
| 863 | |
| 864 | reg l1; |
| 865 | `ifdef FAST_FLUSH |
| 866 | always @(l1clk or siclk or d ) // vcs optimized code |
| 867 | begin |
| 868 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 869 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 870 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 871 | l1 <= 1'b0; |
| 872 | q <= 1'b0; |
| 873 | end |
| 874 | end |
| 875 | `else |
| 876 | always @(l1clk or siclk or soclk or d or si) |
| 877 | begin |
| 878 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 879 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 880 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 881 | |
| 882 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 883 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 884 | end |
| 885 | `endif |
| 886 | `else |
| 887 | wire si_unused; |
| 888 | wire siclk_unused; |
| 889 | wire soclk_unused; |
| 890 | assign si_unused = si; |
| 891 | assign siclk_unused = siclk; |
| 892 | assign soclk_unused = soclk; |
| 893 | |
| 894 | |
| 895 | `ifdef INITLATZERO |
| 896 | initial q = 1'b0; |
| 897 | `endif |
| 898 | |
| 899 | always @(posedge l1clk) |
| 900 | begin |
| 901 | if (!siclk && !soclk) q <= (d&reset); |
| 902 | else q <= 1'bx; |
| 903 | end |
| 904 | `endif |
| 905 | |
| 906 | assign so = q; |
| 907 | |
| 908 | endmodule // dff |
| 909 | module cl_a1_msffmin_fp_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 910 | // RFM 05-14-2004 |
| 911 | // Level sensitive in SCAN_MODE |
| 912 | // Edge triggered when not in SCAN_MODE |
| 913 | |
| 914 | |
| 915 | parameter SIZE = 1; |
| 916 | |
| 917 | output q; |
| 918 | output so; |
| 919 | |
| 920 | input d; |
| 921 | input l1clk; |
| 922 | input si; |
| 923 | input siclk; |
| 924 | input soclk; |
| 925 | input reset; |
| 926 | reg q; |
| 927 | wire so; |
| 928 | wire l1clk, siclk, soclk; |
| 929 | |
| 930 | `ifdef SCAN_MODE |
| 931 | |
| 932 | reg l1; |
| 933 | `ifdef FAST_FLUSH |
| 934 | always @(l1clk or siclk or d ) // vcs optimized code |
| 935 | begin |
| 936 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 937 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 938 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 939 | l1 <= 1'b0; |
| 940 | q <= 1'b0; |
| 941 | end |
| 942 | end |
| 943 | `else |
| 944 | always @(l1clk or siclk or soclk or d or si) |
| 945 | begin |
| 946 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 947 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 948 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 949 | |
| 950 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 951 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 952 | end |
| 953 | `endif |
| 954 | `else |
| 955 | wire si_unused; |
| 956 | wire siclk_unused; |
| 957 | wire soclk_unused; |
| 958 | assign si_unused = si; |
| 959 | assign siclk_unused = siclk; |
| 960 | assign soclk_unused = soclk; |
| 961 | |
| 962 | |
| 963 | `ifdef INITLATZERO |
| 964 | initial q = 1'b0; |
| 965 | `endif |
| 966 | |
| 967 | always @(posedge l1clk) |
| 968 | begin |
| 969 | if (!siclk && !soclk) q <= (d&reset); |
| 970 | else q <= 1'bx; |
| 971 | end |
| 972 | `endif |
| 973 | |
| 974 | assign so = q; |
| 975 | |
| 976 | endmodule // dff |
| 977 | module cl_a1_msffmin_fp_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 978 | // RFM 05-14-2004 |
| 979 | // Level sensitive in SCAN_MODE |
| 980 | // Edge triggered when not in SCAN_MODE |
| 981 | |
| 982 | |
| 983 | parameter SIZE = 1; |
| 984 | |
| 985 | output q; |
| 986 | output so; |
| 987 | |
| 988 | input d; |
| 989 | input l1clk; |
| 990 | input si; |
| 991 | input siclk; |
| 992 | input soclk; |
| 993 | input reset; |
| 994 | reg q; |
| 995 | wire so; |
| 996 | wire l1clk, siclk, soclk; |
| 997 | |
| 998 | `ifdef SCAN_MODE |
| 999 | |
| 1000 | reg l1; |
| 1001 | `ifdef FAST_FLUSH |
| 1002 | always @(l1clk or siclk or d ) // vcs optimized code |
| 1003 | begin |
| 1004 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1005 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 1006 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 1007 | l1 <= 1'b0; |
| 1008 | q <= 1'b0; |
| 1009 | end |
| 1010 | end |
| 1011 | `else |
| 1012 | always @(l1clk or siclk or soclk or d or si) |
| 1013 | begin |
| 1014 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1015 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1016 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1017 | |
| 1018 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1019 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1020 | end |
| 1021 | `endif |
| 1022 | `else |
| 1023 | wire si_unused; |
| 1024 | wire siclk_unused; |
| 1025 | wire soclk_unused; |
| 1026 | assign si_unused = si; |
| 1027 | assign siclk_unused = siclk; |
| 1028 | assign soclk_unused = soclk; |
| 1029 | |
| 1030 | |
| 1031 | `ifdef INITLATZERO |
| 1032 | initial q = 1'b0; |
| 1033 | `endif |
| 1034 | |
| 1035 | always @(posedge l1clk) |
| 1036 | begin |
| 1037 | if (!siclk && !soclk) q <= (d&reset); |
| 1038 | else q <= 1'bx; |
| 1039 | end |
| 1040 | `endif |
| 1041 | |
| 1042 | assign so = q; |
| 1043 | |
| 1044 | endmodule // dff |
| 1045 | module cl_a1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk ); |
| 1046 | // RFM 05-14-2004 |
| 1047 | // Level sensitive in SCAN_MODE |
| 1048 | // Edge triggered when not in SCAN_MODE |
| 1049 | |
| 1050 | |
| 1051 | parameter SIZE = 1; |
| 1052 | |
| 1053 | output q; |
| 1054 | output so; |
| 1055 | |
| 1056 | input d; |
| 1057 | input l1clk; |
| 1058 | input si; |
| 1059 | input siclk; |
| 1060 | input soclk; |
| 1061 | |
| 1062 | reg q; |
| 1063 | wire so; |
| 1064 | wire l1clk, siclk, soclk; |
| 1065 | |
| 1066 | `ifdef SCAN_MODE |
| 1067 | |
| 1068 | reg l1; |
| 1069 | `ifdef FAST_FLUSH |
| 1070 | always @(posedge l1clk or posedge siclk ) begin |
| 1071 | if (siclk) begin |
| 1072 | q <= 1'b0; //pseudo flush reset |
| 1073 | end else begin |
| 1074 | q <= d; |
| 1075 | end |
| 1076 | end |
| 1077 | `else |
| 1078 | |
| 1079 | always @(l1clk or siclk or soclk or d or si) |
| 1080 | begin |
| 1081 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 1082 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1083 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1084 | |
| 1085 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1086 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1087 | end |
| 1088 | `endif |
| 1089 | `else |
| 1090 | wire si_unused; |
| 1091 | wire siclk_unused; |
| 1092 | wire soclk_unused; |
| 1093 | assign si_unused = si; |
| 1094 | assign siclk_unused = siclk; |
| 1095 | assign soclk_unused = soclk; |
| 1096 | |
| 1097 | |
| 1098 | `ifdef INITLATZERO |
| 1099 | initial q = 1'b0; |
| 1100 | `endif |
| 1101 | |
| 1102 | always @(posedge l1clk) |
| 1103 | begin |
| 1104 | if (!siclk && !soclk) q <= d; |
| 1105 | else q <= 1'bx; |
| 1106 | end |
| 1107 | `endif |
| 1108 | |
| 1109 | assign so = q; |
| 1110 | |
| 1111 | endmodule // dff |
| 1112 | |
| 1113 | |
| 1114 | |
| 1115 | |
| 1116 | module cl_a1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk ); |
| 1117 | // RFM 05-14-2004 |
| 1118 | // Level sensitive in SCAN_MODE |
| 1119 | // Edge triggered when not in SCAN_MODE |
| 1120 | |
| 1121 | |
| 1122 | parameter SIZE = 1; |
| 1123 | |
| 1124 | output q; |
| 1125 | output so; |
| 1126 | |
| 1127 | input d; |
| 1128 | input l1clk; |
| 1129 | input si; |
| 1130 | input siclk; |
| 1131 | input soclk; |
| 1132 | |
| 1133 | reg q; |
| 1134 | wire so; |
| 1135 | wire l1clk, siclk, soclk; |
| 1136 | |
| 1137 | `ifdef SCAN_MODE |
| 1138 | |
| 1139 | reg l1; |
| 1140 | `ifdef FAST_FLUSH |
| 1141 | always @(posedge l1clk or posedge siclk ) begin |
| 1142 | if (siclk) begin |
| 1143 | q <= 1'b0; //pseudo flush reset |
| 1144 | end else begin |
| 1145 | q <= d; |
| 1146 | end |
| 1147 | end |
| 1148 | `else |
| 1149 | always @(l1clk or siclk or soclk or d or si) |
| 1150 | begin |
| 1151 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 1152 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1153 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1154 | |
| 1155 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1156 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1157 | end |
| 1158 | `endif |
| 1159 | `else |
| 1160 | wire si_unused; |
| 1161 | wire siclk_unused; |
| 1162 | wire soclk_unused; |
| 1163 | assign si_unused = si; |
| 1164 | assign siclk_unused = siclk; |
| 1165 | assign soclk_unused = soclk; |
| 1166 | |
| 1167 | |
| 1168 | `ifdef INITLATZERO |
| 1169 | initial q = 1'b0; |
| 1170 | `endif |
| 1171 | |
| 1172 | always @(posedge l1clk) |
| 1173 | begin |
| 1174 | if (!siclk && !soclk) q <= d; |
| 1175 | else q <= 1'bx; |
| 1176 | end |
| 1177 | `endif |
| 1178 | |
| 1179 | assign so = q; |
| 1180 | |
| 1181 | endmodule // dff |
| 1182 | module cl_a1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 1183 | // RFM 05-14-2004 |
| 1184 | // Level sensitive in SCAN_MODE |
| 1185 | // Edge triggered when not in SCAN_MODE |
| 1186 | |
| 1187 | |
| 1188 | parameter SIZE = 1; |
| 1189 | |
| 1190 | output q; |
| 1191 | output so; |
| 1192 | |
| 1193 | input d; |
| 1194 | input l1clk; |
| 1195 | input si; |
| 1196 | input siclk; |
| 1197 | input soclk; |
| 1198 | |
| 1199 | reg q; |
| 1200 | wire so; |
| 1201 | wire l1clk, siclk, soclk; |
| 1202 | |
| 1203 | `ifdef SCAN_MODE |
| 1204 | |
| 1205 | reg l1; |
| 1206 | `ifdef FAST_FLUSH |
| 1207 | always @(posedge l1clk or posedge siclk ) begin |
| 1208 | if (siclk) begin |
| 1209 | q <= 1'b0; //pseudo flush reset |
| 1210 | end else begin |
| 1211 | q <= d; |
| 1212 | end |
| 1213 | end |
| 1214 | `else |
| 1215 | always @(l1clk or siclk or soclk or d or si) |
| 1216 | begin |
| 1217 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 1218 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1219 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1220 | |
| 1221 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1222 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1223 | end |
| 1224 | `endif |
| 1225 | `else |
| 1226 | wire si_unused; |
| 1227 | wire siclk_unused; |
| 1228 | wire soclk_unused; |
| 1229 | assign si_unused = si; |
| 1230 | assign siclk_unused = siclk; |
| 1231 | assign soclk_unused = soclk; |
| 1232 | |
| 1233 | |
| 1234 | `ifdef INITLATZERO |
| 1235 | initial q = 1'b0; |
| 1236 | `endif |
| 1237 | |
| 1238 | always @(posedge l1clk) |
| 1239 | begin |
| 1240 | if (!siclk && !soclk) q <= d; |
| 1241 | else q <= 1'bx; |
| 1242 | end |
| 1243 | `endif |
| 1244 | |
| 1245 | assign so = q; |
| 1246 | |
| 1247 | endmodule // dff |
| 1248 | module cl_a1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk ); |
| 1249 | // RFM 05-14-2004 |
| 1250 | // Level sensitive in SCAN_MODE |
| 1251 | // Edge triggered when not in SCAN_MODE |
| 1252 | |
| 1253 | |
| 1254 | parameter SIZE = 1; |
| 1255 | |
| 1256 | output q; |
| 1257 | output so; |
| 1258 | |
| 1259 | input d; |
| 1260 | input l1clk; |
| 1261 | input si; |
| 1262 | input siclk; |
| 1263 | input soclk; |
| 1264 | |
| 1265 | reg q; |
| 1266 | wire so; |
| 1267 | wire l1clk, siclk, soclk; |
| 1268 | |
| 1269 | `ifdef SCAN_MODE |
| 1270 | |
| 1271 | reg l1; |
| 1272 | `ifdef FAST_FLUSH |
| 1273 | always @(posedge l1clk or posedge siclk ) begin |
| 1274 | if (siclk) begin |
| 1275 | q <= 1'b0; //pseudo flush reset |
| 1276 | end else begin |
| 1277 | q <= d; |
| 1278 | end |
| 1279 | end |
| 1280 | `else |
| 1281 | always @(l1clk or siclk or soclk or d or si) |
| 1282 | begin |
| 1283 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 1284 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1285 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1286 | |
| 1287 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1288 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1289 | end |
| 1290 | `endif |
| 1291 | `else |
| 1292 | wire si_unused; |
| 1293 | wire siclk_unused; |
| 1294 | wire soclk_unused; |
| 1295 | assign si_unused = si; |
| 1296 | assign siclk_unused = siclk; |
| 1297 | assign soclk_unused = soclk; |
| 1298 | |
| 1299 | |
| 1300 | `ifdef INITLATZERO |
| 1301 | initial q = 1'b0; |
| 1302 | `endif |
| 1303 | |
| 1304 | always @(posedge l1clk) |
| 1305 | begin |
| 1306 | if (!siclk && !soclk) q <= d; |
| 1307 | else q <= 1'bx; |
| 1308 | end |
| 1309 | `endif |
| 1310 | |
| 1311 | assign so = q; |
| 1312 | |
| 1313 | endmodule // dff |
| 1314 | module cl_a1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk ); |
| 1315 | // RFM 05-14-2004 |
| 1316 | // Level sensitive in SCAN_MODE |
| 1317 | // Edge triggered when not in SCAN_MODE |
| 1318 | |
| 1319 | |
| 1320 | parameter SIZE = 1; |
| 1321 | |
| 1322 | output q; |
| 1323 | output so; |
| 1324 | |
| 1325 | input d; |
| 1326 | input l1clk; |
| 1327 | input si; |
| 1328 | input siclk; |
| 1329 | input soclk; |
| 1330 | |
| 1331 | reg q; |
| 1332 | wire so; |
| 1333 | wire l1clk, siclk, soclk; |
| 1334 | |
| 1335 | `ifdef SCAN_MODE |
| 1336 | |
| 1337 | reg l1; |
| 1338 | `ifdef FAST_FLUSH |
| 1339 | always @(posedge l1clk or posedge siclk ) begin |
| 1340 | if (siclk) begin |
| 1341 | q <= 1'b0; //pseudo flush reset |
| 1342 | end else begin |
| 1343 | q <= d; |
| 1344 | end |
| 1345 | end |
| 1346 | `else |
| 1347 | always @(l1clk or siclk or soclk or d or si) |
| 1348 | begin |
| 1349 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 1350 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1351 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1352 | |
| 1353 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1354 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1355 | end |
| 1356 | `endif |
| 1357 | `else |
| 1358 | wire si_unused; |
| 1359 | wire siclk_unused; |
| 1360 | wire soclk_unused; |
| 1361 | assign si_unused = si; |
| 1362 | assign siclk_unused = siclk; |
| 1363 | assign soclk_unused = soclk; |
| 1364 | |
| 1365 | |
| 1366 | `ifdef INITLATZERO |
| 1367 | initial q = 1'b0; |
| 1368 | `endif |
| 1369 | |
| 1370 | always @(posedge l1clk) |
| 1371 | begin |
| 1372 | if (!siclk && !soclk) q <= d; |
| 1373 | else q <= 1'bx; |
| 1374 | end |
| 1375 | `endif |
| 1376 | |
| 1377 | assign so = q; |
| 1378 | |
| 1379 | endmodule // dff |
| 1380 | module cl_a1_clken_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk, clken); |
| 1381 | // Level sensitive in SCAN_MODE |
| 1382 | // Edge triggered when not in SCAN_MODE |
| 1383 | // created by xl on 3/18 |
| 1384 | |
| 1385 | |
| 1386 | |
| 1387 | output q; |
| 1388 | output so; |
| 1389 | |
| 1390 | input d; |
| 1391 | input l1clk; |
| 1392 | input si; |
| 1393 | input siclk; |
| 1394 | input soclk; |
| 1395 | input clken; |
| 1396 | reg q; |
| 1397 | wire so; |
| 1398 | wire l1clk, siclk, soclk; |
| 1399 | |
| 1400 | `ifdef SCAN_MODE |
| 1401 | |
| 1402 | reg l1; |
| 1403 | |
| 1404 | always @(l1clk or siclk or soclk or d or si) |
| 1405 | begin |
| 1406 | if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data |
| 1407 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1408 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1409 | |
| 1410 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1411 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1412 | end |
| 1413 | |
| 1414 | |
| 1415 | `else |
| 1416 | wire si_unused; |
| 1417 | wire siclk_unused; |
| 1418 | wire soclk_unused; |
| 1419 | assign si_unused = si; |
| 1420 | assign siclk_unused = siclk; |
| 1421 | assign soclk_unused = soclk; |
| 1422 | |
| 1423 | |
| 1424 | `ifdef INITLATZERO |
| 1425 | |
| 1426 | initial q = 1'b0; |
| 1427 | `endif |
| 1428 | |
| 1429 | always @(posedge l1clk) |
| 1430 | begin |
| 1431 | if (!siclk && !soclk) q <= (d & clken ) | (q & !clken); |
| 1432 | else q <= 1'bx; |
| 1433 | end |
| 1434 | `endif |
| 1435 | |
| 1436 | assign so = q; |
| 1437 | |
| 1438 | endmodule |
| 1439 | module cl_a1_msffmin_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 1440 | // RFM 05-14-2004 |
| 1441 | // Level sensitive in SCAN_MODE |
| 1442 | // Edge triggered when not in SCAN_MODE |
| 1443 | |
| 1444 | |
| 1445 | parameter SIZE = 1; |
| 1446 | |
| 1447 | output q; |
| 1448 | output so; |
| 1449 | |
| 1450 | input d; |
| 1451 | input l1clk; |
| 1452 | input si; |
| 1453 | input siclk; |
| 1454 | input soclk; |
| 1455 | input reset; |
| 1456 | reg q; |
| 1457 | wire so; |
| 1458 | wire l1clk, siclk, soclk; |
| 1459 | |
| 1460 | `ifdef SCAN_MODE |
| 1461 | |
| 1462 | reg l1; |
| 1463 | `ifdef FAST_FLUSH |
| 1464 | always @(l1clk or siclk or d ) // vcs optimized code |
| 1465 | begin |
| 1466 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1467 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 1468 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 1469 | l1 <= 1'b0; |
| 1470 | q <= 1'b0; |
| 1471 | end |
| 1472 | end |
| 1473 | `else |
| 1474 | always @(l1clk or siclk or soclk or d or si) |
| 1475 | begin |
| 1476 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1477 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1478 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1479 | |
| 1480 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1481 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1482 | end |
| 1483 | `endif |
| 1484 | `else |
| 1485 | wire si_unused; |
| 1486 | wire siclk_unused; |
| 1487 | wire soclk_unused; |
| 1488 | assign si_unused = si; |
| 1489 | assign siclk_unused = siclk; |
| 1490 | assign soclk_unused = soclk; |
| 1491 | |
| 1492 | |
| 1493 | `ifdef INITLATZERO |
| 1494 | initial q = 1'b0; |
| 1495 | `endif |
| 1496 | |
| 1497 | always @(posedge l1clk) |
| 1498 | begin |
| 1499 | if (!siclk && !soclk) q <= (d&reset); |
| 1500 | else q <= 1'bx; |
| 1501 | end |
| 1502 | `endif |
| 1503 | |
| 1504 | assign so = q; |
| 1505 | |
| 1506 | endmodule // dff |
| 1507 | module cl_a1_msffmin_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 1508 | // RFM 05-14-2004 |
| 1509 | // Level sensitive in SCAN_MODE |
| 1510 | // Edge triggered when not in SCAN_MODE |
| 1511 | |
| 1512 | |
| 1513 | parameter SIZE = 1; |
| 1514 | |
| 1515 | output q; |
| 1516 | output so; |
| 1517 | |
| 1518 | input d; |
| 1519 | input l1clk; |
| 1520 | input si; |
| 1521 | input siclk; |
| 1522 | input soclk; |
| 1523 | input reset; |
| 1524 | reg q; |
| 1525 | wire so; |
| 1526 | wire l1clk, siclk, soclk; |
| 1527 | |
| 1528 | `ifdef SCAN_MODE |
| 1529 | |
| 1530 | reg l1; |
| 1531 | `ifdef FAST_FLUSH |
| 1532 | always @(l1clk or siclk or d ) // vcs optimized code |
| 1533 | begin |
| 1534 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1535 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 1536 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 1537 | l1 <= 1'b0; |
| 1538 | q <= 1'b0; |
| 1539 | end |
| 1540 | end |
| 1541 | `else |
| 1542 | always @(l1clk or siclk or soclk or d or si) |
| 1543 | begin |
| 1544 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1545 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1546 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1547 | |
| 1548 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1549 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1550 | end |
| 1551 | `endif |
| 1552 | `else |
| 1553 | wire si_unused; |
| 1554 | wire siclk_unused; |
| 1555 | wire soclk_unused; |
| 1556 | assign si_unused = si; |
| 1557 | assign siclk_unused = siclk; |
| 1558 | assign soclk_unused = soclk; |
| 1559 | |
| 1560 | |
| 1561 | `ifdef INITLATZERO |
| 1562 | initial q = 1'b0; |
| 1563 | `endif |
| 1564 | |
| 1565 | always @(posedge l1clk) |
| 1566 | begin |
| 1567 | if (!siclk && !soclk) q <= (d&reset); |
| 1568 | else q <= 1'bx; |
| 1569 | end |
| 1570 | `endif |
| 1571 | |
| 1572 | assign so = q; |
| 1573 | |
| 1574 | endmodule // dff |
| 1575 | module cl_a1_msffmin_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 1576 | // RFM 05-14-2004 |
| 1577 | // Level sensitive in SCAN_MODE |
| 1578 | // Edge triggered when not in SCAN_MODE |
| 1579 | |
| 1580 | |
| 1581 | parameter SIZE = 1; |
| 1582 | |
| 1583 | output q; |
| 1584 | output so; |
| 1585 | |
| 1586 | input d; |
| 1587 | input l1clk; |
| 1588 | input si; |
| 1589 | input siclk; |
| 1590 | input soclk; |
| 1591 | input reset; |
| 1592 | reg q; |
| 1593 | wire so; |
| 1594 | wire l1clk, siclk, soclk; |
| 1595 | |
| 1596 | `ifdef SCAN_MODE |
| 1597 | |
| 1598 | reg l1; |
| 1599 | `ifdef FAST_FLUSH |
| 1600 | always @(l1clk or siclk or d ) // vcs optimized code |
| 1601 | begin |
| 1602 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1603 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 1604 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 1605 | l1 <= 1'b0; |
| 1606 | q <= 1'b0; |
| 1607 | end |
| 1608 | end |
| 1609 | `else |
| 1610 | always @(l1clk or siclk or soclk or d or si) |
| 1611 | begin |
| 1612 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1613 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1614 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1615 | |
| 1616 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1617 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1618 | end |
| 1619 | `endif |
| 1620 | `else |
| 1621 | wire si_unused; |
| 1622 | wire siclk_unused; |
| 1623 | wire soclk_unused; |
| 1624 | assign si_unused = si; |
| 1625 | assign siclk_unused = siclk; |
| 1626 | assign soclk_unused = soclk; |
| 1627 | |
| 1628 | |
| 1629 | `ifdef INITLATZERO |
| 1630 | initial q = 1'b0; |
| 1631 | `endif |
| 1632 | |
| 1633 | always @(posedge l1clk) |
| 1634 | begin |
| 1635 | if (!siclk && !soclk) q <= (d&reset); |
| 1636 | else q <= 1'bx; |
| 1637 | end |
| 1638 | `endif |
| 1639 | |
| 1640 | assign so = q; |
| 1641 | |
| 1642 | endmodule // dff |
| 1643 | module cl_a1_msffmin_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 1644 | // RFM 05-14-2004 |
| 1645 | // Level sensitive in SCAN_MODE |
| 1646 | // Edge triggered when not in SCAN_MODE |
| 1647 | |
| 1648 | |
| 1649 | parameter SIZE = 1; |
| 1650 | |
| 1651 | output q; |
| 1652 | output so; |
| 1653 | |
| 1654 | input d; |
| 1655 | input l1clk; |
| 1656 | input si; |
| 1657 | input siclk; |
| 1658 | input soclk; |
| 1659 | input reset; |
| 1660 | reg q; |
| 1661 | wire so; |
| 1662 | wire l1clk, siclk, soclk; |
| 1663 | |
| 1664 | `ifdef SCAN_MODE |
| 1665 | |
| 1666 | reg l1; |
| 1667 | `ifdef FAST_FLUSH |
| 1668 | always @(l1clk or siclk or d ) // vcs optimized code |
| 1669 | begin |
| 1670 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1671 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 1672 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 1673 | l1 <= 1'b0; |
| 1674 | q <= 1'b0; |
| 1675 | end |
| 1676 | end |
| 1677 | `else |
| 1678 | always @(l1clk or siclk or soclk or d or si) |
| 1679 | begin |
| 1680 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1681 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1682 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1683 | |
| 1684 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1685 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1686 | end |
| 1687 | `endif |
| 1688 | `else |
| 1689 | wire si_unused; |
| 1690 | wire siclk_unused; |
| 1691 | wire soclk_unused; |
| 1692 | assign si_unused = si; |
| 1693 | assign siclk_unused = siclk; |
| 1694 | assign soclk_unused = soclk; |
| 1695 | |
| 1696 | |
| 1697 | `ifdef INITLATZERO |
| 1698 | initial q = 1'b0; |
| 1699 | `endif |
| 1700 | |
| 1701 | always @(posedge l1clk) |
| 1702 | begin |
| 1703 | if (!siclk && !soclk) q <= (d&reset); |
| 1704 | else q <= 1'bx; |
| 1705 | end |
| 1706 | `endif |
| 1707 | |
| 1708 | assign so = q; |
| 1709 | |
| 1710 | endmodule // dff |
| 1711 | module cl_a1_msffmin_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 1712 | // RFM 05-14-2004 |
| 1713 | // Level sensitive in SCAN_MODE |
| 1714 | // Edge triggered when not in SCAN_MODE |
| 1715 | |
| 1716 | |
| 1717 | parameter SIZE = 1; |
| 1718 | |
| 1719 | output q; |
| 1720 | output so; |
| 1721 | |
| 1722 | input d; |
| 1723 | input l1clk; |
| 1724 | input si; |
| 1725 | input siclk; |
| 1726 | input soclk; |
| 1727 | input reset; |
| 1728 | reg q; |
| 1729 | wire so; |
| 1730 | wire l1clk, siclk, soclk; |
| 1731 | |
| 1732 | `ifdef SCAN_MODE |
| 1733 | |
| 1734 | reg l1; |
| 1735 | `ifdef FAST_FLUSH |
| 1736 | always @(l1clk or siclk or d ) // vcs optimized code |
| 1737 | begin |
| 1738 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1739 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 1740 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 1741 | l1 <= 1'b0; |
| 1742 | q <= 1'b0; |
| 1743 | end |
| 1744 | end |
| 1745 | `else |
| 1746 | always @(l1clk or siclk or soclk or d or si) |
| 1747 | begin |
| 1748 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 1749 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1750 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1751 | |
| 1752 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1753 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1754 | end |
| 1755 | `endif |
| 1756 | `else |
| 1757 | wire si_unused; |
| 1758 | wire siclk_unused; |
| 1759 | wire soclk_unused; |
| 1760 | assign si_unused = si; |
| 1761 | assign siclk_unused = siclk; |
| 1762 | assign soclk_unused = soclk; |
| 1763 | |
| 1764 | |
| 1765 | `ifdef INITLATZERO |
| 1766 | initial q = 1'b0; |
| 1767 | `endif |
| 1768 | |
| 1769 | always @(posedge l1clk) |
| 1770 | begin |
| 1771 | if (!siclk && !soclk) q <= (d&reset); |
| 1772 | else q <= 1'bx; |
| 1773 | end |
| 1774 | `endif |
| 1775 | |
| 1776 | assign so = q; |
| 1777 | |
| 1778 | endmodule // dff |
| 1779 | module cl_a1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, |
| 1780 | ac_mode, ac_test_signal); |
| 1781 | output q; |
| 1782 | output so; |
| 1783 | |
| 1784 | input d, ac_test_signal; |
| 1785 | input l1clk; |
| 1786 | input si; |
| 1787 | input siclk; |
| 1788 | input soclk; |
| 1789 | input updateclk, ac_mode; |
| 1790 | |
| 1791 | reg q; |
| 1792 | reg so; |
| 1793 | wire l1clk, siclk, soclk, updateclk; |
| 1794 | |
| 1795 | |
| 1796 | reg l1, qm; |
| 1797 | |
| 1798 | always @(l1clk or siclk or soclk or d or si) |
| 1799 | begin |
| 1800 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 1801 | if ( l1clk && siclk) l1 <= si; // Load master with |
| 1802 | // scan or flush |
| 1803 | if (!l1clk && siclk) l1 <= 1'bx; // Conflict between |
| 1804 | // data and scan |
| 1805 | if ( l1clk && !soclk) so <= l1; // Load slave with |
| 1806 | // master data |
| 1807 | if ( l1clk && siclk && !soclk) so <= si; // Flush |
| 1808 | end |
| 1809 | |
| 1810 | initial qm = 1'b0; |
| 1811 | |
| 1812 | always@(updateclk or l1) |
| 1813 | begin |
| 1814 | if(updateclk) qm <=l1; |
| 1815 | end |
| 1816 | always@(ac_mode or qm or ac_test_signal) |
| 1817 | begin |
| 1818 | if(ac_mode==0) q=qm; |
| 1819 | else q=qm ^ ac_test_signal; |
| 1820 | end |
| 1821 | endmodule |
| 1822 | module cl_a1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk); |
| 1823 | |
| 1824 | output latout; |
| 1825 | output so; |
| 1826 | input d; |
| 1827 | input l1clk; |
| 1828 | input si; |
| 1829 | input siclk; |
| 1830 | input soclk; |
| 1831 | |
| 1832 | |
| 1833 | wire so; |
| 1834 | reg s, m; |
| 1835 | |
| 1836 | `ifdef SCAN_MODE |
| 1837 | `ifdef FAST_FLUSH |
| 1838 | always @(posedge l1clk or posedge siclk ) begin |
| 1839 | if (siclk) begin |
| 1840 | m <= 1'b0; //pseudo flush reset |
| 1841 | s <= 1'b0; //pseudo flush reset |
| 1842 | end else begin |
| 1843 | m <= d; |
| 1844 | s <= d; |
| 1845 | end |
| 1846 | end |
| 1847 | |
| 1848 | `else |
| 1849 | always @(l1clk or siclk or soclk or d or si) begin |
| 1850 | |
| 1851 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1852 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 1853 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 1854 | |
| 1855 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1856 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 1857 | end |
| 1858 | `endif // FAST_FLUSH |
| 1859 | `else |
| 1860 | wire si_unused = si; |
| 1861 | `ifdef INITLATZERO |
| 1862 | |
| 1863 | |
| 1864 | initial m = 1'b0; |
| 1865 | `endif |
| 1866 | |
| 1867 | |
| 1868 | always @(l1clk or d or si or siclk) begin |
| 1869 | if(siclk==0 && l1clk==0) m = d; |
| 1870 | else if(siclk && !l1clk) m = 1'bx; |
| 1871 | if(siclk && l1clk) m = si; |
| 1872 | if(l1clk && !soclk) s = m; |
| 1873 | end |
| 1874 | |
| 1875 | `endif |
| 1876 | |
| 1877 | assign latout = m; |
| 1878 | assign so = s; |
| 1879 | |
| 1880 | |
| 1881 | endmodule |
| 1882 | |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | module cl_a1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se ); |
| 1888 | |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | output q; |
| 1894 | output so; |
| 1895 | |
| 1896 | input d; |
| 1897 | input l1clk; |
| 1898 | input si; |
| 1899 | input siclk; |
| 1900 | input soclk; |
| 1901 | input se; |
| 1902 | |
| 1903 | reg q; |
| 1904 | wire so; |
| 1905 | wire l1clk, siclk, soclk; |
| 1906 | |
| 1907 | |
| 1908 | |
| 1909 | reg l1; |
| 1910 | |
| 1911 | always @(l1clk or siclk or soclk or d or si or se) |
| 1912 | begin |
| 1913 | |
| 1914 | if (siclk) l1 <= si; // Load master with scan or flush |
| 1915 | |
| 1916 | if(se && !soclk && l1clk && siclk) q <= si; |
| 1917 | else if ( se && !soclk && l1clk) q <= l1; |
| 1918 | else if ( !soclk && l1clk) q <= d; |
| 1919 | end |
| 1920 | |
| 1921 | |
| 1922 | |
| 1923 | |
| 1924 | `ifdef INITLATZERO |
| 1925 | initial q = 1'b0; |
| 1926 | `endif |
| 1927 | |
| 1928 | |
| 1929 | |
| 1930 | assign so = q; |
| 1931 | |
| 1932 | endmodule // dff |
| 1933 | module cl_a1_clken_msff_4x ( q, so, d, l1clk, si, siclk, soclk, clken); |
| 1934 | // Level sensitive in SCAN_MODE |
| 1935 | // Edge triggered when not in SCAN_MODE |
| 1936 | // created by xl on 3/18 |
| 1937 | |
| 1938 | |
| 1939 | |
| 1940 | output q; |
| 1941 | output so; |
| 1942 | |
| 1943 | input d; |
| 1944 | input l1clk; |
| 1945 | input si; |
| 1946 | input siclk; |
| 1947 | input soclk; |
| 1948 | input clken; |
| 1949 | reg q; |
| 1950 | wire so; |
| 1951 | wire l1clk, siclk, soclk; |
| 1952 | |
| 1953 | `ifdef SCAN_MODE |
| 1954 | |
| 1955 | reg l1; |
| 1956 | `ifdef FAST_FLUSH |
| 1957 | always @(posedge l1clk or posedge siclk ) begin |
| 1958 | if (siclk) begin |
| 1959 | q <= 1'b0; //pseudo flush reset |
| 1960 | end else begin |
| 1961 | q <= (d & clken ) | (q & !clken); |
| 1962 | end |
| 1963 | end |
| 1964 | `else |
| 1965 | always @(l1clk or siclk or soclk or d or si) |
| 1966 | begin |
| 1967 | if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data |
| 1968 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 1969 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 1970 | |
| 1971 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 1972 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 1973 | end |
| 1974 | |
| 1975 | `endif |
| 1976 | `else |
| 1977 | wire si_unused; |
| 1978 | wire siclk_unused; |
| 1979 | wire soclk_unused; |
| 1980 | assign si_unused = si; |
| 1981 | assign siclk_unused = siclk; |
| 1982 | assign soclk_unused = soclk; |
| 1983 | |
| 1984 | |
| 1985 | `ifdef INITLATZERO |
| 1986 | |
| 1987 | initial q = 1'b0; |
| 1988 | `endif |
| 1989 | |
| 1990 | always @(posedge l1clk) |
| 1991 | begin |
| 1992 | if (!siclk && !soclk) q <= (d & clken ) | (q & !clken); |
| 1993 | else q <= 1'bx; |
| 1994 | end |
| 1995 | `endif |
| 1996 | |
| 1997 | assign so = q; |
| 1998 | |
| 1999 | endmodule |
| 2000 | |
| 2001 | module cl_a1_msff_arst_4x ( q, so, d, l1clk, si, siclk, soclk, reset ); |
| 2002 | // RFM 05-14-2004 |
| 2003 | // Level sensitive in SCAN_MODE |
| 2004 | // Edge triggered when not in SCAN_MODE |
| 2005 | |
| 2006 | |
| 2007 | parameter SIZE = 1; |
| 2008 | |
| 2009 | output q; |
| 2010 | output so; |
| 2011 | |
| 2012 | input d; |
| 2013 | input l1clk; |
| 2014 | input si; |
| 2015 | input siclk; |
| 2016 | input soclk; |
| 2017 | input reset; |
| 2018 | |
| 2019 | reg q; |
| 2020 | wire so; |
| 2021 | wire l1clk, siclk, soclk; |
| 2022 | |
| 2023 | `ifdef SCAN_MODE |
| 2024 | |
| 2025 | reg l1; |
| 2026 | |
| 2027 | always @(l1clk or siclk or soclk or d or si or reset) |
| 2028 | begin |
| 2029 | if (reset ) l1 <= 1'b0; |
| 2030 | else if (!l1clk && !siclk) l1 <= d; |
| 2031 | else if ( l1clk && siclk) l1 <= si; |
| 2032 | else if (!l1clk && siclk) l1 <= 1'bx; |
| 2033 | |
| 2034 | if (reset) q <= 1'b0; |
| 2035 | else if ( l1clk && !siclk && !soclk) q <= l1; |
| 2036 | else if ( l1clk && siclk && !soclk) q <= si; |
| 2037 | |
| 2038 | end |
| 2039 | |
| 2040 | |
| 2041 | `else |
| 2042 | wire si_unused; |
| 2043 | wire siclk_unused; |
| 2044 | wire soclk_unused; |
| 2045 | assign si_unused = si; |
| 2046 | assign siclk_unused = siclk; |
| 2047 | assign soclk_unused = soclk; |
| 2048 | |
| 2049 | |
| 2050 | `ifdef INITLATZERO |
| 2051 | initial q = 1'b0; |
| 2052 | `endif |
| 2053 | |
| 2054 | always @(posedge l1clk or posedge reset) |
| 2055 | begin |
| 2056 | |
| 2057 | if ( reset) q <= 1'b0; |
| 2058 | else if (!siclk && !soclk ) q <= d; |
| 2059 | else q <= 1'bx; |
| 2060 | end |
| 2061 | `endif |
| 2062 | |
| 2063 | assign so = q; |
| 2064 | |
| 2065 | endmodule // dff |
| 2066 | |
| 2067 | |
| 2068 | |
| 2069 | module cl_a1_aomux2_12x ( |
| 2070 | in0, |
| 2071 | in1, |
| 2072 | sel0, |
| 2073 | sel1, |
| 2074 | out |
| 2075 | ); |
| 2076 | input in0; |
| 2077 | input in1; |
| 2078 | input sel0; |
| 2079 | input sel1; |
| 2080 | output out; |
| 2081 | |
| 2082 | `ifdef LIB |
| 2083 | assign out = ((sel0 & in0) | |
| 2084 | (sel1 & in1)); |
| 2085 | `endif |
| 2086 | |
| 2087 | |
| 2088 | endmodule |
| 2089 | module cl_a1_aomux2_16x ( |
| 2090 | in0, |
| 2091 | in1, |
| 2092 | sel0, |
| 2093 | sel1, |
| 2094 | out |
| 2095 | ); |
| 2096 | input in0; |
| 2097 | input in1; |
| 2098 | input sel0; |
| 2099 | input sel1; |
| 2100 | output out; |
| 2101 | |
| 2102 | `ifdef LIB |
| 2103 | assign out = ((sel0 & in0) | |
| 2104 | (sel1 & in1)); |
| 2105 | `endif |
| 2106 | |
| 2107 | |
| 2108 | endmodule |
| 2109 | module cl_a1_aomux2_1x ( |
| 2110 | in0, |
| 2111 | in1, |
| 2112 | sel0, |
| 2113 | sel1, |
| 2114 | out |
| 2115 | ); |
| 2116 | input in0; |
| 2117 | input in1; |
| 2118 | input sel0; |
| 2119 | input sel1; |
| 2120 | output out; |
| 2121 | |
| 2122 | `ifdef LIB |
| 2123 | assign out = ((sel0 & in0) | |
| 2124 | (sel1 & in1)); |
| 2125 | `endif |
| 2126 | |
| 2127 | |
| 2128 | endmodule |
| 2129 | module cl_a1_aomux2_2x ( |
| 2130 | in0, |
| 2131 | in1, |
| 2132 | sel0, |
| 2133 | sel1, |
| 2134 | out |
| 2135 | ); |
| 2136 | input in0; |
| 2137 | input in1; |
| 2138 | input sel0; |
| 2139 | input sel1; |
| 2140 | output out; |
| 2141 | |
| 2142 | `ifdef LIB |
| 2143 | assign out = ((sel0 & in0) | |
| 2144 | (sel1 & in1)); |
| 2145 | `endif |
| 2146 | |
| 2147 | |
| 2148 | endmodule |
| 2149 | module cl_a1_aomux2_4x ( |
| 2150 | in0, |
| 2151 | in1, |
| 2152 | sel0, |
| 2153 | sel1, |
| 2154 | out |
| 2155 | ); |
| 2156 | input in0; |
| 2157 | input in1; |
| 2158 | input sel0; |
| 2159 | input sel1; |
| 2160 | output out; |
| 2161 | |
| 2162 | `ifdef LIB |
| 2163 | assign out = ((sel0 & in0) | |
| 2164 | (sel1 & in1)); |
| 2165 | `endif |
| 2166 | |
| 2167 | |
| 2168 | endmodule |
| 2169 | module cl_a1_aomux2_6x ( |
| 2170 | in0, |
| 2171 | in1, |
| 2172 | sel0, |
| 2173 | sel1, |
| 2174 | out |
| 2175 | ); |
| 2176 | input in0; |
| 2177 | input in1; |
| 2178 | input sel0; |
| 2179 | input sel1; |
| 2180 | output out; |
| 2181 | |
| 2182 | `ifdef LIB |
| 2183 | assign out = ((sel0 & in0) | |
| 2184 | (sel1 & in1)); |
| 2185 | `endif |
| 2186 | |
| 2187 | |
| 2188 | endmodule |
| 2189 | module cl_a1_aomux2_8x ( |
| 2190 | in0, |
| 2191 | in1, |
| 2192 | sel0, |
| 2193 | sel1, |
| 2194 | out |
| 2195 | ); |
| 2196 | input in0; |
| 2197 | input in1; |
| 2198 | input sel0; |
| 2199 | input sel1; |
| 2200 | output out; |
| 2201 | |
| 2202 | `ifdef LIB |
| 2203 | assign out = ((sel0 & in0) | |
| 2204 | (sel1 & in1)); |
| 2205 | `endif |
| 2206 | |
| 2207 | |
| 2208 | endmodule |
| 2209 | module cl_a1_aomux3_12x ( |
| 2210 | in0, |
| 2211 | in1, |
| 2212 | in2, |
| 2213 | sel0, |
| 2214 | sel1, |
| 2215 | sel2, |
| 2216 | out |
| 2217 | ); |
| 2218 | input in0; |
| 2219 | input in1; |
| 2220 | input in2; |
| 2221 | input sel0; |
| 2222 | input sel1; |
| 2223 | input sel2; |
| 2224 | output out; |
| 2225 | |
| 2226 | `ifdef LIB |
| 2227 | assign out = ((sel0 & in0) | |
| 2228 | (sel1 & in1) | |
| 2229 | (sel2 & in2)); |
| 2230 | `endif |
| 2231 | |
| 2232 | endmodule |
| 2233 | module cl_a1_aomux3_16x ( |
| 2234 | in0, |
| 2235 | in1, |
| 2236 | in2, |
| 2237 | sel0, |
| 2238 | sel1, |
| 2239 | sel2, |
| 2240 | out |
| 2241 | ); |
| 2242 | input in0; |
| 2243 | input in1; |
| 2244 | input in2; |
| 2245 | input sel0; |
| 2246 | input sel1; |
| 2247 | input sel2; |
| 2248 | output out; |
| 2249 | |
| 2250 | `ifdef LIB |
| 2251 | assign out = ((sel0 & in0) | |
| 2252 | (sel1 & in1) | |
| 2253 | (sel2 & in2)); |
| 2254 | `endif |
| 2255 | |
| 2256 | endmodule |
| 2257 | module cl_a1_aomux3_1x ( |
| 2258 | in0, |
| 2259 | in1, |
| 2260 | in2, |
| 2261 | sel0, |
| 2262 | sel1, |
| 2263 | sel2, |
| 2264 | out |
| 2265 | ); |
| 2266 | input in0; |
| 2267 | input in1; |
| 2268 | input in2; |
| 2269 | input sel0; |
| 2270 | input sel1; |
| 2271 | input sel2; |
| 2272 | output out; |
| 2273 | |
| 2274 | `ifdef LIB |
| 2275 | assign out = ((sel0 & in0) | |
| 2276 | (sel1 & in1) | |
| 2277 | (sel2 & in2)); |
| 2278 | `endif |
| 2279 | |
| 2280 | endmodule |
| 2281 | module cl_a1_aomux3_2x ( |
| 2282 | in0, |
| 2283 | in1, |
| 2284 | in2, |
| 2285 | sel0, |
| 2286 | sel1, |
| 2287 | sel2, |
| 2288 | out |
| 2289 | ); |
| 2290 | input in0; |
| 2291 | input in1; |
| 2292 | input in2; |
| 2293 | input sel0; |
| 2294 | input sel1; |
| 2295 | input sel2; |
| 2296 | output out; |
| 2297 | |
| 2298 | `ifdef LIB |
| 2299 | assign out = ((sel0 & in0) | |
| 2300 | (sel1 & in1) | |
| 2301 | (sel2 & in2)); |
| 2302 | `endif |
| 2303 | |
| 2304 | endmodule |
| 2305 | module cl_a1_aomux3_4x ( |
| 2306 | in0, |
| 2307 | in1, |
| 2308 | in2, |
| 2309 | sel0, |
| 2310 | sel1, |
| 2311 | sel2, |
| 2312 | out |
| 2313 | ); |
| 2314 | input in0; |
| 2315 | input in1; |
| 2316 | input in2; |
| 2317 | input sel0; |
| 2318 | input sel1; |
| 2319 | input sel2; |
| 2320 | output out; |
| 2321 | |
| 2322 | `ifdef LIB |
| 2323 | assign out = ((sel0 & in0) | |
| 2324 | (sel1 & in1) | |
| 2325 | (sel2 & in2)); |
| 2326 | `endif |
| 2327 | |
| 2328 | endmodule |
| 2329 | module cl_a1_aomux3_6x ( |
| 2330 | in0, |
| 2331 | in1, |
| 2332 | in2, |
| 2333 | sel0, |
| 2334 | sel1, |
| 2335 | sel2, |
| 2336 | out |
| 2337 | ); |
| 2338 | input in0; |
| 2339 | input in1; |
| 2340 | input in2; |
| 2341 | input sel0; |
| 2342 | input sel1; |
| 2343 | input sel2; |
| 2344 | output out; |
| 2345 | |
| 2346 | `ifdef LIB |
| 2347 | assign out = ((sel0 & in0) | |
| 2348 | (sel1 & in1) | |
| 2349 | (sel2 & in2)); |
| 2350 | `endif |
| 2351 | |
| 2352 | endmodule |
| 2353 | module cl_a1_aomux3_8x ( |
| 2354 | in0, |
| 2355 | in1, |
| 2356 | in2, |
| 2357 | sel0, |
| 2358 | sel1, |
| 2359 | sel2, |
| 2360 | out |
| 2361 | ); |
| 2362 | input in0; |
| 2363 | input in1; |
| 2364 | input in2; |
| 2365 | input sel0; |
| 2366 | input sel1; |
| 2367 | input sel2; |
| 2368 | output out; |
| 2369 | |
| 2370 | `ifdef LIB |
| 2371 | assign out = ((sel0 & in0) | |
| 2372 | (sel1 & in1) | |
| 2373 | (sel2 & in2)); |
| 2374 | `endif |
| 2375 | |
| 2376 | endmodule |
| 2377 | module cl_a1_aomux4_12x ( |
| 2378 | in0, |
| 2379 | in1, |
| 2380 | in2, |
| 2381 | in3, |
| 2382 | sel0, |
| 2383 | sel1, |
| 2384 | sel2, |
| 2385 | sel3, |
| 2386 | out |
| 2387 | ); |
| 2388 | input in0; |
| 2389 | input in1; |
| 2390 | input in2; |
| 2391 | input in3; |
| 2392 | input sel0; |
| 2393 | input sel1; |
| 2394 | input sel2; |
| 2395 | input sel3; |
| 2396 | output out; |
| 2397 | |
| 2398 | `ifdef LIB |
| 2399 | assign out = ((sel0 & in0) | |
| 2400 | (sel1 & in1) | |
| 2401 | (sel2 & in2) | |
| 2402 | (sel3 & in3)); |
| 2403 | `endif |
| 2404 | |
| 2405 | endmodule |
| 2406 | module cl_a1_aomux4_16x ( |
| 2407 | in0, |
| 2408 | in1, |
| 2409 | in2, |
| 2410 | in3, |
| 2411 | sel0, |
| 2412 | sel1, |
| 2413 | sel2, |
| 2414 | sel3, |
| 2415 | out |
| 2416 | ); |
| 2417 | input in0; |
| 2418 | input in1; |
| 2419 | input in2; |
| 2420 | input in3; |
| 2421 | input sel0; |
| 2422 | input sel1; |
| 2423 | input sel2; |
| 2424 | input sel3; |
| 2425 | output out; |
| 2426 | |
| 2427 | `ifdef LIB |
| 2428 | assign out = ((sel0 & in0) | |
| 2429 | (sel1 & in1) | |
| 2430 | (sel2 & in2) | |
| 2431 | (sel3 & in3)); |
| 2432 | `endif |
| 2433 | |
| 2434 | endmodule |
| 2435 | module cl_a1_aomux4_1x ( |
| 2436 | in0, |
| 2437 | in1, |
| 2438 | in2, |
| 2439 | in3, |
| 2440 | sel0, |
| 2441 | sel1, |
| 2442 | sel2, |
| 2443 | sel3, |
| 2444 | out |
| 2445 | ); |
| 2446 | input in0; |
| 2447 | input in1; |
| 2448 | input in2; |
| 2449 | input in3; |
| 2450 | input sel0; |
| 2451 | input sel1; |
| 2452 | input sel2; |
| 2453 | input sel3; |
| 2454 | output out; |
| 2455 | |
| 2456 | `ifdef LIB |
| 2457 | assign out = ((sel0 & in0) | |
| 2458 | (sel1 & in1) | |
| 2459 | (sel2 & in2) | |
| 2460 | (sel3 & in3)); |
| 2461 | `endif |
| 2462 | |
| 2463 | endmodule |
| 2464 | module cl_a1_aomux4_2x ( |
| 2465 | in0, |
| 2466 | in1, |
| 2467 | in2, |
| 2468 | in3, |
| 2469 | sel0, |
| 2470 | sel1, |
| 2471 | sel2, |
| 2472 | sel3, |
| 2473 | out |
| 2474 | ); |
| 2475 | input in0; |
| 2476 | input in1; |
| 2477 | input in2; |
| 2478 | input in3; |
| 2479 | input sel0; |
| 2480 | input sel1; |
| 2481 | input sel2; |
| 2482 | input sel3; |
| 2483 | output out; |
| 2484 | |
| 2485 | `ifdef LIB |
| 2486 | assign out = ((sel0 & in0) | |
| 2487 | (sel1 & in1) | |
| 2488 | (sel2 & in2) | |
| 2489 | (sel3 & in3)); |
| 2490 | `endif |
| 2491 | |
| 2492 | endmodule |
| 2493 | module cl_a1_aomux4_4x ( |
| 2494 | in0, |
| 2495 | in1, |
| 2496 | in2, |
| 2497 | in3, |
| 2498 | sel0, |
| 2499 | sel1, |
| 2500 | sel2, |
| 2501 | sel3, |
| 2502 | out |
| 2503 | ); |
| 2504 | input in0; |
| 2505 | input in1; |
| 2506 | input in2; |
| 2507 | input in3; |
| 2508 | input sel0; |
| 2509 | input sel1; |
| 2510 | input sel2; |
| 2511 | input sel3; |
| 2512 | output out; |
| 2513 | |
| 2514 | `ifdef LIB |
| 2515 | assign out = ((sel0 & in0) | |
| 2516 | (sel1 & in1) | |
| 2517 | (sel2 & in2) | |
| 2518 | (sel3 & in3)); |
| 2519 | `endif |
| 2520 | |
| 2521 | endmodule |
| 2522 | module cl_a1_aomux4_6x ( |
| 2523 | in0, |
| 2524 | in1, |
| 2525 | in2, |
| 2526 | in3, |
| 2527 | sel0, |
| 2528 | sel1, |
| 2529 | sel2, |
| 2530 | sel3, |
| 2531 | out |
| 2532 | ); |
| 2533 | input in0; |
| 2534 | input in1; |
| 2535 | input in2; |
| 2536 | input in3; |
| 2537 | input sel0; |
| 2538 | input sel1; |
| 2539 | input sel2; |
| 2540 | input sel3; |
| 2541 | output out; |
| 2542 | |
| 2543 | `ifdef LIB |
| 2544 | assign out = ((sel0 & in0) | |
| 2545 | (sel1 & in1) | |
| 2546 | (sel2 & in2) | |
| 2547 | (sel3 & in3)); |
| 2548 | `endif |
| 2549 | |
| 2550 | endmodule |
| 2551 | module cl_a1_aomux4_8x ( |
| 2552 | in0, |
| 2553 | in1, |
| 2554 | in2, |
| 2555 | in3, |
| 2556 | sel0, |
| 2557 | sel1, |
| 2558 | sel2, |
| 2559 | sel3, |
| 2560 | out |
| 2561 | ); |
| 2562 | input in0; |
| 2563 | input in1; |
| 2564 | input in2; |
| 2565 | input in3; |
| 2566 | input sel0; |
| 2567 | input sel1; |
| 2568 | input sel2; |
| 2569 | input sel3; |
| 2570 | output out; |
| 2571 | |
| 2572 | `ifdef LIB |
| 2573 | assign out = ((sel0 & in0) | |
| 2574 | (sel1 & in1) | |
| 2575 | (sel2 & in2) | |
| 2576 | (sel3 & in3)); |
| 2577 | `endif |
| 2578 | |
| 2579 | endmodule |
| 2580 | module cl_a1_aomux4_niu_8x ( |
| 2581 | in0, |
| 2582 | in1, |
| 2583 | in2, |
| 2584 | in3, |
| 2585 | sel0, |
| 2586 | sel1, |
| 2587 | sel2, |
| 2588 | sel3, |
| 2589 | out |
| 2590 | ); |
| 2591 | input in0; |
| 2592 | input in1; |
| 2593 | input in2; |
| 2594 | input in3; |
| 2595 | input sel0; |
| 2596 | input sel1; |
| 2597 | input sel2; |
| 2598 | input sel3; |
| 2599 | output out; |
| 2600 | |
| 2601 | `ifdef LIB |
| 2602 | assign out = ((sel0 & in0) | |
| 2603 | (sel1 & in1) | |
| 2604 | (sel2 & in2) | |
| 2605 | (sel3 & in3)); |
| 2606 | `endif |
| 2607 | |
| 2608 | endmodule |
| 2609 | module cl_a1_aomux5_12x ( |
| 2610 | in0, |
| 2611 | in1, |
| 2612 | in2, |
| 2613 | in3, |
| 2614 | in4, |
| 2615 | sel0, |
| 2616 | sel1, |
| 2617 | sel2, |
| 2618 | sel3, |
| 2619 | sel4, |
| 2620 | out |
| 2621 | ); |
| 2622 | input in0; |
| 2623 | input in1; |
| 2624 | input in2; |
| 2625 | input in3; |
| 2626 | input in4; |
| 2627 | input sel0; |
| 2628 | input sel1; |
| 2629 | input sel2; |
| 2630 | input sel3; |
| 2631 | input sel4; |
| 2632 | output out; |
| 2633 | |
| 2634 | `ifdef LIB |
| 2635 | assign out = ((sel0 & in0) | |
| 2636 | (sel1 & in1) | |
| 2637 | (sel2 & in2) | |
| 2638 | (sel3 & in3) | |
| 2639 | (sel4 & in4)); |
| 2640 | `endif |
| 2641 | |
| 2642 | endmodule |
| 2643 | module cl_a1_aomux5_16x ( |
| 2644 | in0, |
| 2645 | in1, |
| 2646 | in2, |
| 2647 | in3, |
| 2648 | in4, |
| 2649 | sel0, |
| 2650 | sel1, |
| 2651 | sel2, |
| 2652 | sel3, |
| 2653 | sel4, |
| 2654 | out |
| 2655 | ); |
| 2656 | input in0; |
| 2657 | input in1; |
| 2658 | input in2; |
| 2659 | input in3; |
| 2660 | input in4; |
| 2661 | input sel0; |
| 2662 | input sel1; |
| 2663 | input sel2; |
| 2664 | input sel3; |
| 2665 | input sel4; |
| 2666 | output out; |
| 2667 | |
| 2668 | `ifdef LIB |
| 2669 | assign out = ((sel0 & in0) | |
| 2670 | (sel1 & in1) | |
| 2671 | (sel2 & in2) | |
| 2672 | (sel3 & in3) | |
| 2673 | (sel4 & in4)); |
| 2674 | `endif |
| 2675 | |
| 2676 | endmodule |
| 2677 | module cl_a1_aomux5_1x ( |
| 2678 | in0, |
| 2679 | in1, |
| 2680 | in2, |
| 2681 | in3, |
| 2682 | in4, |
| 2683 | sel0, |
| 2684 | sel1, |
| 2685 | sel2, |
| 2686 | sel3, |
| 2687 | sel4, |
| 2688 | out |
| 2689 | ); |
| 2690 | input in0; |
| 2691 | input in1; |
| 2692 | input in2; |
| 2693 | input in3; |
| 2694 | input in4; |
| 2695 | input sel0; |
| 2696 | input sel1; |
| 2697 | input sel2; |
| 2698 | input sel3; |
| 2699 | input sel4; |
| 2700 | output out; |
| 2701 | |
| 2702 | `ifdef LIB |
| 2703 | assign out = ((sel0 & in0) | |
| 2704 | (sel1 & in1) | |
| 2705 | (sel2 & in2) | |
| 2706 | (sel3 & in3) | |
| 2707 | (sel4 & in4)); |
| 2708 | `endif |
| 2709 | |
| 2710 | endmodule |
| 2711 | module cl_a1_aomux5_2x ( |
| 2712 | in0, |
| 2713 | in1, |
| 2714 | in2, |
| 2715 | in3, |
| 2716 | in4, |
| 2717 | sel0, |
| 2718 | sel1, |
| 2719 | sel2, |
| 2720 | sel3, |
| 2721 | sel4, |
| 2722 | out |
| 2723 | ); |
| 2724 | input in0; |
| 2725 | input in1; |
| 2726 | input in2; |
| 2727 | input in3; |
| 2728 | input in4; |
| 2729 | input sel0; |
| 2730 | input sel1; |
| 2731 | input sel2; |
| 2732 | input sel3; |
| 2733 | input sel4; |
| 2734 | output out; |
| 2735 | |
| 2736 | `ifdef LIB |
| 2737 | assign out = ((sel0 & in0) | |
| 2738 | (sel1 & in1) | |
| 2739 | (sel2 & in2) | |
| 2740 | (sel3 & in3) | |
| 2741 | (sel4 & in4)); |
| 2742 | `endif |
| 2743 | |
| 2744 | endmodule |
| 2745 | module cl_a1_aomux5_4x ( |
| 2746 | in0, |
| 2747 | in1, |
| 2748 | in2, |
| 2749 | in3, |
| 2750 | in4, |
| 2751 | sel0, |
| 2752 | sel1, |
| 2753 | sel2, |
| 2754 | sel3, |
| 2755 | sel4, |
| 2756 | out |
| 2757 | ); |
| 2758 | input in0; |
| 2759 | input in1; |
| 2760 | input in2; |
| 2761 | input in3; |
| 2762 | input in4; |
| 2763 | input sel0; |
| 2764 | input sel1; |
| 2765 | input sel2; |
| 2766 | input sel3; |
| 2767 | input sel4; |
| 2768 | output out; |
| 2769 | |
| 2770 | `ifdef LIB |
| 2771 | assign out = ((sel0 & in0) | |
| 2772 | (sel1 & in1) | |
| 2773 | (sel2 & in2) | |
| 2774 | (sel3 & in3) | |
| 2775 | (sel4 & in4)); |
| 2776 | `endif |
| 2777 | |
| 2778 | endmodule |
| 2779 | module cl_a1_aomux5_6x ( |
| 2780 | in0, |
| 2781 | in1, |
| 2782 | in2, |
| 2783 | in3, |
| 2784 | in4, |
| 2785 | sel0, |
| 2786 | sel1, |
| 2787 | sel2, |
| 2788 | sel3, |
| 2789 | sel4, |
| 2790 | out |
| 2791 | ); |
| 2792 | input in0; |
| 2793 | input in1; |
| 2794 | input in2; |
| 2795 | input in3; |
| 2796 | input in4; |
| 2797 | input sel0; |
| 2798 | input sel1; |
| 2799 | input sel2; |
| 2800 | input sel3; |
| 2801 | input sel4; |
| 2802 | output out; |
| 2803 | |
| 2804 | `ifdef LIB |
| 2805 | assign out = ((sel0 & in0) | |
| 2806 | (sel1 & in1) | |
| 2807 | (sel2 & in2) | |
| 2808 | (sel3 & in3) | |
| 2809 | (sel4 & in4)); |
| 2810 | `endif |
| 2811 | |
| 2812 | endmodule |
| 2813 | module cl_a1_aomux5_8x ( |
| 2814 | in0, |
| 2815 | in1, |
| 2816 | in2, |
| 2817 | in3, |
| 2818 | in4, |
| 2819 | sel0, |
| 2820 | sel1, |
| 2821 | sel2, |
| 2822 | sel3, |
| 2823 | sel4, |
| 2824 | out |
| 2825 | ); |
| 2826 | input in0; |
| 2827 | input in1; |
| 2828 | input in2; |
| 2829 | input in3; |
| 2830 | input in4; |
| 2831 | input sel0; |
| 2832 | input sel1; |
| 2833 | input sel2; |
| 2834 | input sel3; |
| 2835 | input sel4; |
| 2836 | output out; |
| 2837 | |
| 2838 | `ifdef LIB |
| 2839 | assign out = ((sel0 & in0) | |
| 2840 | (sel1 & in1) | |
| 2841 | (sel2 & in2) | |
| 2842 | (sel3 & in3) | |
| 2843 | (sel4 & in4)); |
| 2844 | `endif |
| 2845 | |
| 2846 | endmodule |
| 2847 | module cl_a1_aomux6_12x ( |
| 2848 | in0, |
| 2849 | in1, |
| 2850 | in2, |
| 2851 | in3, |
| 2852 | in4, |
| 2853 | in5, |
| 2854 | sel0, |
| 2855 | sel1, |
| 2856 | sel2, |
| 2857 | sel3, |
| 2858 | sel4, |
| 2859 | sel5, |
| 2860 | out |
| 2861 | ); |
| 2862 | input in0; |
| 2863 | input in1; |
| 2864 | input in2; |
| 2865 | input in3; |
| 2866 | input in4; |
| 2867 | input in5; |
| 2868 | input sel0; |
| 2869 | input sel1; |
| 2870 | input sel2; |
| 2871 | input sel3; |
| 2872 | input sel4; |
| 2873 | input sel5; |
| 2874 | output out; |
| 2875 | |
| 2876 | `ifdef LIB |
| 2877 | assign out = ((sel0 & in0) | |
| 2878 | (sel1 & in1) | |
| 2879 | (sel2 & in2) | |
| 2880 | (sel3 & in3) | |
| 2881 | (sel4 & in4) | |
| 2882 | (sel5 & in5)); |
| 2883 | `endif |
| 2884 | |
| 2885 | endmodule |
| 2886 | module cl_a1_aomux6_16x ( |
| 2887 | in0, |
| 2888 | in1, |
| 2889 | in2, |
| 2890 | in3, |
| 2891 | in4, |
| 2892 | in5, |
| 2893 | sel0, |
| 2894 | sel1, |
| 2895 | sel2, |
| 2896 | sel3, |
| 2897 | sel4, |
| 2898 | sel5, |
| 2899 | out |
| 2900 | ); |
| 2901 | input in0; |
| 2902 | input in1; |
| 2903 | input in2; |
| 2904 | input in3; |
| 2905 | input in4; |
| 2906 | input in5; |
| 2907 | input sel0; |
| 2908 | input sel1; |
| 2909 | input sel2; |
| 2910 | input sel3; |
| 2911 | input sel4; |
| 2912 | input sel5; |
| 2913 | output out; |
| 2914 | |
| 2915 | `ifdef LIB |
| 2916 | assign out = ((sel0 & in0) | |
| 2917 | (sel1 & in1) | |
| 2918 | (sel2 & in2) | |
| 2919 | (sel3 & in3) | |
| 2920 | (sel4 & in4) | |
| 2921 | (sel5 & in5)); |
| 2922 | `endif |
| 2923 | |
| 2924 | endmodule |
| 2925 | module cl_a1_aomux6_1x ( |
| 2926 | in0, |
| 2927 | in1, |
| 2928 | in2, |
| 2929 | in3, |
| 2930 | in4, |
| 2931 | in5, |
| 2932 | sel0, |
| 2933 | sel1, |
| 2934 | sel2, |
| 2935 | sel3, |
| 2936 | sel4, |
| 2937 | sel5, |
| 2938 | out |
| 2939 | ); |
| 2940 | input in0; |
| 2941 | input in1; |
| 2942 | input in2; |
| 2943 | input in3; |
| 2944 | input in4; |
| 2945 | input in5; |
| 2946 | input sel0; |
| 2947 | input sel1; |
| 2948 | input sel2; |
| 2949 | input sel3; |
| 2950 | input sel4; |
| 2951 | input sel5; |
| 2952 | output out; |
| 2953 | |
| 2954 | `ifdef LIB |
| 2955 | assign out = ((sel0 & in0) | |
| 2956 | (sel1 & in1) | |
| 2957 | (sel2 & in2) | |
| 2958 | (sel3 & in3) | |
| 2959 | (sel4 & in4) | |
| 2960 | (sel5 & in5)); |
| 2961 | `endif |
| 2962 | |
| 2963 | endmodule |
| 2964 | module cl_a1_aomux6_2x ( |
| 2965 | in0, |
| 2966 | in1, |
| 2967 | in2, |
| 2968 | in3, |
| 2969 | in4, |
| 2970 | in5, |
| 2971 | sel0, |
| 2972 | sel1, |
| 2973 | sel2, |
| 2974 | sel3, |
| 2975 | sel4, |
| 2976 | sel5, |
| 2977 | out |
| 2978 | ); |
| 2979 | input in0; |
| 2980 | input in1; |
| 2981 | input in2; |
| 2982 | input in3; |
| 2983 | input in4; |
| 2984 | input in5; |
| 2985 | input sel0; |
| 2986 | input sel1; |
| 2987 | input sel2; |
| 2988 | input sel3; |
| 2989 | input sel4; |
| 2990 | input sel5; |
| 2991 | output out; |
| 2992 | |
| 2993 | `ifdef LIB |
| 2994 | assign out = ((sel0 & in0) | |
| 2995 | (sel1 & in1) | |
| 2996 | (sel2 & in2) | |
| 2997 | (sel3 & in3) | |
| 2998 | (sel4 & in4) | |
| 2999 | (sel5 & in5)); |
| 3000 | `endif |
| 3001 | |
| 3002 | endmodule |
| 3003 | module cl_a1_aomux6_4x ( |
| 3004 | in0, |
| 3005 | in1, |
| 3006 | in2, |
| 3007 | in3, |
| 3008 | in4, |
| 3009 | in5, |
| 3010 | sel0, |
| 3011 | sel1, |
| 3012 | sel2, |
| 3013 | sel3, |
| 3014 | sel4, |
| 3015 | sel5, |
| 3016 | out |
| 3017 | ); |
| 3018 | input in0; |
| 3019 | input in1; |
| 3020 | input in2; |
| 3021 | input in3; |
| 3022 | input in4; |
| 3023 | input in5; |
| 3024 | input sel0; |
| 3025 | input sel1; |
| 3026 | input sel2; |
| 3027 | input sel3; |
| 3028 | input sel4; |
| 3029 | input sel5; |
| 3030 | output out; |
| 3031 | |
| 3032 | `ifdef LIB |
| 3033 | assign out = ((sel0 & in0) | |
| 3034 | (sel1 & in1) | |
| 3035 | (sel2 & in2) | |
| 3036 | (sel3 & in3) | |
| 3037 | (sel4 & in4) | |
| 3038 | (sel5 & in5)); |
| 3039 | `endif |
| 3040 | |
| 3041 | endmodule |
| 3042 | module cl_a1_aomux6_6x ( |
| 3043 | in0, |
| 3044 | in1, |
| 3045 | in2, |
| 3046 | in3, |
| 3047 | in4, |
| 3048 | in5, |
| 3049 | sel0, |
| 3050 | sel1, |
| 3051 | sel2, |
| 3052 | sel3, |
| 3053 | sel4, |
| 3054 | sel5, |
| 3055 | out |
| 3056 | ); |
| 3057 | input in0; |
| 3058 | input in1; |
| 3059 | input in2; |
| 3060 | input in3; |
| 3061 | input in4; |
| 3062 | input in5; |
| 3063 | input sel0; |
| 3064 | input sel1; |
| 3065 | input sel2; |
| 3066 | input sel3; |
| 3067 | input sel4; |
| 3068 | input sel5; |
| 3069 | output out; |
| 3070 | |
| 3071 | `ifdef LIB |
| 3072 | assign out = ((sel0 & in0) | |
| 3073 | (sel1 & in1) | |
| 3074 | (sel2 & in2) | |
| 3075 | (sel3 & in3) | |
| 3076 | (sel4 & in4) | |
| 3077 | (sel5 & in5)); |
| 3078 | `endif |
| 3079 | |
| 3080 | endmodule |
| 3081 | module cl_a1_aomux6_8x ( |
| 3082 | in0, |
| 3083 | in1, |
| 3084 | in2, |
| 3085 | in3, |
| 3086 | in4, |
| 3087 | in5, |
| 3088 | sel0, |
| 3089 | sel1, |
| 3090 | sel2, |
| 3091 | sel3, |
| 3092 | sel4, |
| 3093 | sel5, |
| 3094 | out |
| 3095 | ); |
| 3096 | input in0; |
| 3097 | input in1; |
| 3098 | input in2; |
| 3099 | input in3; |
| 3100 | input in4; |
| 3101 | input in5; |
| 3102 | input sel0; |
| 3103 | input sel1; |
| 3104 | input sel2; |
| 3105 | input sel3; |
| 3106 | input sel4; |
| 3107 | input sel5; |
| 3108 | output out; |
| 3109 | |
| 3110 | `ifdef LIB |
| 3111 | assign out = ((sel0 & in0) | |
| 3112 | (sel1 & in1) | |
| 3113 | (sel2 & in2) | |
| 3114 | (sel3 & in3) | |
| 3115 | (sel4 & in4) | |
| 3116 | (sel5 & in5)); |
| 3117 | `endif |
| 3118 | |
| 3119 | endmodule |
| 3120 | module cl_a1_aomux6_by2_1x ( |
| 3121 | in0, |
| 3122 | in1, |
| 3123 | in2, |
| 3124 | in3, |
| 3125 | in4, |
| 3126 | in5, |
| 3127 | sel0, |
| 3128 | sel1, |
| 3129 | sel2, |
| 3130 | sel3, |
| 3131 | sel4, |
| 3132 | sel5, |
| 3133 | out |
| 3134 | ); |
| 3135 | input in0; |
| 3136 | input in1; |
| 3137 | input in2; |
| 3138 | input in3; |
| 3139 | input in4; |
| 3140 | input in5; |
| 3141 | input sel0; |
| 3142 | input sel1; |
| 3143 | input sel2; |
| 3144 | input sel3; |
| 3145 | input sel4; |
| 3146 | input sel5; |
| 3147 | output out; |
| 3148 | |
| 3149 | `ifdef LIB |
| 3150 | assign out = ((sel0 & in0) | |
| 3151 | (sel1 & in1) | |
| 3152 | (sel2 & in2) | |
| 3153 | (sel3 & in3) | |
| 3154 | (sel4 & in4) | |
| 3155 | (sel5 & in5)); |
| 3156 | `endif |
| 3157 | |
| 3158 | endmodule |
| 3159 | module cl_a1_aomux6_by2_2x ( |
| 3160 | in0, |
| 3161 | in1, |
| 3162 | in2, |
| 3163 | in3, |
| 3164 | in4, |
| 3165 | in5, |
| 3166 | sel0, |
| 3167 | sel1, |
| 3168 | sel2, |
| 3169 | sel3, |
| 3170 | sel4, |
| 3171 | sel5, |
| 3172 | out |
| 3173 | ); |
| 3174 | input in0; |
| 3175 | input in1; |
| 3176 | input in2; |
| 3177 | input in3; |
| 3178 | input in4; |
| 3179 | input in5; |
| 3180 | input sel0; |
| 3181 | input sel1; |
| 3182 | input sel2; |
| 3183 | input sel3; |
| 3184 | input sel4; |
| 3185 | input sel5; |
| 3186 | output out; |
| 3187 | |
| 3188 | `ifdef LIB |
| 3189 | assign out = ((sel0 & in0) | |
| 3190 | (sel1 & in1) | |
| 3191 | (sel2 & in2) | |
| 3192 | (sel3 & in3) | |
| 3193 | (sel4 & in4) | |
| 3194 | (sel5 & in5)); |
| 3195 | `endif |
| 3196 | |
| 3197 | endmodule |
| 3198 | module cl_a1_aomux7_12x ( |
| 3199 | in0, |
| 3200 | in1, |
| 3201 | in2, |
| 3202 | in3, |
| 3203 | in4, |
| 3204 | in5, |
| 3205 | in6, |
| 3206 | sel0, |
| 3207 | sel1, |
| 3208 | sel2, |
| 3209 | sel3, |
| 3210 | sel4, |
| 3211 | sel5, |
| 3212 | sel6, |
| 3213 | out |
| 3214 | ); |
| 3215 | input in0; |
| 3216 | input in1; |
| 3217 | input in2; |
| 3218 | input in3; |
| 3219 | input in4; |
| 3220 | input in5; |
| 3221 | input in6; |
| 3222 | input sel0; |
| 3223 | input sel1; |
| 3224 | input sel2; |
| 3225 | input sel3; |
| 3226 | input sel4; |
| 3227 | input sel5; |
| 3228 | input sel6; |
| 3229 | output out; |
| 3230 | |
| 3231 | `ifdef LIB |
| 3232 | assign out = ((sel0 & in0) | |
| 3233 | (sel1 & in1) | |
| 3234 | (sel2 & in2) | |
| 3235 | (sel3 & in3) | |
| 3236 | (sel4 & in4) | |
| 3237 | (sel5 & in5) | |
| 3238 | (sel6 & in6)); |
| 3239 | `endif |
| 3240 | |
| 3241 | endmodule |
| 3242 | module cl_a1_aomux7_16x ( |
| 3243 | in0, |
| 3244 | in1, |
| 3245 | in2, |
| 3246 | in3, |
| 3247 | in4, |
| 3248 | in5, |
| 3249 | in6, |
| 3250 | sel0, |
| 3251 | sel1, |
| 3252 | sel2, |
| 3253 | sel3, |
| 3254 | sel4, |
| 3255 | sel5, |
| 3256 | sel6, |
| 3257 | out |
| 3258 | ); |
| 3259 | input in0; |
| 3260 | input in1; |
| 3261 | input in2; |
| 3262 | input in3; |
| 3263 | input in4; |
| 3264 | input in5; |
| 3265 | input in6; |
| 3266 | input sel0; |
| 3267 | input sel1; |
| 3268 | input sel2; |
| 3269 | input sel3; |
| 3270 | input sel4; |
| 3271 | input sel5; |
| 3272 | input sel6; |
| 3273 | output out; |
| 3274 | |
| 3275 | `ifdef LIB |
| 3276 | assign out = ((sel0 & in0) | |
| 3277 | (sel1 & in1) | |
| 3278 | (sel2 & in2) | |
| 3279 | (sel3 & in3) | |
| 3280 | (sel4 & in4) | |
| 3281 | (sel5 & in5) | |
| 3282 | (sel6 & in6)); |
| 3283 | `endif |
| 3284 | |
| 3285 | endmodule |
| 3286 | module cl_a1_aomux7_1x ( |
| 3287 | in0, |
| 3288 | in1, |
| 3289 | in2, |
| 3290 | in3, |
| 3291 | in4, |
| 3292 | in5, |
| 3293 | in6, |
| 3294 | sel0, |
| 3295 | sel1, |
| 3296 | sel2, |
| 3297 | sel3, |
| 3298 | sel4, |
| 3299 | sel5, |
| 3300 | sel6, |
| 3301 | out |
| 3302 | ); |
| 3303 | input in0; |
| 3304 | input in1; |
| 3305 | input in2; |
| 3306 | input in3; |
| 3307 | input in4; |
| 3308 | input in5; |
| 3309 | input in6; |
| 3310 | input sel0; |
| 3311 | input sel1; |
| 3312 | input sel2; |
| 3313 | input sel3; |
| 3314 | input sel4; |
| 3315 | input sel5; |
| 3316 | input sel6; |
| 3317 | output out; |
| 3318 | |
| 3319 | `ifdef LIB |
| 3320 | assign out = ((sel0 & in0) | |
| 3321 | (sel1 & in1) | |
| 3322 | (sel2 & in2) | |
| 3323 | (sel3 & in3) | |
| 3324 | (sel4 & in4) | |
| 3325 | (sel5 & in5) | |
| 3326 | (sel6 & in6)); |
| 3327 | `endif |
| 3328 | |
| 3329 | endmodule |
| 3330 | module cl_a1_aomux7_2x ( |
| 3331 | in0, |
| 3332 | in1, |
| 3333 | in2, |
| 3334 | in3, |
| 3335 | in4, |
| 3336 | in5, |
| 3337 | in6, |
| 3338 | sel0, |
| 3339 | sel1, |
| 3340 | sel2, |
| 3341 | sel3, |
| 3342 | sel4, |
| 3343 | sel5, |
| 3344 | sel6, |
| 3345 | out |
| 3346 | ); |
| 3347 | input in0; |
| 3348 | input in1; |
| 3349 | input in2; |
| 3350 | input in3; |
| 3351 | input in4; |
| 3352 | input in5; |
| 3353 | input in6; |
| 3354 | input sel0; |
| 3355 | input sel1; |
| 3356 | input sel2; |
| 3357 | input sel3; |
| 3358 | input sel4; |
| 3359 | input sel5; |
| 3360 | input sel6; |
| 3361 | output out; |
| 3362 | |
| 3363 | `ifdef LIB |
| 3364 | assign out = ((sel0 & in0) | |
| 3365 | (sel1 & in1) | |
| 3366 | (sel2 & in2) | |
| 3367 | (sel3 & in3) | |
| 3368 | (sel4 & in4) | |
| 3369 | (sel5 & in5) | |
| 3370 | (sel6 & in6)); |
| 3371 | `endif |
| 3372 | |
| 3373 | endmodule |
| 3374 | module cl_a1_aomux7_4x ( |
| 3375 | in0, |
| 3376 | in1, |
| 3377 | in2, |
| 3378 | in3, |
| 3379 | in4, |
| 3380 | in5, |
| 3381 | in6, |
| 3382 | sel0, |
| 3383 | sel1, |
| 3384 | sel2, |
| 3385 | sel3, |
| 3386 | sel4, |
| 3387 | sel5, |
| 3388 | sel6, |
| 3389 | out |
| 3390 | ); |
| 3391 | input in0; |
| 3392 | input in1; |
| 3393 | input in2; |
| 3394 | input in3; |
| 3395 | input in4; |
| 3396 | input in5; |
| 3397 | input in6; |
| 3398 | input sel0; |
| 3399 | input sel1; |
| 3400 | input sel2; |
| 3401 | input sel3; |
| 3402 | input sel4; |
| 3403 | input sel5; |
| 3404 | input sel6; |
| 3405 | output out; |
| 3406 | |
| 3407 | `ifdef LIB |
| 3408 | assign out = ((sel0 & in0) | |
| 3409 | (sel1 & in1) | |
| 3410 | (sel2 & in2) | |
| 3411 | (sel3 & in3) | |
| 3412 | (sel4 & in4) | |
| 3413 | (sel5 & in5) | |
| 3414 | (sel6 & in6)); |
| 3415 | `endif |
| 3416 | |
| 3417 | endmodule |
| 3418 | module cl_a1_aomux7_6x ( |
| 3419 | in0, |
| 3420 | in1, |
| 3421 | in2, |
| 3422 | in3, |
| 3423 | in4, |
| 3424 | in5, |
| 3425 | in6, |
| 3426 | sel0, |
| 3427 | sel1, |
| 3428 | sel2, |
| 3429 | sel3, |
| 3430 | sel4, |
| 3431 | sel5, |
| 3432 | sel6, |
| 3433 | out |
| 3434 | ); |
| 3435 | input in0; |
| 3436 | input in1; |
| 3437 | input in2; |
| 3438 | input in3; |
| 3439 | input in4; |
| 3440 | input in5; |
| 3441 | input in6; |
| 3442 | input sel0; |
| 3443 | input sel1; |
| 3444 | input sel2; |
| 3445 | input sel3; |
| 3446 | input sel4; |
| 3447 | input sel5; |
| 3448 | input sel6; |
| 3449 | output out; |
| 3450 | |
| 3451 | `ifdef LIB |
| 3452 | assign out = ((sel0 & in0) | |
| 3453 | (sel1 & in1) | |
| 3454 | (sel2 & in2) | |
| 3455 | (sel3 & in3) | |
| 3456 | (sel4 & in4) | |
| 3457 | (sel5 & in5) | |
| 3458 | (sel6 & in6)); |
| 3459 | `endif |
| 3460 | |
| 3461 | endmodule |
| 3462 | module cl_a1_aomux7_8x ( |
| 3463 | in0, |
| 3464 | in1, |
| 3465 | in2, |
| 3466 | in3, |
| 3467 | in4, |
| 3468 | in5, |
| 3469 | in6, |
| 3470 | sel0, |
| 3471 | sel1, |
| 3472 | sel2, |
| 3473 | sel3, |
| 3474 | sel4, |
| 3475 | sel5, |
| 3476 | sel6, |
| 3477 | out |
| 3478 | ); |
| 3479 | input in0; |
| 3480 | input in1; |
| 3481 | input in2; |
| 3482 | input in3; |
| 3483 | input in4; |
| 3484 | input in5; |
| 3485 | input in6; |
| 3486 | input sel0; |
| 3487 | input sel1; |
| 3488 | input sel2; |
| 3489 | input sel3; |
| 3490 | input sel4; |
| 3491 | input sel5; |
| 3492 | input sel6; |
| 3493 | output out; |
| 3494 | |
| 3495 | `ifdef LIB |
| 3496 | assign out = ((sel0 & in0) | |
| 3497 | (sel1 & in1) | |
| 3498 | (sel2 & in2) | |
| 3499 | (sel3 & in3) | |
| 3500 | (sel4 & in4) | |
| 3501 | (sel5 & in5) | |
| 3502 | (sel6 & in6)); |
| 3503 | `endif |
| 3504 | |
| 3505 | endmodule |
| 3506 | module cl_a1_aomux7_by2_1x ( |
| 3507 | in0, |
| 3508 | in1, |
| 3509 | in2, |
| 3510 | in3, |
| 3511 | in4, |
| 3512 | in5, |
| 3513 | in6, |
| 3514 | sel0, |
| 3515 | sel1, |
| 3516 | sel2, |
| 3517 | sel3, |
| 3518 | sel4, |
| 3519 | sel5, |
| 3520 | sel6, |
| 3521 | out |
| 3522 | ); |
| 3523 | input in0; |
| 3524 | input in1; |
| 3525 | input in2; |
| 3526 | input in3; |
| 3527 | input in4; |
| 3528 | input in5; |
| 3529 | input in6; |
| 3530 | input sel0; |
| 3531 | input sel1; |
| 3532 | input sel2; |
| 3533 | input sel3; |
| 3534 | input sel4; |
| 3535 | input sel5; |
| 3536 | input sel6; |
| 3537 | output out; |
| 3538 | |
| 3539 | `ifdef LIB |
| 3540 | assign out = ((sel0 & in0) | |
| 3541 | (sel1 & in1) | |
| 3542 | (sel2 & in2) | |
| 3543 | (sel3 & in3) | |
| 3544 | (sel4 & in4) | |
| 3545 | (sel5 & in5) | |
| 3546 | (sel6 & in6)); |
| 3547 | `endif |
| 3548 | |
| 3549 | endmodule |
| 3550 | module cl_a1_aomux7_by2_2x ( |
| 3551 | in0, |
| 3552 | in1, |
| 3553 | in2, |
| 3554 | in3, |
| 3555 | in4, |
| 3556 | in5, |
| 3557 | in6, |
| 3558 | sel0, |
| 3559 | sel1, |
| 3560 | sel2, |
| 3561 | sel3, |
| 3562 | sel4, |
| 3563 | sel5, |
| 3564 | sel6, |
| 3565 | out |
| 3566 | ); |
| 3567 | input in0; |
| 3568 | input in1; |
| 3569 | input in2; |
| 3570 | input in3; |
| 3571 | input in4; |
| 3572 | input in5; |
| 3573 | input in6; |
| 3574 | input sel0; |
| 3575 | input sel1; |
| 3576 | input sel2; |
| 3577 | input sel3; |
| 3578 | input sel4; |
| 3579 | input sel5; |
| 3580 | input sel6; |
| 3581 | output out; |
| 3582 | |
| 3583 | `ifdef LIB |
| 3584 | assign out = ((sel0 & in0) | |
| 3585 | (sel1 & in1) | |
| 3586 | (sel2 & in2) | |
| 3587 | (sel3 & in3) | |
| 3588 | (sel4 & in4) | |
| 3589 | (sel5 & in5) | |
| 3590 | (sel6 & in6)); |
| 3591 | `endif |
| 3592 | |
| 3593 | endmodule |
| 3594 | module cl_a1_aomux8_12x ( |
| 3595 | in0, |
| 3596 | in1, |
| 3597 | in2, |
| 3598 | in3, |
| 3599 | in4, |
| 3600 | in5, |
| 3601 | in6, |
| 3602 | in7, |
| 3603 | sel0, |
| 3604 | sel1, |
| 3605 | sel2, |
| 3606 | sel3, |
| 3607 | sel4, |
| 3608 | sel5, |
| 3609 | sel6, |
| 3610 | sel7, |
| 3611 | out |
| 3612 | ); |
| 3613 | input in0; |
| 3614 | input in1; |
| 3615 | input in2; |
| 3616 | input in3; |
| 3617 | input in4; |
| 3618 | input in5; |
| 3619 | input in6; |
| 3620 | input in7; |
| 3621 | input sel0; |
| 3622 | input sel1; |
| 3623 | input sel2; |
| 3624 | input sel3; |
| 3625 | input sel4; |
| 3626 | input sel5; |
| 3627 | input sel6; |
| 3628 | input sel7; |
| 3629 | output out; |
| 3630 | |
| 3631 | `ifdef LIB |
| 3632 | assign out = ((sel0 & in0) | |
| 3633 | (sel1 & in1) | |
| 3634 | (sel2 & in2) | |
| 3635 | (sel3 & in3) | |
| 3636 | (sel4 & in4) | |
| 3637 | (sel5 & in5) | |
| 3638 | (sel6 & in6) | |
| 3639 | (sel7 & in7)); |
| 3640 | `endif |
| 3641 | |
| 3642 | |
| 3643 | endmodule |
| 3644 | module cl_a1_aomux8_16x ( |
| 3645 | in0, |
| 3646 | in1, |
| 3647 | in2, |
| 3648 | in3, |
| 3649 | in4, |
| 3650 | in5, |
| 3651 | in6, |
| 3652 | in7, |
| 3653 | sel0, |
| 3654 | sel1, |
| 3655 | sel2, |
| 3656 | sel3, |
| 3657 | sel4, |
| 3658 | sel5, |
| 3659 | sel6, |
| 3660 | sel7, |
| 3661 | out |
| 3662 | ); |
| 3663 | input in0; |
| 3664 | input in1; |
| 3665 | input in2; |
| 3666 | input in3; |
| 3667 | input in4; |
| 3668 | input in5; |
| 3669 | input in6; |
| 3670 | input in7; |
| 3671 | input sel0; |
| 3672 | input sel1; |
| 3673 | input sel2; |
| 3674 | input sel3; |
| 3675 | input sel4; |
| 3676 | input sel5; |
| 3677 | input sel6; |
| 3678 | input sel7; |
| 3679 | output out; |
| 3680 | |
| 3681 | `ifdef LIB |
| 3682 | assign out = ((sel0 & in0) | |
| 3683 | (sel1 & in1) | |
| 3684 | (sel2 & in2) | |
| 3685 | (sel3 & in3) | |
| 3686 | (sel4 & in4) | |
| 3687 | (sel5 & in5) | |
| 3688 | (sel6 & in6) | |
| 3689 | (sel7 & in7)); |
| 3690 | `endif |
| 3691 | |
| 3692 | |
| 3693 | endmodule |
| 3694 | module cl_a1_aomux8_1x ( |
| 3695 | in0, |
| 3696 | in1, |
| 3697 | in2, |
| 3698 | in3, |
| 3699 | in4, |
| 3700 | in5, |
| 3701 | in6, |
| 3702 | in7, |
| 3703 | sel0, |
| 3704 | sel1, |
| 3705 | sel2, |
| 3706 | sel3, |
| 3707 | sel4, |
| 3708 | sel5, |
| 3709 | sel6, |
| 3710 | sel7, |
| 3711 | out |
| 3712 | ); |
| 3713 | input in0; |
| 3714 | input in1; |
| 3715 | input in2; |
| 3716 | input in3; |
| 3717 | input in4; |
| 3718 | input in5; |
| 3719 | input in6; |
| 3720 | input in7; |
| 3721 | input sel0; |
| 3722 | input sel1; |
| 3723 | input sel2; |
| 3724 | input sel3; |
| 3725 | input sel4; |
| 3726 | input sel5; |
| 3727 | input sel6; |
| 3728 | input sel7; |
| 3729 | output out; |
| 3730 | |
| 3731 | `ifdef LIB |
| 3732 | assign out = ((sel0 & in0) | |
| 3733 | (sel1 & in1) | |
| 3734 | (sel2 & in2) | |
| 3735 | (sel3 & in3) | |
| 3736 | (sel4 & in4) | |
| 3737 | (sel5 & in5) | |
| 3738 | (sel6 & in6) | |
| 3739 | (sel7 & in7)); |
| 3740 | `endif |
| 3741 | |
| 3742 | |
| 3743 | endmodule |
| 3744 | module cl_a1_aomux8_2x ( |
| 3745 | in0, |
| 3746 | in1, |
| 3747 | in2, |
| 3748 | in3, |
| 3749 | in4, |
| 3750 | in5, |
| 3751 | in6, |
| 3752 | in7, |
| 3753 | sel0, |
| 3754 | sel1, |
| 3755 | sel2, |
| 3756 | sel3, |
| 3757 | sel4, |
| 3758 | sel5, |
| 3759 | sel6, |
| 3760 | sel7, |
| 3761 | out |
| 3762 | ); |
| 3763 | input in0; |
| 3764 | input in1; |
| 3765 | input in2; |
| 3766 | input in3; |
| 3767 | input in4; |
| 3768 | input in5; |
| 3769 | input in6; |
| 3770 | input in7; |
| 3771 | input sel0; |
| 3772 | input sel1; |
| 3773 | input sel2; |
| 3774 | input sel3; |
| 3775 | input sel4; |
| 3776 | input sel5; |
| 3777 | input sel6; |
| 3778 | input sel7; |
| 3779 | output out; |
| 3780 | |
| 3781 | `ifdef LIB |
| 3782 | assign out = ((sel0 & in0) | |
| 3783 | (sel1 & in1) | |
| 3784 | (sel2 & in2) | |
| 3785 | (sel3 & in3) | |
| 3786 | (sel4 & in4) | |
| 3787 | (sel5 & in5) | |
| 3788 | (sel6 & in6) | |
| 3789 | (sel7 & in7)); |
| 3790 | `endif |
| 3791 | |
| 3792 | |
| 3793 | endmodule |
| 3794 | module cl_a1_aomux8_4x ( |
| 3795 | in0, |
| 3796 | in1, |
| 3797 | in2, |
| 3798 | in3, |
| 3799 | in4, |
| 3800 | in5, |
| 3801 | in6, |
| 3802 | in7, |
| 3803 | sel0, |
| 3804 | sel1, |
| 3805 | sel2, |
| 3806 | sel3, |
| 3807 | sel4, |
| 3808 | sel5, |
| 3809 | sel6, |
| 3810 | sel7, |
| 3811 | out |
| 3812 | ); |
| 3813 | input in0; |
| 3814 | input in1; |
| 3815 | input in2; |
| 3816 | input in3; |
| 3817 | input in4; |
| 3818 | input in5; |
| 3819 | input in6; |
| 3820 | input in7; |
| 3821 | input sel0; |
| 3822 | input sel1; |
| 3823 | input sel2; |
| 3824 | input sel3; |
| 3825 | input sel4; |
| 3826 | input sel5; |
| 3827 | input sel6; |
| 3828 | input sel7; |
| 3829 | output out; |
| 3830 | |
| 3831 | `ifdef LIB |
| 3832 | assign out = ((sel0 & in0) | |
| 3833 | (sel1 & in1) | |
| 3834 | (sel2 & in2) | |
| 3835 | (sel3 & in3) | |
| 3836 | (sel4 & in4) | |
| 3837 | (sel5 & in5) | |
| 3838 | (sel6 & in6) | |
| 3839 | (sel7 & in7)); |
| 3840 | `endif |
| 3841 | |
| 3842 | |
| 3843 | endmodule |
| 3844 | module cl_a1_aomux8_6x ( |
| 3845 | in0, |
| 3846 | in1, |
| 3847 | in2, |
| 3848 | in3, |
| 3849 | in4, |
| 3850 | in5, |
| 3851 | in6, |
| 3852 | in7, |
| 3853 | sel0, |
| 3854 | sel1, |
| 3855 | sel2, |
| 3856 | sel3, |
| 3857 | sel4, |
| 3858 | sel5, |
| 3859 | sel6, |
| 3860 | sel7, |
| 3861 | out |
| 3862 | ); |
| 3863 | input in0; |
| 3864 | input in1; |
| 3865 | input in2; |
| 3866 | input in3; |
| 3867 | input in4; |
| 3868 | input in5; |
| 3869 | input in6; |
| 3870 | input in7; |
| 3871 | input sel0; |
| 3872 | input sel1; |
| 3873 | input sel2; |
| 3874 | input sel3; |
| 3875 | input sel4; |
| 3876 | input sel5; |
| 3877 | input sel6; |
| 3878 | input sel7; |
| 3879 | output out; |
| 3880 | |
| 3881 | `ifdef LIB |
| 3882 | assign out = ((sel0 & in0) | |
| 3883 | (sel1 & in1) | |
| 3884 | (sel2 & in2) | |
| 3885 | (sel3 & in3) | |
| 3886 | (sel4 & in4) | |
| 3887 | (sel5 & in5) | |
| 3888 | (sel6 & in6) | |
| 3889 | (sel7 & in7)); |
| 3890 | `endif |
| 3891 | |
| 3892 | |
| 3893 | endmodule |
| 3894 | module cl_a1_aomux8_8x ( |
| 3895 | in0, |
| 3896 | in1, |
| 3897 | in2, |
| 3898 | in3, |
| 3899 | in4, |
| 3900 | in5, |
| 3901 | in6, |
| 3902 | in7, |
| 3903 | sel0, |
| 3904 | sel1, |
| 3905 | sel2, |
| 3906 | sel3, |
| 3907 | sel4, |
| 3908 | sel5, |
| 3909 | sel6, |
| 3910 | sel7, |
| 3911 | out |
| 3912 | ); |
| 3913 | input in0; |
| 3914 | input in1; |
| 3915 | input in2; |
| 3916 | input in3; |
| 3917 | input in4; |
| 3918 | input in5; |
| 3919 | input in6; |
| 3920 | input in7; |
| 3921 | input sel0; |
| 3922 | input sel1; |
| 3923 | input sel2; |
| 3924 | input sel3; |
| 3925 | input sel4; |
| 3926 | input sel5; |
| 3927 | input sel6; |
| 3928 | input sel7; |
| 3929 | output out; |
| 3930 | |
| 3931 | `ifdef LIB |
| 3932 | assign out = ((sel0 & in0) | |
| 3933 | (sel1 & in1) | |
| 3934 | (sel2 & in2) | |
| 3935 | (sel3 & in3) | |
| 3936 | (sel4 & in4) | |
| 3937 | (sel5 & in5) | |
| 3938 | (sel6 & in6) | |
| 3939 | (sel7 & in7)); |
| 3940 | `endif |
| 3941 | |
| 3942 | |
| 3943 | endmodule |
| 3944 | module cl_a1_aomux8_by2_1x ( |
| 3945 | in0, |
| 3946 | in1, |
| 3947 | in2, |
| 3948 | in3, |
| 3949 | in4, |
| 3950 | in5, |
| 3951 | in6, |
| 3952 | in7, |
| 3953 | sel0, |
| 3954 | sel1, |
| 3955 | sel2, |
| 3956 | sel3, |
| 3957 | sel4, |
| 3958 | sel5, |
| 3959 | sel6, |
| 3960 | sel7, |
| 3961 | out |
| 3962 | ); |
| 3963 | input in0; |
| 3964 | input in1; |
| 3965 | input in2; |
| 3966 | input in3; |
| 3967 | input in4; |
| 3968 | input in5; |
| 3969 | input in6; |
| 3970 | input in7; |
| 3971 | input sel0; |
| 3972 | input sel1; |
| 3973 | input sel2; |
| 3974 | input sel3; |
| 3975 | input sel4; |
| 3976 | input sel5; |
| 3977 | input sel6; |
| 3978 | input sel7; |
| 3979 | output out; |
| 3980 | |
| 3981 | `ifdef LIB |
| 3982 | assign out = ((sel0 & in0) | |
| 3983 | (sel1 & in1) | |
| 3984 | (sel2 & in2) | |
| 3985 | (sel3 & in3) | |
| 3986 | (sel4 & in4) | |
| 3987 | (sel5 & in5) | |
| 3988 | (sel6 & in6) | |
| 3989 | (sel7 & in7)); |
| 3990 | `endif |
| 3991 | |
| 3992 | |
| 3993 | endmodule |
| 3994 | module cl_a1_aomux8_by2_2x ( |
| 3995 | in0, |
| 3996 | in1, |
| 3997 | in2, |
| 3998 | in3, |
| 3999 | in4, |
| 4000 | in5, |
| 4001 | in6, |
| 4002 | in7, |
| 4003 | sel0, |
| 4004 | sel1, |
| 4005 | sel2, |
| 4006 | sel3, |
| 4007 | sel4, |
| 4008 | sel5, |
| 4009 | sel6, |
| 4010 | sel7, |
| 4011 | out |
| 4012 | ); |
| 4013 | input in0; |
| 4014 | input in1; |
| 4015 | input in2; |
| 4016 | input in3; |
| 4017 | input in4; |
| 4018 | input in5; |
| 4019 | input in6; |
| 4020 | input in7; |
| 4021 | input sel0; |
| 4022 | input sel1; |
| 4023 | input sel2; |
| 4024 | input sel3; |
| 4025 | input sel4; |
| 4026 | input sel5; |
| 4027 | input sel6; |
| 4028 | input sel7; |
| 4029 | output out; |
| 4030 | |
| 4031 | `ifdef LIB |
| 4032 | assign out = ((sel0 & in0) | |
| 4033 | (sel1 & in1) | |
| 4034 | (sel2 & in2) | |
| 4035 | (sel3 & in3) | |
| 4036 | (sel4 & in4) | |
| 4037 | (sel5 & in5) | |
| 4038 | (sel6 & in6) | |
| 4039 | (sel7 & in7)); |
| 4040 | `endif |
| 4041 | |
| 4042 | |
| 4043 | endmodule |
| 4044 | module cl_a1_l1hdr_12x ( |
| 4045 | l2clk, |
| 4046 | se, |
| 4047 | pce, |
| 4048 | pce_ov, |
| 4049 | stop, |
| 4050 | l1clk |
| 4051 | |
| 4052 | ); |
| 4053 | |
| 4054 | |
| 4055 | |
| 4056 | |
| 4057 | input l2clk; // level 2 clock, from clock grid |
| 4058 | input se; // Scan Enable |
| 4059 | input pce; // Clock enable for local power savings |
| 4060 | input pce_ov; // TCU sourced clock enable override for testing |
| 4061 | input stop; // TCU/CCU sourced clock stop for debug |
| 4062 | output l1clk; |
| 4063 | `ifdef FORMAL_TOOL |
| 4064 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4065 | assign l1clk = (l2clk & l1en) | se; |
| 4066 | `else |
| 4067 | `ifdef LIB |
| 4068 | reg l1en; |
| 4069 | |
| 4070 | |
| 4071 | `ifdef SCAN_MODE |
| 4072 | always @ (l2clk or stop or pce or pce_ov) |
| 4073 | begin |
| 4074 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4075 | end |
| 4076 | `else |
| 4077 | always @ (negedge l2clk ) |
| 4078 | begin |
| 4079 | l1en <= (~stop & ( pce | pce_ov )); |
| 4080 | end |
| 4081 | `endif |
| 4082 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4083 | |
| 4084 | |
| 4085 | |
| 4086 | `endif |
| 4087 | `endif |
| 4088 | |
| 4089 | endmodule |
| 4090 | |
| 4091 | module cl_a1_l1hdr_16x ( |
| 4092 | l2clk, |
| 4093 | se, |
| 4094 | pce, |
| 4095 | pce_ov, |
| 4096 | stop, |
| 4097 | l1clk |
| 4098 | ); |
| 4099 | // RFM 05/21/2004 |
| 4100 | |
| 4101 | |
| 4102 | |
| 4103 | input l2clk; // level 2 clock, from clock grid |
| 4104 | input se; // Scan Enable |
| 4105 | input pce; // Clock enable for local power savings |
| 4106 | input pce_ov; // TCU sourced clock enable override for testing |
| 4107 | input stop; // TCU/CCU sourced clock stop for debug |
| 4108 | output l1clk; |
| 4109 | `ifdef FORMAL_TOOL |
| 4110 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4111 | assign l1clk = (l2clk & l1en) | se; |
| 4112 | `else |
| 4113 | `ifdef LIB |
| 4114 | reg l1en; |
| 4115 | |
| 4116 | |
| 4117 | |
| 4118 | `ifdef SCAN_MODE |
| 4119 | always @ (l2clk or stop or pce or pce_ov) |
| 4120 | begin |
| 4121 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4122 | end |
| 4123 | `else |
| 4124 | always @ (negedge l2clk ) |
| 4125 | begin |
| 4126 | l1en <= (~stop & ( pce | pce_ov )); |
| 4127 | end |
| 4128 | `endif |
| 4129 | |
| 4130 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4131 | |
| 4132 | |
| 4133 | |
| 4134 | `endif |
| 4135 | `endif |
| 4136 | |
| 4137 | endmodule |
| 4138 | module cl_a1_l1hdr_24x ( |
| 4139 | l2clk, |
| 4140 | se, |
| 4141 | pce, |
| 4142 | pce_ov, |
| 4143 | stop, |
| 4144 | l1clk |
| 4145 | ); |
| 4146 | // RFM 05/21/2004 |
| 4147 | |
| 4148 | |
| 4149 | |
| 4150 | input l2clk; // level 2 clock, from clock grid |
| 4151 | input se; // Scan Enable |
| 4152 | input pce; // Clock enable for local power savings |
| 4153 | input pce_ov; // TCU sourced clock enable override for testing |
| 4154 | input stop; // TCU/CCU sourced clock stop for debug |
| 4155 | output l1clk; |
| 4156 | `ifdef FORMAL_TOOL |
| 4157 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4158 | assign l1clk = (l2clk & l1en) | se; |
| 4159 | `else |
| 4160 | `ifdef LIB |
| 4161 | reg l1en; |
| 4162 | |
| 4163 | |
| 4164 | |
| 4165 | `ifdef SCAN_MODE |
| 4166 | always @ (l2clk or stop or pce or pce_ov) |
| 4167 | begin |
| 4168 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4169 | end |
| 4170 | `else |
| 4171 | always @ (negedge l2clk ) |
| 4172 | begin |
| 4173 | l1en <= (~stop & ( pce | pce_ov )); |
| 4174 | end |
| 4175 | `endif |
| 4176 | |
| 4177 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4178 | |
| 4179 | |
| 4180 | `endif |
| 4181 | `endif |
| 4182 | |
| 4183 | endmodule |
| 4184 | module cl_a1_l1hdr_32x ( |
| 4185 | l2clk, |
| 4186 | se, |
| 4187 | pce, |
| 4188 | pce_ov, |
| 4189 | stop, |
| 4190 | l1clk |
| 4191 | ); |
| 4192 | // RFM 05/21/2004 |
| 4193 | |
| 4194 | |
| 4195 | |
| 4196 | input l2clk; // level 2 clock, from clock grid |
| 4197 | input se; // Scan Enable |
| 4198 | input pce; // Clock enable for local power savings |
| 4199 | input pce_ov; // TCU sourced clock enable override for testing |
| 4200 | input stop; // TCU/CCU sourced clock stop for debug |
| 4201 | output l1clk; |
| 4202 | `ifdef FORMAL_TOOL |
| 4203 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4204 | assign l1clk = (l2clk & l1en) | se; |
| 4205 | `else |
| 4206 | `ifdef LIB |
| 4207 | reg l1en; |
| 4208 | |
| 4209 | |
| 4210 | |
| 4211 | `ifdef SCAN_MODE |
| 4212 | always @ (l2clk or stop or pce or pce_ov) |
| 4213 | begin |
| 4214 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4215 | end |
| 4216 | `else |
| 4217 | always @ (negedge l2clk ) |
| 4218 | begin |
| 4219 | l1en <= (~stop & ( pce | pce_ov )); |
| 4220 | end |
| 4221 | `endif |
| 4222 | |
| 4223 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4224 | |
| 4225 | |
| 4226 | |
| 4227 | `endif |
| 4228 | `endif |
| 4229 | |
| 4230 | endmodule |
| 4231 | |
| 4232 | module cl_a1_l1hdr_4x ( |
| 4233 | l2clk, |
| 4234 | se, |
| 4235 | pce, |
| 4236 | pce_ov, |
| 4237 | stop, |
| 4238 | l1clk |
| 4239 | ); |
| 4240 | // RFM 05/21/2004 |
| 4241 | |
| 4242 | |
| 4243 | |
| 4244 | input l2clk; // level 2 clock, from clock grid |
| 4245 | input se; // Scan Enable |
| 4246 | input pce; // Clock enable for local power savings |
| 4247 | input pce_ov; // TCU sourced clock enable override for testing |
| 4248 | input stop; // TCU/CCU sourced clock stop for debug |
| 4249 | output l1clk; |
| 4250 | `ifdef FORMAL_TOOL |
| 4251 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4252 | assign l1clk = (l2clk & l1en) | se; |
| 4253 | `else |
| 4254 | `ifdef LIB |
| 4255 | reg l1en; |
| 4256 | |
| 4257 | |
| 4258 | |
| 4259 | `ifdef SCAN_MODE |
| 4260 | always @ (l2clk or stop or pce or pce_ov) |
| 4261 | begin |
| 4262 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4263 | end |
| 4264 | `else |
| 4265 | always @ (negedge l2clk ) |
| 4266 | begin |
| 4267 | l1en <= (~stop & ( pce | pce_ov )); |
| 4268 | end |
| 4269 | `endif |
| 4270 | |
| 4271 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4272 | |
| 4273 | |
| 4274 | |
| 4275 | `endif |
| 4276 | `endif |
| 4277 | |
| 4278 | endmodule |
| 4279 | module cl_a1_l1hdr_48x ( |
| 4280 | l2clk, |
| 4281 | se, |
| 4282 | pce, |
| 4283 | pce_ov, |
| 4284 | stop, |
| 4285 | l1clk |
| 4286 | |
| 4287 | ); |
| 4288 | |
| 4289 | |
| 4290 | |
| 4291 | |
| 4292 | input l2clk; // level 2 clock, from clock grid |
| 4293 | input se; // Scan Enable |
| 4294 | input pce; // Clock enable for local power savings |
| 4295 | input pce_ov; // TCU sourced clock enable override for testing |
| 4296 | input stop; // TCU/CCU sourced clock stop for debug |
| 4297 | output l1clk; |
| 4298 | `ifdef FORMAL_TOOL |
| 4299 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4300 | assign l1clk = (l2clk & l1en) | se; |
| 4301 | `else |
| 4302 | `ifdef LIB |
| 4303 | reg l1en; |
| 4304 | |
| 4305 | |
| 4306 | |
| 4307 | `ifdef SCAN_MODE |
| 4308 | always @ (l2clk or stop or pce or pce_ov) |
| 4309 | begin |
| 4310 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4311 | end |
| 4312 | `else |
| 4313 | always @ (negedge l2clk ) |
| 4314 | begin |
| 4315 | l1en <= (~stop & ( pce | pce_ov )); |
| 4316 | end |
| 4317 | `endif |
| 4318 | |
| 4319 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4320 | |
| 4321 | |
| 4322 | |
| 4323 | `endif |
| 4324 | `endif |
| 4325 | |
| 4326 | endmodule |
| 4327 | module cl_a1_l1hdr_64x ( |
| 4328 | l2clk, |
| 4329 | se, |
| 4330 | pce, |
| 4331 | pce_ov, |
| 4332 | stop, |
| 4333 | l1clk |
| 4334 | |
| 4335 | ); |
| 4336 | |
| 4337 | |
| 4338 | |
| 4339 | |
| 4340 | input l2clk; // level 2 clock, from clock grid |
| 4341 | input se; // Scan Enable |
| 4342 | input pce; // Clock enable for local power savings |
| 4343 | input pce_ov; // TCU sourced clock enable override for testing |
| 4344 | input stop; // TCU/CCU sourced clock stop for debug |
| 4345 | output l1clk; |
| 4346 | `ifdef FORMAL_TOOL |
| 4347 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4348 | assign l1clk = (l2clk & l1en) | se; |
| 4349 | `else |
| 4350 | `ifdef LIB |
| 4351 | reg l1en; |
| 4352 | |
| 4353 | |
| 4354 | |
| 4355 | `ifdef SCAN_MODE |
| 4356 | always @ (l2clk or stop or pce or pce_ov) |
| 4357 | begin |
| 4358 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4359 | end |
| 4360 | `else |
| 4361 | always @ (negedge l2clk ) |
| 4362 | begin |
| 4363 | l1en <= (~stop & ( pce | pce_ov )); |
| 4364 | end |
| 4365 | `endif |
| 4366 | |
| 4367 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4368 | |
| 4369 | |
| 4370 | |
| 4371 | `endif |
| 4372 | `endif |
| 4373 | |
| 4374 | endmodule |
| 4375 | module cl_a1_l1hdr_8x ( |
| 4376 | l2clk, |
| 4377 | se, |
| 4378 | pce, |
| 4379 | pce_ov, |
| 4380 | stop, |
| 4381 | l1clk |
| 4382 | ); |
| 4383 | // RFM 05/21/2004 |
| 4384 | |
| 4385 | |
| 4386 | |
| 4387 | input l2clk; // level 2 clock, from clock grid |
| 4388 | input se; // Scan Enable |
| 4389 | input pce; // Clock enable for local power savings |
| 4390 | input pce_ov; // TCU sourced clock enable override for testing |
| 4391 | input stop; // TCU/CCU sourced clock stop for debug |
| 4392 | output l1clk; |
| 4393 | `ifdef FORMAL_TOOL |
| 4394 | wire l1en = (~stop & ( pce | pce_ov )); |
| 4395 | assign l1clk = (l2clk & l1en) | se; |
| 4396 | `else |
| 4397 | `ifdef LIB |
| 4398 | reg l1en; |
| 4399 | |
| 4400 | |
| 4401 | `ifdef SCAN_MODE |
| 4402 | always @ (l2clk or stop or pce or pce_ov) |
| 4403 | begin |
| 4404 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 4405 | end |
| 4406 | `else |
| 4407 | always @ (negedge l2clk ) |
| 4408 | begin |
| 4409 | l1en <= (~stop & ( pce | pce_ov )); |
| 4410 | end |
| 4411 | `endif |
| 4412 | |
| 4413 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 4414 | |
| 4415 | |
| 4416 | |
| 4417 | `endif |
| 4418 | `endif |
| 4419 | |
| 4420 | endmodule |
| 4421 | |
| 4422 | module cl_a1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4423 | // RFM 05-14-2004 |
| 4424 | // Level sensitive in SCAN_MODE |
| 4425 | // Edge triggered when not in SCAN_MODE |
| 4426 | |
| 4427 | |
| 4428 | parameter SIZE = 1; |
| 4429 | |
| 4430 | output q; |
| 4431 | output so; |
| 4432 | |
| 4433 | input d; |
| 4434 | input l1clk; |
| 4435 | input si; |
| 4436 | input siclk; |
| 4437 | input soclk; |
| 4438 | |
| 4439 | reg q; |
| 4440 | wire so; |
| 4441 | wire l1clk, siclk, soclk; |
| 4442 | |
| 4443 | `ifdef SCAN_MODE |
| 4444 | |
| 4445 | reg l1; |
| 4446 | `ifdef FAST_FLUSH |
| 4447 | always @(posedge l1clk or posedge siclk ) begin |
| 4448 | if (siclk) begin |
| 4449 | q <= 1'b0; //pseudo flush reset |
| 4450 | end else begin |
| 4451 | q <= d; |
| 4452 | end |
| 4453 | end |
| 4454 | `else |
| 4455 | always @(l1clk or siclk or soclk or d or si) |
| 4456 | begin |
| 4457 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4458 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4459 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4460 | |
| 4461 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4462 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4463 | end |
| 4464 | `endif |
| 4465 | `else |
| 4466 | wire si_unused; |
| 4467 | wire siclk_unused; |
| 4468 | wire soclk_unused; |
| 4469 | assign si_unused = si; |
| 4470 | assign siclk_unused = siclk; |
| 4471 | assign soclk_unused = soclk; |
| 4472 | |
| 4473 | |
| 4474 | `ifdef INITLATZERO |
| 4475 | initial q = 1'b0; |
| 4476 | `endif |
| 4477 | |
| 4478 | always @(posedge l1clk) |
| 4479 | begin |
| 4480 | if (!siclk && !soclk) q <= d; |
| 4481 | else q <= 1'bx; |
| 4482 | end |
| 4483 | `endif |
| 4484 | |
| 4485 | assign so = q; |
| 4486 | |
| 4487 | endmodule // dff |
| 4488 | |
| 4489 | |
| 4490 | |
| 4491 | |
| 4492 | module cl_a1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4493 | // RFM 05-14-2004 |
| 4494 | // Level sensitive in SCAN_MODE |
| 4495 | // Edge triggered when not in SCAN_MODE |
| 4496 | |
| 4497 | |
| 4498 | parameter SIZE = 1; |
| 4499 | |
| 4500 | output q; |
| 4501 | output so; |
| 4502 | |
| 4503 | input d; |
| 4504 | input l1clk; |
| 4505 | input si; |
| 4506 | input siclk; |
| 4507 | input soclk; |
| 4508 | |
| 4509 | reg q; |
| 4510 | wire so; |
| 4511 | wire l1clk, siclk, soclk; |
| 4512 | |
| 4513 | `ifdef SCAN_MODE |
| 4514 | `ifdef FAST_FLUSH |
| 4515 | always @(posedge l1clk or posedge siclk ) begin |
| 4516 | if (siclk) begin |
| 4517 | q <= 1'b0; //pseudo flush reset |
| 4518 | end else begin |
| 4519 | q <= d; |
| 4520 | end |
| 4521 | end |
| 4522 | `else |
| 4523 | reg l1; |
| 4524 | |
| 4525 | always @(l1clk or siclk or soclk or d or si) |
| 4526 | begin |
| 4527 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4528 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4529 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4530 | |
| 4531 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4532 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4533 | end |
| 4534 | `endif |
| 4535 | `else |
| 4536 | wire si_unused; |
| 4537 | wire siclk_unused; |
| 4538 | wire soclk_unused; |
| 4539 | assign si_unused = si; |
| 4540 | assign siclk_unused = siclk; |
| 4541 | assign soclk_unused = soclk; |
| 4542 | |
| 4543 | |
| 4544 | `ifdef INITLATZERO |
| 4545 | initial q = 1'b0; |
| 4546 | `endif |
| 4547 | |
| 4548 | always @(posedge l1clk) |
| 4549 | begin |
| 4550 | if (!siclk && !soclk) q <= d; |
| 4551 | else q <= 1'bx; |
| 4552 | end |
| 4553 | `endif |
| 4554 | |
| 4555 | assign so = q; |
| 4556 | |
| 4557 | endmodule // dff |
| 4558 | module cl_a1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4559 | // RFM 05-14-2004 |
| 4560 | // Level sensitive in SCAN_MODE |
| 4561 | // Edge triggered when not in SCAN_MODE |
| 4562 | |
| 4563 | |
| 4564 | parameter SIZE = 1; |
| 4565 | |
| 4566 | output q; |
| 4567 | output so; |
| 4568 | |
| 4569 | input d; |
| 4570 | input l1clk; |
| 4571 | input si; |
| 4572 | input siclk; |
| 4573 | input soclk; |
| 4574 | |
| 4575 | reg q; |
| 4576 | wire so; |
| 4577 | wire l1clk, siclk, soclk; |
| 4578 | |
| 4579 | `ifdef SCAN_MODE |
| 4580 | |
| 4581 | reg l1; |
| 4582 | `ifdef FAST_FLUSH |
| 4583 | always @(posedge l1clk or posedge siclk ) begin |
| 4584 | if (siclk) begin |
| 4585 | q <= 1'b0; //pseudo flush reset |
| 4586 | end else begin |
| 4587 | q <= d; |
| 4588 | end |
| 4589 | end |
| 4590 | `else |
| 4591 | always @(l1clk or siclk or soclk or d or si) |
| 4592 | begin |
| 4593 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4594 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4595 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4596 | |
| 4597 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4598 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4599 | end |
| 4600 | `endif |
| 4601 | `else |
| 4602 | wire si_unused; |
| 4603 | wire siclk_unused; |
| 4604 | wire soclk_unused; |
| 4605 | assign si_unused = si; |
| 4606 | assign siclk_unused = siclk; |
| 4607 | assign soclk_unused = soclk; |
| 4608 | |
| 4609 | |
| 4610 | `ifdef INITLATZERO |
| 4611 | initial q = 1'b0; |
| 4612 | `endif |
| 4613 | |
| 4614 | always @(posedge l1clk) |
| 4615 | begin |
| 4616 | if (!siclk && !soclk) q <= d; |
| 4617 | else q <= 1'bx; |
| 4618 | end |
| 4619 | `endif |
| 4620 | |
| 4621 | assign so = q; |
| 4622 | |
| 4623 | endmodule // dff |
| 4624 | module cl_a1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4625 | // RFM 05-14-2004 |
| 4626 | // Level sensitive in SCAN_MODE |
| 4627 | // Edge triggered when not in SCAN_MODE |
| 4628 | |
| 4629 | |
| 4630 | parameter SIZE = 1; |
| 4631 | |
| 4632 | output q; |
| 4633 | output so; |
| 4634 | |
| 4635 | input d; |
| 4636 | input l1clk; |
| 4637 | input si; |
| 4638 | input siclk; |
| 4639 | input soclk; |
| 4640 | |
| 4641 | reg q; |
| 4642 | wire so; |
| 4643 | wire l1clk, siclk, soclk; |
| 4644 | |
| 4645 | `ifdef SCAN_MODE |
| 4646 | |
| 4647 | reg l1; |
| 4648 | `ifdef FAST_FLUSH |
| 4649 | always @(posedge l1clk or posedge siclk ) begin |
| 4650 | if (siclk) begin |
| 4651 | q <= 1'b0; //pseudo flush reset |
| 4652 | end else begin |
| 4653 | q <= d; |
| 4654 | end |
| 4655 | end |
| 4656 | `else |
| 4657 | always @(l1clk or siclk or soclk or d or si) |
| 4658 | begin |
| 4659 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4660 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4661 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4662 | |
| 4663 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4664 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4665 | end |
| 4666 | `endif |
| 4667 | `else |
| 4668 | wire si_unused; |
| 4669 | wire siclk_unused; |
| 4670 | wire soclk_unused; |
| 4671 | assign si_unused = si; |
| 4672 | assign siclk_unused = siclk; |
| 4673 | assign soclk_unused = soclk; |
| 4674 | |
| 4675 | |
| 4676 | `ifdef INITLATZERO |
| 4677 | initial q = 1'b0; |
| 4678 | `endif |
| 4679 | |
| 4680 | always @(posedge l1clk) |
| 4681 | begin |
| 4682 | if (!siclk && !soclk) q <= d; |
| 4683 | else q <= 1'bx; |
| 4684 | end |
| 4685 | `endif |
| 4686 | |
| 4687 | assign so = q; |
| 4688 | |
| 4689 | endmodule // dff |
| 4690 | module cl_a1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4691 | // RFM 05-14-2004 |
| 4692 | // Level sensitive in SCAN_MODE |
| 4693 | // Edge triggered when not in SCAN_MODE |
| 4694 | |
| 4695 | |
| 4696 | parameter SIZE = 1; |
| 4697 | |
| 4698 | output q; |
| 4699 | output so; |
| 4700 | |
| 4701 | input d; |
| 4702 | input l1clk; |
| 4703 | input si; |
| 4704 | input siclk; |
| 4705 | input soclk; |
| 4706 | |
| 4707 | reg q; |
| 4708 | wire so; |
| 4709 | wire l1clk, siclk, soclk; |
| 4710 | |
| 4711 | `ifdef SCAN_MODE |
| 4712 | |
| 4713 | reg l1; |
| 4714 | `ifdef FAST_FLUSH |
| 4715 | always @(posedge l1clk or posedge siclk ) begin |
| 4716 | if (siclk) begin |
| 4717 | q <= 1'b0; //pseudo flush reset |
| 4718 | end else begin |
| 4719 | q <= d; |
| 4720 | end |
| 4721 | end |
| 4722 | `else |
| 4723 | always @(l1clk or siclk or soclk or d or si) |
| 4724 | begin |
| 4725 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4726 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4727 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4728 | |
| 4729 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4730 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4731 | end |
| 4732 | `endif |
| 4733 | `else |
| 4734 | wire si_unused; |
| 4735 | wire siclk_unused; |
| 4736 | wire soclk_unused; |
| 4737 | assign si_unused = si; |
| 4738 | assign siclk_unused = siclk; |
| 4739 | assign soclk_unused = soclk; |
| 4740 | |
| 4741 | |
| 4742 | `ifdef INITLATZERO |
| 4743 | initial q = 1'b0; |
| 4744 | `endif |
| 4745 | |
| 4746 | always @(posedge l1clk) |
| 4747 | begin |
| 4748 | if (!siclk && !soclk) q <= d; |
| 4749 | else q <= 1'bx; |
| 4750 | end |
| 4751 | `endif |
| 4752 | |
| 4753 | assign so = q; |
| 4754 | |
| 4755 | endmodule // dff |
| 4756 | module cl_a1_msff_lp_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4757 | // RFM 05-14-2004 |
| 4758 | // Level sensitive in SCAN_MODE |
| 4759 | // Edge triggered when not in SCAN_MODE |
| 4760 | |
| 4761 | |
| 4762 | parameter SIZE = 1; |
| 4763 | |
| 4764 | output q; |
| 4765 | output so; |
| 4766 | |
| 4767 | input d; |
| 4768 | input l1clk; |
| 4769 | input si; |
| 4770 | input siclk; |
| 4771 | input soclk; |
| 4772 | |
| 4773 | reg q; |
| 4774 | wire so; |
| 4775 | wire l1clk, siclk, soclk; |
| 4776 | |
| 4777 | `ifdef SCAN_MODE |
| 4778 | |
| 4779 | reg l1; |
| 4780 | `ifdef FAST_FLUSH |
| 4781 | always @(posedge l1clk or posedge siclk ) begin |
| 4782 | if (siclk) begin |
| 4783 | q <= 1'b0; //pseudo flush reset |
| 4784 | end else begin |
| 4785 | q <= d; |
| 4786 | end |
| 4787 | end |
| 4788 | `else |
| 4789 | always @(l1clk or siclk or soclk or d or si) |
| 4790 | begin |
| 4791 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4792 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4793 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4794 | |
| 4795 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4796 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4797 | end |
| 4798 | `endif |
| 4799 | `else |
| 4800 | wire si_unused; |
| 4801 | wire siclk_unused; |
| 4802 | wire soclk_unused; |
| 4803 | assign si_unused = si; |
| 4804 | assign siclk_unused = siclk; |
| 4805 | assign soclk_unused = soclk; |
| 4806 | |
| 4807 | |
| 4808 | `ifdef INITLATZERO |
| 4809 | initial q = 1'b0; |
| 4810 | `endif |
| 4811 | |
| 4812 | always @(posedge l1clk) |
| 4813 | begin |
| 4814 | if (!siclk && !soclk) q <= d; |
| 4815 | else q <= 1'bx; |
| 4816 | end |
| 4817 | `endif |
| 4818 | |
| 4819 | assign so = q; |
| 4820 | |
| 4821 | endmodule // dff |
| 4822 | |
| 4823 | |
| 4824 | module cl_a1_msff_16x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4825 | // RFM 05-14-2004 |
| 4826 | // Level sensitive in SCAN_MODE |
| 4827 | // Edge triggered when not in SCAN_MODE |
| 4828 | |
| 4829 | |
| 4830 | parameter SIZE = 1; |
| 4831 | |
| 4832 | output q; |
| 4833 | output so; |
| 4834 | |
| 4835 | input d; |
| 4836 | input l1clk; |
| 4837 | input si; |
| 4838 | input siclk; |
| 4839 | input soclk; |
| 4840 | |
| 4841 | reg q; |
| 4842 | wire so; |
| 4843 | wire l1clk, siclk, soclk; |
| 4844 | |
| 4845 | `ifdef SCAN_MODE |
| 4846 | |
| 4847 | reg l1; |
| 4848 | `ifdef FAST_FLUSH |
| 4849 | always @(posedge l1clk or posedge siclk ) begin |
| 4850 | if (siclk) begin |
| 4851 | q <= 1'b0; //pseudo flush reset |
| 4852 | end else begin |
| 4853 | q <= d; |
| 4854 | end |
| 4855 | end |
| 4856 | `else |
| 4857 | always @(l1clk or siclk or soclk or d or si) |
| 4858 | begin |
| 4859 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4860 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4861 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4862 | |
| 4863 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4864 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4865 | end |
| 4866 | `endif |
| 4867 | `else |
| 4868 | wire si_unused; |
| 4869 | wire siclk_unused; |
| 4870 | wire soclk_unused; |
| 4871 | assign si_unused = si; |
| 4872 | assign siclk_unused = siclk; |
| 4873 | assign soclk_unused = soclk; |
| 4874 | |
| 4875 | |
| 4876 | `ifdef INITLATZERO |
| 4877 | initial q = 1'b0; |
| 4878 | `endif |
| 4879 | |
| 4880 | always @(posedge l1clk) |
| 4881 | begin |
| 4882 | if (!siclk && !soclk) q <= d; |
| 4883 | else q <= 1'bx; |
| 4884 | end |
| 4885 | `endif |
| 4886 | |
| 4887 | assign so = q; |
| 4888 | |
| 4889 | endmodule // dff |
| 4890 | module cl_a1_msff_1x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4891 | // RFM 05-14-2004 |
| 4892 | // Level sensitive in SCAN_MODE |
| 4893 | // Edge triggered when not in SCAN_MODE |
| 4894 | |
| 4895 | |
| 4896 | parameter SIZE = 1; |
| 4897 | |
| 4898 | output q; |
| 4899 | output so; |
| 4900 | |
| 4901 | input d; |
| 4902 | input l1clk; |
| 4903 | input si; |
| 4904 | input siclk; |
| 4905 | input soclk; |
| 4906 | |
| 4907 | reg q; |
| 4908 | wire so; |
| 4909 | wire l1clk, siclk, soclk; |
| 4910 | |
| 4911 | `ifdef SCAN_MODE |
| 4912 | reg l1; |
| 4913 | `ifdef FAST_FLUSH |
| 4914 | always @(posedge l1clk or posedge siclk ) begin |
| 4915 | if (siclk) begin |
| 4916 | q <= 1'b0; //pseudo flush reset |
| 4917 | end else begin |
| 4918 | q <= d; |
| 4919 | end |
| 4920 | end |
| 4921 | `else |
| 4922 | always @(l1clk or siclk or soclk or d or si) |
| 4923 | begin |
| 4924 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4925 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4926 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4927 | |
| 4928 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4929 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4930 | end |
| 4931 | `endif |
| 4932 | `else |
| 4933 | wire si_unused; |
| 4934 | wire siclk_unused; |
| 4935 | wire soclk_unused; |
| 4936 | assign si_unused = si; |
| 4937 | assign siclk_unused = siclk; |
| 4938 | assign soclk_unused = soclk; |
| 4939 | |
| 4940 | |
| 4941 | `ifdef INITLATZERO |
| 4942 | initial q = 1'b0; |
| 4943 | `endif |
| 4944 | |
| 4945 | always @(posedge l1clk) |
| 4946 | begin |
| 4947 | if (!siclk && !soclk) q <= d; |
| 4948 | else q <= 1'bx; |
| 4949 | end |
| 4950 | `endif |
| 4951 | |
| 4952 | assign so = q; |
| 4953 | |
| 4954 | endmodule // dff |
| 4955 | |
| 4956 | |
| 4957 | module cl_a1_msff_32x ( q, so, d, l1clk, si, siclk, soclk ); |
| 4958 | // RFM 05-14-2004 |
| 4959 | // Level sensitive in SCAN_MODE |
| 4960 | // Edge triggered when not in SCAN_MODE |
| 4961 | |
| 4962 | |
| 4963 | parameter SIZE = 1; |
| 4964 | |
| 4965 | output q; |
| 4966 | output so; |
| 4967 | |
| 4968 | input d; |
| 4969 | input l1clk; |
| 4970 | input si; |
| 4971 | input siclk; |
| 4972 | input soclk; |
| 4973 | |
| 4974 | reg q; |
| 4975 | wire so; |
| 4976 | wire l1clk, siclk, soclk; |
| 4977 | |
| 4978 | `ifdef SCAN_MODE |
| 4979 | reg l1; |
| 4980 | `ifdef FAST_FLUSH |
| 4981 | always @(posedge l1clk or posedge siclk ) begin |
| 4982 | if (siclk) begin |
| 4983 | q <= 1'b0; //pseudo flush reset |
| 4984 | end else begin |
| 4985 | q <= d; |
| 4986 | end |
| 4987 | end |
| 4988 | `else |
| 4989 | |
| 4990 | always @(l1clk or siclk or soclk or d or si) |
| 4991 | begin |
| 4992 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 4993 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 4994 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 4995 | |
| 4996 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 4997 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 4998 | end |
| 4999 | `endif |
| 5000 | `else |
| 5001 | wire si_unused; |
| 5002 | wire siclk_unused; |
| 5003 | wire soclk_unused; |
| 5004 | assign si_unused = si; |
| 5005 | assign siclk_unused = siclk; |
| 5006 | assign soclk_unused = soclk; |
| 5007 | |
| 5008 | |
| 5009 | `ifdef INITLATZERO |
| 5010 | initial q = 1'b0; |
| 5011 | `endif |
| 5012 | |
| 5013 | always @(posedge l1clk) |
| 5014 | begin |
| 5015 | if (!siclk && !soclk) q <= d; |
| 5016 | else q <= 1'bx; |
| 5017 | end |
| 5018 | `endif |
| 5019 | |
| 5020 | assign so = q; |
| 5021 | |
| 5022 | endmodule // dff |
| 5023 | module cl_a1_msff_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 5024 | // RFM 05-14-2004 |
| 5025 | // Level sensitive in SCAN_MODE |
| 5026 | // Edge triggered when not in SCAN_MODE |
| 5027 | |
| 5028 | |
| 5029 | parameter SIZE = 1; |
| 5030 | |
| 5031 | output q; |
| 5032 | output so; |
| 5033 | |
| 5034 | input d; |
| 5035 | input l1clk; |
| 5036 | input si; |
| 5037 | input siclk; |
| 5038 | input soclk; |
| 5039 | |
| 5040 | reg q; |
| 5041 | wire so; |
| 5042 | wire l1clk, siclk, soclk; |
| 5043 | |
| 5044 | `ifdef SCAN_MODE |
| 5045 | |
| 5046 | reg l1; |
| 5047 | `ifdef FAST_FLUSH |
| 5048 | always @(posedge l1clk or posedge siclk ) begin |
| 5049 | if (siclk) begin |
| 5050 | q <= 1'b0; //pseudo flush reset |
| 5051 | end else begin |
| 5052 | q <= d; |
| 5053 | end |
| 5054 | end |
| 5055 | `else |
| 5056 | always @(l1clk or siclk or soclk or d or si) |
| 5057 | begin |
| 5058 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5059 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5060 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5061 | |
| 5062 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5063 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5064 | end |
| 5065 | `endif |
| 5066 | `else |
| 5067 | wire si_unused; |
| 5068 | wire siclk_unused; |
| 5069 | wire soclk_unused; |
| 5070 | assign si_unused = si; |
| 5071 | assign siclk_unused = siclk; |
| 5072 | assign soclk_unused = soclk; |
| 5073 | |
| 5074 | |
| 5075 | `ifdef INITLATZERO |
| 5076 | initial q = 1'b0; |
| 5077 | `endif |
| 5078 | |
| 5079 | always @(posedge l1clk) |
| 5080 | begin |
| 5081 | if (!siclk && !soclk) q <= d; |
| 5082 | else q <= 1'bx; |
| 5083 | end |
| 5084 | `endif |
| 5085 | |
| 5086 | assign so = q; |
| 5087 | |
| 5088 | endmodule // dff |
| 5089 | module cl_a1_msff_8x ( q, so, d, l1clk, si, siclk, soclk ); |
| 5090 | // RFM 05-14-2004 |
| 5091 | // Level sensitive in SCAN_MODE |
| 5092 | // Edge triggered when not in SCAN_MODE |
| 5093 | |
| 5094 | |
| 5095 | parameter SIZE = 1; |
| 5096 | |
| 5097 | output q; |
| 5098 | output so; |
| 5099 | |
| 5100 | input d; |
| 5101 | input l1clk; |
| 5102 | input si; |
| 5103 | input siclk; |
| 5104 | input soclk; |
| 5105 | |
| 5106 | reg q; |
| 5107 | wire so; |
| 5108 | wire l1clk, siclk, soclk; |
| 5109 | |
| 5110 | `ifdef SCAN_MODE |
| 5111 | reg l1; |
| 5112 | `ifdef FAST_FLUSH |
| 5113 | always @(posedge l1clk or posedge siclk ) begin |
| 5114 | if (siclk) begin |
| 5115 | q <= 1'b0; //pseudo flush reset |
| 5116 | end else begin |
| 5117 | q <= d; |
| 5118 | end |
| 5119 | end |
| 5120 | `else |
| 5121 | |
| 5122 | always @(l1clk or siclk or soclk or d or si) |
| 5123 | begin |
| 5124 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5125 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5126 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5127 | |
| 5128 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5129 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5130 | end |
| 5131 | `endif |
| 5132 | `else |
| 5133 | wire si_unused; |
| 5134 | wire siclk_unused; |
| 5135 | wire soclk_unused; |
| 5136 | assign si_unused = si; |
| 5137 | assign siclk_unused = siclk; |
| 5138 | assign soclk_unused = soclk; |
| 5139 | |
| 5140 | |
| 5141 | `ifdef INITLATZERO |
| 5142 | initial q = 1'b0; |
| 5143 | `endif |
| 5144 | |
| 5145 | always @(posedge l1clk) |
| 5146 | begin |
| 5147 | if (!siclk && !soclk) q <= d; |
| 5148 | else q <= 1'bx; |
| 5149 | end |
| 5150 | `endif |
| 5151 | |
| 5152 | assign so = q; |
| 5153 | |
| 5154 | endmodule // dff |
| 5155 | |
| 5156 | module cl_a1_msff_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 5157 | // RFM 05-14-2004 |
| 5158 | // Level sensitive in SCAN_MODE |
| 5159 | // Edge triggered when not in SCAN_MODE |
| 5160 | |
| 5161 | |
| 5162 | parameter SIZE = 1; |
| 5163 | |
| 5164 | output q; |
| 5165 | output so; |
| 5166 | |
| 5167 | input d; |
| 5168 | input l1clk; |
| 5169 | input si; |
| 5170 | input siclk; |
| 5171 | input soclk; |
| 5172 | input reset; |
| 5173 | reg q; |
| 5174 | wire so; |
| 5175 | wire l1clk, siclk, soclk; |
| 5176 | |
| 5177 | `ifdef SCAN_MODE |
| 5178 | reg l1; |
| 5179 | `ifdef FAST_FLUSH |
| 5180 | always @(l1clk or siclk or d ) // vcs optimized code |
| 5181 | begin |
| 5182 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5183 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 5184 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 5185 | l1 <= 1'b0; |
| 5186 | q <= 1'b0; |
| 5187 | end |
| 5188 | end |
| 5189 | `else |
| 5190 | always @(l1clk or siclk or soclk or d or si) |
| 5191 | begin |
| 5192 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5193 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5194 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5195 | |
| 5196 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5197 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5198 | end |
| 5199 | `endif |
| 5200 | `else |
| 5201 | wire si_unused; |
| 5202 | wire siclk_unused; |
| 5203 | wire soclk_unused; |
| 5204 | assign si_unused = si; |
| 5205 | assign siclk_unused = siclk; |
| 5206 | assign soclk_unused = soclk; |
| 5207 | |
| 5208 | |
| 5209 | `ifdef INITLATZERO |
| 5210 | initial q = 1'b0; |
| 5211 | `endif |
| 5212 | |
| 5213 | always @(posedge l1clk) |
| 5214 | begin |
| 5215 | if (!siclk && !soclk) q <= (d&reset); |
| 5216 | else q <= 1'bx; |
| 5217 | end |
| 5218 | `endif |
| 5219 | |
| 5220 | assign so = q; |
| 5221 | |
| 5222 | endmodule // dff |
| 5223 | module cl_a1_msff_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 5224 | // RFM 05-14-2004 |
| 5225 | // Level sensitive in SCAN_MODE |
| 5226 | // Edge triggered when not in SCAN_MODE |
| 5227 | |
| 5228 | |
| 5229 | parameter SIZE = 1; |
| 5230 | |
| 5231 | output q; |
| 5232 | output so; |
| 5233 | |
| 5234 | input d; |
| 5235 | input l1clk; |
| 5236 | input si; |
| 5237 | input siclk; |
| 5238 | input soclk; |
| 5239 | input reset; |
| 5240 | reg q; |
| 5241 | wire so; |
| 5242 | wire l1clk, siclk, soclk; |
| 5243 | |
| 5244 | `ifdef SCAN_MODE |
| 5245 | |
| 5246 | reg l1; |
| 5247 | `ifdef FAST_FLUSH |
| 5248 | always @(l1clk or siclk or d ) // vcs optimized code |
| 5249 | begin |
| 5250 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5251 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 5252 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 5253 | l1 <= 1'b0; |
| 5254 | q <= 1'b0; |
| 5255 | end |
| 5256 | end |
| 5257 | `else |
| 5258 | always @(l1clk or siclk or soclk or d or si) |
| 5259 | begin |
| 5260 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5261 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5262 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5263 | |
| 5264 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5265 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5266 | end |
| 5267 | `endif |
| 5268 | `else |
| 5269 | wire si_unused; |
| 5270 | wire siclk_unused; |
| 5271 | wire soclk_unused; |
| 5272 | assign si_unused = si; |
| 5273 | assign siclk_unused = siclk; |
| 5274 | assign soclk_unused = soclk; |
| 5275 | |
| 5276 | |
| 5277 | `ifdef INITLATZERO |
| 5278 | initial q = 1'b0; |
| 5279 | `endif |
| 5280 | |
| 5281 | always @(posedge l1clk) |
| 5282 | begin |
| 5283 | if (!siclk && !soclk) q <= (d&reset); |
| 5284 | else q <= 1'bx; |
| 5285 | end |
| 5286 | `endif |
| 5287 | |
| 5288 | assign so = q; |
| 5289 | |
| 5290 | endmodule // dff |
| 5291 | module cl_a1_msff_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 5292 | // RFM 05-14-2004 |
| 5293 | // Level sensitive in SCAN_MODE |
| 5294 | // Edge triggered when not in SCAN_MODE |
| 5295 | |
| 5296 | |
| 5297 | parameter SIZE = 1; |
| 5298 | |
| 5299 | output q; |
| 5300 | output so; |
| 5301 | |
| 5302 | input d; |
| 5303 | input l1clk; |
| 5304 | input si; |
| 5305 | input siclk; |
| 5306 | input soclk; |
| 5307 | input reset; |
| 5308 | reg q; |
| 5309 | wire so; |
| 5310 | wire l1clk, siclk, soclk; |
| 5311 | |
| 5312 | `ifdef SCAN_MODE |
| 5313 | |
| 5314 | reg l1; |
| 5315 | `ifdef FAST_FLUSH |
| 5316 | always @(l1clk or siclk or d ) // vcs optimized code |
| 5317 | begin |
| 5318 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5319 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 5320 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 5321 | l1 <= 1'b0; |
| 5322 | q <= 1'b0; |
| 5323 | end |
| 5324 | end |
| 5325 | `else |
| 5326 | always @(l1clk or siclk or soclk or d or si) |
| 5327 | begin |
| 5328 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5329 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5330 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5331 | |
| 5332 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5333 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5334 | end |
| 5335 | `endif |
| 5336 | `else |
| 5337 | wire si_unused; |
| 5338 | wire siclk_unused; |
| 5339 | wire soclk_unused; |
| 5340 | assign si_unused = si; |
| 5341 | assign siclk_unused = siclk; |
| 5342 | assign soclk_unused = soclk; |
| 5343 | |
| 5344 | |
| 5345 | `ifdef INITLATZERO |
| 5346 | initial q = 1'b0; |
| 5347 | `endif |
| 5348 | |
| 5349 | always @(posedge l1clk) |
| 5350 | begin |
| 5351 | if (!siclk && !soclk) q <= (d&reset); |
| 5352 | else q <= 1'bx; |
| 5353 | end |
| 5354 | `endif |
| 5355 | |
| 5356 | assign so = q; |
| 5357 | |
| 5358 | endmodule // dff |
| 5359 | module cl_a1_msff_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 5360 | // RFM 05-14-2004 |
| 5361 | // Level sensitive in SCAN_MODE |
| 5362 | // Edge triggered when not in SCAN_MODE |
| 5363 | |
| 5364 | |
| 5365 | parameter SIZE = 1; |
| 5366 | |
| 5367 | output q; |
| 5368 | output so; |
| 5369 | |
| 5370 | input d; |
| 5371 | input l1clk; |
| 5372 | input si; |
| 5373 | input siclk; |
| 5374 | input soclk; |
| 5375 | input reset; |
| 5376 | reg q; |
| 5377 | wire so; |
| 5378 | wire l1clk, siclk, soclk; |
| 5379 | |
| 5380 | `ifdef SCAN_MODE |
| 5381 | |
| 5382 | reg l1; |
| 5383 | `ifdef FAST_FLUSH |
| 5384 | always @(l1clk or siclk or d ) // vcs optimized code |
| 5385 | begin |
| 5386 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5387 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 5388 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 5389 | l1 <= 1'b0; |
| 5390 | q <= 1'b0; |
| 5391 | end |
| 5392 | end |
| 5393 | `else |
| 5394 | always @(l1clk or siclk or soclk or d or si) |
| 5395 | begin |
| 5396 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5397 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5398 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5399 | |
| 5400 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5401 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5402 | end |
| 5403 | `endif |
| 5404 | `else |
| 5405 | wire si_unused; |
| 5406 | wire siclk_unused; |
| 5407 | wire soclk_unused; |
| 5408 | assign si_unused = si; |
| 5409 | assign siclk_unused = siclk; |
| 5410 | assign soclk_unused = soclk; |
| 5411 | |
| 5412 | |
| 5413 | `ifdef INITLATZERO |
| 5414 | initial q = 1'b0; |
| 5415 | `endif |
| 5416 | |
| 5417 | always @(posedge l1clk) |
| 5418 | begin |
| 5419 | if (!siclk && !soclk) q <= (d&reset); |
| 5420 | else q <= 1'bx; |
| 5421 | end |
| 5422 | `endif |
| 5423 | |
| 5424 | assign so = q; |
| 5425 | |
| 5426 | endmodule // dff |
| 5427 | module cl_a1_msff_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); |
| 5428 | // RFM 05-14-2004 |
| 5429 | // Level sensitive in SCAN_MODE |
| 5430 | // Edge triggered when not in SCAN_MODE |
| 5431 | |
| 5432 | |
| 5433 | parameter SIZE = 1; |
| 5434 | |
| 5435 | output q; |
| 5436 | output so; |
| 5437 | |
| 5438 | input d; |
| 5439 | input l1clk; |
| 5440 | input si; |
| 5441 | input siclk; |
| 5442 | input soclk; |
| 5443 | input reset; |
| 5444 | reg q; |
| 5445 | wire so; |
| 5446 | wire l1clk, siclk, soclk; |
| 5447 | |
| 5448 | `ifdef SCAN_MODE |
| 5449 | |
| 5450 | reg l1; |
| 5451 | `ifdef FAST_FLUSH |
| 5452 | always @(l1clk or siclk or d ) // vcs optimized code |
| 5453 | begin |
| 5454 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5455 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data |
| 5456 | else if ( l1clk && siclk) begin // Conflict between data and scan |
| 5457 | l1 <= 1'b0; |
| 5458 | q <= 1'b0; |
| 5459 | end |
| 5460 | end |
| 5461 | `else |
| 5462 | always @(l1clk or siclk or soclk or d or si) |
| 5463 | begin |
| 5464 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data |
| 5465 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5466 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5467 | |
| 5468 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5469 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5470 | end |
| 5471 | `endif |
| 5472 | `else |
| 5473 | wire si_unused; |
| 5474 | wire siclk_unused; |
| 5475 | wire soclk_unused; |
| 5476 | assign si_unused = si; |
| 5477 | assign siclk_unused = siclk; |
| 5478 | assign soclk_unused = soclk; |
| 5479 | |
| 5480 | |
| 5481 | `ifdef INITLATZERO |
| 5482 | initial q = 1'b0; |
| 5483 | `endif |
| 5484 | |
| 5485 | always @(posedge l1clk) |
| 5486 | begin |
| 5487 | if (!siclk && !soclk) q <= (d&reset); |
| 5488 | else q <= 1'bx; |
| 5489 | end |
| 5490 | `endif |
| 5491 | |
| 5492 | assign so = q; |
| 5493 | |
| 5494 | endmodule // dff |
| 5495 | |
| 5496 | |
| 5497 | module cl_a1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk ); |
| 5498 | // RFM 05-14-2004 |
| 5499 | // Level sensitive in SCAN_MODE |
| 5500 | // Edge triggered when not in SCAN_MODE |
| 5501 | |
| 5502 | |
| 5503 | parameter SIZE = 1; |
| 5504 | |
| 5505 | output q_l; |
| 5506 | output so; |
| 5507 | |
| 5508 | input d; |
| 5509 | input l1clk; |
| 5510 | input si; |
| 5511 | input siclk; |
| 5512 | input soclk; |
| 5513 | |
| 5514 | reg q_l; |
| 5515 | reg q; |
| 5516 | wire so; |
| 5517 | wire l1clk, siclk, soclk; |
| 5518 | |
| 5519 | `ifdef SCAN_MODE |
| 5520 | reg l1; |
| 5521 | `ifdef FAST_FLUSH |
| 5522 | always @(posedge l1clk or posedge siclk ) begin |
| 5523 | if (siclk) begin |
| 5524 | q <= 1'b0; //pseudo flush reset |
| 5525 | end else begin |
| 5526 | q <= d; |
| 5527 | end |
| 5528 | end |
| 5529 | `else |
| 5530 | |
| 5531 | always @(l1clk or siclk or soclk or d or si) |
| 5532 | begin |
| 5533 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5534 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5535 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5536 | |
| 5537 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5538 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5539 | end |
| 5540 | `endif |
| 5541 | `else |
| 5542 | wire si_unused; |
| 5543 | wire siclk_unused; |
| 5544 | wire soclk_unused; |
| 5545 | assign si_unused = si; |
| 5546 | assign siclk_unused = siclk; |
| 5547 | assign soclk_unused = soclk; |
| 5548 | |
| 5549 | |
| 5550 | `ifdef INITLATZERO |
| 5551 | initial q_l = 1'b1; |
| 5552 | initial q = 1'b0; |
| 5553 | `endif |
| 5554 | |
| 5555 | always @(posedge l1clk) |
| 5556 | begin |
| 5557 | if (!siclk && !soclk) q <= d; |
| 5558 | else q <= 1'bx; |
| 5559 | end |
| 5560 | `endif |
| 5561 | |
| 5562 | |
| 5563 | always @ (q) |
| 5564 | begin |
| 5565 | q_l=~q; |
| 5566 | end |
| 5567 | |
| 5568 | |
| 5569 | |
| 5570 | assign so = q; |
| 5571 | |
| 5572 | endmodule // dff |
| 5573 | |
| 5574 | module cl_a1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk ); |
| 5575 | // RFM 05-14-2004 |
| 5576 | // Level sensitive in SCAN_MODE |
| 5577 | // Edge triggered when not in SCAN_MODE |
| 5578 | |
| 5579 | |
| 5580 | parameter SIZE = 1; |
| 5581 | |
| 5582 | output q_l; |
| 5583 | output so; |
| 5584 | |
| 5585 | input d; |
| 5586 | input l1clk; |
| 5587 | input si; |
| 5588 | input siclk; |
| 5589 | input soclk; |
| 5590 | |
| 5591 | reg q_l; |
| 5592 | reg q; |
| 5593 | wire so; |
| 5594 | wire l1clk, siclk, soclk; |
| 5595 | |
| 5596 | `ifdef SCAN_MODE |
| 5597 | |
| 5598 | reg l1; |
| 5599 | `ifdef FAST_FLUSH |
| 5600 | always @(posedge l1clk or posedge siclk ) begin |
| 5601 | if (siclk) begin |
| 5602 | q <= 1'b0; //pseudo flush reset |
| 5603 | end else begin |
| 5604 | q <= d; |
| 5605 | end |
| 5606 | end |
| 5607 | `else |
| 5608 | always @(l1clk or siclk or soclk or d or si) |
| 5609 | begin |
| 5610 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5611 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5612 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5613 | |
| 5614 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5615 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5616 | end |
| 5617 | `endif |
| 5618 | `else |
| 5619 | wire si_unused; |
| 5620 | wire siclk_unused; |
| 5621 | wire soclk_unused; |
| 5622 | assign si_unused = si; |
| 5623 | assign siclk_unused = siclk; |
| 5624 | assign soclk_unused = soclk; |
| 5625 | |
| 5626 | |
| 5627 | `ifdef INITLATZERO |
| 5628 | initial q_l = 1'b1; |
| 5629 | initial q = 1'b0; |
| 5630 | `endif |
| 5631 | |
| 5632 | always @(posedge l1clk) |
| 5633 | begin |
| 5634 | if (!siclk && !soclk) q <= d; |
| 5635 | else q <= 1'bx; |
| 5636 | end |
| 5637 | `endif |
| 5638 | |
| 5639 | |
| 5640 | always @ (q) |
| 5641 | begin |
| 5642 | q_l=~q; |
| 5643 | end |
| 5644 | |
| 5645 | |
| 5646 | |
| 5647 | assign so = q; |
| 5648 | |
| 5649 | endmodule // dff |
| 5650 | |
| 5651 | |
| 5652 | module cl_a1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk ); |
| 5653 | // RFM 05-14-2004 |
| 5654 | // Level sensitive in SCAN_MODE |
| 5655 | // Edge triggered when not in SCAN_MODE |
| 5656 | |
| 5657 | |
| 5658 | parameter SIZE = 1; |
| 5659 | |
| 5660 | output q_l; |
| 5661 | output so; |
| 5662 | |
| 5663 | input d; |
| 5664 | input l1clk; |
| 5665 | input si; |
| 5666 | input siclk; |
| 5667 | input soclk; |
| 5668 | |
| 5669 | reg q_l; |
| 5670 | reg q; |
| 5671 | wire so; |
| 5672 | wire l1clk, siclk, soclk; |
| 5673 | |
| 5674 | `ifdef SCAN_MODE |
| 5675 | reg l1; |
| 5676 | `ifdef FAST_FLUSH |
| 5677 | always @(posedge l1clk or posedge siclk ) begin |
| 5678 | if (siclk) begin |
| 5679 | q <= 1'b0; //pseudo flush reset |
| 5680 | end else begin |
| 5681 | q <= d; |
| 5682 | end |
| 5683 | end |
| 5684 | `else |
| 5685 | |
| 5686 | always @(l1clk or siclk or soclk or d or si) |
| 5687 | begin |
| 5688 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5689 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5690 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5691 | |
| 5692 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5693 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5694 | end |
| 5695 | `endif |
| 5696 | `else |
| 5697 | wire si_unused; |
| 5698 | wire siclk_unused; |
| 5699 | wire soclk_unused; |
| 5700 | assign si_unused = si; |
| 5701 | assign siclk_unused = siclk; |
| 5702 | assign soclk_unused = soclk; |
| 5703 | |
| 5704 | |
| 5705 | `ifdef INITLATZERO |
| 5706 | initial q_l = 1'b1; |
| 5707 | initial q = 1'b0; |
| 5708 | `endif |
| 5709 | |
| 5710 | always @(posedge l1clk) |
| 5711 | begin |
| 5712 | if (!siclk && !soclk) q <= d; |
| 5713 | else q <= 1'bx; |
| 5714 | end |
| 5715 | `endif |
| 5716 | |
| 5717 | |
| 5718 | always @ (q) |
| 5719 | begin |
| 5720 | q_l=~q; |
| 5721 | end |
| 5722 | |
| 5723 | |
| 5724 | |
| 5725 | assign so = q; |
| 5726 | |
| 5727 | endmodule // dff |
| 5728 | |
| 5729 | |
| 5730 | module cl_a1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk ); |
| 5731 | // RFM 05-14-2004 |
| 5732 | // Level sensitive in SCAN_MODE |
| 5733 | // Edge triggered when not in SCAN_MODE |
| 5734 | |
| 5735 | |
| 5736 | parameter SIZE = 1; |
| 5737 | |
| 5738 | output q_l; |
| 5739 | output so; |
| 5740 | |
| 5741 | input d; |
| 5742 | input l1clk; |
| 5743 | input si; |
| 5744 | input siclk; |
| 5745 | input soclk; |
| 5746 | |
| 5747 | reg q_l; |
| 5748 | reg q; |
| 5749 | wire so; |
| 5750 | wire l1clk, siclk, soclk; |
| 5751 | |
| 5752 | `ifdef SCAN_MODE |
| 5753 | reg l1; |
| 5754 | `ifdef FAST_FLUSH |
| 5755 | always @(posedge l1clk or posedge siclk ) begin |
| 5756 | if (siclk) begin |
| 5757 | q <= 1'b0; //pseudo flush reset |
| 5758 | end else begin |
| 5759 | q <= d; |
| 5760 | end |
| 5761 | end |
| 5762 | `else |
| 5763 | |
| 5764 | always @(l1clk or siclk or soclk or d or si) |
| 5765 | begin |
| 5766 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5767 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5768 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5769 | |
| 5770 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5771 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5772 | end |
| 5773 | `endif |
| 5774 | `else |
| 5775 | wire si_unused; |
| 5776 | wire siclk_unused; |
| 5777 | wire soclk_unused; |
| 5778 | assign si_unused = si; |
| 5779 | assign siclk_unused = siclk; |
| 5780 | assign soclk_unused = soclk; |
| 5781 | |
| 5782 | |
| 5783 | `ifdef INITLATZERO |
| 5784 | initial q_l = 1'b1; |
| 5785 | initial q = 1'b0; |
| 5786 | `endif |
| 5787 | |
| 5788 | always @(posedge l1clk) |
| 5789 | begin |
| 5790 | if (!siclk && !soclk) q <= d; |
| 5791 | else q <= 1'bx; |
| 5792 | end |
| 5793 | `endif |
| 5794 | |
| 5795 | |
| 5796 | always @ (q) |
| 5797 | begin |
| 5798 | q_l=~q; |
| 5799 | end |
| 5800 | |
| 5801 | |
| 5802 | |
| 5803 | assign so = q; |
| 5804 | |
| 5805 | endmodule // dff |
| 5806 | |
| 5807 | module cl_a1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk ); |
| 5808 | // RFM 05-14-2004 |
| 5809 | // Level sensitive in SCAN_MODE |
| 5810 | // Edge triggered when not in SCAN_MODE |
| 5811 | |
| 5812 | |
| 5813 | parameter SIZE = 1; |
| 5814 | |
| 5815 | output q_l; |
| 5816 | output so; |
| 5817 | |
| 5818 | input d; |
| 5819 | input l1clk; |
| 5820 | input si; |
| 5821 | input siclk; |
| 5822 | input soclk; |
| 5823 | |
| 5824 | reg q_l; |
| 5825 | reg q; |
| 5826 | wire so; |
| 5827 | wire l1clk, siclk, soclk; |
| 5828 | |
| 5829 | `ifdef SCAN_MODE |
| 5830 | reg l1; |
| 5831 | `ifdef FAST_FLUSH |
| 5832 | always @(posedge l1clk or posedge siclk ) begin |
| 5833 | if (siclk) begin |
| 5834 | q <= 1'b0; //pseudo flush reset |
| 5835 | end else begin |
| 5836 | q <= d; |
| 5837 | end |
| 5838 | end |
| 5839 | `else |
| 5840 | |
| 5841 | always @(l1clk or siclk or soclk or d or si) |
| 5842 | begin |
| 5843 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5844 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5845 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5846 | |
| 5847 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data |
| 5848 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 5849 | end |
| 5850 | `endif |
| 5851 | `else |
| 5852 | wire si_unused; |
| 5853 | wire siclk_unused; |
| 5854 | wire soclk_unused; |
| 5855 | assign si_unused = si; |
| 5856 | assign siclk_unused = siclk; |
| 5857 | assign soclk_unused = soclk; |
| 5858 | |
| 5859 | |
| 5860 | `ifdef INITLATZERO |
| 5861 | initial q_l = 1'b1; |
| 5862 | initial q = 1'b0; |
| 5863 | `endif |
| 5864 | |
| 5865 | always @(posedge l1clk) |
| 5866 | begin |
| 5867 | if (!siclk && !soclk) q <= d; |
| 5868 | else q <= 1'bx; |
| 5869 | end |
| 5870 | `endif |
| 5871 | |
| 5872 | |
| 5873 | always @ (q) |
| 5874 | begin |
| 5875 | q_l=~q; |
| 5876 | end |
| 5877 | |
| 5878 | |
| 5879 | |
| 5880 | assign so = q; |
| 5881 | |
| 5882 | endmodule // dff |
| 5883 | |
| 5884 | |
| 5885 | |
| 5886 | |
| 5887 | |
| 5888 | |
| 5889 | module cl_a1_msffjtag_4x ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk ); |
| 5890 | |
| 5891 | output q; |
| 5892 | output so; |
| 5893 | |
| 5894 | input d; |
| 5895 | input l1clk; |
| 5896 | input si; |
| 5897 | input siclk; |
| 5898 | input soclk; |
| 5899 | input reset; |
| 5900 | input updateclk; |
| 5901 | `ifdef LIB |
| 5902 | reg q; |
| 5903 | reg so; |
| 5904 | wire l1clk, siclk, soclk, updateclk; |
| 5905 | |
| 5906 | reg l1; |
| 5907 | |
| 5908 | always @(l1clk or siclk or soclk or d or si or reset) |
| 5909 | begin |
| 5910 | if (!l1clk && !siclk) l1 <= d; // Load master with data |
| 5911 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush |
| 5912 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan |
| 5913 | if (reset) so <=1'b0; |
| 5914 | if ( l1clk && !siclk && !soclk && !reset) so <= l1; // Load slave with master data |
| 5915 | if ( l1clk && siclk && !soclk && !reset) so <= si; // Flush |
| 5916 | end |
| 5917 | |
| 5918 | `ifdef INITLATZERO |
| 5919 | initial q = 1'b0; |
| 5920 | `endif |
| 5921 | |
| 5922 | |
| 5923 | |
| 5924 | always@(updateclk or reset or l1) |
| 5925 | begin |
| 5926 | if(reset) q <=1'b0; |
| 5927 | else if(updateclk) q <=l1; |
| 5928 | |
| 5929 | |
| 5930 | |
| 5931 | end |
| 5932 | `endif |
| 5933 | endmodule |
| 5934 | |
| 5935 | |
| 5936 | |
| 5937 | |
| 5938 | module cl_a1_clksyncff_4x(l1clk, d, si, siclk, soclk, q, so); |
| 5939 | input l1clk, d, si, siclk, soclk; |
| 5940 | output q, so; |
| 5941 | wire q1o, slo; |
| 5942 | |
| 5943 | cl_a1_msff_4x xx0 ( .l1clk(l1clk), .d(d), .si(si), .siclk(siclk), .soclk(soclk), .q(q1o), .so(slo)); |
| 5944 | cl_a1_msff_4x xx1 ( .l1clk(l1clk), .d(q1o), .si(slo), .siclk(siclk), .soclk(soclk), .q(q), .so(so)); |
| 5945 | endmodule |
| 5946 | module cl_a1_bs_cell2_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, mode, |
| 5947 | muxd, highz_n); |
| 5948 | |
| 5949 | output q; |
| 5950 | output so; |
| 5951 | |
| 5952 | input d, highz_n; |
| 5953 | input l1clk; |
| 5954 | input si; |
| 5955 | input siclk; |
| 5956 | input soclk; |
| 5957 | |
| 5958 | input updateclk, mode, muxd; |
| 5959 | |
| 5960 | reg q; |
| 5961 | reg so; |
| 5962 | wire l1clk, siclk, soclk, updateclk; |
| 5963 | |
| 5964 | |
| 5965 | reg l1, qm; |
| 5966 | |
| 5967 | always @(l1clk or siclk or soclk or d or si) |
| 5968 | begin |
| 5969 | if (!l1clk && !siclk) l1 <= d; |
| 5970 | if ( l1clk && siclk) l1 <= si; |
| 5971 | if (!l1clk && siclk) l1 <= 1'bx; |
| 5972 | if ( l1clk && !soclk) so <= l1; |
| 5973 | if ( l1clk && siclk && !soclk) so <= si; // Flush |
| 5974 | end |
| 5975 | `ifdef INITLATZERO |
| 5976 | initial qm = 1'b0; |
| 5977 | `endif |
| 5978 | always@(updateclk or l1) |
| 5979 | begin |
| 5980 | if(updateclk) qm <=l1; |
| 5981 | end |
| 5982 | always@(mode or muxd or qm or highz_n) |
| 5983 | begin |
| 5984 | if(mode==0) q=(qm && highz_n); |
| 5985 | else q=muxd; |
| 5986 | end |
| 5987 | endmodule |
| 5988 | |
| 5989 | module cl_a1_clk_buf_16x ( |
| 5990 | in, |
| 5991 | out |
| 5992 | ); |
| 5993 | input in; |
| 5994 | output out; |
| 5995 | |
| 5996 | `ifdef LIB |
| 5997 | //assign out = in; |
| 5998 | buf (out, in); |
| 5999 | `endif |
| 6000 | |
| 6001 | endmodule |
| 6002 | module cl_a1_clk_buf_20x ( |
| 6003 | in, |
| 6004 | out |
| 6005 | ); |
| 6006 | input in; |
| 6007 | output out; |
| 6008 | |
| 6009 | `ifdef LIB |
| 6010 | //assign out = in; |
| 6011 | buf (out, in); |
| 6012 | `endif |
| 6013 | |
| 6014 | endmodule |
| 6015 | module cl_a1_clk_buf_24x ( |
| 6016 | in, |
| 6017 | out |
| 6018 | ); |
| 6019 | input in; |
| 6020 | output out; |
| 6021 | |
| 6022 | `ifdef LIB |
| 6023 | //assign out = in; |
| 6024 | buf (out, in); |
| 6025 | `endif |
| 6026 | |
| 6027 | endmodule |
| 6028 | module cl_a1_clk_buf_32x ( |
| 6029 | in, |
| 6030 | out |
| 6031 | ); |
| 6032 | input in; |
| 6033 | output out; |
| 6034 | |
| 6035 | `ifdef LIB |
| 6036 | //assign out = in; |
| 6037 | buf (out, in); |
| 6038 | `endif |
| 6039 | |
| 6040 | endmodule |
| 6041 | module cl_a1_clk_buf_48x ( |
| 6042 | in, |
| 6043 | out |
| 6044 | ); |
| 6045 | input in; |
| 6046 | output out; |
| 6047 | |
| 6048 | `ifdef LIB |
| 6049 | //assign out = in; |
| 6050 | buf (out, in); |
| 6051 | `endif |
| 6052 | |
| 6053 | endmodule |
| 6054 | module cl_a1_clk_buf_64x ( |
| 6055 | in, |
| 6056 | out |
| 6057 | ); |
| 6058 | input in; |
| 6059 | output out; |
| 6060 | |
| 6061 | `ifdef LIB |
| 6062 | //assign out = in; |
| 6063 | buf (out, in); |
| 6064 | `endif |
| 6065 | |
| 6066 | endmodule |
| 6067 | module cl_a1_clk_buf_8x ( |
| 6068 | in, |
| 6069 | out |
| 6070 | ); |
| 6071 | input in; |
| 6072 | output out; |
| 6073 | |
| 6074 | `ifdef LIB |
| 6075 | //assign out = in; |
| 6076 | buf (out, in); |
| 6077 | `endif |
| 6078 | |
| 6079 | endmodule |
| 6080 | module cl_a1_clk_inv_16x ( |
| 6081 | in, |
| 6082 | out |
| 6083 | ); |
| 6084 | input in; |
| 6085 | output out; |
| 6086 | |
| 6087 | `ifdef LIB |
| 6088 | //assign out = ~in; |
| 6089 | not (out, in); |
| 6090 | `endif |
| 6091 | |
| 6092 | endmodule |
| 6093 | module cl_a1_clk_inv_20x ( |
| 6094 | clkin, |
| 6095 | clkout |
| 6096 | ); |
| 6097 | input clkin; |
| 6098 | output clkout; |
| 6099 | |
| 6100 | `ifdef LIB |
| 6101 | //assign clkout = ~clkin; |
| 6102 | not (clkout, clkin); |
| 6103 | `endif |
| 6104 | |
| 6105 | endmodule |
| 6106 | module cl_a1_clk_inv_24x ( |
| 6107 | in, |
| 6108 | out |
| 6109 | ); |
| 6110 | input in; |
| 6111 | output out; |
| 6112 | |
| 6113 | `ifdef LIB |
| 6114 | //assign out = ~in; |
| 6115 | not (out, in); |
| 6116 | `endif |
| 6117 | |
| 6118 | endmodule |
| 6119 | module cl_a1_clk_inv_32x ( |
| 6120 | in, |
| 6121 | out |
| 6122 | ); |
| 6123 | input in; |
| 6124 | output out; |
| 6125 | |
| 6126 | `ifdef LIB |
| 6127 | //assign out = ~in; |
| 6128 | not (out, in); |
| 6129 | `endif |
| 6130 | |
| 6131 | endmodule |
| 6132 | module cl_a1_clk_inv_48x ( |
| 6133 | in, |
| 6134 | out |
| 6135 | ); |
| 6136 | input in; |
| 6137 | output out; |
| 6138 | |
| 6139 | `ifdef LIB |
| 6140 | //assign out = ~in; |
| 6141 | not (out, in); |
| 6142 | `endif |
| 6143 | |
| 6144 | endmodule |
| 6145 | module cl_a1_clk_inv_64x ( |
| 6146 | in, |
| 6147 | out |
| 6148 | ); |
| 6149 | input in; |
| 6150 | output out; |
| 6151 | |
| 6152 | `ifdef LIB |
| 6153 | //assign out = ~in; |
| 6154 | not (out, in); |
| 6155 | `endif |
| 6156 | |
| 6157 | endmodule |
| 6158 | module cl_a1_clk_inv_8x ( |
| 6159 | clkin, |
| 6160 | clkout |
| 6161 | ); |
| 6162 | input clkin; |
| 6163 | output clkout; |
| 6164 | |
| 6165 | `ifdef LIB |
| 6166 | //assign clkout = ~clkin; |
| 6167 | not (clkout, clkin); |
| 6168 | `endif |
| 6169 | |
| 6170 | endmodule |
| 6171 | module cl_a1_clk_mux2_16x ( |
| 6172 | in0, |
| 6173 | in1, |
| 6174 | sel0, |
| 6175 | out |
| 6176 | ); |
| 6177 | input in0; |
| 6178 | input in1; |
| 6179 | input sel0; |
| 6180 | output out; |
| 6181 | |
| 6182 | `ifdef LIB |
| 6183 | reg out; |
| 6184 | always @ ( sel0 or in0 or in1) |
| 6185 | case ( sel0 ) |
| 6186 | 1'b1: out = in0; |
| 6187 | 1'b0: out = in1; |
| 6188 | |
| 6189 | default: out = 1'bx; |
| 6190 | |
| 6191 | endcase |
| 6192 | `endif |
| 6193 | |
| 6194 | endmodule |
| 6195 | |
| 6196 | module cl_a1_clk_mux2_24x ( |
| 6197 | in0, |
| 6198 | in1, |
| 6199 | sel0, |
| 6200 | out |
| 6201 | ); |
| 6202 | input in0; |
| 6203 | input in1; |
| 6204 | input sel0; |
| 6205 | output out; |
| 6206 | |
| 6207 | `ifdef LIB |
| 6208 | reg out; |
| 6209 | always @ ( sel0 or in0 or in1) |
| 6210 | case ( sel0 ) |
| 6211 | 1'b1: out = in0; |
| 6212 | 1'b0: out = in1; |
| 6213 | |
| 6214 | default: out = 1'bx; |
| 6215 | |
| 6216 | endcase |
| 6217 | `endif |
| 6218 | |
| 6219 | endmodule |
| 6220 | |
| 6221 | module cl_a1_clk_mux2_32x ( |
| 6222 | in0, |
| 6223 | in1, |
| 6224 | sel0, |
| 6225 | out |
| 6226 | ); |
| 6227 | input in0; |
| 6228 | input in1; |
| 6229 | input sel0; |
| 6230 | output out; |
| 6231 | |
| 6232 | `ifdef LIB |
| 6233 | reg out; |
| 6234 | always @ ( sel0 or in0 or in1) |
| 6235 | case ( sel0 ) |
| 6236 | 1'b1: out = in0; |
| 6237 | 1'b0: out = in1; |
| 6238 | |
| 6239 | default: out = 1'bx; |
| 6240 | |
| 6241 | endcase |
| 6242 | `endif |
| 6243 | |
| 6244 | endmodule |
| 6245 | |
| 6246 | module cl_a1_clk_mux2_8x ( |
| 6247 | in0, |
| 6248 | in1, |
| 6249 | sel0, |
| 6250 | out |
| 6251 | ); |
| 6252 | input in0; |
| 6253 | input in1; |
| 6254 | input sel0; |
| 6255 | output out; |
| 6256 | |
| 6257 | `ifdef LIB |
| 6258 | reg out; |
| 6259 | always @ ( sel0 or in0 or in1) |
| 6260 | case ( sel0 ) |
| 6261 | 1'b1: out = in0; |
| 6262 | 1'b0: out = in1; |
| 6263 | |
| 6264 | default: out = 1'bx; |
| 6265 | |
| 6266 | endcase |
| 6267 | `endif |
| 6268 | |
| 6269 | endmodule |
| 6270 | |
| 6271 | // -------------------------------------------------- |
| 6272 | // File: cl_a1_aoi12_12x.behV |
| 6273 | // Auto generated verilog module by HnBCellAuto |
| 6274 | // |
| 6275 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 6276 | // By: balmiki |
| 6277 | // -------------------------------------------------- |
| 6278 | // |
| 6279 | module cl_a1_aoi12_12x ( |
| 6280 | out, |
| 6281 | in10, |
| 6282 | in00, |
| 6283 | in01 ); |
| 6284 | |
| 6285 | output out; |
| 6286 | input in10; |
| 6287 | input in00; |
| 6288 | input in01; |
| 6289 | |
| 6290 | `ifdef LIB |
| 6291 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 6292 | `endif |
| 6293 | |
| 6294 | endmodule |
| 6295 | // -------------------------------------------------- |
| 6296 | // File: cl_a1_aoi12_16x.behV |
| 6297 | // Auto generated verilog module by HnBCellAuto |
| 6298 | // |
| 6299 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 6300 | // By: balmiki |
| 6301 | // -------------------------------------------------- |
| 6302 | // |
| 6303 | module cl_a1_aoi12_16x ( |
| 6304 | out, |
| 6305 | in10, |
| 6306 | in00, |
| 6307 | in01 ); |
| 6308 | |
| 6309 | output out; |
| 6310 | input in10; |
| 6311 | input in00; |
| 6312 | input in01; |
| 6313 | |
| 6314 | `ifdef LIB |
| 6315 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 6316 | `endif |
| 6317 | |
| 6318 | endmodule |
| 6319 | // -------------------------------------------------- |
| 6320 | // File: cl_a1_aoi12_1x.behV |
| 6321 | // Auto generated verilog module by HnBCellAuto |
| 6322 | // |
| 6323 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST |
| 6324 | // By: balmiki |
| 6325 | // -------------------------------------------------- |
| 6326 | // |
| 6327 | module cl_a1_aoi12_1x ( |
| 6328 | out, |
| 6329 | in10, |
| 6330 | in00, |
| 6331 | in01 ); |
| 6332 | |
| 6333 | output out; |
| 6334 | input in10; |
| 6335 | input in00; |
| 6336 | input in01; |
| 6337 | |
| 6338 | `ifdef LIB |
| 6339 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 6340 | `endif |
| 6341 | |
| 6342 | endmodule |
| 6343 | // -------------------------------------------------- |
| 6344 | // File: cl_a1_aoi12_2x.behV |
| 6345 | // Auto generated verilog module by HnBCellAuto |
| 6346 | // |
| 6347 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 6348 | // By: balmiki |
| 6349 | // -------------------------------------------------- |
| 6350 | // |
| 6351 | module cl_a1_aoi12_2x ( |
| 6352 | out, |
| 6353 | in10, |
| 6354 | in00, |
| 6355 | in01 ); |
| 6356 | |
| 6357 | output out; |
| 6358 | input in10; |
| 6359 | input in00; |
| 6360 | input in01; |
| 6361 | |
| 6362 | `ifdef LIB |
| 6363 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 6364 | `endif |
| 6365 | |
| 6366 | endmodule |
| 6367 | // -------------------------------------------------- |
| 6368 | // File: cl_a1_aoi12_4x.behV |
| 6369 | // Auto generated verilog module by HnBCellAuto |
| 6370 | // |
| 6371 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 6372 | // By: balmiki |
| 6373 | // -------------------------------------------------- |
| 6374 | // |
| 6375 | module cl_a1_aoi12_4x ( |
| 6376 | out, |
| 6377 | in10, |
| 6378 | in00, |
| 6379 | in01 ); |
| 6380 | |
| 6381 | output out; |
| 6382 | input in10; |
| 6383 | input in00; |
| 6384 | input in01; |
| 6385 | |
| 6386 | `ifdef LIB |
| 6387 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 6388 | `endif |
| 6389 | |
| 6390 | endmodule |
| 6391 | // -------------------------------------------------- |
| 6392 | // File: cl_a1_aoi12_8x.behV |
| 6393 | // Auto generated verilog module by HnBCellAuto |
| 6394 | // |
| 6395 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 6396 | // By: balmiki |
| 6397 | // -------------------------------------------------- |
| 6398 | // |
| 6399 | module cl_a1_aoi12_8x ( |
| 6400 | out, |
| 6401 | in10, |
| 6402 | in00, |
| 6403 | in01 ); |
| 6404 | |
| 6405 | output out; |
| 6406 | input in10; |
| 6407 | input in00; |
| 6408 | input in01; |
| 6409 | |
| 6410 | `ifdef LIB |
| 6411 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 6412 | `endif |
| 6413 | |
| 6414 | endmodule |
| 6415 | // -------------------------------------------------- |
| 6416 | // File: cl_a1_aoi21_12x.behV |
| 6417 | // Auto generated verilog module by HnBCellAuto |
| 6418 | // |
| 6419 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 6420 | // By: balmiki |
| 6421 | // -------------------------------------------------- |
| 6422 | // |
| 6423 | module cl_a1_aoi21_12x ( |
| 6424 | out, |
| 6425 | in10, |
| 6426 | in11, |
| 6427 | in00 ); |
| 6428 | |
| 6429 | output out; |
| 6430 | input in10; |
| 6431 | input in11; |
| 6432 | input in00; |
| 6433 | |
| 6434 | `ifdef LIB |
| 6435 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 6436 | `endif |
| 6437 | |
| 6438 | endmodule |
| 6439 | // -------------------------------------------------- |
| 6440 | // File: cl_a1_aoi21_16x.behV |
| 6441 | // Auto generated verilog module by HnBCellAuto |
| 6442 | // |
| 6443 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 6444 | // By: balmiki |
| 6445 | // -------------------------------------------------- |
| 6446 | // |
| 6447 | module cl_a1_aoi21_16x ( |
| 6448 | out, |
| 6449 | in10, |
| 6450 | in11, |
| 6451 | in00 ); |
| 6452 | |
| 6453 | output out; |
| 6454 | input in10; |
| 6455 | input in11; |
| 6456 | input in00; |
| 6457 | |
| 6458 | `ifdef LIB |
| 6459 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 6460 | `endif |
| 6461 | |
| 6462 | endmodule |
| 6463 | // -------------------------------------------------- |
| 6464 | // File: cl_a1_aoi21_1x.behV |
| 6465 | // Auto generated verilog module by HnBCellAuto |
| 6466 | // |
| 6467 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 6468 | // By: balmiki |
| 6469 | // -------------------------------------------------- |
| 6470 | // |
| 6471 | module cl_a1_aoi21_1x ( |
| 6472 | out, |
| 6473 | in10, |
| 6474 | in11, |
| 6475 | in00 ); |
| 6476 | |
| 6477 | output out; |
| 6478 | input in10; |
| 6479 | input in11; |
| 6480 | input in00; |
| 6481 | |
| 6482 | `ifdef LIB |
| 6483 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 6484 | `endif |
| 6485 | |
| 6486 | endmodule |
| 6487 | // -------------------------------------------------- |
| 6488 | // File: cl_a1_aoi21_2x.behV |
| 6489 | // Auto generated verilog module by HnBCellAuto |
| 6490 | // |
| 6491 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 6492 | // By: balmiki |
| 6493 | // -------------------------------------------------- |
| 6494 | // |
| 6495 | module cl_a1_aoi21_2x ( |
| 6496 | out, |
| 6497 | in10, |
| 6498 | in11, |
| 6499 | in00 ); |
| 6500 | |
| 6501 | output out; |
| 6502 | input in10; |
| 6503 | input in11; |
| 6504 | input in00; |
| 6505 | |
| 6506 | `ifdef LIB |
| 6507 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 6508 | `endif |
| 6509 | |
| 6510 | endmodule |
| 6511 | // -------------------------------------------------- |
| 6512 | // File: cl_a1_aoi21_4x.behV |
| 6513 | // Auto generated verilog module by HnBCellAuto |
| 6514 | // |
| 6515 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 6516 | // By: balmiki |
| 6517 | // -------------------------------------------------- |
| 6518 | // |
| 6519 | module cl_a1_aoi21_4x ( |
| 6520 | out, |
| 6521 | in10, |
| 6522 | in11, |
| 6523 | in00 ); |
| 6524 | |
| 6525 | output out; |
| 6526 | input in10; |
| 6527 | input in11; |
| 6528 | input in00; |
| 6529 | |
| 6530 | `ifdef LIB |
| 6531 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 6532 | `endif |
| 6533 | |
| 6534 | endmodule |
| 6535 | // -------------------------------------------------- |
| 6536 | // File: cl_a1_aoi21_8x.behV |
| 6537 | // Auto generated verilog module by HnBCellAuto |
| 6538 | // |
| 6539 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 6540 | // By: balmiki |
| 6541 | // -------------------------------------------------- |
| 6542 | // |
| 6543 | module cl_a1_aoi21_8x ( |
| 6544 | out, |
| 6545 | in10, |
| 6546 | in11, |
| 6547 | in00 ); |
| 6548 | |
| 6549 | output out; |
| 6550 | input in10; |
| 6551 | input in11; |
| 6552 | input in00; |
| 6553 | |
| 6554 | `ifdef LIB |
| 6555 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 6556 | `endif |
| 6557 | |
| 6558 | endmodule |
| 6559 | // -------------------------------------------------- |
| 6560 | // File: cl_a1_aoi22_12x.behV |
| 6561 | // Auto generated verilog module by HnBCellAuto |
| 6562 | // |
| 6563 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 6564 | // By: balmiki |
| 6565 | // -------------------------------------------------- |
| 6566 | // |
| 6567 | module cl_a1_aoi22_12x ( |
| 6568 | out, |
| 6569 | in10, |
| 6570 | in11, |
| 6571 | in00, |
| 6572 | in01 ); |
| 6573 | |
| 6574 | output out; |
| 6575 | input in10; |
| 6576 | input in11; |
| 6577 | input in00; |
| 6578 | input in01; |
| 6579 | |
| 6580 | `ifdef LIB |
| 6581 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 6582 | `endif |
| 6583 | |
| 6584 | endmodule |
| 6585 | |
| 6586 | // -------------------------------------------------- |
| 6587 | // File: cl_a1_aoi22_1x.behV |
| 6588 | // Auto generated verilog module by HnBCellAuto |
| 6589 | // |
| 6590 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT |
| 6591 | // By: balmiki |
| 6592 | // -------------------------------------------------- |
| 6593 | // |
| 6594 | module cl_a1_aoi22_1x ( |
| 6595 | out, |
| 6596 | in10, |
| 6597 | in11, |
| 6598 | in00, |
| 6599 | in01 ); |
| 6600 | |
| 6601 | output out; |
| 6602 | input in10; |
| 6603 | input in11; |
| 6604 | input in00; |
| 6605 | input in01; |
| 6606 | |
| 6607 | `ifdef LIB |
| 6608 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 6609 | `endif |
| 6610 | |
| 6611 | endmodule |
| 6612 | // -------------------------------------------------- |
| 6613 | // File: cl_a1_aoi22_2x.behV |
| 6614 | // Auto generated verilog module by HnBCellAuto |
| 6615 | // |
| 6616 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 6617 | // By: balmiki |
| 6618 | // -------------------------------------------------- |
| 6619 | // |
| 6620 | module cl_a1_aoi22_2x ( |
| 6621 | out, |
| 6622 | in10, |
| 6623 | in11, |
| 6624 | in00, |
| 6625 | in01 ); |
| 6626 | |
| 6627 | output out; |
| 6628 | input in10; |
| 6629 | input in11; |
| 6630 | input in00; |
| 6631 | input in01; |
| 6632 | |
| 6633 | `ifdef LIB |
| 6634 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 6635 | `endif |
| 6636 | |
| 6637 | endmodule |
| 6638 | // -------------------------------------------------- |
| 6639 | // File: cl_a1_aoi22_4x.behV |
| 6640 | // Auto generated verilog module by HnBCellAuto |
| 6641 | // |
| 6642 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 6643 | // By: balmiki |
| 6644 | // -------------------------------------------------- |
| 6645 | // |
| 6646 | module cl_a1_aoi22_4x ( |
| 6647 | out, |
| 6648 | in10, |
| 6649 | in11, |
| 6650 | in00, |
| 6651 | in01 ); |
| 6652 | |
| 6653 | output out; |
| 6654 | input in10; |
| 6655 | input in11; |
| 6656 | input in00; |
| 6657 | input in01; |
| 6658 | |
| 6659 | `ifdef LIB |
| 6660 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 6661 | `endif |
| 6662 | |
| 6663 | endmodule |
| 6664 | // -------------------------------------------------- |
| 6665 | // File: cl_a1_aoi22_8x.behV |
| 6666 | // Auto generated verilog module by HnBCellAuto |
| 6667 | // |
| 6668 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 6669 | // By: balmiki |
| 6670 | // -------------------------------------------------- |
| 6671 | // |
| 6672 | module cl_a1_aoi22_8x ( |
| 6673 | out, |
| 6674 | in10, |
| 6675 | in11, |
| 6676 | in00, |
| 6677 | in01 ); |
| 6678 | |
| 6679 | output out; |
| 6680 | input in10; |
| 6681 | input in11; |
| 6682 | input in00; |
| 6683 | input in01; |
| 6684 | |
| 6685 | `ifdef LIB |
| 6686 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 6687 | `endif |
| 6688 | |
| 6689 | endmodule |
| 6690 | |
| 6691 | |
| 6692 | // -------------------------------------------------- |
| 6693 | // File: cl_a1_aoi33_1x.behV |
| 6694 | // Auto generated verilog module by HnBCellAuto |
| 6695 | // |
| 6696 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST |
| 6697 | // By: balmiki |
| 6698 | // -------------------------------------------------- |
| 6699 | // |
| 6700 | module cl_a1_aoi33_1x ( |
| 6701 | out, |
| 6702 | in10, |
| 6703 | in11, |
| 6704 | in12, |
| 6705 | in00, |
| 6706 | in01, |
| 6707 | in02 ); |
| 6708 | |
| 6709 | output out; |
| 6710 | input in10; |
| 6711 | input in11; |
| 6712 | input in12; |
| 6713 | input in00; |
| 6714 | input in01; |
| 6715 | input in02; |
| 6716 | |
| 6717 | `ifdef LIB |
| 6718 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 6719 | `endif |
| 6720 | |
| 6721 | endmodule |
| 6722 | // -------------------------------------------------- |
| 6723 | // File: cl_a1_aoi33_2x.behV |
| 6724 | // Auto generated verilog module by HnBCellAuto |
| 6725 | // |
| 6726 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 6727 | // By: balmiki |
| 6728 | // -------------------------------------------------- |
| 6729 | // |
| 6730 | module cl_a1_aoi33_2x ( |
| 6731 | out, |
| 6732 | in10, |
| 6733 | in11, |
| 6734 | in12, |
| 6735 | in00, |
| 6736 | in01, |
| 6737 | in02 ); |
| 6738 | |
| 6739 | output out; |
| 6740 | input in10; |
| 6741 | input in11; |
| 6742 | input in12; |
| 6743 | input in00; |
| 6744 | input in01; |
| 6745 | input in02; |
| 6746 | |
| 6747 | `ifdef LIB |
| 6748 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 6749 | `endif |
| 6750 | |
| 6751 | endmodule |
| 6752 | // -------------------------------------------------- |
| 6753 | // File: cl_a1_aoi33_4x.behV |
| 6754 | // Auto generated verilog module by HnBCellAuto |
| 6755 | // |
| 6756 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 6757 | // By: balmiki |
| 6758 | // -------------------------------------------------- |
| 6759 | // |
| 6760 | module cl_a1_aoi33_4x ( |
| 6761 | out, |
| 6762 | in10, |
| 6763 | in11, |
| 6764 | in12, |
| 6765 | in00, |
| 6766 | in01, |
| 6767 | in02 ); |
| 6768 | |
| 6769 | output out; |
| 6770 | input in10; |
| 6771 | input in11; |
| 6772 | input in12; |
| 6773 | input in00; |
| 6774 | input in01; |
| 6775 | input in02; |
| 6776 | |
| 6777 | `ifdef LIB |
| 6778 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 6779 | `endif |
| 6780 | |
| 6781 | endmodule |
| 6782 | // -------------------------------------------------- |
| 6783 | // File: cl_a1_aoi33_8x.behV |
| 6784 | // Auto generated verilog module by HnBCellAuto |
| 6785 | // |
| 6786 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 6787 | // By: balmiki |
| 6788 | // -------------------------------------------------- |
| 6789 | // |
| 6790 | module cl_a1_aoi33_8x ( |
| 6791 | out, |
| 6792 | in10, |
| 6793 | in11, |
| 6794 | in12, |
| 6795 | in00, |
| 6796 | in01, |
| 6797 | in02 ); |
| 6798 | |
| 6799 | output out; |
| 6800 | input in10; |
| 6801 | input in11; |
| 6802 | input in12; |
| 6803 | input in00; |
| 6804 | input in01; |
| 6805 | input in02; |
| 6806 | |
| 6807 | `ifdef LIB |
| 6808 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 6809 | `endif |
| 6810 | |
| 6811 | endmodule |
| 6812 | module cl_a1_rep_32x ( |
| 6813 | in, |
| 6814 | out |
| 6815 | ); |
| 6816 | input in; |
| 6817 | output out; |
| 6818 | |
| 6819 | `ifdef LIB |
| 6820 | //assign out = in; |
| 6821 | buf (out, in); |
| 6822 | `endif |
| 6823 | |
| 6824 | endmodule |
| 6825 | module cl_a1_rep_40x ( |
| 6826 | in, |
| 6827 | out |
| 6828 | ); |
| 6829 | input in; |
| 6830 | output out; |
| 6831 | |
| 6832 | `ifdef LIB |
| 6833 | //assign out = in; |
| 6834 | buf (out, in); |
| 6835 | `endif |
| 6836 | |
| 6837 | endmodule |
| 6838 | module cl_a1_rep_24x ( |
| 6839 | in, |
| 6840 | out |
| 6841 | ); |
| 6842 | input in; |
| 6843 | output out; |
| 6844 | |
| 6845 | `ifdef LIB |
| 6846 | //assign out = in; |
| 6847 | buf (out, in); |
| 6848 | `endif |
| 6849 | |
| 6850 | endmodule |
| 6851 | module cl_a1_rep_16x ( |
| 6852 | in, |
| 6853 | out |
| 6854 | ); |
| 6855 | input in; |
| 6856 | output out; |
| 6857 | |
| 6858 | `ifdef LIB |
| 6859 | //assign out = in; |
| 6860 | buf (out, in); |
| 6861 | `endif |
| 6862 | |
| 6863 | endmodule |
| 6864 | module cl_a1_rep_8x ( |
| 6865 | in, |
| 6866 | out |
| 6867 | ); |
| 6868 | input in; |
| 6869 | output out; |
| 6870 | |
| 6871 | `ifdef LIB |
| 6872 | //assign out = in; |
| 6873 | buf (out, in); |
| 6874 | `endif |
| 6875 | |
| 6876 | endmodule |
| 6877 | module cl_a1_rep_48x ( |
| 6878 | in, |
| 6879 | out |
| 6880 | ); |
| 6881 | input in; |
| 6882 | output out; |
| 6883 | |
| 6884 | `ifdef LIB |
| 6885 | //assign out = in; |
| 6886 | buf (out, in); |
| 6887 | `endif |
| 6888 | |
| 6889 | endmodule |
| 6890 | module cl_a1_rep_dcp2x_32x ( |
| 6891 | in, |
| 6892 | out |
| 6893 | ); |
| 6894 | input in; |
| 6895 | output out; |
| 6896 | |
| 6897 | `ifdef LIB |
| 6898 | //assign out = in; |
| 6899 | buf (out, in); |
| 6900 | `endif |
| 6901 | |
| 6902 | endmodule |
| 6903 | |
| 6904 | module cl_a1_rep_dcp2x_16x ( |
| 6905 | in, |
| 6906 | out |
| 6907 | ); |
| 6908 | input in; |
| 6909 | output out; |
| 6910 | |
| 6911 | `ifdef LIB |
| 6912 | //assign out = in; |
| 6913 | buf (out, in); |
| 6914 | `endif |
| 6915 | |
| 6916 | endmodule |
| 6917 | module cl_a1_rep_dcp2x_24x ( |
| 6918 | in, |
| 6919 | out |
| 6920 | ); |
| 6921 | input in; |
| 6922 | output out; |
| 6923 | |
| 6924 | `ifdef LIB |
| 6925 | //assign out = in; |
| 6926 | buf (out, in); |
| 6927 | `endif |
| 6928 | |
| 6929 | endmodule |
| 6930 | module cl_a1_rep_dcp2x_40x ( |
| 6931 | in, |
| 6932 | out |
| 6933 | ); |
| 6934 | input in; |
| 6935 | output out; |
| 6936 | |
| 6937 | `ifdef LIB |
| 6938 | //assign out = in; |
| 6939 | buf (out, in); |
| 6940 | `endif |
| 6941 | |
| 6942 | endmodule |
| 6943 | module cl_a1_rep_dcp2x_48x ( |
| 6944 | in, |
| 6945 | out |
| 6946 | ); |
| 6947 | input in; |
| 6948 | output out; |
| 6949 | |
| 6950 | `ifdef LIB |
| 6951 | //assign out = in; |
| 6952 | buf (out, in); |
| 6953 | `endif |
| 6954 | |
| 6955 | endmodule |
| 6956 | module cl_a1_rep_dcp_32x ( |
| 6957 | in, |
| 6958 | out |
| 6959 | ); |
| 6960 | input in; |
| 6961 | output out; |
| 6962 | |
| 6963 | `ifdef LIB |
| 6964 | //assign out = in; |
| 6965 | buf (out, in); |
| 6966 | `endif |
| 6967 | |
| 6968 | endmodule |
| 6969 | |
| 6970 | module cl_a1_rep_dcp_16x ( |
| 6971 | in, |
| 6972 | out |
| 6973 | ); |
| 6974 | input in; |
| 6975 | output out; |
| 6976 | |
| 6977 | `ifdef LIB |
| 6978 | //assign out = in; |
| 6979 | buf (out, in); |
| 6980 | `endif |
| 6981 | |
| 6982 | endmodule |
| 6983 | module cl_a1_rep_dcp_24x ( |
| 6984 | in, |
| 6985 | out |
| 6986 | ); |
| 6987 | input in; |
| 6988 | output out; |
| 6989 | |
| 6990 | `ifdef LIB |
| 6991 | //assign out = in; |
| 6992 | buf (out, in); |
| 6993 | `endif |
| 6994 | |
| 6995 | endmodule |
| 6996 | module cl_a1_rep_dcp_40x ( |
| 6997 | in, |
| 6998 | out |
| 6999 | ); |
| 7000 | input in; |
| 7001 | output out; |
| 7002 | |
| 7003 | `ifdef LIB |
| 7004 | //assign out = in; |
| 7005 | buf (out, in); |
| 7006 | `endif |
| 7007 | |
| 7008 | endmodule |
| 7009 | module cl_a1_rep_dcp_48x ( |
| 7010 | in, |
| 7011 | out |
| 7012 | ); |
| 7013 | input in; |
| 7014 | output out; |
| 7015 | |
| 7016 | `ifdef LIB |
| 7017 | //assign out = in; |
| 7018 | buf (out, in); |
| 7019 | `endif |
| 7020 | |
| 7021 | endmodule |
| 7022 | module cl_a1_rep_dcp50k_48x ( |
| 7023 | in, |
| 7024 | out |
| 7025 | ); |
| 7026 | input in; |
| 7027 | output out; |
| 7028 | |
| 7029 | `ifdef LIB |
| 7030 | //assign out = in; |
| 7031 | buf (out, in); |
| 7032 | `endif |
| 7033 | |
| 7034 | endmodule |
| 7035 | module cl_a1_rep_dcp50k_32x ( |
| 7036 | in, |
| 7037 | out |
| 7038 | ); |
| 7039 | input in; |
| 7040 | output out; |
| 7041 | |
| 7042 | `ifdef LIB |
| 7043 | //assign out = in; |
| 7044 | buf (out, in); |
| 7045 | `endif |
| 7046 | |
| 7047 | endmodule |
| 7048 | module cl_a1_rep_dcp50k_40x ( |
| 7049 | in, |
| 7050 | out |
| 7051 | ); |
| 7052 | input in; |
| 7053 | output out; |
| 7054 | |
| 7055 | `ifdef LIB |
| 7056 | //assign out = in; |
| 7057 | buf (out, in); |
| 7058 | `endif |
| 7059 | |
| 7060 | endmodule |
| 7061 | |
| 7062 | module cl_a1_buf_12x ( |
| 7063 | in, |
| 7064 | out |
| 7065 | ); |
| 7066 | input in; |
| 7067 | output out; |
| 7068 | |
| 7069 | `ifdef LIB |
| 7070 | //assign out = in; |
| 7071 | buf (out, in); |
| 7072 | `endif |
| 7073 | |
| 7074 | endmodule |
| 7075 | module cl_a1_buf_16x ( |
| 7076 | in, |
| 7077 | out |
| 7078 | ); |
| 7079 | input in; |
| 7080 | output out; |
| 7081 | |
| 7082 | `ifdef LIB |
| 7083 | //assign out = in; |
| 7084 | buf (out, in); |
| 7085 | `endif |
| 7086 | |
| 7087 | endmodule |
| 7088 | module cl_a1_buf_1x ( |
| 7089 | in, |
| 7090 | out |
| 7091 | ); |
| 7092 | input in; |
| 7093 | output out; |
| 7094 | |
| 7095 | `ifdef LIB |
| 7096 | //assign out = in; |
| 7097 | buf (out, in); |
| 7098 | `endif |
| 7099 | |
| 7100 | endmodule |
| 7101 | module cl_a1_buf_20x ( |
| 7102 | in, |
| 7103 | out |
| 7104 | ); |
| 7105 | input in; |
| 7106 | output out; |
| 7107 | |
| 7108 | `ifdef LIB |
| 7109 | //assign out = in; |
| 7110 | buf (out, in); |
| 7111 | `endif |
| 7112 | |
| 7113 | endmodule |
| 7114 | module cl_a1_buf_24x ( |
| 7115 | in, |
| 7116 | out |
| 7117 | ); |
| 7118 | input in; |
| 7119 | output out; |
| 7120 | |
| 7121 | `ifdef LIB |
| 7122 | //assign out = in; |
| 7123 | buf (out, in); |
| 7124 | `endif |
| 7125 | |
| 7126 | endmodule |
| 7127 | module cl_a1_buf_28x ( |
| 7128 | in, |
| 7129 | out |
| 7130 | ); |
| 7131 | input in; |
| 7132 | output out; |
| 7133 | |
| 7134 | `ifdef LIB |
| 7135 | //assign out = in; |
| 7136 | buf (out, in); |
| 7137 | `endif |
| 7138 | |
| 7139 | endmodule |
| 7140 | module cl_a1_buf_2x ( |
| 7141 | in, |
| 7142 | out |
| 7143 | ); |
| 7144 | input in; |
| 7145 | output out; |
| 7146 | |
| 7147 | `ifdef LIB |
| 7148 | //assign out = in; |
| 7149 | buf (out, in); |
| 7150 | `endif |
| 7151 | |
| 7152 | endmodule |
| 7153 | module cl_a1_buf_32x ( |
| 7154 | in, |
| 7155 | out |
| 7156 | ); |
| 7157 | input in; |
| 7158 | output out; |
| 7159 | |
| 7160 | `ifdef LIB |
| 7161 | //assign out = in; |
| 7162 | buf (out, in); |
| 7163 | `endif |
| 7164 | |
| 7165 | endmodule |
| 7166 | module cl_a1_buf_36x ( |
| 7167 | in, |
| 7168 | out |
| 7169 | ); |
| 7170 | input in; |
| 7171 | output out; |
| 7172 | |
| 7173 | `ifdef LIB |
| 7174 | //assign out = in; |
| 7175 | buf (out, in); |
| 7176 | `endif |
| 7177 | |
| 7178 | endmodule |
| 7179 | module cl_a1_buf_40x ( |
| 7180 | in, |
| 7181 | out |
| 7182 | ); |
| 7183 | input in; |
| 7184 | output out; |
| 7185 | |
| 7186 | `ifdef LIB |
| 7187 | //assign out = in; |
| 7188 | buf (out, in); |
| 7189 | `endif |
| 7190 | |
| 7191 | endmodule |
| 7192 | module cl_a1_buf_44x ( |
| 7193 | in, |
| 7194 | out |
| 7195 | ); |
| 7196 | input in; |
| 7197 | output out; |
| 7198 | |
| 7199 | `ifdef LIB |
| 7200 | //assign out = in; |
| 7201 | buf (out, in); |
| 7202 | `endif |
| 7203 | |
| 7204 | endmodule |
| 7205 | module cl_a1_buf_48x ( |
| 7206 | in, |
| 7207 | out |
| 7208 | ); |
| 7209 | input in; |
| 7210 | output out; |
| 7211 | |
| 7212 | `ifdef LIB |
| 7213 | //assign out = in; |
| 7214 | buf (out, in); |
| 7215 | `endif |
| 7216 | |
| 7217 | endmodule |
| 7218 | module cl_a1_buf_4x ( |
| 7219 | in, |
| 7220 | out |
| 7221 | ); |
| 7222 | input in; |
| 7223 | output out; |
| 7224 | |
| 7225 | `ifdef LIB |
| 7226 | //assign out = in; |
| 7227 | buf (out, in); |
| 7228 | `endif |
| 7229 | |
| 7230 | endmodule |
| 7231 | module cl_a1_buf_56x ( |
| 7232 | in, |
| 7233 | out |
| 7234 | ); |
| 7235 | input in; |
| 7236 | output out; |
| 7237 | |
| 7238 | `ifdef LIB |
| 7239 | //assign out = in; |
| 7240 | buf (out, in); |
| 7241 | `endif |
| 7242 | |
| 7243 | endmodule |
| 7244 | module cl_a1_buf_64x ( |
| 7245 | in, |
| 7246 | out |
| 7247 | ); |
| 7248 | input in; |
| 7249 | output out; |
| 7250 | |
| 7251 | `ifdef LIB |
| 7252 | //assign out = in; |
| 7253 | buf (out, in); |
| 7254 | `endif |
| 7255 | |
| 7256 | endmodule |
| 7257 | module cl_a1_buf_6x ( |
| 7258 | in, |
| 7259 | out |
| 7260 | ); |
| 7261 | input in; |
| 7262 | output out; |
| 7263 | |
| 7264 | `ifdef LIB |
| 7265 | //assign out = in; |
| 7266 | buf (out, in); |
| 7267 | `endif |
| 7268 | |
| 7269 | endmodule |
| 7270 | module cl_a1_buf_8x ( |
| 7271 | in, |
| 7272 | out |
| 7273 | ); |
| 7274 | input in; |
| 7275 | output out; |
| 7276 | |
| 7277 | `ifdef LIB |
| 7278 | //assign out = in; |
| 7279 | buf (out, in); |
| 7280 | `endif |
| 7281 | |
| 7282 | endmodule |
| 7283 | module cl_a1_bufmin_1x ( |
| 7284 | in, |
| 7285 | out |
| 7286 | ); |
| 7287 | input in; |
| 7288 | output out; |
| 7289 | |
| 7290 | `ifdef LIB |
| 7291 | //assign out = in; |
| 7292 | buf (out, in); |
| 7293 | `endif |
| 7294 | |
| 7295 | endmodule |
| 7296 | module cl_a1_bufmin_4x ( |
| 7297 | in, |
| 7298 | out |
| 7299 | ); |
| 7300 | input in; |
| 7301 | output out; |
| 7302 | |
| 7303 | `ifdef LIB |
| 7304 | //assign out = in; |
| 7305 | buf (out, in); |
| 7306 | `endif |
| 7307 | |
| 7308 | endmodule |
| 7309 | module cl_a1_bufmin_8x ( |
| 7310 | in, |
| 7311 | out |
| 7312 | ); |
| 7313 | input in; |
| 7314 | output out; |
| 7315 | |
| 7316 | `ifdef LIB |
| 7317 | //assign out = in; |
| 7318 | buf (out, in); |
| 7319 | `endif |
| 7320 | |
| 7321 | endmodule |
| 7322 | module cl_a1_bufmin_16x ( |
| 7323 | in, |
| 7324 | out |
| 7325 | ); |
| 7326 | input in; |
| 7327 | output out; |
| 7328 | |
| 7329 | `ifdef LIB |
| 7330 | //assign out = in; |
| 7331 | buf (out, in); |
| 7332 | `endif |
| 7333 | |
| 7334 | endmodule |
| 7335 | module cl_a1_bufmin_32x ( |
| 7336 | in, |
| 7337 | out |
| 7338 | ); |
| 7339 | input in; |
| 7340 | output out; |
| 7341 | |
| 7342 | `ifdef LIB |
| 7343 | //assign out = in; |
| 7344 | buf (out, in); |
| 7345 | `endif |
| 7346 | |
| 7347 | endmodule |
| 7348 | module cl_a1_csa32_16x ( |
| 7349 | in0, |
| 7350 | in1, |
| 7351 | in2, |
| 7352 | carry, |
| 7353 | sum |
| 7354 | ); |
| 7355 | input in0; |
| 7356 | input in1; |
| 7357 | input in2; |
| 7358 | output carry; |
| 7359 | output sum; |
| 7360 | |
| 7361 | `ifdef LIB |
| 7362 | assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2); |
| 7363 | assign sum = (in0 ^ in1 ^ in2); |
| 7364 | `endif |
| 7365 | |
| 7366 | endmodule |
| 7367 | module cl_a1_csa32_4x ( |
| 7368 | in0, |
| 7369 | in1, |
| 7370 | in2, |
| 7371 | carry, |
| 7372 | sum |
| 7373 | ); |
| 7374 | input in0; |
| 7375 | input in1; |
| 7376 | input in2; |
| 7377 | output carry; |
| 7378 | output sum; |
| 7379 | |
| 7380 | `ifdef LIB |
| 7381 | assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2); |
| 7382 | assign sum = (in0 ^ in1 ^ in2); |
| 7383 | `endif |
| 7384 | |
| 7385 | endmodule |
| 7386 | |
| 7387 | module cl_a1_inv_12x ( |
| 7388 | in, |
| 7389 | out |
| 7390 | ); |
| 7391 | input in; |
| 7392 | output out; |
| 7393 | |
| 7394 | `ifdef LIB |
| 7395 | //assign out = ~in; |
| 7396 | not (out, in); |
| 7397 | `endif |
| 7398 | |
| 7399 | endmodule |
| 7400 | module cl_a1_inv_16x ( |
| 7401 | in, |
| 7402 | out |
| 7403 | ); |
| 7404 | input in; |
| 7405 | output out; |
| 7406 | |
| 7407 | `ifdef LIB |
| 7408 | //assign out = ~in; |
| 7409 | not (out, in); |
| 7410 | `endif |
| 7411 | |
| 7412 | endmodule |
| 7413 | module cl_a1_inv_1x ( |
| 7414 | in, |
| 7415 | out |
| 7416 | ); |
| 7417 | input in; |
| 7418 | output out; |
| 7419 | |
| 7420 | `ifdef LIB |
| 7421 | //assign out = ~in; |
| 7422 | not (out, in); |
| 7423 | `endif |
| 7424 | |
| 7425 | endmodule |
| 7426 | module cl_a1_inv_20x ( |
| 7427 | in, |
| 7428 | out |
| 7429 | ); |
| 7430 | input in; |
| 7431 | output out; |
| 7432 | |
| 7433 | `ifdef LIB |
| 7434 | //assign out = ~in; |
| 7435 | not (out, in); |
| 7436 | `endif |
| 7437 | |
| 7438 | endmodule |
| 7439 | module cl_a1_inv_24x ( |
| 7440 | in, |
| 7441 | out |
| 7442 | ); |
| 7443 | input in; |
| 7444 | output out; |
| 7445 | |
| 7446 | `ifdef LIB |
| 7447 | //assign out = ~in; |
| 7448 | not (out, in); |
| 7449 | `endif |
| 7450 | |
| 7451 | endmodule |
| 7452 | module cl_a1_inv_28x ( |
| 7453 | in, |
| 7454 | out |
| 7455 | ); |
| 7456 | input in; |
| 7457 | output out; |
| 7458 | |
| 7459 | `ifdef LIB |
| 7460 | //assign out = ~in; |
| 7461 | not (out, in); |
| 7462 | `endif |
| 7463 | |
| 7464 | endmodule |
| 7465 | module cl_a1_inv_2x ( |
| 7466 | in, |
| 7467 | out |
| 7468 | ); |
| 7469 | input in; |
| 7470 | output out; |
| 7471 | |
| 7472 | `ifdef LIB |
| 7473 | //assign out = ~in; |
| 7474 | not (out, in); |
| 7475 | `endif |
| 7476 | |
| 7477 | endmodule |
| 7478 | module cl_a1_inv_32x ( |
| 7479 | in, |
| 7480 | out |
| 7481 | ); |
| 7482 | input in; |
| 7483 | output out; |
| 7484 | |
| 7485 | `ifdef LIB |
| 7486 | //assign out = ~in; |
| 7487 | not (out, in); |
| 7488 | `endif |
| 7489 | |
| 7490 | endmodule |
| 7491 | module cl_a1_inv_36x ( |
| 7492 | in, |
| 7493 | out |
| 7494 | ); |
| 7495 | input in; |
| 7496 | output out; |
| 7497 | |
| 7498 | `ifdef LIB |
| 7499 | //assign out = ~in; |
| 7500 | not (out, in); |
| 7501 | `endif |
| 7502 | |
| 7503 | endmodule |
| 7504 | module cl_a1_inv_40x ( |
| 7505 | in, |
| 7506 | out |
| 7507 | ); |
| 7508 | input in; |
| 7509 | output out; |
| 7510 | |
| 7511 | `ifdef LIB |
| 7512 | //assign out = ~in; |
| 7513 | not (out, in); |
| 7514 | `endif |
| 7515 | |
| 7516 | endmodule |
| 7517 | module cl_a1_inv_44x ( |
| 7518 | in, |
| 7519 | out |
| 7520 | ); |
| 7521 | input in; |
| 7522 | output out; |
| 7523 | |
| 7524 | `ifdef LIB |
| 7525 | //assign out = ~in; |
| 7526 | not (out, in); |
| 7527 | `endif |
| 7528 | |
| 7529 | endmodule |
| 7530 | module cl_a1_inv_48x ( |
| 7531 | in, |
| 7532 | out |
| 7533 | ); |
| 7534 | input in; |
| 7535 | output out; |
| 7536 | |
| 7537 | `ifdef LIB |
| 7538 | //assign out = ~in; |
| 7539 | not (out, in); |
| 7540 | `endif |
| 7541 | |
| 7542 | endmodule |
| 7543 | module cl_a1_inv_4x ( |
| 7544 | in, |
| 7545 | out |
| 7546 | ); |
| 7547 | input in; |
| 7548 | output out; |
| 7549 | |
| 7550 | `ifdef LIB |
| 7551 | //assign out = ~in; |
| 7552 | not (out, in); |
| 7553 | `endif |
| 7554 | |
| 7555 | endmodule |
| 7556 | module cl_a1_inv_56x ( |
| 7557 | in, |
| 7558 | out |
| 7559 | ); |
| 7560 | input in; |
| 7561 | output out; |
| 7562 | |
| 7563 | `ifdef LIB |
| 7564 | //assign out = ~in; |
| 7565 | not (out, in); |
| 7566 | `endif |
| 7567 | |
| 7568 | endmodule |
| 7569 | module cl_a1_inv_64x ( |
| 7570 | in, |
| 7571 | out |
| 7572 | ); |
| 7573 | input in; |
| 7574 | output out; |
| 7575 | |
| 7576 | `ifdef LIB |
| 7577 | //assign out = ~in; |
| 7578 | not (out, in); |
| 7579 | `endif |
| 7580 | |
| 7581 | endmodule |
| 7582 | module cl_a1_inv_6x ( |
| 7583 | in, |
| 7584 | out |
| 7585 | ); |
| 7586 | input in; |
| 7587 | output out; |
| 7588 | |
| 7589 | `ifdef LIB |
| 7590 | //assign out = ~in; |
| 7591 | not (out, in); |
| 7592 | `endif |
| 7593 | |
| 7594 | endmodule |
| 7595 | module cl_a1_inv_8x ( |
| 7596 | in, |
| 7597 | out |
| 7598 | ); |
| 7599 | input in; |
| 7600 | output out; |
| 7601 | |
| 7602 | `ifdef LIB |
| 7603 | //assign out = ~in; |
| 7604 | not (out, in); |
| 7605 | `endif |
| 7606 | |
| 7607 | endmodule |
| 7608 | module cl_a1_nand2_12x ( |
| 7609 | in0, |
| 7610 | in1, |
| 7611 | out |
| 7612 | ); |
| 7613 | input in0; |
| 7614 | input in1; |
| 7615 | output out; |
| 7616 | |
| 7617 | `ifdef LIB |
| 7618 | assign out = ~(in0 & in1); |
| 7619 | `endif |
| 7620 | |
| 7621 | endmodule |
| 7622 | module cl_a1_nand2_16x ( |
| 7623 | in0, |
| 7624 | in1, |
| 7625 | out |
| 7626 | ); |
| 7627 | input in0; |
| 7628 | input in1; |
| 7629 | output out; |
| 7630 | |
| 7631 | `ifdef LIB |
| 7632 | assign out = ~(in0 & in1); |
| 7633 | `endif |
| 7634 | |
| 7635 | endmodule |
| 7636 | module cl_a1_nand2_1x ( |
| 7637 | in0, |
| 7638 | in1, |
| 7639 | out |
| 7640 | ); |
| 7641 | input in0; |
| 7642 | input in1; |
| 7643 | output out; |
| 7644 | |
| 7645 | `ifdef LIB |
| 7646 | assign out = ~(in0 & in1); |
| 7647 | `endif |
| 7648 | |
| 7649 | endmodule |
| 7650 | module cl_a1_nand2_20x ( |
| 7651 | in0, |
| 7652 | in1, |
| 7653 | out |
| 7654 | ); |
| 7655 | input in0; |
| 7656 | input in1; |
| 7657 | output out; |
| 7658 | |
| 7659 | `ifdef LIB |
| 7660 | assign out = ~(in0 & in1); |
| 7661 | `endif |
| 7662 | |
| 7663 | endmodule |
| 7664 | module cl_a1_nand2_24x ( |
| 7665 | in0, |
| 7666 | in1, |
| 7667 | out |
| 7668 | ); |
| 7669 | input in0; |
| 7670 | input in1; |
| 7671 | output out; |
| 7672 | |
| 7673 | `ifdef LIB |
| 7674 | assign out = ~(in0 & in1); |
| 7675 | `endif |
| 7676 | |
| 7677 | endmodule |
| 7678 | module cl_a1_nand2_28x ( |
| 7679 | in0, |
| 7680 | in1, |
| 7681 | out |
| 7682 | ); |
| 7683 | input in0; |
| 7684 | input in1; |
| 7685 | output out; |
| 7686 | |
| 7687 | `ifdef LIB |
| 7688 | assign out = ~(in0 & in1); |
| 7689 | `endif |
| 7690 | |
| 7691 | endmodule |
| 7692 | module cl_a1_nand2_2x ( |
| 7693 | in0, |
| 7694 | in1, |
| 7695 | out |
| 7696 | ); |
| 7697 | input in0; |
| 7698 | input in1; |
| 7699 | output out; |
| 7700 | |
| 7701 | `ifdef LIB |
| 7702 | assign out = ~(in0 & in1); |
| 7703 | `endif |
| 7704 | |
| 7705 | endmodule |
| 7706 | module cl_a1_nand2_32x ( |
| 7707 | in0, |
| 7708 | in1, |
| 7709 | out |
| 7710 | ); |
| 7711 | input in0; |
| 7712 | input in1; |
| 7713 | output out; |
| 7714 | |
| 7715 | `ifdef LIB |
| 7716 | assign out = ~(in0 & in1); |
| 7717 | `endif |
| 7718 | |
| 7719 | endmodule |
| 7720 | module cl_a1_nand2_4x ( |
| 7721 | in0, |
| 7722 | in1, |
| 7723 | out |
| 7724 | ); |
| 7725 | input in0; |
| 7726 | input in1; |
| 7727 | output out; |
| 7728 | |
| 7729 | `ifdef LIB |
| 7730 | assign out = ~(in0 & in1); |
| 7731 | `endif |
| 7732 | |
| 7733 | endmodule |
| 7734 | module cl_a1_nand2_6x ( |
| 7735 | in0, |
| 7736 | in1, |
| 7737 | out |
| 7738 | ); |
| 7739 | input in0; |
| 7740 | input in1; |
| 7741 | output out; |
| 7742 | |
| 7743 | `ifdef LIB |
| 7744 | assign out = ~(in0 & in1); |
| 7745 | `endif |
| 7746 | |
| 7747 | endmodule |
| 7748 | module cl_a1_nand2_8x ( |
| 7749 | in0, |
| 7750 | in1, |
| 7751 | out |
| 7752 | ); |
| 7753 | input in0; |
| 7754 | input in1; |
| 7755 | output out; |
| 7756 | |
| 7757 | `ifdef LIB |
| 7758 | assign out = ~(in0 & in1); |
| 7759 | `endif |
| 7760 | |
| 7761 | endmodule |
| 7762 | module cl_a1_nand3_12x ( |
| 7763 | in0, |
| 7764 | in1, |
| 7765 | in2, |
| 7766 | out |
| 7767 | ); |
| 7768 | input in0; |
| 7769 | input in1; |
| 7770 | input in2; |
| 7771 | output out; |
| 7772 | |
| 7773 | `ifdef LIB |
| 7774 | assign out = ~(in0 & in1 & in2); |
| 7775 | `endif |
| 7776 | |
| 7777 | endmodule |
| 7778 | module cl_a1_nand3_16x ( |
| 7779 | in0, |
| 7780 | in1, |
| 7781 | in2, |
| 7782 | out |
| 7783 | ); |
| 7784 | input in0; |
| 7785 | input in1; |
| 7786 | input in2; |
| 7787 | output out; |
| 7788 | |
| 7789 | `ifdef LIB |
| 7790 | assign out = ~(in0 & in1 & in2); |
| 7791 | `endif |
| 7792 | |
| 7793 | endmodule |
| 7794 | module cl_a1_nand3_1x ( |
| 7795 | in0, |
| 7796 | in1, |
| 7797 | in2, |
| 7798 | out |
| 7799 | ); |
| 7800 | input in0; |
| 7801 | input in1; |
| 7802 | input in2; |
| 7803 | output out; |
| 7804 | |
| 7805 | `ifdef LIB |
| 7806 | assign out = ~(in0 & in1 & in2); |
| 7807 | `endif |
| 7808 | |
| 7809 | endmodule |
| 7810 | module cl_a1_nand3_20x ( |
| 7811 | in0, |
| 7812 | in1, |
| 7813 | in2, |
| 7814 | out |
| 7815 | ); |
| 7816 | input in0; |
| 7817 | input in1; |
| 7818 | input in2; |
| 7819 | output out; |
| 7820 | |
| 7821 | `ifdef LIB |
| 7822 | assign out = ~(in0 & in1 & in2); |
| 7823 | `endif |
| 7824 | |
| 7825 | endmodule |
| 7826 | module cl_a1_nand3_24x ( |
| 7827 | in0, |
| 7828 | in1, |
| 7829 | in2, |
| 7830 | out |
| 7831 | ); |
| 7832 | input in0; |
| 7833 | input in1; |
| 7834 | input in2; |
| 7835 | output out; |
| 7836 | |
| 7837 | `ifdef LIB |
| 7838 | assign out = ~(in0 & in1 & in2); |
| 7839 | `endif |
| 7840 | |
| 7841 | endmodule |
| 7842 | |
| 7843 | module cl_a1_nand3_2x ( |
| 7844 | in0, |
| 7845 | in1, |
| 7846 | in2, |
| 7847 | out |
| 7848 | ); |
| 7849 | input in0; |
| 7850 | input in1; |
| 7851 | input in2; |
| 7852 | output out; |
| 7853 | |
| 7854 | `ifdef LIB |
| 7855 | assign out = ~(in0 & in1 & in2); |
| 7856 | `endif |
| 7857 | |
| 7858 | endmodule |
| 7859 | |
| 7860 | module cl_a1_nand3_4x ( |
| 7861 | in0, |
| 7862 | in1, |
| 7863 | in2, |
| 7864 | out |
| 7865 | ); |
| 7866 | input in0; |
| 7867 | input in1; |
| 7868 | input in2; |
| 7869 | output out; |
| 7870 | |
| 7871 | `ifdef LIB |
| 7872 | assign out = ~(in0 & in1 & in2); |
| 7873 | `endif |
| 7874 | |
| 7875 | endmodule |
| 7876 | module cl_a1_nand3_6x ( |
| 7877 | in0, |
| 7878 | in1, |
| 7879 | in2, |
| 7880 | out |
| 7881 | ); |
| 7882 | input in0; |
| 7883 | input in1; |
| 7884 | input in2; |
| 7885 | output out; |
| 7886 | |
| 7887 | `ifdef LIB |
| 7888 | assign out = ~(in0 & in1 & in2); |
| 7889 | `endif |
| 7890 | |
| 7891 | endmodule |
| 7892 | module cl_a1_nand3_8x ( |
| 7893 | in0, |
| 7894 | in1, |
| 7895 | in2, |
| 7896 | out |
| 7897 | ); |
| 7898 | input in0; |
| 7899 | input in1; |
| 7900 | input in2; |
| 7901 | output out; |
| 7902 | |
| 7903 | `ifdef LIB |
| 7904 | assign out = ~(in0 & in1 & in2); |
| 7905 | `endif |
| 7906 | |
| 7907 | endmodule |
| 7908 | module cl_a1_nand4_12x ( |
| 7909 | in0, |
| 7910 | in1, |
| 7911 | in2, |
| 7912 | in3, |
| 7913 | out |
| 7914 | ); |
| 7915 | input in0; |
| 7916 | input in1; |
| 7917 | input in2; |
| 7918 | input in3; |
| 7919 | output out; |
| 7920 | |
| 7921 | `ifdef LIB |
| 7922 | assign out = ~(in0 & in1 & in2 & in3); |
| 7923 | `endif |
| 7924 | |
| 7925 | endmodule |
| 7926 | module cl_a1_nand4_16x ( |
| 7927 | in0, |
| 7928 | in1, |
| 7929 | in2, |
| 7930 | in3, |
| 7931 | out |
| 7932 | ); |
| 7933 | input in0; |
| 7934 | input in1; |
| 7935 | input in2; |
| 7936 | input in3; |
| 7937 | output out; |
| 7938 | |
| 7939 | `ifdef LIB |
| 7940 | assign out = ~(in0 & in1 & in2 & in3); |
| 7941 | `endif |
| 7942 | |
| 7943 | endmodule |
| 7944 | module cl_a1_nand4_1x ( |
| 7945 | in0, |
| 7946 | in1, |
| 7947 | in2, |
| 7948 | in3, |
| 7949 | out |
| 7950 | ); |
| 7951 | input in0; |
| 7952 | input in1; |
| 7953 | input in2; |
| 7954 | input in3; |
| 7955 | output out; |
| 7956 | |
| 7957 | `ifdef LIB |
| 7958 | assign out = ~(in0 & in1 & in2 & in3); |
| 7959 | `endif |
| 7960 | |
| 7961 | endmodule |
| 7962 | |
| 7963 | |
| 7964 | module cl_a1_nand4_2x ( |
| 7965 | in0, |
| 7966 | in1, |
| 7967 | in2, |
| 7968 | in3, |
| 7969 | out |
| 7970 | ); |
| 7971 | input in0; |
| 7972 | input in1; |
| 7973 | input in2; |
| 7974 | input in3; |
| 7975 | output out; |
| 7976 | |
| 7977 | `ifdef LIB |
| 7978 | assign out = ~(in0 & in1 & in2 & in3); |
| 7979 | `endif |
| 7980 | |
| 7981 | endmodule |
| 7982 | |
| 7983 | module cl_a1_nand4_4x ( |
| 7984 | in0, |
| 7985 | in1, |
| 7986 | in2, |
| 7987 | in3, |
| 7988 | out |
| 7989 | ); |
| 7990 | input in0; |
| 7991 | input in1; |
| 7992 | input in2; |
| 7993 | input in3; |
| 7994 | output out; |
| 7995 | |
| 7996 | `ifdef LIB |
| 7997 | assign out = ~(in0 & in1 & in2 & in3); |
| 7998 | `endif |
| 7999 | |
| 8000 | endmodule |
| 8001 | module cl_a1_nand4_6x ( |
| 8002 | in0, |
| 8003 | in1, |
| 8004 | in2, |
| 8005 | in3, |
| 8006 | out |
| 8007 | ); |
| 8008 | input in0; |
| 8009 | input in1; |
| 8010 | input in2; |
| 8011 | input in3; |
| 8012 | output out; |
| 8013 | |
| 8014 | `ifdef LIB |
| 8015 | assign out = ~(in0 & in1 & in2 & in3); |
| 8016 | `endif |
| 8017 | |
| 8018 | endmodule |
| 8019 | module cl_a1_nand4_8x ( |
| 8020 | in0, |
| 8021 | in1, |
| 8022 | in2, |
| 8023 | in3, |
| 8024 | out |
| 8025 | ); |
| 8026 | input in0; |
| 8027 | input in1; |
| 8028 | input in2; |
| 8029 | input in3; |
| 8030 | output out; |
| 8031 | |
| 8032 | `ifdef LIB |
| 8033 | assign out = ~(in0 & in1 & in2 & in3); |
| 8034 | `endif |
| 8035 | |
| 8036 | endmodule |
| 8037 | module cl_a1_nor2_12x ( |
| 8038 | in0, |
| 8039 | in1, |
| 8040 | out |
| 8041 | ); |
| 8042 | input in0; |
| 8043 | input in1; |
| 8044 | output out; |
| 8045 | |
| 8046 | `ifdef LIB |
| 8047 | assign out = ~(in0 | in1); |
| 8048 | `endif |
| 8049 | |
| 8050 | endmodule |
| 8051 | module cl_a1_nor2_16x ( |
| 8052 | in0, |
| 8053 | in1, |
| 8054 | out |
| 8055 | ); |
| 8056 | input in0; |
| 8057 | input in1; |
| 8058 | output out; |
| 8059 | |
| 8060 | `ifdef LIB |
| 8061 | assign out = ~(in0 | in1); |
| 8062 | `endif |
| 8063 | |
| 8064 | endmodule |
| 8065 | module cl_a1_nor2_1x ( |
| 8066 | in0, |
| 8067 | in1, |
| 8068 | out |
| 8069 | ); |
| 8070 | input in0; |
| 8071 | input in1; |
| 8072 | output out; |
| 8073 | |
| 8074 | `ifdef LIB |
| 8075 | assign out = ~(in0 | in1); |
| 8076 | `endif |
| 8077 | |
| 8078 | endmodule |
| 8079 | module cl_a1_nor2_2x ( |
| 8080 | in0, |
| 8081 | in1, |
| 8082 | out |
| 8083 | ); |
| 8084 | input in0; |
| 8085 | input in1; |
| 8086 | output out; |
| 8087 | |
| 8088 | `ifdef LIB |
| 8089 | assign out = ~(in0 | in1); |
| 8090 | `endif |
| 8091 | |
| 8092 | endmodule |
| 8093 | module cl_a1_nor2_4x ( |
| 8094 | in0, |
| 8095 | in1, |
| 8096 | out |
| 8097 | ); |
| 8098 | input in0; |
| 8099 | input in1; |
| 8100 | output out; |
| 8101 | |
| 8102 | `ifdef LIB |
| 8103 | assign out = ~(in0 | in1); |
| 8104 | `endif |
| 8105 | |
| 8106 | endmodule |
| 8107 | module cl_a1_nor2_6x ( |
| 8108 | in0, |
| 8109 | in1, |
| 8110 | out |
| 8111 | ); |
| 8112 | input in0; |
| 8113 | input in1; |
| 8114 | output out; |
| 8115 | |
| 8116 | `ifdef LIB |
| 8117 | assign out = ~(in0 | in1); |
| 8118 | `endif |
| 8119 | |
| 8120 | endmodule |
| 8121 | module cl_a1_nor2_8x ( |
| 8122 | in0, |
| 8123 | in1, |
| 8124 | out |
| 8125 | ); |
| 8126 | input in0; |
| 8127 | input in1; |
| 8128 | output out; |
| 8129 | |
| 8130 | `ifdef LIB |
| 8131 | assign out = ~(in0 | in1); |
| 8132 | `endif |
| 8133 | |
| 8134 | endmodule |
| 8135 | module cl_a1_nor3_1x ( |
| 8136 | in0, |
| 8137 | in1, |
| 8138 | in2, |
| 8139 | out |
| 8140 | ); |
| 8141 | input in0; |
| 8142 | input in1; |
| 8143 | input in2; |
| 8144 | output out; |
| 8145 | |
| 8146 | `ifdef LIB |
| 8147 | assign out = ~(in0 | in1 | in2); |
| 8148 | `endif |
| 8149 | |
| 8150 | endmodule |
| 8151 | module cl_a1_nor3_2x ( |
| 8152 | in0, |
| 8153 | in1, |
| 8154 | in2, |
| 8155 | out |
| 8156 | ); |
| 8157 | input in0; |
| 8158 | input in1; |
| 8159 | input in2; |
| 8160 | output out; |
| 8161 | |
| 8162 | `ifdef LIB |
| 8163 | assign out = ~(in0 | in1 | in2); |
| 8164 | `endif |
| 8165 | |
| 8166 | endmodule |
| 8167 | module cl_a1_nor3_4x ( |
| 8168 | in0, |
| 8169 | in1, |
| 8170 | in2, |
| 8171 | out |
| 8172 | ); |
| 8173 | input in0; |
| 8174 | input in1; |
| 8175 | input in2; |
| 8176 | output out; |
| 8177 | |
| 8178 | `ifdef LIB |
| 8179 | assign out = ~(in0 | in1 | in2); |
| 8180 | `endif |
| 8181 | |
| 8182 | endmodule |
| 8183 | // -------------------------------------------------- |
| 8184 | // File: cl_a1_oai12_12x.behV |
| 8185 | // Auto generated verilog module by HnBCellAuto |
| 8186 | // |
| 8187 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 8188 | // By: balmiki |
| 8189 | // -------------------------------------------------- |
| 8190 | // |
| 8191 | module cl_a1_oai12_12x ( |
| 8192 | out, |
| 8193 | in10, |
| 8194 | in00, |
| 8195 | in01 ); |
| 8196 | |
| 8197 | output out; |
| 8198 | input in10; |
| 8199 | input in00; |
| 8200 | input in01; |
| 8201 | |
| 8202 | `ifdef LIB |
| 8203 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 8204 | `endif |
| 8205 | |
| 8206 | endmodule |
| 8207 | // -------------------------------------------------- |
| 8208 | // File: cl_a1_oai12_16x.behV |
| 8209 | // Auto generated verilog module by HnBCellAuto |
| 8210 | // |
| 8211 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 8212 | // By: balmiki |
| 8213 | // -------------------------------------------------- |
| 8214 | // |
| 8215 | module cl_a1_oai12_16x ( |
| 8216 | out, |
| 8217 | in10, |
| 8218 | in00, |
| 8219 | in01 ); |
| 8220 | |
| 8221 | output out; |
| 8222 | input in10; |
| 8223 | input in00; |
| 8224 | input in01; |
| 8225 | |
| 8226 | `ifdef LIB |
| 8227 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 8228 | `endif |
| 8229 | |
| 8230 | endmodule |
| 8231 | // -------------------------------------------------- |
| 8232 | // File: cl_a1_oai12_1x.behV |
| 8233 | // Auto generated verilog module by HnBCellAuto |
| 8234 | // |
| 8235 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 8236 | // By: balmiki |
| 8237 | // -------------------------------------------------- |
| 8238 | // |
| 8239 | module cl_a1_oai12_1x ( |
| 8240 | out, |
| 8241 | in10, |
| 8242 | in00, |
| 8243 | in01 ); |
| 8244 | |
| 8245 | output out; |
| 8246 | input in10; |
| 8247 | input in00; |
| 8248 | input in01; |
| 8249 | |
| 8250 | `ifdef LIB |
| 8251 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 8252 | `endif |
| 8253 | |
| 8254 | endmodule |
| 8255 | // -------------------------------------------------- |
| 8256 | // File: cl_a1_oai12_2x.behV |
| 8257 | // Auto generated verilog module by HnBCellAuto |
| 8258 | // |
| 8259 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 8260 | // By: balmiki |
| 8261 | // -------------------------------------------------- |
| 8262 | // |
| 8263 | module cl_a1_oai12_2x ( |
| 8264 | out, |
| 8265 | in10, |
| 8266 | in00, |
| 8267 | in01 ); |
| 8268 | |
| 8269 | output out; |
| 8270 | input in10; |
| 8271 | input in00; |
| 8272 | input in01; |
| 8273 | |
| 8274 | `ifdef LIB |
| 8275 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 8276 | `endif |
| 8277 | |
| 8278 | endmodule |
| 8279 | // -------------------------------------------------- |
| 8280 | // File: cl_a1_oai12_4x.behV |
| 8281 | // Auto generated verilog module by HnBCellAuto |
| 8282 | // |
| 8283 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 8284 | // By: balmiki |
| 8285 | // -------------------------------------------------- |
| 8286 | // |
| 8287 | module cl_a1_oai12_4x ( |
| 8288 | out, |
| 8289 | in10, |
| 8290 | in00, |
| 8291 | in01 ); |
| 8292 | |
| 8293 | output out; |
| 8294 | input in10; |
| 8295 | input in00; |
| 8296 | input in01; |
| 8297 | |
| 8298 | `ifdef LIB |
| 8299 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 8300 | `endif |
| 8301 | |
| 8302 | endmodule |
| 8303 | // -------------------------------------------------- |
| 8304 | // File: cl_a1_oai12_8x.behV |
| 8305 | // Auto generated verilog module by HnBCellAuto |
| 8306 | // |
| 8307 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 8308 | // By: balmiki |
| 8309 | // -------------------------------------------------- |
| 8310 | // |
| 8311 | module cl_a1_oai12_8x ( |
| 8312 | out, |
| 8313 | in10, |
| 8314 | in00, |
| 8315 | in01 ); |
| 8316 | |
| 8317 | output out; |
| 8318 | input in10; |
| 8319 | input in00; |
| 8320 | input in01; |
| 8321 | |
| 8322 | `ifdef LIB |
| 8323 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 8324 | `endif |
| 8325 | |
| 8326 | endmodule |
| 8327 | // -------------------------------------------------- |
| 8328 | // File: cl_a1_oai21_12x.behV |
| 8329 | // Auto generated verilog module by HnBCellAuto |
| 8330 | // |
| 8331 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 8332 | // By: balmiki |
| 8333 | // -------------------------------------------------- |
| 8334 | // |
| 8335 | module cl_a1_oai21_12x ( |
| 8336 | out, |
| 8337 | in10, |
| 8338 | in11, |
| 8339 | in00 ); |
| 8340 | |
| 8341 | output out; |
| 8342 | input in10; |
| 8343 | input in11; |
| 8344 | input in00; |
| 8345 | |
| 8346 | `ifdef LIB |
| 8347 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 8348 | `endif |
| 8349 | |
| 8350 | endmodule |
| 8351 | // -------------------------------------------------- |
| 8352 | // File: cl_a1_oai21_16x.behV |
| 8353 | // Auto generated verilog module by HnBCellAuto |
| 8354 | // |
| 8355 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 8356 | // By: balmiki |
| 8357 | // -------------------------------------------------- |
| 8358 | // |
| 8359 | module cl_a1_oai21_16x ( |
| 8360 | out, |
| 8361 | in10, |
| 8362 | in11, |
| 8363 | in00 ); |
| 8364 | |
| 8365 | output out; |
| 8366 | input in10; |
| 8367 | input in11; |
| 8368 | input in00; |
| 8369 | |
| 8370 | `ifdef LIB |
| 8371 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 8372 | `endif |
| 8373 | |
| 8374 | endmodule |
| 8375 | // -------------------------------------------------- |
| 8376 | // File: cl_a1_oai21_1x.behV |
| 8377 | // Auto generated verilog module by HnBCellAuto |
| 8378 | // |
| 8379 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST |
| 8380 | // By: balmiki |
| 8381 | // -------------------------------------------------- |
| 8382 | // |
| 8383 | module cl_a1_oai21_1x ( |
| 8384 | out, |
| 8385 | in10, |
| 8386 | in11, |
| 8387 | in00 ); |
| 8388 | |
| 8389 | output out; |
| 8390 | input in10; |
| 8391 | input in11; |
| 8392 | input in00; |
| 8393 | |
| 8394 | `ifdef LIB |
| 8395 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 8396 | `endif |
| 8397 | |
| 8398 | endmodule |
| 8399 | // -------------------------------------------------- |
| 8400 | // File: cl_a1_oai21_2x.behV |
| 8401 | // Auto generated verilog module by HnBCellAuto |
| 8402 | // |
| 8403 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 8404 | // By: balmiki |
| 8405 | // -------------------------------------------------- |
| 8406 | // |
| 8407 | module cl_a1_oai21_2x ( |
| 8408 | out, |
| 8409 | in10, |
| 8410 | in11, |
| 8411 | in00 ); |
| 8412 | |
| 8413 | output out; |
| 8414 | input in10; |
| 8415 | input in11; |
| 8416 | input in00; |
| 8417 | |
| 8418 | `ifdef LIB |
| 8419 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 8420 | `endif |
| 8421 | |
| 8422 | endmodule |
| 8423 | // -------------------------------------------------- |
| 8424 | // File: cl_a1_oai21_4x.behV |
| 8425 | // Auto generated verilog module by HnBCellAuto |
| 8426 | // |
| 8427 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 8428 | // By: balmiki |
| 8429 | // -------------------------------------------------- |
| 8430 | // |
| 8431 | module cl_a1_oai21_4x ( |
| 8432 | out, |
| 8433 | in10, |
| 8434 | in11, |
| 8435 | in00 ); |
| 8436 | |
| 8437 | output out; |
| 8438 | input in10; |
| 8439 | input in11; |
| 8440 | input in00; |
| 8441 | |
| 8442 | `ifdef LIB |
| 8443 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 8444 | `endif |
| 8445 | |
| 8446 | endmodule |
| 8447 | // -------------------------------------------------- |
| 8448 | // File: cl_a1_oai21_8x.behV |
| 8449 | // Auto generated verilog module by HnBCellAuto |
| 8450 | // |
| 8451 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 8452 | // By: balmiki |
| 8453 | // -------------------------------------------------- |
| 8454 | // |
| 8455 | module cl_a1_oai21_8x ( |
| 8456 | out, |
| 8457 | in10, |
| 8458 | in11, |
| 8459 | in00 ); |
| 8460 | |
| 8461 | output out; |
| 8462 | input in10; |
| 8463 | input in11; |
| 8464 | input in00; |
| 8465 | |
| 8466 | `ifdef LIB |
| 8467 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 8468 | `endif |
| 8469 | |
| 8470 | endmodule |
| 8471 | // -------------------------------------------------- |
| 8472 | // File: cl_a1_oai22_12x.behV |
| 8473 | // Auto generated verilog module by HnBCellAuto |
| 8474 | // |
| 8475 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 8476 | // By: balmiki |
| 8477 | // -------------------------------------------------- |
| 8478 | // |
| 8479 | module cl_a1_oai22_12x ( |
| 8480 | out, |
| 8481 | in10, |
| 8482 | in11, |
| 8483 | in00, |
| 8484 | in01 ); |
| 8485 | |
| 8486 | output out; |
| 8487 | input in10; |
| 8488 | input in11; |
| 8489 | input in00; |
| 8490 | input in01; |
| 8491 | |
| 8492 | `ifdef LIB |
| 8493 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 8494 | `endif |
| 8495 | |
| 8496 | endmodule |
| 8497 | // -------------------------------------------------- |
| 8498 | // File: cl_a1_oai22_16x.behV |
| 8499 | // Auto generated verilog module by HnBCellAuto |
| 8500 | // |
| 8501 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 8502 | // By: balmiki |
| 8503 | // -------------------------------------------------- |
| 8504 | // |
| 8505 | module cl_a1_oai22_16x ( |
| 8506 | out, |
| 8507 | in10, |
| 8508 | in11, |
| 8509 | in00, |
| 8510 | in01 ); |
| 8511 | |
| 8512 | output out; |
| 8513 | input in10; |
| 8514 | input in11; |
| 8515 | input in00; |
| 8516 | input in01; |
| 8517 | |
| 8518 | `ifdef LIB |
| 8519 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 8520 | `endif |
| 8521 | |
| 8522 | endmodule |
| 8523 | // -------------------------------------------------- |
| 8524 | // File: cl_a1_oai22_1x.behV |
| 8525 | // Auto generated verilog module by HnBCellAuto |
| 8526 | // |
| 8527 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 8528 | // By: balmiki |
| 8529 | // -------------------------------------------------- |
| 8530 | // |
| 8531 | module cl_a1_oai22_1x ( |
| 8532 | out, |
| 8533 | in10, |
| 8534 | in11, |
| 8535 | in00, |
| 8536 | in01 ); |
| 8537 | |
| 8538 | output out; |
| 8539 | input in10; |
| 8540 | input in11; |
| 8541 | input in00; |
| 8542 | input in01; |
| 8543 | |
| 8544 | `ifdef LIB |
| 8545 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 8546 | `endif |
| 8547 | |
| 8548 | endmodule |
| 8549 | // -------------------------------------------------- |
| 8550 | // File: cl_a1_oai22_2x.behV |
| 8551 | // Auto generated verilog module by HnBCellAuto |
| 8552 | // |
| 8553 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 8554 | // By: balmiki |
| 8555 | // -------------------------------------------------- |
| 8556 | // |
| 8557 | module cl_a1_oai22_2x ( |
| 8558 | out, |
| 8559 | in10, |
| 8560 | in11, |
| 8561 | in00, |
| 8562 | in01 ); |
| 8563 | |
| 8564 | output out; |
| 8565 | input in10; |
| 8566 | input in11; |
| 8567 | input in00; |
| 8568 | input in01; |
| 8569 | |
| 8570 | `ifdef LIB |
| 8571 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 8572 | `endif |
| 8573 | |
| 8574 | endmodule |
| 8575 | // -------------------------------------------------- |
| 8576 | // File: cl_a1_oai22_4x.behV |
| 8577 | // Auto generated verilog module by HnBCellAuto |
| 8578 | // |
| 8579 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 8580 | // By: balmiki |
| 8581 | // -------------------------------------------------- |
| 8582 | // |
| 8583 | module cl_a1_oai22_4x ( |
| 8584 | out, |
| 8585 | in10, |
| 8586 | in11, |
| 8587 | in00, |
| 8588 | in01 ); |
| 8589 | |
| 8590 | output out; |
| 8591 | input in10; |
| 8592 | input in11; |
| 8593 | input in00; |
| 8594 | input in01; |
| 8595 | |
| 8596 | `ifdef LIB |
| 8597 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 8598 | `endif |
| 8599 | |
| 8600 | endmodule |
| 8601 | // -------------------------------------------------- |
| 8602 | // File: cl_a1_oai22_8x.behV |
| 8603 | // Auto generated verilog module by HnBCellAuto |
| 8604 | // |
| 8605 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 8606 | // By: balmiki |
| 8607 | // -------------------------------------------------- |
| 8608 | // |
| 8609 | module cl_a1_oai22_8x ( |
| 8610 | out, |
| 8611 | in10, |
| 8612 | in11, |
| 8613 | in00, |
| 8614 | in01 ); |
| 8615 | |
| 8616 | output out; |
| 8617 | input in10; |
| 8618 | input in11; |
| 8619 | input in00; |
| 8620 | input in01; |
| 8621 | |
| 8622 | `ifdef LIB |
| 8623 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 8624 | `endif |
| 8625 | |
| 8626 | endmodule |
| 8627 | module cl_a1_xnor2_16x ( |
| 8628 | in0, |
| 8629 | in1, |
| 8630 | out |
| 8631 | ); |
| 8632 | input in0; |
| 8633 | input in1; |
| 8634 | output out; |
| 8635 | |
| 8636 | `ifdef LIB |
| 8637 | assign out = ~(in0 ^ in1); |
| 8638 | `endif |
| 8639 | |
| 8640 | endmodule |
| 8641 | |
| 8642 | module cl_a1_xnor2_1x ( |
| 8643 | in0, |
| 8644 | in1, |
| 8645 | out |
| 8646 | ); |
| 8647 | input in0; |
| 8648 | input in1; |
| 8649 | output out; |
| 8650 | |
| 8651 | `ifdef LIB |
| 8652 | assign out = ~(in0 ^ in1); |
| 8653 | `endif |
| 8654 | |
| 8655 | endmodule |
| 8656 | module cl_a1_xnor2_2x ( |
| 8657 | in0, |
| 8658 | in1, |
| 8659 | out |
| 8660 | ); |
| 8661 | input in0; |
| 8662 | input in1; |
| 8663 | output out; |
| 8664 | |
| 8665 | `ifdef LIB |
| 8666 | assign out = ~(in0 ^ in1); |
| 8667 | `endif |
| 8668 | |
| 8669 | endmodule |
| 8670 | module cl_a1_xnor2_4x ( |
| 8671 | in0, |
| 8672 | in1, |
| 8673 | out |
| 8674 | ); |
| 8675 | input in0; |
| 8676 | input in1; |
| 8677 | output out; |
| 8678 | |
| 8679 | `ifdef LIB |
| 8680 | assign out = ~(in0 ^ in1); |
| 8681 | `endif |
| 8682 | |
| 8683 | endmodule |
| 8684 | module cl_a1_xnor2_6x ( |
| 8685 | in0, |
| 8686 | in1, |
| 8687 | out |
| 8688 | ); |
| 8689 | input in0; |
| 8690 | input in1; |
| 8691 | output out; |
| 8692 | |
| 8693 | `ifdef LIB |
| 8694 | assign out = ~(in0 ^ in1); |
| 8695 | `endif |
| 8696 | |
| 8697 | endmodule |
| 8698 | module cl_a1_xnor2_8x ( |
| 8699 | in0, |
| 8700 | in1, |
| 8701 | out |
| 8702 | ); |
| 8703 | input in0; |
| 8704 | input in1; |
| 8705 | output out; |
| 8706 | |
| 8707 | `ifdef LIB |
| 8708 | assign out = ~(in0 ^ in1); |
| 8709 | `endif |
| 8710 | |
| 8711 | endmodule |
| 8712 | |
| 8713 | module cl_a1_xnor3_16x ( |
| 8714 | in0, |
| 8715 | in1, |
| 8716 | in2, |
| 8717 | out |
| 8718 | ); |
| 8719 | input in0; |
| 8720 | input in1; |
| 8721 | input in2; |
| 8722 | output out; |
| 8723 | |
| 8724 | `ifdef LIB |
| 8725 | assign out = ~(in0 ^ in1 ^ in2); |
| 8726 | `endif |
| 8727 | |
| 8728 | |
| 8729 | |
| 8730 | endmodule |
| 8731 | module cl_a1_xnor3_1x ( |
| 8732 | in0, |
| 8733 | in1, |
| 8734 | in2, |
| 8735 | out |
| 8736 | ); |
| 8737 | input in0; |
| 8738 | input in1; |
| 8739 | input in2; |
| 8740 | output out; |
| 8741 | |
| 8742 | `ifdef LIB |
| 8743 | assign out = ~(in0 ^ in1 ^ in2); |
| 8744 | `endif |
| 8745 | |
| 8746 | |
| 8747 | |
| 8748 | endmodule |
| 8749 | module cl_a1_xnor3_2x ( |
| 8750 | in0, |
| 8751 | in1, |
| 8752 | in2, |
| 8753 | out |
| 8754 | ); |
| 8755 | input in0; |
| 8756 | input in1; |
| 8757 | input in2; |
| 8758 | output out; |
| 8759 | |
| 8760 | `ifdef LIB |
| 8761 | assign out = ~(in0 ^ in1 ^ in2); |
| 8762 | `endif |
| 8763 | |
| 8764 | |
| 8765 | |
| 8766 | endmodule |
| 8767 | module cl_a1_xnor3_4x ( |
| 8768 | in0, |
| 8769 | in1, |
| 8770 | in2, |
| 8771 | out |
| 8772 | ); |
| 8773 | input in0; |
| 8774 | input in1; |
| 8775 | input in2; |
| 8776 | output out; |
| 8777 | |
| 8778 | `ifdef LIB |
| 8779 | assign out = ~(in0 ^ in1 ^ in2); |
| 8780 | `endif |
| 8781 | |
| 8782 | |
| 8783 | |
| 8784 | endmodule |
| 8785 | module cl_a1_xnor3_6x ( |
| 8786 | in0, |
| 8787 | in1, |
| 8788 | in2, |
| 8789 | out |
| 8790 | ); |
| 8791 | input in0; |
| 8792 | input in1; |
| 8793 | input in2; |
| 8794 | output out; |
| 8795 | |
| 8796 | `ifdef LIB |
| 8797 | assign out = ~(in0 ^ in1 ^ in2); |
| 8798 | `endif |
| 8799 | |
| 8800 | |
| 8801 | |
| 8802 | endmodule |
| 8803 | module cl_a1_xnor3_8x ( |
| 8804 | in0, |
| 8805 | in1, |
| 8806 | in2, |
| 8807 | out |
| 8808 | ); |
| 8809 | input in0; |
| 8810 | input in1; |
| 8811 | input in2; |
| 8812 | output out; |
| 8813 | |
| 8814 | `ifdef LIB |
| 8815 | assign out = ~(in0 ^ in1 ^ in2); |
| 8816 | `endif |
| 8817 | |
| 8818 | |
| 8819 | |
| 8820 | endmodule |
| 8821 | module cl_a1_xor2_16x ( |
| 8822 | in0, |
| 8823 | in1, |
| 8824 | out |
| 8825 | ); |
| 8826 | input in0; |
| 8827 | input in1; |
| 8828 | output out; |
| 8829 | |
| 8830 | `ifdef LIB |
| 8831 | assign out = in0 ^ in1; |
| 8832 | `endif |
| 8833 | |
| 8834 | endmodule |
| 8835 | |
| 8836 | module cl_a1_xor2_1x ( |
| 8837 | in0, |
| 8838 | in1, |
| 8839 | out |
| 8840 | ); |
| 8841 | input in0; |
| 8842 | input in1; |
| 8843 | output out; |
| 8844 | |
| 8845 | `ifdef LIB |
| 8846 | assign out = in0 ^ in1; |
| 8847 | `endif |
| 8848 | |
| 8849 | endmodule |
| 8850 | module cl_a1_xor2_2x ( |
| 8851 | in0, |
| 8852 | in1, |
| 8853 | out |
| 8854 | ); |
| 8855 | input in0; |
| 8856 | input in1; |
| 8857 | output out; |
| 8858 | |
| 8859 | `ifdef LIB |
| 8860 | assign out = in0 ^ in1; |
| 8861 | `endif |
| 8862 | |
| 8863 | endmodule |
| 8864 | module cl_a1_xor2_4x ( |
| 8865 | in0, |
| 8866 | in1, |
| 8867 | out |
| 8868 | ); |
| 8869 | input in0; |
| 8870 | input in1; |
| 8871 | output out; |
| 8872 | |
| 8873 | `ifdef LIB |
| 8874 | assign out = in0 ^ in1; |
| 8875 | `endif |
| 8876 | |
| 8877 | endmodule |
| 8878 | module cl_a1_xor2_6x ( |
| 8879 | in0, |
| 8880 | in1, |
| 8881 | out |
| 8882 | ); |
| 8883 | input in0; |
| 8884 | input in1; |
| 8885 | output out; |
| 8886 | |
| 8887 | `ifdef LIB |
| 8888 | assign out = in0 ^ in1; |
| 8889 | `endif |
| 8890 | |
| 8891 | endmodule |
| 8892 | module cl_a1_xor2_8x ( |
| 8893 | in0, |
| 8894 | in1, |
| 8895 | out |
| 8896 | ); |
| 8897 | input in0; |
| 8898 | input in1; |
| 8899 | output out; |
| 8900 | |
| 8901 | `ifdef LIB |
| 8902 | assign out = in0 ^ in1; |
| 8903 | `endif |
| 8904 | |
| 8905 | endmodule |
| 8906 | module cl_a1_xor3_16x ( |
| 8907 | in0, |
| 8908 | in1, |
| 8909 | in2, |
| 8910 | out |
| 8911 | ); |
| 8912 | input in0; |
| 8913 | input in1; |
| 8914 | input in2; |
| 8915 | output out; |
| 8916 | |
| 8917 | `ifdef LIB |
| 8918 | assign out = in0 ^ in1 ^ in2; |
| 8919 | `endif |
| 8920 | |
| 8921 | |
| 8922 | endmodule |
| 8923 | |
| 8924 | module cl_a1_xor3_1x ( |
| 8925 | in0, |
| 8926 | in1, |
| 8927 | in2, |
| 8928 | out |
| 8929 | ); |
| 8930 | input in0; |
| 8931 | input in1; |
| 8932 | input in2; |
| 8933 | output out; |
| 8934 | |
| 8935 | `ifdef LIB |
| 8936 | assign out = in0 ^ in1 ^ in2; |
| 8937 | `endif |
| 8938 | |
| 8939 | |
| 8940 | endmodule |
| 8941 | module cl_a1_xor3_2x ( |
| 8942 | in0, |
| 8943 | in1, |
| 8944 | in2, |
| 8945 | out |
| 8946 | ); |
| 8947 | input in0; |
| 8948 | input in1; |
| 8949 | input in2; |
| 8950 | output out; |
| 8951 | |
| 8952 | `ifdef LIB |
| 8953 | assign out = in0 ^ in1 ^ in2; |
| 8954 | `endif |
| 8955 | |
| 8956 | |
| 8957 | endmodule |
| 8958 | module cl_a1_xor3_4x ( |
| 8959 | in0, |
| 8960 | in1, |
| 8961 | in2, |
| 8962 | out |
| 8963 | ); |
| 8964 | input in0; |
| 8965 | input in1; |
| 8966 | input in2; |
| 8967 | output out; |
| 8968 | |
| 8969 | `ifdef LIB |
| 8970 | assign out = in0 ^ in1 ^ in2; |
| 8971 | `endif |
| 8972 | |
| 8973 | |
| 8974 | endmodule |
| 8975 | module cl_a1_xor3_6x ( |
| 8976 | in0, |
| 8977 | in1, |
| 8978 | in2, |
| 8979 | out |
| 8980 | ); |
| 8981 | input in0; |
| 8982 | input in1; |
| 8983 | input in2; |
| 8984 | output out; |
| 8985 | |
| 8986 | `ifdef LIB |
| 8987 | assign out = in0 ^ in1 ^ in2; |
| 8988 | `endif |
| 8989 | |
| 8990 | |
| 8991 | endmodule |
| 8992 | module cl_a1_xor3_8x ( |
| 8993 | in0, |
| 8994 | in1, |
| 8995 | in2, |
| 8996 | out |
| 8997 | ); |
| 8998 | input in0; |
| 8999 | input in1; |
| 9000 | input in2; |
| 9001 | output out; |
| 9002 | |
| 9003 | `ifdef LIB |
| 9004 | assign out = in0 ^ in1 ^ in2; |
| 9005 | `endif |
| 9006 | |
| 9007 | |
| 9008 | endmodule |
| 9009 | |
| 9010 | |
| 9011 | |
| 9012 | module cl_a1_muxprotect_2x ( |
| 9013 | d0, |
| 9014 | d1, |
| 9015 | d2, |
| 9016 | d3, |
| 9017 | scan_en, |
| 9018 | e0, |
| 9019 | e1, |
| 9020 | e2, |
| 9021 | e3 |
| 9022 | ); |
| 9023 | input d0; |
| 9024 | input d1; |
| 9025 | input d2; |
| 9026 | input d3; |
| 9027 | input scan_en; |
| 9028 | output e0; |
| 9029 | output e1; |
| 9030 | output e2; |
| 9031 | output e3; |
| 9032 | |
| 9033 | `ifdef LIB |
| 9034 | assign e0 = scan_en | d0; |
| 9035 | assign e1= ~scan_en & d1; |
| 9036 | assign e2= ~scan_en & d2; |
| 9037 | assign e3= ~scan_en & d3; |
| 9038 | `endif |
| 9039 | |
| 9040 | endmodule |
| 9041 | |
| 9042 | module cl_a1_add64_8x ( |
| 9043 | cin, |
| 9044 | in0, |
| 9045 | in1, |
| 9046 | out, |
| 9047 | cout |
| 9048 | ); |
| 9049 | input cin; |
| 9050 | input [63:0] in0; |
| 9051 | input [63:0] in1; |
| 9052 | output [63:0] out; |
| 9053 | output cout; |
| 9054 | |
| 9055 | `ifdef LIB |
| 9056 | assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin}); |
| 9057 | `endif |
| 9058 | |
| 9059 | endmodule |
| 9060 | |
| 9061 | |
| 9062 | |
| 9063 | |
| 9064 | |
| 9065 | |
| 9066 | |