| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: cl_a1gb.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module cl_a1gb_aoi12_12x ( |
| 36 | out, |
| 37 | in10, |
| 38 | in00, |
| 39 | in01 ); |
| 40 | |
| 41 | output out; |
| 42 | input in10; |
| 43 | input in00; |
| 44 | input in01; |
| 45 | |
| 46 | `ifdef LIB |
| 47 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 48 | `endif |
| 49 | |
| 50 | endmodule |
| 51 | // -------------------------------------------------- |
| 52 | // File: cl_a1gb_aoi12_16x.behV |
| 53 | // Auto generated verilog module by HnBCellAuto |
| 54 | // |
| 55 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 56 | // By: balmiki |
| 57 | // -------------------------------------------------- |
| 58 | // |
| 59 | module cl_a1gb_aoi12_16x ( |
| 60 | out, |
| 61 | in10, |
| 62 | in00, |
| 63 | in01 ); |
| 64 | |
| 65 | output out; |
| 66 | input in10; |
| 67 | input in00; |
| 68 | input in01; |
| 69 | |
| 70 | `ifdef LIB |
| 71 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 72 | `endif |
| 73 | |
| 74 | endmodule |
| 75 | // -------------------------------------------------- |
| 76 | // File: cl_a1gb_aoi12_1x.behV |
| 77 | // Auto generated verilog module by HnBCellAuto |
| 78 | // |
| 79 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST |
| 80 | // By: balmiki |
| 81 | // -------------------------------------------------- |
| 82 | // |
| 83 | module cl_a1gb_aoi12_1x ( |
| 84 | out, |
| 85 | in10, |
| 86 | in00, |
| 87 | in01 ); |
| 88 | |
| 89 | output out; |
| 90 | input in10; |
| 91 | input in00; |
| 92 | input in01; |
| 93 | |
| 94 | `ifdef LIB |
| 95 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 96 | `endif |
| 97 | |
| 98 | endmodule |
| 99 | // -------------------------------------------------- |
| 100 | // File: cl_a1gb_aoi12_2x.behV |
| 101 | // Auto generated verilog module by HnBCellAuto |
| 102 | // |
| 103 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 104 | // By: balmiki |
| 105 | // -------------------------------------------------- |
| 106 | // |
| 107 | module cl_a1gb_aoi12_2x ( |
| 108 | out, |
| 109 | in10, |
| 110 | in00, |
| 111 | in01 ); |
| 112 | |
| 113 | output out; |
| 114 | input in10; |
| 115 | input in00; |
| 116 | input in01; |
| 117 | |
| 118 | `ifdef LIB |
| 119 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 120 | `endif |
| 121 | |
| 122 | endmodule |
| 123 | // -------------------------------------------------- |
| 124 | // File: cl_a1gb_aoi12_4x.behV |
| 125 | // Auto generated verilog module by HnBCellAuto |
| 126 | // |
| 127 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 128 | // By: balmiki |
| 129 | // -------------------------------------------------- |
| 130 | // |
| 131 | module cl_a1gb_aoi12_4x ( |
| 132 | out, |
| 133 | in10, |
| 134 | in00, |
| 135 | in01 ); |
| 136 | |
| 137 | output out; |
| 138 | input in10; |
| 139 | input in00; |
| 140 | input in01; |
| 141 | |
| 142 | `ifdef LIB |
| 143 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 144 | `endif |
| 145 | |
| 146 | endmodule |
| 147 | // -------------------------------------------------- |
| 148 | // File: cl_a1gb_aoi12_8x.behV |
| 149 | // Auto generated verilog module by HnBCellAuto |
| 150 | // |
| 151 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 152 | // By: balmiki |
| 153 | // -------------------------------------------------- |
| 154 | // |
| 155 | module cl_a1gb_aoi12_8x ( |
| 156 | out, |
| 157 | in10, |
| 158 | in00, |
| 159 | in01 ); |
| 160 | |
| 161 | output out; |
| 162 | input in10; |
| 163 | input in00; |
| 164 | input in01; |
| 165 | |
| 166 | `ifdef LIB |
| 167 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 168 | `endif |
| 169 | |
| 170 | endmodule |
| 171 | // -------------------------------------------------- |
| 172 | // File: cl_a1gb_aoi21_12x.behV |
| 173 | // Auto generated verilog module by HnBCellAuto |
| 174 | // |
| 175 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 176 | // By: balmiki |
| 177 | // -------------------------------------------------- |
| 178 | // |
| 179 | module cl_a1gb_aoi21_12x ( |
| 180 | out, |
| 181 | in10, |
| 182 | in11, |
| 183 | in00 ); |
| 184 | |
| 185 | output out; |
| 186 | input in10; |
| 187 | input in11; |
| 188 | input in00; |
| 189 | |
| 190 | `ifdef LIB |
| 191 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 192 | `endif |
| 193 | |
| 194 | endmodule |
| 195 | // -------------------------------------------------- |
| 196 | // File: cl_a1gb_aoi21_16x.behV |
| 197 | // Auto generated verilog module by HnBCellAuto |
| 198 | // |
| 199 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 200 | // By: balmiki |
| 201 | // -------------------------------------------------- |
| 202 | // |
| 203 | module cl_a1gb_aoi21_16x ( |
| 204 | out, |
| 205 | in10, |
| 206 | in11, |
| 207 | in00 ); |
| 208 | |
| 209 | output out; |
| 210 | input in10; |
| 211 | input in11; |
| 212 | input in00; |
| 213 | |
| 214 | `ifdef LIB |
| 215 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 216 | `endif |
| 217 | |
| 218 | endmodule |
| 219 | // -------------------------------------------------- |
| 220 | // File: cl_a1gb_aoi21_1x.behV |
| 221 | // Auto generated verilog module by HnBCellAuto |
| 222 | // |
| 223 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 224 | // By: balmiki |
| 225 | // -------------------------------------------------- |
| 226 | // |
| 227 | module cl_a1gb_aoi21_1x ( |
| 228 | out, |
| 229 | in10, |
| 230 | in11, |
| 231 | in00 ); |
| 232 | |
| 233 | output out; |
| 234 | input in10; |
| 235 | input in11; |
| 236 | input in00; |
| 237 | |
| 238 | `ifdef LIB |
| 239 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 240 | `endif |
| 241 | |
| 242 | endmodule |
| 243 | // -------------------------------------------------- |
| 244 | // File: cl_a1gb_aoi21_2x.behV |
| 245 | // Auto generated verilog module by HnBCellAuto |
| 246 | // |
| 247 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 248 | // By: balmiki |
| 249 | // -------------------------------------------------- |
| 250 | // |
| 251 | module cl_a1gb_aoi21_2x ( |
| 252 | out, |
| 253 | in10, |
| 254 | in11, |
| 255 | in00 ); |
| 256 | |
| 257 | output out; |
| 258 | input in10; |
| 259 | input in11; |
| 260 | input in00; |
| 261 | |
| 262 | `ifdef LIB |
| 263 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 264 | `endif |
| 265 | |
| 266 | endmodule |
| 267 | // -------------------------------------------------- |
| 268 | // File: cl_a1gb_aoi21_4x.behV |
| 269 | // Auto generated verilog module by HnBCellAuto |
| 270 | // |
| 271 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 272 | // By: balmiki |
| 273 | // -------------------------------------------------- |
| 274 | // |
| 275 | module cl_a1gb_aoi21_4x ( |
| 276 | out, |
| 277 | in10, |
| 278 | in11, |
| 279 | in00 ); |
| 280 | |
| 281 | output out; |
| 282 | input in10; |
| 283 | input in11; |
| 284 | input in00; |
| 285 | |
| 286 | `ifdef LIB |
| 287 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 288 | `endif |
| 289 | |
| 290 | endmodule |
| 291 | // -------------------------------------------------- |
| 292 | // File: cl_a1gb_aoi21_8x.behV |
| 293 | // Auto generated verilog module by HnBCellAuto |
| 294 | // |
| 295 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 296 | // By: balmiki |
| 297 | // -------------------------------------------------- |
| 298 | // |
| 299 | module cl_a1gb_aoi21_8x ( |
| 300 | out, |
| 301 | in10, |
| 302 | in11, |
| 303 | in00 ); |
| 304 | |
| 305 | output out; |
| 306 | input in10; |
| 307 | input in11; |
| 308 | input in00; |
| 309 | |
| 310 | `ifdef LIB |
| 311 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 312 | `endif |
| 313 | |
| 314 | endmodule |
| 315 | // -------------------------------------------------- |
| 316 | // File: cl_a1gb_aoi22_12x.behV |
| 317 | // Auto generated verilog module by HnBCellAuto |
| 318 | // |
| 319 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 320 | // By: balmiki |
| 321 | // -------------------------------------------------- |
| 322 | // |
| 323 | module cl_a1gb_aoi22_12x ( |
| 324 | out, |
| 325 | in10, |
| 326 | in11, |
| 327 | in00, |
| 328 | in01 ); |
| 329 | |
| 330 | output out; |
| 331 | input in10; |
| 332 | input in11; |
| 333 | input in00; |
| 334 | input in01; |
| 335 | |
| 336 | `ifdef LIB |
| 337 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 338 | `endif |
| 339 | |
| 340 | endmodule |
| 341 | |
| 342 | // -------------------------------------------------- |
| 343 | // File: cl_a1gb_aoi22_1x.behV |
| 344 | // Auto generated verilog module by HnBCellAuto |
| 345 | // |
| 346 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT |
| 347 | // By: balmiki |
| 348 | // -------------------------------------------------- |
| 349 | // |
| 350 | module cl_a1gb_aoi22_1x ( |
| 351 | out, |
| 352 | in10, |
| 353 | in11, |
| 354 | in00, |
| 355 | in01 ); |
| 356 | |
| 357 | output out; |
| 358 | input in10; |
| 359 | input in11; |
| 360 | input in00; |
| 361 | input in01; |
| 362 | |
| 363 | `ifdef LIB |
| 364 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 365 | `endif |
| 366 | |
| 367 | endmodule |
| 368 | // -------------------------------------------------- |
| 369 | // File: cl_a1gb_aoi22_2x.behV |
| 370 | // Auto generated verilog module by HnBCellAuto |
| 371 | // |
| 372 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 373 | // By: balmiki |
| 374 | // -------------------------------------------------- |
| 375 | // |
| 376 | module cl_a1gb_aoi22_2x ( |
| 377 | out, |
| 378 | in10, |
| 379 | in11, |
| 380 | in00, |
| 381 | in01 ); |
| 382 | |
| 383 | output out; |
| 384 | input in10; |
| 385 | input in11; |
| 386 | input in00; |
| 387 | input in01; |
| 388 | |
| 389 | `ifdef LIB |
| 390 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 391 | `endif |
| 392 | |
| 393 | endmodule |
| 394 | // -------------------------------------------------- |
| 395 | // File: cl_a1gb_aoi22_4x.behV |
| 396 | // Auto generated verilog module by HnBCellAuto |
| 397 | // |
| 398 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 399 | // By: balmiki |
| 400 | // -------------------------------------------------- |
| 401 | // |
| 402 | module cl_a1gb_aoi22_4x ( |
| 403 | out, |
| 404 | in10, |
| 405 | in11, |
| 406 | in00, |
| 407 | in01 ); |
| 408 | |
| 409 | output out; |
| 410 | input in10; |
| 411 | input in11; |
| 412 | input in00; |
| 413 | input in01; |
| 414 | |
| 415 | `ifdef LIB |
| 416 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 417 | `endif |
| 418 | |
| 419 | endmodule |
| 420 | // -------------------------------------------------- |
| 421 | // File: cl_a1gb_aoi22_8x.behV |
| 422 | // Auto generated verilog module by HnBCellAuto |
| 423 | // |
| 424 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 425 | // By: balmiki |
| 426 | // -------------------------------------------------- |
| 427 | // |
| 428 | module cl_a1gb_aoi22_8x ( |
| 429 | out, |
| 430 | in10, |
| 431 | in11, |
| 432 | in00, |
| 433 | in01 ); |
| 434 | |
| 435 | output out; |
| 436 | input in10; |
| 437 | input in11; |
| 438 | input in00; |
| 439 | input in01; |
| 440 | |
| 441 | `ifdef LIB |
| 442 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 443 | `endif |
| 444 | |
| 445 | endmodule |
| 446 | |
| 447 | |
| 448 | // -------------------------------------------------- |
| 449 | // File: cl_a1gb_aoi33_1x.behV |
| 450 | // Auto generated verilog module by HnBCellAuto |
| 451 | // |
| 452 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST |
| 453 | // By: balmiki |
| 454 | // -------------------------------------------------- |
| 455 | // |
| 456 | module cl_a1gb_aoi33_1x ( |
| 457 | out, |
| 458 | in10, |
| 459 | in11, |
| 460 | in12, |
| 461 | in00, |
| 462 | in01, |
| 463 | in02 ); |
| 464 | |
| 465 | output out; |
| 466 | input in10; |
| 467 | input in11; |
| 468 | input in12; |
| 469 | input in00; |
| 470 | input in01; |
| 471 | input in02; |
| 472 | |
| 473 | `ifdef LIB |
| 474 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 475 | `endif |
| 476 | |
| 477 | endmodule |
| 478 | // -------------------------------------------------- |
| 479 | // File: cl_a1gb_aoi33_2x.behV |
| 480 | // Auto generated verilog module by HnBCellAuto |
| 481 | // |
| 482 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 483 | // By: balmiki |
| 484 | // -------------------------------------------------- |
| 485 | // |
| 486 | module cl_a1gb_aoi33_2x ( |
| 487 | out, |
| 488 | in10, |
| 489 | in11, |
| 490 | in12, |
| 491 | in00, |
| 492 | in01, |
| 493 | in02 ); |
| 494 | |
| 495 | output out; |
| 496 | input in10; |
| 497 | input in11; |
| 498 | input in12; |
| 499 | input in00; |
| 500 | input in01; |
| 501 | input in02; |
| 502 | |
| 503 | `ifdef LIB |
| 504 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 505 | `endif |
| 506 | |
| 507 | endmodule |
| 508 | // -------------------------------------------------- |
| 509 | // File: cl_a1gb_aoi33_4x.behV |
| 510 | // Auto generated verilog module by HnBCellAuto |
| 511 | // |
| 512 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 513 | // By: balmiki |
| 514 | // -------------------------------------------------- |
| 515 | // |
| 516 | module cl_a1gb_aoi33_4x ( |
| 517 | out, |
| 518 | in10, |
| 519 | in11, |
| 520 | in12, |
| 521 | in00, |
| 522 | in01, |
| 523 | in02 ); |
| 524 | |
| 525 | output out; |
| 526 | input in10; |
| 527 | input in11; |
| 528 | input in12; |
| 529 | input in00; |
| 530 | input in01; |
| 531 | input in02; |
| 532 | |
| 533 | `ifdef LIB |
| 534 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 535 | `endif |
| 536 | |
| 537 | endmodule |
| 538 | // -------------------------------------------------- |
| 539 | // File: cl_a1gb_aoi33_8x.behV |
| 540 | // Auto generated verilog module by HnBCellAuto |
| 541 | // |
| 542 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 543 | // By: balmiki |
| 544 | // -------------------------------------------------- |
| 545 | // |
| 546 | module cl_a1gb_aoi33_8x ( |
| 547 | out, |
| 548 | in10, |
| 549 | in11, |
| 550 | in12, |
| 551 | in00, |
| 552 | in01, |
| 553 | in02 ); |
| 554 | |
| 555 | output out; |
| 556 | input in10; |
| 557 | input in11; |
| 558 | input in12; |
| 559 | input in00; |
| 560 | input in01; |
| 561 | input in02; |
| 562 | |
| 563 | `ifdef LIB |
| 564 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 565 | `endif |
| 566 | |
| 567 | endmodule |
| 568 | |
| 569 | |
| 570 | module cl_a1gb_buf_12x ( |
| 571 | in, |
| 572 | out |
| 573 | ); |
| 574 | input in; |
| 575 | output out; |
| 576 | |
| 577 | `ifdef LIB |
| 578 | //assign out = in; |
| 579 | buf (out, in); |
| 580 | `endif |
| 581 | |
| 582 | endmodule |
| 583 | module cl_a1gb_buf_16x ( |
| 584 | in, |
| 585 | out |
| 586 | ); |
| 587 | input in; |
| 588 | output out; |
| 589 | |
| 590 | `ifdef LIB |
| 591 | //assign out = in; |
| 592 | buf (out, in); |
| 593 | `endif |
| 594 | |
| 595 | endmodule |
| 596 | module cl_a1gb_buf_1x ( |
| 597 | in, |
| 598 | out |
| 599 | ); |
| 600 | input in; |
| 601 | output out; |
| 602 | |
| 603 | `ifdef LIB |
| 604 | //assign out = in; |
| 605 | buf (out, in); |
| 606 | `endif |
| 607 | |
| 608 | endmodule |
| 609 | module cl_a1gb_buf_20x ( |
| 610 | in, |
| 611 | out |
| 612 | ); |
| 613 | input in; |
| 614 | output out; |
| 615 | |
| 616 | `ifdef LIB |
| 617 | //assign out = in; |
| 618 | buf (out, in); |
| 619 | `endif |
| 620 | |
| 621 | endmodule |
| 622 | module cl_a1gb_buf_24x ( |
| 623 | in, |
| 624 | out |
| 625 | ); |
| 626 | input in; |
| 627 | output out; |
| 628 | |
| 629 | `ifdef LIB |
| 630 | //assign out = in; |
| 631 | buf (out, in); |
| 632 | `endif |
| 633 | |
| 634 | endmodule |
| 635 | module cl_a1gb_buf_28x ( |
| 636 | in, |
| 637 | out |
| 638 | ); |
| 639 | input in; |
| 640 | output out; |
| 641 | |
| 642 | `ifdef LIB |
| 643 | //assign out = in; |
| 644 | buf (out, in); |
| 645 | `endif |
| 646 | |
| 647 | endmodule |
| 648 | module cl_a1gb_buf_2x ( |
| 649 | in, |
| 650 | out |
| 651 | ); |
| 652 | input in; |
| 653 | output out; |
| 654 | |
| 655 | `ifdef LIB |
| 656 | //assign out = in; |
| 657 | buf (out, in); |
| 658 | `endif |
| 659 | |
| 660 | endmodule |
| 661 | module cl_a1gb_buf_32x ( |
| 662 | in, |
| 663 | out |
| 664 | ); |
| 665 | input in; |
| 666 | output out; |
| 667 | |
| 668 | `ifdef LIB |
| 669 | //assign out = in; |
| 670 | buf (out, in); |
| 671 | `endif |
| 672 | |
| 673 | endmodule |
| 674 | module cl_a1gb_buf_36x ( |
| 675 | in, |
| 676 | out |
| 677 | ); |
| 678 | input in; |
| 679 | output out; |
| 680 | |
| 681 | `ifdef LIB |
| 682 | //assign out = in; |
| 683 | buf (out, in); |
| 684 | `endif |
| 685 | |
| 686 | endmodule |
| 687 | module cl_a1gb_buf_40x ( |
| 688 | in, |
| 689 | out |
| 690 | ); |
| 691 | input in; |
| 692 | output out; |
| 693 | |
| 694 | `ifdef LIB |
| 695 | //assign out = in; |
| 696 | buf (out, in); |
| 697 | `endif |
| 698 | |
| 699 | endmodule |
| 700 | module cl_a1gb_buf_44x ( |
| 701 | in, |
| 702 | out |
| 703 | ); |
| 704 | input in; |
| 705 | output out; |
| 706 | |
| 707 | `ifdef LIB |
| 708 | //assign out = in; |
| 709 | buf (out, in); |
| 710 | `endif |
| 711 | |
| 712 | endmodule |
| 713 | module cl_a1gb_buf_48x ( |
| 714 | in, |
| 715 | out |
| 716 | ); |
| 717 | input in; |
| 718 | output out; |
| 719 | |
| 720 | `ifdef LIB |
| 721 | //assign out = in; |
| 722 | buf (out, in); |
| 723 | `endif |
| 724 | |
| 725 | endmodule |
| 726 | module cl_a1gb_buf_4x ( |
| 727 | in, |
| 728 | out |
| 729 | ); |
| 730 | input in; |
| 731 | output out; |
| 732 | |
| 733 | `ifdef LIB |
| 734 | //assign out = in; |
| 735 | buf (out, in); |
| 736 | `endif |
| 737 | |
| 738 | endmodule |
| 739 | module cl_a1gb_buf_56x ( |
| 740 | in, |
| 741 | out |
| 742 | ); |
| 743 | input in; |
| 744 | output out; |
| 745 | |
| 746 | `ifdef LIB |
| 747 | //assign out = in; |
| 748 | buf (out, in); |
| 749 | `endif |
| 750 | |
| 751 | endmodule |
| 752 | module cl_a1gb_buf_64x ( |
| 753 | in, |
| 754 | out |
| 755 | ); |
| 756 | input in; |
| 757 | output out; |
| 758 | |
| 759 | `ifdef LIB |
| 760 | //assign out = in; |
| 761 | buf (out, in); |
| 762 | `endif |
| 763 | |
| 764 | endmodule |
| 765 | module cl_a1gb_buf_6x ( |
| 766 | in, |
| 767 | out |
| 768 | ); |
| 769 | input in; |
| 770 | output out; |
| 771 | |
| 772 | `ifdef LIB |
| 773 | //assign out = in; |
| 774 | buf (out, in); |
| 775 | `endif |
| 776 | |
| 777 | endmodule |
| 778 | module cl_a1gb_buf_8x ( |
| 779 | in, |
| 780 | out |
| 781 | ); |
| 782 | input in; |
| 783 | output out; |
| 784 | |
| 785 | `ifdef LIB |
| 786 | //assign out = in; |
| 787 | buf (out, in); |
| 788 | `endif |
| 789 | |
| 790 | endmodule |
| 791 | module cl_a1gb_bufmin_1x ( |
| 792 | in, |
| 793 | out |
| 794 | ); |
| 795 | input in; |
| 796 | output out; |
| 797 | |
| 798 | `ifdef LIB |
| 799 | //assign out = in; |
| 800 | buf (out, in); |
| 801 | `endif |
| 802 | |
| 803 | endmodule |
| 804 | |
| 805 | module cl_a1gb_bufmin_16x ( |
| 806 | in, |
| 807 | out |
| 808 | ); |
| 809 | input in; |
| 810 | output out; |
| 811 | |
| 812 | `ifdef LIB |
| 813 | //assign out = in; |
| 814 | buf (out, in); |
| 815 | `endif |
| 816 | |
| 817 | endmodule |
| 818 | module cl_a1gb_bufmin_32x ( |
| 819 | in, |
| 820 | out |
| 821 | ); |
| 822 | input in; |
| 823 | output out; |
| 824 | |
| 825 | `ifdef LIB |
| 826 | //assign out = in; |
| 827 | buf (out, in); |
| 828 | `endif |
| 829 | |
| 830 | endmodule |
| 831 | |
| 832 | module cl_a1gb_inv_12x ( |
| 833 | in, |
| 834 | out |
| 835 | ); |
| 836 | input in; |
| 837 | output out; |
| 838 | |
| 839 | `ifdef LIB |
| 840 | //assign out = ~in; |
| 841 | not (out, in); |
| 842 | `endif |
| 843 | |
| 844 | endmodule |
| 845 | module cl_a1gb_inv_16x ( |
| 846 | in, |
| 847 | out |
| 848 | ); |
| 849 | input in; |
| 850 | output out; |
| 851 | |
| 852 | `ifdef LIB |
| 853 | //assign out = ~in; |
| 854 | not (out, in); |
| 855 | `endif |
| 856 | |
| 857 | endmodule |
| 858 | module cl_a1gb_inv_1x ( |
| 859 | in, |
| 860 | out |
| 861 | ); |
| 862 | input in; |
| 863 | output out; |
| 864 | |
| 865 | `ifdef LIB |
| 866 | //assign out = ~in; |
| 867 | not (out, in); |
| 868 | `endif |
| 869 | |
| 870 | endmodule |
| 871 | module cl_a1gb_inv_20x ( |
| 872 | in, |
| 873 | out |
| 874 | ); |
| 875 | input in; |
| 876 | output out; |
| 877 | |
| 878 | `ifdef LIB |
| 879 | //assign out = ~in; |
| 880 | not (out, in); |
| 881 | `endif |
| 882 | |
| 883 | endmodule |
| 884 | module cl_a1gb_inv_24x ( |
| 885 | in, |
| 886 | out |
| 887 | ); |
| 888 | input in; |
| 889 | output out; |
| 890 | |
| 891 | `ifdef LIB |
| 892 | //assign out = ~in; |
| 893 | not (out, in); |
| 894 | `endif |
| 895 | |
| 896 | endmodule |
| 897 | module cl_a1gb_inv_28x ( |
| 898 | in, |
| 899 | out |
| 900 | ); |
| 901 | input in; |
| 902 | output out; |
| 903 | |
| 904 | `ifdef LIB |
| 905 | //assign out = ~in; |
| 906 | not (out, in); |
| 907 | `endif |
| 908 | |
| 909 | endmodule |
| 910 | module cl_a1gb_inv_2x ( |
| 911 | in, |
| 912 | out |
| 913 | ); |
| 914 | input in; |
| 915 | output out; |
| 916 | |
| 917 | `ifdef LIB |
| 918 | //assign out = ~in; |
| 919 | not (out, in); |
| 920 | `endif |
| 921 | |
| 922 | endmodule |
| 923 | module cl_a1gb_inv_32x ( |
| 924 | in, |
| 925 | out |
| 926 | ); |
| 927 | input in; |
| 928 | output out; |
| 929 | |
| 930 | `ifdef LIB |
| 931 | //assign out = ~in; |
| 932 | not (out, in); |
| 933 | `endif |
| 934 | |
| 935 | endmodule |
| 936 | module cl_a1gb_inv_36x ( |
| 937 | in, |
| 938 | out |
| 939 | ); |
| 940 | input in; |
| 941 | output out; |
| 942 | |
| 943 | `ifdef LIB |
| 944 | //assign out = ~in; |
| 945 | not (out, in); |
| 946 | `endif |
| 947 | |
| 948 | endmodule |
| 949 | module cl_a1gb_inv_40x ( |
| 950 | in, |
| 951 | out |
| 952 | ); |
| 953 | input in; |
| 954 | output out; |
| 955 | |
| 956 | `ifdef LIB |
| 957 | //assign out = ~in; |
| 958 | not (out, in); |
| 959 | `endif |
| 960 | |
| 961 | endmodule |
| 962 | module cl_a1gb_inv_44x ( |
| 963 | in, |
| 964 | out |
| 965 | ); |
| 966 | input in; |
| 967 | output out; |
| 968 | |
| 969 | `ifdef LIB |
| 970 | //assign out = ~in; |
| 971 | not (out, in); |
| 972 | `endif |
| 973 | |
| 974 | endmodule |
| 975 | module cl_a1gb_inv_48x ( |
| 976 | in, |
| 977 | out |
| 978 | ); |
| 979 | input in; |
| 980 | output out; |
| 981 | |
| 982 | `ifdef LIB |
| 983 | //assign out = ~in; |
| 984 | not (out, in); |
| 985 | `endif |
| 986 | |
| 987 | endmodule |
| 988 | module cl_a1gb_inv_4x ( |
| 989 | in, |
| 990 | out |
| 991 | ); |
| 992 | input in; |
| 993 | output out; |
| 994 | |
| 995 | `ifdef LIB |
| 996 | //assign out = ~in; |
| 997 | not (out, in); |
| 998 | `endif |
| 999 | |
| 1000 | endmodule |
| 1001 | module cl_a1gb_inv_56x ( |
| 1002 | in, |
| 1003 | out |
| 1004 | ); |
| 1005 | input in; |
| 1006 | output out; |
| 1007 | |
| 1008 | `ifdef LIB |
| 1009 | //assign out = ~in; |
| 1010 | not (out, in); |
| 1011 | `endif |
| 1012 | |
| 1013 | endmodule |
| 1014 | module cl_a1gb_inv_64x ( |
| 1015 | in, |
| 1016 | out |
| 1017 | ); |
| 1018 | input in; |
| 1019 | output out; |
| 1020 | |
| 1021 | `ifdef LIB |
| 1022 | //assign out = ~in; |
| 1023 | not (out, in); |
| 1024 | `endif |
| 1025 | |
| 1026 | endmodule |
| 1027 | module cl_a1gb_inv_6x ( |
| 1028 | in, |
| 1029 | out |
| 1030 | ); |
| 1031 | input in; |
| 1032 | output out; |
| 1033 | |
| 1034 | `ifdef LIB |
| 1035 | //assign out = ~in; |
| 1036 | not (out, in); |
| 1037 | `endif |
| 1038 | |
| 1039 | endmodule |
| 1040 | module cl_a1gb_inv_8x ( |
| 1041 | in, |
| 1042 | out |
| 1043 | ); |
| 1044 | input in; |
| 1045 | output out; |
| 1046 | |
| 1047 | `ifdef LIB |
| 1048 | //assign out = ~in; |
| 1049 | not (out, in); |
| 1050 | `endif |
| 1051 | |
| 1052 | endmodule |
| 1053 | module cl_a1gb_nand2_12x ( |
| 1054 | in0, |
| 1055 | in1, |
| 1056 | out |
| 1057 | ); |
| 1058 | input in0; |
| 1059 | input in1; |
| 1060 | output out; |
| 1061 | |
| 1062 | `ifdef LIB |
| 1063 | assign out = ~(in0 & in1); |
| 1064 | `endif |
| 1065 | |
| 1066 | endmodule |
| 1067 | module cl_a1gb_nand2_16x ( |
| 1068 | in0, |
| 1069 | in1, |
| 1070 | out |
| 1071 | ); |
| 1072 | input in0; |
| 1073 | input in1; |
| 1074 | output out; |
| 1075 | |
| 1076 | `ifdef LIB |
| 1077 | assign out = ~(in0 & in1); |
| 1078 | `endif |
| 1079 | |
| 1080 | endmodule |
| 1081 | module cl_a1gb_nand2_1x ( |
| 1082 | in0, |
| 1083 | in1, |
| 1084 | out |
| 1085 | ); |
| 1086 | input in0; |
| 1087 | input in1; |
| 1088 | output out; |
| 1089 | |
| 1090 | `ifdef LIB |
| 1091 | assign out = ~(in0 & in1); |
| 1092 | `endif |
| 1093 | |
| 1094 | endmodule |
| 1095 | module cl_a1gb_nand2_20x ( |
| 1096 | in0, |
| 1097 | in1, |
| 1098 | out |
| 1099 | ); |
| 1100 | input in0; |
| 1101 | input in1; |
| 1102 | output out; |
| 1103 | |
| 1104 | `ifdef LIB |
| 1105 | assign out = ~(in0 & in1); |
| 1106 | `endif |
| 1107 | |
| 1108 | endmodule |
| 1109 | module cl_a1gb_nand2_24x ( |
| 1110 | in0, |
| 1111 | in1, |
| 1112 | out |
| 1113 | ); |
| 1114 | input in0; |
| 1115 | input in1; |
| 1116 | output out; |
| 1117 | |
| 1118 | `ifdef LIB |
| 1119 | assign out = ~(in0 & in1); |
| 1120 | `endif |
| 1121 | |
| 1122 | endmodule |
| 1123 | module cl_a1gb_nand2_28x ( |
| 1124 | in0, |
| 1125 | in1, |
| 1126 | out |
| 1127 | ); |
| 1128 | input in0; |
| 1129 | input in1; |
| 1130 | output out; |
| 1131 | |
| 1132 | `ifdef LIB |
| 1133 | assign out = ~(in0 & in1); |
| 1134 | `endif |
| 1135 | |
| 1136 | endmodule |
| 1137 | module cl_a1gb_nand2_2x ( |
| 1138 | in0, |
| 1139 | in1, |
| 1140 | out |
| 1141 | ); |
| 1142 | input in0; |
| 1143 | input in1; |
| 1144 | output out; |
| 1145 | |
| 1146 | `ifdef LIB |
| 1147 | assign out = ~(in0 & in1); |
| 1148 | `endif |
| 1149 | |
| 1150 | endmodule |
| 1151 | module cl_a1gb_nand2_32x ( |
| 1152 | in0, |
| 1153 | in1, |
| 1154 | out |
| 1155 | ); |
| 1156 | input in0; |
| 1157 | input in1; |
| 1158 | output out; |
| 1159 | |
| 1160 | `ifdef LIB |
| 1161 | assign out = ~(in0 & in1); |
| 1162 | `endif |
| 1163 | |
| 1164 | endmodule |
| 1165 | module cl_a1gb_nand2_4x ( |
| 1166 | in0, |
| 1167 | in1, |
| 1168 | out |
| 1169 | ); |
| 1170 | input in0; |
| 1171 | input in1; |
| 1172 | output out; |
| 1173 | |
| 1174 | `ifdef LIB |
| 1175 | assign out = ~(in0 & in1); |
| 1176 | `endif |
| 1177 | |
| 1178 | endmodule |
| 1179 | module cl_a1gb_nand2_6x ( |
| 1180 | in0, |
| 1181 | in1, |
| 1182 | out |
| 1183 | ); |
| 1184 | input in0; |
| 1185 | input in1; |
| 1186 | output out; |
| 1187 | |
| 1188 | `ifdef LIB |
| 1189 | assign out = ~(in0 & in1); |
| 1190 | `endif |
| 1191 | |
| 1192 | endmodule |
| 1193 | module cl_a1gb_nand2_8x ( |
| 1194 | in0, |
| 1195 | in1, |
| 1196 | out |
| 1197 | ); |
| 1198 | input in0; |
| 1199 | input in1; |
| 1200 | output out; |
| 1201 | |
| 1202 | `ifdef LIB |
| 1203 | assign out = ~(in0 & in1); |
| 1204 | `endif |
| 1205 | |
| 1206 | endmodule |
| 1207 | module cl_a1gb_nand3_12x ( |
| 1208 | in0, |
| 1209 | in1, |
| 1210 | in2, |
| 1211 | out |
| 1212 | ); |
| 1213 | input in0; |
| 1214 | input in1; |
| 1215 | input in2; |
| 1216 | output out; |
| 1217 | |
| 1218 | `ifdef LIB |
| 1219 | assign out = ~(in0 & in1 & in2); |
| 1220 | `endif |
| 1221 | |
| 1222 | endmodule |
| 1223 | module cl_a1gb_nand3_16x ( |
| 1224 | in0, |
| 1225 | in1, |
| 1226 | in2, |
| 1227 | out |
| 1228 | ); |
| 1229 | input in0; |
| 1230 | input in1; |
| 1231 | input in2; |
| 1232 | output out; |
| 1233 | |
| 1234 | `ifdef LIB |
| 1235 | assign out = ~(in0 & in1 & in2); |
| 1236 | `endif |
| 1237 | |
| 1238 | endmodule |
| 1239 | module cl_a1gb_nand3_1x ( |
| 1240 | in0, |
| 1241 | in1, |
| 1242 | in2, |
| 1243 | out |
| 1244 | ); |
| 1245 | input in0; |
| 1246 | input in1; |
| 1247 | input in2; |
| 1248 | output out; |
| 1249 | |
| 1250 | `ifdef LIB |
| 1251 | assign out = ~(in0 & in1 & in2); |
| 1252 | `endif |
| 1253 | |
| 1254 | endmodule |
| 1255 | module cl_a1gb_nand3_20x ( |
| 1256 | in0, |
| 1257 | in1, |
| 1258 | in2, |
| 1259 | out |
| 1260 | ); |
| 1261 | input in0; |
| 1262 | input in1; |
| 1263 | input in2; |
| 1264 | output out; |
| 1265 | |
| 1266 | `ifdef LIB |
| 1267 | assign out = ~(in0 & in1 & in2); |
| 1268 | `endif |
| 1269 | |
| 1270 | endmodule |
| 1271 | module cl_a1gb_nand3_24x ( |
| 1272 | in0, |
| 1273 | in1, |
| 1274 | in2, |
| 1275 | out |
| 1276 | ); |
| 1277 | input in0; |
| 1278 | input in1; |
| 1279 | input in2; |
| 1280 | output out; |
| 1281 | |
| 1282 | `ifdef LIB |
| 1283 | assign out = ~(in0 & in1 & in2); |
| 1284 | `endif |
| 1285 | |
| 1286 | endmodule |
| 1287 | |
| 1288 | module cl_a1gb_nand3_2x ( |
| 1289 | in0, |
| 1290 | in1, |
| 1291 | in2, |
| 1292 | out |
| 1293 | ); |
| 1294 | input in0; |
| 1295 | input in1; |
| 1296 | input in2; |
| 1297 | output out; |
| 1298 | |
| 1299 | `ifdef LIB |
| 1300 | assign out = ~(in0 & in1 & in2); |
| 1301 | `endif |
| 1302 | |
| 1303 | endmodule |
| 1304 | |
| 1305 | module cl_a1gb_nand3_4x ( |
| 1306 | in0, |
| 1307 | in1, |
| 1308 | in2, |
| 1309 | out |
| 1310 | ); |
| 1311 | input in0; |
| 1312 | input in1; |
| 1313 | input in2; |
| 1314 | output out; |
| 1315 | |
| 1316 | `ifdef LIB |
| 1317 | assign out = ~(in0 & in1 & in2); |
| 1318 | `endif |
| 1319 | |
| 1320 | endmodule |
| 1321 | module cl_a1gb_nand3_6x ( |
| 1322 | in0, |
| 1323 | in1, |
| 1324 | in2, |
| 1325 | out |
| 1326 | ); |
| 1327 | input in0; |
| 1328 | input in1; |
| 1329 | input in2; |
| 1330 | output out; |
| 1331 | |
| 1332 | `ifdef LIB |
| 1333 | assign out = ~(in0 & in1 & in2); |
| 1334 | `endif |
| 1335 | |
| 1336 | endmodule |
| 1337 | module cl_a1gb_nand3_8x ( |
| 1338 | in0, |
| 1339 | in1, |
| 1340 | in2, |
| 1341 | out |
| 1342 | ); |
| 1343 | input in0; |
| 1344 | input in1; |
| 1345 | input in2; |
| 1346 | output out; |
| 1347 | |
| 1348 | `ifdef LIB |
| 1349 | assign out = ~(in0 & in1 & in2); |
| 1350 | `endif |
| 1351 | |
| 1352 | endmodule |
| 1353 | module cl_a1gb_nand4_12x ( |
| 1354 | in0, |
| 1355 | in1, |
| 1356 | in2, |
| 1357 | in3, |
| 1358 | out |
| 1359 | ); |
| 1360 | input in0; |
| 1361 | input in1; |
| 1362 | input in2; |
| 1363 | input in3; |
| 1364 | output out; |
| 1365 | |
| 1366 | `ifdef LIB |
| 1367 | assign out = ~(in0 & in1 & in2 & in3); |
| 1368 | `endif |
| 1369 | |
| 1370 | endmodule |
| 1371 | module cl_a1gb_nand4_16x ( |
| 1372 | in0, |
| 1373 | in1, |
| 1374 | in2, |
| 1375 | in3, |
| 1376 | out |
| 1377 | ); |
| 1378 | input in0; |
| 1379 | input in1; |
| 1380 | input in2; |
| 1381 | input in3; |
| 1382 | output out; |
| 1383 | |
| 1384 | `ifdef LIB |
| 1385 | assign out = ~(in0 & in1 & in2 & in3); |
| 1386 | `endif |
| 1387 | |
| 1388 | endmodule |
| 1389 | module cl_a1gb_nand4_1x ( |
| 1390 | in0, |
| 1391 | in1, |
| 1392 | in2, |
| 1393 | in3, |
| 1394 | out |
| 1395 | ); |
| 1396 | input in0; |
| 1397 | input in1; |
| 1398 | input in2; |
| 1399 | input in3; |
| 1400 | output out; |
| 1401 | |
| 1402 | `ifdef LIB |
| 1403 | assign out = ~(in0 & in1 & in2 & in3); |
| 1404 | `endif |
| 1405 | |
| 1406 | endmodule |
| 1407 | |
| 1408 | |
| 1409 | module cl_a1gb_nand4_2x ( |
| 1410 | in0, |
| 1411 | in1, |
| 1412 | in2, |
| 1413 | in3, |
| 1414 | out |
| 1415 | ); |
| 1416 | input in0; |
| 1417 | input in1; |
| 1418 | input in2; |
| 1419 | input in3; |
| 1420 | output out; |
| 1421 | |
| 1422 | `ifdef LIB |
| 1423 | assign out = ~(in0 & in1 & in2 & in3); |
| 1424 | `endif |
| 1425 | |
| 1426 | endmodule |
| 1427 | |
| 1428 | module cl_a1gb_nand4_4x ( |
| 1429 | in0, |
| 1430 | in1, |
| 1431 | in2, |
| 1432 | in3, |
| 1433 | out |
| 1434 | ); |
| 1435 | input in0; |
| 1436 | input in1; |
| 1437 | input in2; |
| 1438 | input in3; |
| 1439 | output out; |
| 1440 | |
| 1441 | `ifdef LIB |
| 1442 | assign out = ~(in0 & in1 & in2 & in3); |
| 1443 | `endif |
| 1444 | |
| 1445 | endmodule |
| 1446 | module cl_a1gb_nand4_6x ( |
| 1447 | in0, |
| 1448 | in1, |
| 1449 | in2, |
| 1450 | in3, |
| 1451 | out |
| 1452 | ); |
| 1453 | input in0; |
| 1454 | input in1; |
| 1455 | input in2; |
| 1456 | input in3; |
| 1457 | output out; |
| 1458 | |
| 1459 | `ifdef LIB |
| 1460 | assign out = ~(in0 & in1 & in2 & in3); |
| 1461 | `endif |
| 1462 | |
| 1463 | endmodule |
| 1464 | module cl_a1gb_nand4_8x ( |
| 1465 | in0, |
| 1466 | in1, |
| 1467 | in2, |
| 1468 | in3, |
| 1469 | out |
| 1470 | ); |
| 1471 | input in0; |
| 1472 | input in1; |
| 1473 | input in2; |
| 1474 | input in3; |
| 1475 | output out; |
| 1476 | |
| 1477 | `ifdef LIB |
| 1478 | assign out = ~(in0 & in1 & in2 & in3); |
| 1479 | `endif |
| 1480 | |
| 1481 | endmodule |
| 1482 | module cl_a1gb_nor2_12x ( |
| 1483 | in0, |
| 1484 | in1, |
| 1485 | out |
| 1486 | ); |
| 1487 | input in0; |
| 1488 | input in1; |
| 1489 | output out; |
| 1490 | |
| 1491 | `ifdef LIB |
| 1492 | assign out = ~(in0 | in1); |
| 1493 | `endif |
| 1494 | |
| 1495 | endmodule |
| 1496 | module cl_a1gb_nor2_16x ( |
| 1497 | in0, |
| 1498 | in1, |
| 1499 | out |
| 1500 | ); |
| 1501 | input in0; |
| 1502 | input in1; |
| 1503 | output out; |
| 1504 | |
| 1505 | `ifdef LIB |
| 1506 | assign out = ~(in0 | in1); |
| 1507 | `endif |
| 1508 | |
| 1509 | endmodule |
| 1510 | module cl_a1gb_nor2_1x ( |
| 1511 | in0, |
| 1512 | in1, |
| 1513 | out |
| 1514 | ); |
| 1515 | input in0; |
| 1516 | input in1; |
| 1517 | output out; |
| 1518 | |
| 1519 | `ifdef LIB |
| 1520 | assign out = ~(in0 | in1); |
| 1521 | `endif |
| 1522 | |
| 1523 | endmodule |
| 1524 | module cl_a1gb_nor2_2x ( |
| 1525 | in0, |
| 1526 | in1, |
| 1527 | out |
| 1528 | ); |
| 1529 | input in0; |
| 1530 | input in1; |
| 1531 | output out; |
| 1532 | |
| 1533 | `ifdef LIB |
| 1534 | assign out = ~(in0 | in1); |
| 1535 | `endif |
| 1536 | |
| 1537 | endmodule |
| 1538 | module cl_a1gb_nor2_4x ( |
| 1539 | in0, |
| 1540 | in1, |
| 1541 | out |
| 1542 | ); |
| 1543 | input in0; |
| 1544 | input in1; |
| 1545 | output out; |
| 1546 | |
| 1547 | `ifdef LIB |
| 1548 | assign out = ~(in0 | in1); |
| 1549 | `endif |
| 1550 | |
| 1551 | endmodule |
| 1552 | module cl_a1gb_nor2_6x ( |
| 1553 | in0, |
| 1554 | in1, |
| 1555 | out |
| 1556 | ); |
| 1557 | input in0; |
| 1558 | input in1; |
| 1559 | output out; |
| 1560 | |
| 1561 | `ifdef LIB |
| 1562 | assign out = ~(in0 | in1); |
| 1563 | `endif |
| 1564 | |
| 1565 | endmodule |
| 1566 | module cl_a1gb_nor2_8x ( |
| 1567 | in0, |
| 1568 | in1, |
| 1569 | out |
| 1570 | ); |
| 1571 | input in0; |
| 1572 | input in1; |
| 1573 | output out; |
| 1574 | |
| 1575 | `ifdef LIB |
| 1576 | assign out = ~(in0 | in1); |
| 1577 | `endif |
| 1578 | |
| 1579 | endmodule |
| 1580 | module cl_a1gb_nor3_1x ( |
| 1581 | in0, |
| 1582 | in1, |
| 1583 | in2, |
| 1584 | out |
| 1585 | ); |
| 1586 | input in0; |
| 1587 | input in1; |
| 1588 | input in2; |
| 1589 | output out; |
| 1590 | |
| 1591 | `ifdef LIB |
| 1592 | assign out = ~(in0 | in1 | in2); |
| 1593 | `endif |
| 1594 | |
| 1595 | endmodule |
| 1596 | module cl_a1gb_nor3_2x ( |
| 1597 | in0, |
| 1598 | in1, |
| 1599 | in2, |
| 1600 | out |
| 1601 | ); |
| 1602 | input in0; |
| 1603 | input in1; |
| 1604 | input in2; |
| 1605 | output out; |
| 1606 | |
| 1607 | `ifdef LIB |
| 1608 | assign out = ~(in0 | in1 | in2); |
| 1609 | `endif |
| 1610 | |
| 1611 | endmodule |
| 1612 | module cl_a1gb_nor3_4x ( |
| 1613 | in0, |
| 1614 | in1, |
| 1615 | in2, |
| 1616 | out |
| 1617 | ); |
| 1618 | input in0; |
| 1619 | input in1; |
| 1620 | input in2; |
| 1621 | output out; |
| 1622 | |
| 1623 | `ifdef LIB |
| 1624 | assign out = ~(in0 | in1 | in2); |
| 1625 | `endif |
| 1626 | |
| 1627 | endmodule |
| 1628 | // -------------------------------------------------- |
| 1629 | // File: cl_a1gb_oai12_12x.behV |
| 1630 | // Auto generated verilog module by HnBCellAuto |
| 1631 | // |
| 1632 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1633 | // By: balmiki |
| 1634 | // -------------------------------------------------- |
| 1635 | // |
| 1636 | module cl_a1gb_oai12_12x ( |
| 1637 | out, |
| 1638 | in10, |
| 1639 | in00, |
| 1640 | in01 ); |
| 1641 | |
| 1642 | output out; |
| 1643 | input in10; |
| 1644 | input in00; |
| 1645 | input in01; |
| 1646 | |
| 1647 | `ifdef LIB |
| 1648 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1649 | `endif |
| 1650 | |
| 1651 | endmodule |
| 1652 | // -------------------------------------------------- |
| 1653 | // File: cl_a1gb_oai12_16x.behV |
| 1654 | // Auto generated verilog module by HnBCellAuto |
| 1655 | // |
| 1656 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1657 | // By: balmiki |
| 1658 | // -------------------------------------------------- |
| 1659 | // |
| 1660 | module cl_a1gb_oai12_16x ( |
| 1661 | out, |
| 1662 | in10, |
| 1663 | in00, |
| 1664 | in01 ); |
| 1665 | |
| 1666 | output out; |
| 1667 | input in10; |
| 1668 | input in00; |
| 1669 | input in01; |
| 1670 | |
| 1671 | `ifdef LIB |
| 1672 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1673 | `endif |
| 1674 | |
| 1675 | endmodule |
| 1676 | // -------------------------------------------------- |
| 1677 | // File: cl_a1gb_oai12_1x.behV |
| 1678 | // Auto generated verilog module by HnBCellAuto |
| 1679 | // |
| 1680 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1681 | // By: balmiki |
| 1682 | // -------------------------------------------------- |
| 1683 | // |
| 1684 | module cl_a1gb_oai12_1x ( |
| 1685 | out, |
| 1686 | in10, |
| 1687 | in00, |
| 1688 | in01 ); |
| 1689 | |
| 1690 | output out; |
| 1691 | input in10; |
| 1692 | input in00; |
| 1693 | input in01; |
| 1694 | |
| 1695 | `ifdef LIB |
| 1696 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1697 | `endif |
| 1698 | |
| 1699 | endmodule |
| 1700 | // -------------------------------------------------- |
| 1701 | // File: cl_a1gb_oai12_2x.behV |
| 1702 | // Auto generated verilog module by HnBCellAuto |
| 1703 | // |
| 1704 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1705 | // By: balmiki |
| 1706 | // -------------------------------------------------- |
| 1707 | // |
| 1708 | module cl_a1gb_oai12_2x ( |
| 1709 | out, |
| 1710 | in10, |
| 1711 | in00, |
| 1712 | in01 ); |
| 1713 | |
| 1714 | output out; |
| 1715 | input in10; |
| 1716 | input in00; |
| 1717 | input in01; |
| 1718 | |
| 1719 | `ifdef LIB |
| 1720 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1721 | `endif |
| 1722 | |
| 1723 | endmodule |
| 1724 | // -------------------------------------------------- |
| 1725 | // File: cl_a1gb_oai12_4x.behV |
| 1726 | // Auto generated verilog module by HnBCellAuto |
| 1727 | // |
| 1728 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1729 | // By: balmiki |
| 1730 | // -------------------------------------------------- |
| 1731 | // |
| 1732 | module cl_a1gb_oai12_4x ( |
| 1733 | out, |
| 1734 | in10, |
| 1735 | in00, |
| 1736 | in01 ); |
| 1737 | |
| 1738 | output out; |
| 1739 | input in10; |
| 1740 | input in00; |
| 1741 | input in01; |
| 1742 | |
| 1743 | `ifdef LIB |
| 1744 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1745 | `endif |
| 1746 | |
| 1747 | endmodule |
| 1748 | // -------------------------------------------------- |
| 1749 | // File: cl_a1gb_oai12_8x.behV |
| 1750 | // Auto generated verilog module by HnBCellAuto |
| 1751 | // |
| 1752 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1753 | // By: balmiki |
| 1754 | // -------------------------------------------------- |
| 1755 | // |
| 1756 | module cl_a1gb_oai12_8x ( |
| 1757 | out, |
| 1758 | in10, |
| 1759 | in00, |
| 1760 | in01 ); |
| 1761 | |
| 1762 | output out; |
| 1763 | input in10; |
| 1764 | input in00; |
| 1765 | input in01; |
| 1766 | |
| 1767 | `ifdef LIB |
| 1768 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1769 | `endif |
| 1770 | |
| 1771 | endmodule |
| 1772 | // -------------------------------------------------- |
| 1773 | // File: cl_a1gb_oai21_12x.behV |
| 1774 | // Auto generated verilog module by HnBCellAuto |
| 1775 | // |
| 1776 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1777 | // By: balmiki |
| 1778 | // -------------------------------------------------- |
| 1779 | // |
| 1780 | module cl_a1gb_oai21_12x ( |
| 1781 | out, |
| 1782 | in10, |
| 1783 | in11, |
| 1784 | in00 ); |
| 1785 | |
| 1786 | output out; |
| 1787 | input in10; |
| 1788 | input in11; |
| 1789 | input in00; |
| 1790 | |
| 1791 | `ifdef LIB |
| 1792 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1793 | `endif |
| 1794 | |
| 1795 | endmodule |
| 1796 | // -------------------------------------------------- |
| 1797 | // File: cl_a1gb_oai21_16x.behV |
| 1798 | // Auto generated verilog module by HnBCellAuto |
| 1799 | // |
| 1800 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1801 | // By: balmiki |
| 1802 | // -------------------------------------------------- |
| 1803 | // |
| 1804 | module cl_a1gb_oai21_16x ( |
| 1805 | out, |
| 1806 | in10, |
| 1807 | in11, |
| 1808 | in00 ); |
| 1809 | |
| 1810 | output out; |
| 1811 | input in10; |
| 1812 | input in11; |
| 1813 | input in00; |
| 1814 | |
| 1815 | `ifdef LIB |
| 1816 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1817 | `endif |
| 1818 | |
| 1819 | endmodule |
| 1820 | // -------------------------------------------------- |
| 1821 | // File: cl_a1gb_oai21_1x.behV |
| 1822 | // Auto generated verilog module by HnBCellAuto |
| 1823 | // |
| 1824 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST |
| 1825 | // By: balmiki |
| 1826 | // -------------------------------------------------- |
| 1827 | // |
| 1828 | module cl_a1gb_oai21_1x ( |
| 1829 | out, |
| 1830 | in10, |
| 1831 | in11, |
| 1832 | in00 ); |
| 1833 | |
| 1834 | output out; |
| 1835 | input in10; |
| 1836 | input in11; |
| 1837 | input in00; |
| 1838 | |
| 1839 | `ifdef LIB |
| 1840 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1841 | `endif |
| 1842 | |
| 1843 | endmodule |
| 1844 | // -------------------------------------------------- |
| 1845 | // File: cl_a1gb_oai21_2x.behV |
| 1846 | // Auto generated verilog module by HnBCellAuto |
| 1847 | // |
| 1848 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 1849 | // By: balmiki |
| 1850 | // -------------------------------------------------- |
| 1851 | // |
| 1852 | module cl_a1gb_oai21_2x ( |
| 1853 | out, |
| 1854 | in10, |
| 1855 | in11, |
| 1856 | in00 ); |
| 1857 | |
| 1858 | output out; |
| 1859 | input in10; |
| 1860 | input in11; |
| 1861 | input in00; |
| 1862 | |
| 1863 | `ifdef LIB |
| 1864 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1865 | `endif |
| 1866 | |
| 1867 | endmodule |
| 1868 | // -------------------------------------------------- |
| 1869 | // File: cl_a1gb_oai21_4x.behV |
| 1870 | // Auto generated verilog module by HnBCellAuto |
| 1871 | // |
| 1872 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 1873 | // By: balmiki |
| 1874 | // -------------------------------------------------- |
| 1875 | // |
| 1876 | module cl_a1gb_oai21_4x ( |
| 1877 | out, |
| 1878 | in10, |
| 1879 | in11, |
| 1880 | in00 ); |
| 1881 | |
| 1882 | output out; |
| 1883 | input in10; |
| 1884 | input in11; |
| 1885 | input in00; |
| 1886 | |
| 1887 | `ifdef LIB |
| 1888 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1889 | `endif |
| 1890 | |
| 1891 | endmodule |
| 1892 | // -------------------------------------------------- |
| 1893 | // File: cl_a1gb_oai21_8x.behV |
| 1894 | // Auto generated verilog module by HnBCellAuto |
| 1895 | // |
| 1896 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 1897 | // By: balmiki |
| 1898 | // -------------------------------------------------- |
| 1899 | // |
| 1900 | module cl_a1gb_oai21_8x ( |
| 1901 | out, |
| 1902 | in10, |
| 1903 | in11, |
| 1904 | in00 ); |
| 1905 | |
| 1906 | output out; |
| 1907 | input in10; |
| 1908 | input in11; |
| 1909 | input in00; |
| 1910 | |
| 1911 | `ifdef LIB |
| 1912 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1913 | `endif |
| 1914 | |
| 1915 | endmodule |
| 1916 | // -------------------------------------------------- |
| 1917 | // File: cl_a1gb_oai22_12x.behV |
| 1918 | // Auto generated verilog module by HnBCellAuto |
| 1919 | // |
| 1920 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1921 | // By: balmiki |
| 1922 | // -------------------------------------------------- |
| 1923 | // |
| 1924 | module cl_a1gb_oai22_12x ( |
| 1925 | out, |
| 1926 | in10, |
| 1927 | in11, |
| 1928 | in00, |
| 1929 | in01 ); |
| 1930 | |
| 1931 | output out; |
| 1932 | input in10; |
| 1933 | input in11; |
| 1934 | input in00; |
| 1935 | input in01; |
| 1936 | |
| 1937 | `ifdef LIB |
| 1938 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1939 | `endif |
| 1940 | |
| 1941 | endmodule |
| 1942 | // -------------------------------------------------- |
| 1943 | // File: cl_a1gb_oai22_16x.behV |
| 1944 | // Auto generated verilog module by HnBCellAuto |
| 1945 | // |
| 1946 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1947 | // By: balmiki |
| 1948 | // -------------------------------------------------- |
| 1949 | // |
| 1950 | module cl_a1gb_oai22_16x ( |
| 1951 | out, |
| 1952 | in10, |
| 1953 | in11, |
| 1954 | in00, |
| 1955 | in01 ); |
| 1956 | |
| 1957 | output out; |
| 1958 | input in10; |
| 1959 | input in11; |
| 1960 | input in00; |
| 1961 | input in01; |
| 1962 | |
| 1963 | `ifdef LIB |
| 1964 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1965 | `endif |
| 1966 | |
| 1967 | endmodule |
| 1968 | // -------------------------------------------------- |
| 1969 | // File: cl_a1gb_oai22_1x.behV |
| 1970 | // Auto generated verilog module by HnBCellAuto |
| 1971 | // |
| 1972 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1973 | // By: balmiki |
| 1974 | // -------------------------------------------------- |
| 1975 | // |
| 1976 | module cl_a1gb_oai22_1x ( |
| 1977 | out, |
| 1978 | in10, |
| 1979 | in11, |
| 1980 | in00, |
| 1981 | in01 ); |
| 1982 | |
| 1983 | output out; |
| 1984 | input in10; |
| 1985 | input in11; |
| 1986 | input in00; |
| 1987 | input in01; |
| 1988 | |
| 1989 | `ifdef LIB |
| 1990 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1991 | `endif |
| 1992 | |
| 1993 | endmodule |
| 1994 | // -------------------------------------------------- |
| 1995 | // File: cl_a1gb_oai22_2x.behV |
| 1996 | // Auto generated verilog module by HnBCellAuto |
| 1997 | // |
| 1998 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 1999 | // By: balmiki |
| 2000 | // -------------------------------------------------- |
| 2001 | // |
| 2002 | module cl_a1gb_oai22_2x ( |
| 2003 | out, |
| 2004 | in10, |
| 2005 | in11, |
| 2006 | in00, |
| 2007 | in01 ); |
| 2008 | |
| 2009 | output out; |
| 2010 | input in10; |
| 2011 | input in11; |
| 2012 | input in00; |
| 2013 | input in01; |
| 2014 | |
| 2015 | `ifdef LIB |
| 2016 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2017 | `endif |
| 2018 | |
| 2019 | endmodule |
| 2020 | // -------------------------------------------------- |
| 2021 | // File: cl_a1gb_oai22_4x.behV |
| 2022 | // Auto generated verilog module by HnBCellAuto |
| 2023 | // |
| 2024 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 2025 | // By: balmiki |
| 2026 | // -------------------------------------------------- |
| 2027 | // |
| 2028 | module cl_a1gb_oai22_4x ( |
| 2029 | out, |
| 2030 | in10, |
| 2031 | in11, |
| 2032 | in00, |
| 2033 | in01 ); |
| 2034 | |
| 2035 | output out; |
| 2036 | input in10; |
| 2037 | input in11; |
| 2038 | input in00; |
| 2039 | input in01; |
| 2040 | |
| 2041 | `ifdef LIB |
| 2042 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2043 | `endif |
| 2044 | |
| 2045 | endmodule |
| 2046 | // -------------------------------------------------- |
| 2047 | // File: cl_a1gb_oai22_8x.behV |
| 2048 | // Auto generated verilog module by HnBCellAuto |
| 2049 | // |
| 2050 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 2051 | // By: balmiki |
| 2052 | // -------------------------------------------------- |
| 2053 | // |
| 2054 | module cl_a1gb_oai22_8x ( |
| 2055 | out, |
| 2056 | in10, |
| 2057 | in11, |
| 2058 | in00, |
| 2059 | in01 ); |
| 2060 | |
| 2061 | output out; |
| 2062 | input in10; |
| 2063 | input in11; |
| 2064 | input in00; |
| 2065 | input in01; |
| 2066 | |
| 2067 | `ifdef LIB |
| 2068 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2069 | `endif |
| 2070 | |
| 2071 | endmodule |
| 2072 | module cl_a1gb_xnor2_16x ( |
| 2073 | in0, |
| 2074 | in1, |
| 2075 | out |
| 2076 | ); |
| 2077 | input in0; |
| 2078 | input in1; |
| 2079 | output out; |
| 2080 | |
| 2081 | `ifdef LIB |
| 2082 | assign out = ~(in0 ^ in1); |
| 2083 | `endif |
| 2084 | |
| 2085 | endmodule |
| 2086 | |
| 2087 | module cl_a1gb_xnor2_1x ( |
| 2088 | in0, |
| 2089 | in1, |
| 2090 | out |
| 2091 | ); |
| 2092 | input in0; |
| 2093 | input in1; |
| 2094 | output out; |
| 2095 | |
| 2096 | `ifdef LIB |
| 2097 | assign out = ~(in0 ^ in1); |
| 2098 | `endif |
| 2099 | |
| 2100 | endmodule |
| 2101 | module cl_a1gb_xnor2_2x ( |
| 2102 | in0, |
| 2103 | in1, |
| 2104 | out |
| 2105 | ); |
| 2106 | input in0; |
| 2107 | input in1; |
| 2108 | output out; |
| 2109 | |
| 2110 | `ifdef LIB |
| 2111 | assign out = ~(in0 ^ in1); |
| 2112 | `endif |
| 2113 | |
| 2114 | endmodule |
| 2115 | module cl_a1gb_xnor2_4x ( |
| 2116 | in0, |
| 2117 | in1, |
| 2118 | out |
| 2119 | ); |
| 2120 | input in0; |
| 2121 | input in1; |
| 2122 | output out; |
| 2123 | |
| 2124 | `ifdef LIB |
| 2125 | assign out = ~(in0 ^ in1); |
| 2126 | `endif |
| 2127 | |
| 2128 | endmodule |
| 2129 | module cl_a1gb_xnor2_6x ( |
| 2130 | in0, |
| 2131 | in1, |
| 2132 | out |
| 2133 | ); |
| 2134 | input in0; |
| 2135 | input in1; |
| 2136 | output out; |
| 2137 | |
| 2138 | `ifdef LIB |
| 2139 | assign out = ~(in0 ^ in1); |
| 2140 | `endif |
| 2141 | |
| 2142 | endmodule |
| 2143 | module cl_a1gb_xnor2_8x ( |
| 2144 | in0, |
| 2145 | in1, |
| 2146 | out |
| 2147 | ); |
| 2148 | input in0; |
| 2149 | input in1; |
| 2150 | output out; |
| 2151 | |
| 2152 | `ifdef LIB |
| 2153 | assign out = ~(in0 ^ in1); |
| 2154 | `endif |
| 2155 | |
| 2156 | endmodule |
| 2157 | |
| 2158 | module cl_a1gb_xnor3_16x ( |
| 2159 | in0, |
| 2160 | in1, |
| 2161 | in2, |
| 2162 | out |
| 2163 | ); |
| 2164 | input in0; |
| 2165 | input in1; |
| 2166 | input in2; |
| 2167 | output out; |
| 2168 | |
| 2169 | `ifdef LIB |
| 2170 | assign out = ~(in0 ^ in1 ^ in2); |
| 2171 | `endif |
| 2172 | |
| 2173 | |
| 2174 | |
| 2175 | endmodule |
| 2176 | module cl_a1gb_xnor3_1x ( |
| 2177 | in0, |
| 2178 | in1, |
| 2179 | in2, |
| 2180 | out |
| 2181 | ); |
| 2182 | input in0; |
| 2183 | input in1; |
| 2184 | input in2; |
| 2185 | output out; |
| 2186 | |
| 2187 | `ifdef LIB |
| 2188 | assign out = ~(in0 ^ in1 ^ in2); |
| 2189 | `endif |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | endmodule |
| 2194 | module cl_a1gb_xnor3_2x ( |
| 2195 | in0, |
| 2196 | in1, |
| 2197 | in2, |
| 2198 | out |
| 2199 | ); |
| 2200 | input in0; |
| 2201 | input in1; |
| 2202 | input in2; |
| 2203 | output out; |
| 2204 | |
| 2205 | `ifdef LIB |
| 2206 | assign out = ~(in0 ^ in1 ^ in2); |
| 2207 | `endif |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | endmodule |
| 2212 | module cl_a1gb_xnor3_4x ( |
| 2213 | in0, |
| 2214 | in1, |
| 2215 | in2, |
| 2216 | out |
| 2217 | ); |
| 2218 | input in0; |
| 2219 | input in1; |
| 2220 | input in2; |
| 2221 | output out; |
| 2222 | |
| 2223 | `ifdef LIB |
| 2224 | assign out = ~(in0 ^ in1 ^ in2); |
| 2225 | `endif |
| 2226 | |
| 2227 | |
| 2228 | |
| 2229 | endmodule |
| 2230 | module cl_a1gb_xnor3_6x ( |
| 2231 | in0, |
| 2232 | in1, |
| 2233 | in2, |
| 2234 | out |
| 2235 | ); |
| 2236 | input in0; |
| 2237 | input in1; |
| 2238 | input in2; |
| 2239 | output out; |
| 2240 | |
| 2241 | `ifdef LIB |
| 2242 | assign out = ~(in0 ^ in1 ^ in2); |
| 2243 | `endif |
| 2244 | |
| 2245 | |
| 2246 | |
| 2247 | endmodule |
| 2248 | module cl_a1gb_xnor3_8x ( |
| 2249 | in0, |
| 2250 | in1, |
| 2251 | in2, |
| 2252 | out |
| 2253 | ); |
| 2254 | input in0; |
| 2255 | input in1; |
| 2256 | input in2; |
| 2257 | output out; |
| 2258 | |
| 2259 | `ifdef LIB |
| 2260 | assign out = ~(in0 ^ in1 ^ in2); |
| 2261 | `endif |
| 2262 | |
| 2263 | |
| 2264 | |
| 2265 | endmodule |
| 2266 | module cl_a1gb_xor2_16x ( |
| 2267 | in0, |
| 2268 | in1, |
| 2269 | out |
| 2270 | ); |
| 2271 | input in0; |
| 2272 | input in1; |
| 2273 | output out; |
| 2274 | |
| 2275 | `ifdef LIB |
| 2276 | assign out = in0 ^ in1; |
| 2277 | `endif |
| 2278 | |
| 2279 | endmodule |
| 2280 | |
| 2281 | module cl_a1gb_xor2_1x ( |
| 2282 | in0, |
| 2283 | in1, |
| 2284 | out |
| 2285 | ); |
| 2286 | input in0; |
| 2287 | input in1; |
| 2288 | output out; |
| 2289 | |
| 2290 | `ifdef LIB |
| 2291 | assign out = in0 ^ in1; |
| 2292 | `endif |
| 2293 | |
| 2294 | endmodule |
| 2295 | module cl_a1gb_xor2_2x ( |
| 2296 | in0, |
| 2297 | in1, |
| 2298 | out |
| 2299 | ); |
| 2300 | input in0; |
| 2301 | input in1; |
| 2302 | output out; |
| 2303 | |
| 2304 | `ifdef LIB |
| 2305 | assign out = in0 ^ in1; |
| 2306 | `endif |
| 2307 | |
| 2308 | endmodule |
| 2309 | module cl_a1gb_xor2_4x ( |
| 2310 | in0, |
| 2311 | in1, |
| 2312 | out |
| 2313 | ); |
| 2314 | input in0; |
| 2315 | input in1; |
| 2316 | output out; |
| 2317 | |
| 2318 | `ifdef LIB |
| 2319 | assign out = in0 ^ in1; |
| 2320 | `endif |
| 2321 | |
| 2322 | endmodule |
| 2323 | module cl_a1gb_xor2_6x ( |
| 2324 | in0, |
| 2325 | in1, |
| 2326 | out |
| 2327 | ); |
| 2328 | input in0; |
| 2329 | input in1; |
| 2330 | output out; |
| 2331 | |
| 2332 | `ifdef LIB |
| 2333 | assign out = in0 ^ in1; |
| 2334 | `endif |
| 2335 | |
| 2336 | endmodule |
| 2337 | module cl_a1gb_xor2_8x ( |
| 2338 | in0, |
| 2339 | in1, |
| 2340 | out |
| 2341 | ); |
| 2342 | input in0; |
| 2343 | input in1; |
| 2344 | output out; |
| 2345 | |
| 2346 | `ifdef LIB |
| 2347 | assign out = in0 ^ in1; |
| 2348 | `endif |
| 2349 | |
| 2350 | endmodule |
| 2351 | module cl_a1gb_xor3_16x ( |
| 2352 | in0, |
| 2353 | in1, |
| 2354 | in2, |
| 2355 | out |
| 2356 | ); |
| 2357 | input in0; |
| 2358 | input in1; |
| 2359 | input in2; |
| 2360 | output out; |
| 2361 | |
| 2362 | `ifdef LIB |
| 2363 | assign out = in0 ^ in1 ^ in2; |
| 2364 | `endif |
| 2365 | |
| 2366 | |
| 2367 | endmodule |
| 2368 | |
| 2369 | module cl_a1gb_xor3_1x ( |
| 2370 | in0, |
| 2371 | in1, |
| 2372 | in2, |
| 2373 | out |
| 2374 | ); |
| 2375 | input in0; |
| 2376 | input in1; |
| 2377 | input in2; |
| 2378 | output out; |
| 2379 | |
| 2380 | `ifdef LIB |
| 2381 | assign out = in0 ^ in1 ^ in2; |
| 2382 | `endif |
| 2383 | |
| 2384 | |
| 2385 | endmodule |
| 2386 | module cl_a1gb_xor3_2x ( |
| 2387 | in0, |
| 2388 | in1, |
| 2389 | in2, |
| 2390 | out |
| 2391 | ); |
| 2392 | input in0; |
| 2393 | input in1; |
| 2394 | input in2; |
| 2395 | output out; |
| 2396 | |
| 2397 | `ifdef LIB |
| 2398 | assign out = in0 ^ in1 ^ in2; |
| 2399 | `endif |
| 2400 | |
| 2401 | |
| 2402 | endmodule |
| 2403 | module cl_a1gb_xor3_4x ( |
| 2404 | in0, |
| 2405 | in1, |
| 2406 | in2, |
| 2407 | out |
| 2408 | ); |
| 2409 | input in0; |
| 2410 | input in1; |
| 2411 | input in2; |
| 2412 | output out; |
| 2413 | |
| 2414 | `ifdef LIB |
| 2415 | assign out = in0 ^ in1 ^ in2; |
| 2416 | `endif |
| 2417 | |
| 2418 | |
| 2419 | endmodule |
| 2420 | module cl_a1gb_xor3_6x ( |
| 2421 | in0, |
| 2422 | in1, |
| 2423 | in2, |
| 2424 | out |
| 2425 | ); |
| 2426 | input in0; |
| 2427 | input in1; |
| 2428 | input in2; |
| 2429 | output out; |
| 2430 | |
| 2431 | `ifdef LIB |
| 2432 | assign out = in0 ^ in1 ^ in2; |
| 2433 | `endif |
| 2434 | |
| 2435 | |
| 2436 | endmodule |
| 2437 | module cl_a1gb_xor3_8x ( |
| 2438 | in0, |
| 2439 | in1, |
| 2440 | in2, |
| 2441 | out |
| 2442 | ); |
| 2443 | input in0; |
| 2444 | input in1; |
| 2445 | input in2; |
| 2446 | output out; |
| 2447 | |
| 2448 | `ifdef LIB |
| 2449 | assign out = in0 ^ in1 ^ in2; |
| 2450 | `endif |
| 2451 | |
| 2452 | |
| 2453 | endmodule |
| 2454 | |
| 2455 | module cl_a1gb_rep_32x ( |
| 2456 | in, |
| 2457 | out |
| 2458 | ); |
| 2459 | input in; |
| 2460 | output out; |
| 2461 | |
| 2462 | `ifdef LIB |
| 2463 | //assign out = in; |
| 2464 | buf (out, in); |
| 2465 | `endif |
| 2466 | |
| 2467 | endmodule |
| 2468 | module cl_a1gb_rep_40x ( |
| 2469 | in, |
| 2470 | out |
| 2471 | ); |
| 2472 | input in; |
| 2473 | output out; |
| 2474 | |
| 2475 | `ifdef LIB |
| 2476 | //assign out = in; |
| 2477 | buf (out, in); |
| 2478 | `endif |
| 2479 | |
| 2480 | endmodule |
| 2481 | module cl_a1gb_rep_24x ( |
| 2482 | in, |
| 2483 | out |
| 2484 | ); |
| 2485 | input in; |
| 2486 | output out; |
| 2487 | |
| 2488 | `ifdef LIB |
| 2489 | //assign out = in; |
| 2490 | buf (out, in); |
| 2491 | `endif |
| 2492 | |
| 2493 | endmodule |
| 2494 | module cl_a1gb_rep_16x ( |
| 2495 | in, |
| 2496 | out |
| 2497 | ); |
| 2498 | input in; |
| 2499 | output out; |
| 2500 | |
| 2501 | `ifdef LIB |
| 2502 | //assign out = in; |
| 2503 | buf (out, in); |
| 2504 | `endif |
| 2505 | |
| 2506 | endmodule |
| 2507 | module cl_a1gb_rep_8x ( |
| 2508 | in, |
| 2509 | out |
| 2510 | ); |
| 2511 | input in; |
| 2512 | output out; |
| 2513 | |
| 2514 | `ifdef LIB |
| 2515 | //assign out = in; |
| 2516 | buf (out, in); |
| 2517 | `endif |
| 2518 | |
| 2519 | endmodule |
| 2520 | module cl_a1gb_rep_48x ( |
| 2521 | in, |
| 2522 | out |
| 2523 | ); |
| 2524 | input in; |
| 2525 | output out; |
| 2526 | |
| 2527 | `ifdef LIB |
| 2528 | //assign out = in; |
| 2529 | buf (out, in); |
| 2530 | `endif |
| 2531 | |
| 2532 | endmodule |
| 2533 | |
| 2534 | module cl_a1gb_aomux2_12x ( |
| 2535 | in0, |
| 2536 | in1, |
| 2537 | sel0, |
| 2538 | sel1, |
| 2539 | out |
| 2540 | ); |
| 2541 | input in0; |
| 2542 | input in1; |
| 2543 | input sel0; |
| 2544 | input sel1; |
| 2545 | output out; |
| 2546 | |
| 2547 | `ifdef LIB |
| 2548 | assign out = ((sel0 & in0) | |
| 2549 | (sel1 & in1)); |
| 2550 | `endif |
| 2551 | |
| 2552 | |
| 2553 | endmodule |
| 2554 | module cl_a1gb_aomux2_16x ( |
| 2555 | in0, |
| 2556 | in1, |
| 2557 | sel0, |
| 2558 | sel1, |
| 2559 | out |
| 2560 | ); |
| 2561 | input in0; |
| 2562 | input in1; |
| 2563 | input sel0; |
| 2564 | input sel1; |
| 2565 | output out; |
| 2566 | |
| 2567 | `ifdef LIB |
| 2568 | assign out = ((sel0 & in0) | |
| 2569 | (sel1 & in1)); |
| 2570 | `endif |
| 2571 | |
| 2572 | |
| 2573 | endmodule |
| 2574 | module cl_a1gb_aomux2_1x ( |
| 2575 | in0, |
| 2576 | in1, |
| 2577 | sel0, |
| 2578 | sel1, |
| 2579 | out |
| 2580 | ); |
| 2581 | input in0; |
| 2582 | input in1; |
| 2583 | input sel0; |
| 2584 | input sel1; |
| 2585 | output out; |
| 2586 | |
| 2587 | `ifdef LIB |
| 2588 | assign out = ((sel0 & in0) | |
| 2589 | (sel1 & in1)); |
| 2590 | `endif |
| 2591 | |
| 2592 | |
| 2593 | endmodule |
| 2594 | module cl_a1gb_aomux2_2x ( |
| 2595 | in0, |
| 2596 | in1, |
| 2597 | sel0, |
| 2598 | sel1, |
| 2599 | out |
| 2600 | ); |
| 2601 | input in0; |
| 2602 | input in1; |
| 2603 | input sel0; |
| 2604 | input sel1; |
| 2605 | output out; |
| 2606 | |
| 2607 | `ifdef LIB |
| 2608 | assign out = ((sel0 & in0) | |
| 2609 | (sel1 & in1)); |
| 2610 | `endif |
| 2611 | |
| 2612 | |
| 2613 | endmodule |
| 2614 | module cl_a1gb_aomux2_4x ( |
| 2615 | in0, |
| 2616 | in1, |
| 2617 | sel0, |
| 2618 | sel1, |
| 2619 | out |
| 2620 | ); |
| 2621 | input in0; |
| 2622 | input in1; |
| 2623 | input sel0; |
| 2624 | input sel1; |
| 2625 | output out; |
| 2626 | |
| 2627 | `ifdef LIB |
| 2628 | assign out = ((sel0 & in0) | |
| 2629 | (sel1 & in1)); |
| 2630 | `endif |
| 2631 | |
| 2632 | |
| 2633 | endmodule |
| 2634 | module cl_a1gb_aomux2_6x ( |
| 2635 | in0, |
| 2636 | in1, |
| 2637 | sel0, |
| 2638 | sel1, |
| 2639 | out |
| 2640 | ); |
| 2641 | input in0; |
| 2642 | input in1; |
| 2643 | input sel0; |
| 2644 | input sel1; |
| 2645 | output out; |
| 2646 | |
| 2647 | `ifdef LIB |
| 2648 | assign out = ((sel0 & in0) | |
| 2649 | (sel1 & in1)); |
| 2650 | `endif |
| 2651 | |
| 2652 | |
| 2653 | endmodule |
| 2654 | module cl_a1gb_aomux2_8x ( |
| 2655 | in0, |
| 2656 | in1, |
| 2657 | sel0, |
| 2658 | sel1, |
| 2659 | out |
| 2660 | ); |
| 2661 | input in0; |
| 2662 | input in1; |
| 2663 | input sel0; |
| 2664 | input sel1; |
| 2665 | output out; |
| 2666 | |
| 2667 | `ifdef LIB |
| 2668 | assign out = ((sel0 & in0) | |
| 2669 | (sel1 & in1)); |
| 2670 | `endif |
| 2671 | |
| 2672 | |
| 2673 | endmodule |
| 2674 | module cl_a1gb_aomux3_12x ( |
| 2675 | in0, |
| 2676 | in1, |
| 2677 | in2, |
| 2678 | sel0, |
| 2679 | sel1, |
| 2680 | sel2, |
| 2681 | out |
| 2682 | ); |
| 2683 | input in0; |
| 2684 | input in1; |
| 2685 | input in2; |
| 2686 | input sel0; |
| 2687 | input sel1; |
| 2688 | input sel2; |
| 2689 | output out; |
| 2690 | |
| 2691 | `ifdef LIB |
| 2692 | assign out = ((sel0 & in0) | |
| 2693 | (sel1 & in1) | |
| 2694 | (sel2 & in2)); |
| 2695 | `endif |
| 2696 | |
| 2697 | endmodule |
| 2698 | module cl_a1gb_aomux3_16x ( |
| 2699 | in0, |
| 2700 | in1, |
| 2701 | in2, |
| 2702 | sel0, |
| 2703 | sel1, |
| 2704 | sel2, |
| 2705 | out |
| 2706 | ); |
| 2707 | input in0; |
| 2708 | input in1; |
| 2709 | input in2; |
| 2710 | input sel0; |
| 2711 | input sel1; |
| 2712 | input sel2; |
| 2713 | output out; |
| 2714 | |
| 2715 | `ifdef LIB |
| 2716 | assign out = ((sel0 & in0) | |
| 2717 | (sel1 & in1) | |
| 2718 | (sel2 & in2)); |
| 2719 | `endif |
| 2720 | |
| 2721 | endmodule |
| 2722 | module cl_a1gb_aomux3_1x ( |
| 2723 | in0, |
| 2724 | in1, |
| 2725 | in2, |
| 2726 | sel0, |
| 2727 | sel1, |
| 2728 | sel2, |
| 2729 | out |
| 2730 | ); |
| 2731 | input in0; |
| 2732 | input in1; |
| 2733 | input in2; |
| 2734 | input sel0; |
| 2735 | input sel1; |
| 2736 | input sel2; |
| 2737 | output out; |
| 2738 | |
| 2739 | `ifdef LIB |
| 2740 | assign out = ((sel0 & in0) | |
| 2741 | (sel1 & in1) | |
| 2742 | (sel2 & in2)); |
| 2743 | `endif |
| 2744 | |
| 2745 | endmodule |
| 2746 | module cl_a1gb_aomux3_2x ( |
| 2747 | in0, |
| 2748 | in1, |
| 2749 | in2, |
| 2750 | sel0, |
| 2751 | sel1, |
| 2752 | sel2, |
| 2753 | out |
| 2754 | ); |
| 2755 | input in0; |
| 2756 | input in1; |
| 2757 | input in2; |
| 2758 | input sel0; |
| 2759 | input sel1; |
| 2760 | input sel2; |
| 2761 | output out; |
| 2762 | |
| 2763 | `ifdef LIB |
| 2764 | assign out = ((sel0 & in0) | |
| 2765 | (sel1 & in1) | |
| 2766 | (sel2 & in2)); |
| 2767 | `endif |
| 2768 | |
| 2769 | endmodule |
| 2770 | module cl_a1gb_aomux3_4x ( |
| 2771 | in0, |
| 2772 | in1, |
| 2773 | in2, |
| 2774 | sel0, |
| 2775 | sel1, |
| 2776 | sel2, |
| 2777 | out |
| 2778 | ); |
| 2779 | input in0; |
| 2780 | input in1; |
| 2781 | input in2; |
| 2782 | input sel0; |
| 2783 | input sel1; |
| 2784 | input sel2; |
| 2785 | output out; |
| 2786 | |
| 2787 | `ifdef LIB |
| 2788 | assign out = ((sel0 & in0) | |
| 2789 | (sel1 & in1) | |
| 2790 | (sel2 & in2)); |
| 2791 | `endif |
| 2792 | |
| 2793 | endmodule |
| 2794 | module cl_a1gb_aomux3_6x ( |
| 2795 | in0, |
| 2796 | in1, |
| 2797 | in2, |
| 2798 | sel0, |
| 2799 | sel1, |
| 2800 | sel2, |
| 2801 | out |
| 2802 | ); |
| 2803 | input in0; |
| 2804 | input in1; |
| 2805 | input in2; |
| 2806 | input sel0; |
| 2807 | input sel1; |
| 2808 | input sel2; |
| 2809 | output out; |
| 2810 | |
| 2811 | `ifdef LIB |
| 2812 | assign out = ((sel0 & in0) | |
| 2813 | (sel1 & in1) | |
| 2814 | (sel2 & in2)); |
| 2815 | `endif |
| 2816 | |
| 2817 | endmodule |
| 2818 | module cl_a1gb_aomux3_8x ( |
| 2819 | in0, |
| 2820 | in1, |
| 2821 | in2, |
| 2822 | sel0, |
| 2823 | sel1, |
| 2824 | sel2, |
| 2825 | out |
| 2826 | ); |
| 2827 | input in0; |
| 2828 | input in1; |
| 2829 | input in2; |
| 2830 | input sel0; |
| 2831 | input sel1; |
| 2832 | input sel2; |
| 2833 | output out; |
| 2834 | |
| 2835 | `ifdef LIB |
| 2836 | assign out = ((sel0 & in0) | |
| 2837 | (sel1 & in1) | |
| 2838 | (sel2 & in2)); |
| 2839 | `endif |
| 2840 | |
| 2841 | endmodule |
| 2842 | module cl_a1gb_aomux4_12x ( |
| 2843 | in0, |
| 2844 | in1, |
| 2845 | in2, |
| 2846 | in3, |
| 2847 | sel0, |
| 2848 | sel1, |
| 2849 | sel2, |
| 2850 | sel3, |
| 2851 | out |
| 2852 | ); |
| 2853 | input in0; |
| 2854 | input in1; |
| 2855 | input in2; |
| 2856 | input in3; |
| 2857 | input sel0; |
| 2858 | input sel1; |
| 2859 | input sel2; |
| 2860 | input sel3; |
| 2861 | output out; |
| 2862 | |
| 2863 | `ifdef LIB |
| 2864 | assign out = ((sel0 & in0) | |
| 2865 | (sel1 & in1) | |
| 2866 | (sel2 & in2) | |
| 2867 | (sel3 & in3)); |
| 2868 | `endif |
| 2869 | |
| 2870 | endmodule |
| 2871 | module cl_a1gb_aomux4_16x ( |
| 2872 | in0, |
| 2873 | in1, |
| 2874 | in2, |
| 2875 | in3, |
| 2876 | sel0, |
| 2877 | sel1, |
| 2878 | sel2, |
| 2879 | sel3, |
| 2880 | out |
| 2881 | ); |
| 2882 | input in0; |
| 2883 | input in1; |
| 2884 | input in2; |
| 2885 | input in3; |
| 2886 | input sel0; |
| 2887 | input sel1; |
| 2888 | input sel2; |
| 2889 | input sel3; |
| 2890 | output out; |
| 2891 | |
| 2892 | `ifdef LIB |
| 2893 | assign out = ((sel0 & in0) | |
| 2894 | (sel1 & in1) | |
| 2895 | (sel2 & in2) | |
| 2896 | (sel3 & in3)); |
| 2897 | `endif |
| 2898 | |
| 2899 | endmodule |
| 2900 | module cl_a1gb_aomux4_1x ( |
| 2901 | in0, |
| 2902 | in1, |
| 2903 | in2, |
| 2904 | in3, |
| 2905 | sel0, |
| 2906 | sel1, |
| 2907 | sel2, |
| 2908 | sel3, |
| 2909 | out |
| 2910 | ); |
| 2911 | input in0; |
| 2912 | input in1; |
| 2913 | input in2; |
| 2914 | input in3; |
| 2915 | input sel0; |
| 2916 | input sel1; |
| 2917 | input sel2; |
| 2918 | input sel3; |
| 2919 | output out; |
| 2920 | |
| 2921 | `ifdef LIB |
| 2922 | assign out = ((sel0 & in0) | |
| 2923 | (sel1 & in1) | |
| 2924 | (sel2 & in2) | |
| 2925 | (sel3 & in3)); |
| 2926 | `endif |
| 2927 | |
| 2928 | endmodule |
| 2929 | module cl_a1gb_aomux4_2x ( |
| 2930 | in0, |
| 2931 | in1, |
| 2932 | in2, |
| 2933 | in3, |
| 2934 | sel0, |
| 2935 | sel1, |
| 2936 | sel2, |
| 2937 | sel3, |
| 2938 | out |
| 2939 | ); |
| 2940 | input in0; |
| 2941 | input in1; |
| 2942 | input in2; |
| 2943 | input in3; |
| 2944 | input sel0; |
| 2945 | input sel1; |
| 2946 | input sel2; |
| 2947 | input sel3; |
| 2948 | output out; |
| 2949 | |
| 2950 | `ifdef LIB |
| 2951 | assign out = ((sel0 & in0) | |
| 2952 | (sel1 & in1) | |
| 2953 | (sel2 & in2) | |
| 2954 | (sel3 & in3)); |
| 2955 | `endif |
| 2956 | |
| 2957 | endmodule |
| 2958 | module cl_a1gb_aomux4_4x ( |
| 2959 | in0, |
| 2960 | in1, |
| 2961 | in2, |
| 2962 | in3, |
| 2963 | sel0, |
| 2964 | sel1, |
| 2965 | sel2, |
| 2966 | sel3, |
| 2967 | out |
| 2968 | ); |
| 2969 | input in0; |
| 2970 | input in1; |
| 2971 | input in2; |
| 2972 | input in3; |
| 2973 | input sel0; |
| 2974 | input sel1; |
| 2975 | input sel2; |
| 2976 | input sel3; |
| 2977 | output out; |
| 2978 | |
| 2979 | `ifdef LIB |
| 2980 | assign out = ((sel0 & in0) | |
| 2981 | (sel1 & in1) | |
| 2982 | (sel2 & in2) | |
| 2983 | (sel3 & in3)); |
| 2984 | `endif |
| 2985 | |
| 2986 | endmodule |
| 2987 | module cl_a1gb_aomux4_6x ( |
| 2988 | in0, |
| 2989 | in1, |
| 2990 | in2, |
| 2991 | in3, |
| 2992 | sel0, |
| 2993 | sel1, |
| 2994 | sel2, |
| 2995 | sel3, |
| 2996 | out |
| 2997 | ); |
| 2998 | input in0; |
| 2999 | input in1; |
| 3000 | input in2; |
| 3001 | input in3; |
| 3002 | input sel0; |
| 3003 | input sel1; |
| 3004 | input sel2; |
| 3005 | input sel3; |
| 3006 | output out; |
| 3007 | |
| 3008 | `ifdef LIB |
| 3009 | assign out = ((sel0 & in0) | |
| 3010 | (sel1 & in1) | |
| 3011 | (sel2 & in2) | |
| 3012 | (sel3 & in3)); |
| 3013 | `endif |
| 3014 | |
| 3015 | endmodule |
| 3016 | module cl_a1gb_aomux4_8x ( |
| 3017 | in0, |
| 3018 | in1, |
| 3019 | in2, |
| 3020 | in3, |
| 3021 | sel0, |
| 3022 | sel1, |
| 3023 | sel2, |
| 3024 | sel3, |
| 3025 | out |
| 3026 | ); |
| 3027 | input in0; |
| 3028 | input in1; |
| 3029 | input in2; |
| 3030 | input in3; |
| 3031 | input sel0; |
| 3032 | input sel1; |
| 3033 | input sel2; |
| 3034 | input sel3; |
| 3035 | output out; |
| 3036 | |
| 3037 | `ifdef LIB |
| 3038 | assign out = ((sel0 & in0) | |
| 3039 | (sel1 & in1) | |
| 3040 | (sel2 & in2) | |
| 3041 | (sel3 & in3)); |
| 3042 | `endif |
| 3043 | |
| 3044 | endmodule |
| 3045 | module cl_a1gb_aomux5_12x ( |
| 3046 | in0, |
| 3047 | in1, |
| 3048 | in2, |
| 3049 | in3, |
| 3050 | in4, |
| 3051 | sel0, |
| 3052 | sel1, |
| 3053 | sel2, |
| 3054 | sel3, |
| 3055 | sel4, |
| 3056 | out |
| 3057 | ); |
| 3058 | input in0; |
| 3059 | input in1; |
| 3060 | input in2; |
| 3061 | input in3; |
| 3062 | input in4; |
| 3063 | input sel0; |
| 3064 | input sel1; |
| 3065 | input sel2; |
| 3066 | input sel3; |
| 3067 | input sel4; |
| 3068 | output out; |
| 3069 | |
| 3070 | `ifdef LIB |
| 3071 | assign out = ((sel0 & in0) | |
| 3072 | (sel1 & in1) | |
| 3073 | (sel2 & in2) | |
| 3074 | (sel3 & in3) | |
| 3075 | (sel4 & in4)); |
| 3076 | `endif |
| 3077 | |
| 3078 | endmodule |
| 3079 | module cl_a1gb_aomux5_16x ( |
| 3080 | in0, |
| 3081 | in1, |
| 3082 | in2, |
| 3083 | in3, |
| 3084 | in4, |
| 3085 | sel0, |
| 3086 | sel1, |
| 3087 | sel2, |
| 3088 | sel3, |
| 3089 | sel4, |
| 3090 | out |
| 3091 | ); |
| 3092 | input in0; |
| 3093 | input in1; |
| 3094 | input in2; |
| 3095 | input in3; |
| 3096 | input in4; |
| 3097 | input sel0; |
| 3098 | input sel1; |
| 3099 | input sel2; |
| 3100 | input sel3; |
| 3101 | input sel4; |
| 3102 | output out; |
| 3103 | |
| 3104 | `ifdef LIB |
| 3105 | assign out = ((sel0 & in0) | |
| 3106 | (sel1 & in1) | |
| 3107 | (sel2 & in2) | |
| 3108 | (sel3 & in3) | |
| 3109 | (sel4 & in4)); |
| 3110 | `endif |
| 3111 | |
| 3112 | endmodule |
| 3113 | module cl_a1gb_aomux5_1x ( |
| 3114 | in0, |
| 3115 | in1, |
| 3116 | in2, |
| 3117 | in3, |
| 3118 | in4, |
| 3119 | sel0, |
| 3120 | sel1, |
| 3121 | sel2, |
| 3122 | sel3, |
| 3123 | sel4, |
| 3124 | out |
| 3125 | ); |
| 3126 | input in0; |
| 3127 | input in1; |
| 3128 | input in2; |
| 3129 | input in3; |
| 3130 | input in4; |
| 3131 | input sel0; |
| 3132 | input sel1; |
| 3133 | input sel2; |
| 3134 | input sel3; |
| 3135 | input sel4; |
| 3136 | output out; |
| 3137 | |
| 3138 | `ifdef LIB |
| 3139 | assign out = ((sel0 & in0) | |
| 3140 | (sel1 & in1) | |
| 3141 | (sel2 & in2) | |
| 3142 | (sel3 & in3) | |
| 3143 | (sel4 & in4)); |
| 3144 | `endif |
| 3145 | |
| 3146 | endmodule |
| 3147 | module cl_a1gb_aomux5_2x ( |
| 3148 | in0, |
| 3149 | in1, |
| 3150 | in2, |
| 3151 | in3, |
| 3152 | in4, |
| 3153 | sel0, |
| 3154 | sel1, |
| 3155 | sel2, |
| 3156 | sel3, |
| 3157 | sel4, |
| 3158 | out |
| 3159 | ); |
| 3160 | input in0; |
| 3161 | input in1; |
| 3162 | input in2; |
| 3163 | input in3; |
| 3164 | input in4; |
| 3165 | input sel0; |
| 3166 | input sel1; |
| 3167 | input sel2; |
| 3168 | input sel3; |
| 3169 | input sel4; |
| 3170 | output out; |
| 3171 | |
| 3172 | `ifdef LIB |
| 3173 | assign out = ((sel0 & in0) | |
| 3174 | (sel1 & in1) | |
| 3175 | (sel2 & in2) | |
| 3176 | (sel3 & in3) | |
| 3177 | (sel4 & in4)); |
| 3178 | `endif |
| 3179 | |
| 3180 | endmodule |
| 3181 | module cl_a1gb_aomux5_4x ( |
| 3182 | in0, |
| 3183 | in1, |
| 3184 | in2, |
| 3185 | in3, |
| 3186 | in4, |
| 3187 | sel0, |
| 3188 | sel1, |
| 3189 | sel2, |
| 3190 | sel3, |
| 3191 | sel4, |
| 3192 | out |
| 3193 | ); |
| 3194 | input in0; |
| 3195 | input in1; |
| 3196 | input in2; |
| 3197 | input in3; |
| 3198 | input in4; |
| 3199 | input sel0; |
| 3200 | input sel1; |
| 3201 | input sel2; |
| 3202 | input sel3; |
| 3203 | input sel4; |
| 3204 | output out; |
| 3205 | |
| 3206 | `ifdef LIB |
| 3207 | assign out = ((sel0 & in0) | |
| 3208 | (sel1 & in1) | |
| 3209 | (sel2 & in2) | |
| 3210 | (sel3 & in3) | |
| 3211 | (sel4 & in4)); |
| 3212 | `endif |
| 3213 | |
| 3214 | endmodule |
| 3215 | module cl_a1gb_aomux5_6x ( |
| 3216 | in0, |
| 3217 | in1, |
| 3218 | in2, |
| 3219 | in3, |
| 3220 | in4, |
| 3221 | sel0, |
| 3222 | sel1, |
| 3223 | sel2, |
| 3224 | sel3, |
| 3225 | sel4, |
| 3226 | out |
| 3227 | ); |
| 3228 | input in0; |
| 3229 | input in1; |
| 3230 | input in2; |
| 3231 | input in3; |
| 3232 | input in4; |
| 3233 | input sel0; |
| 3234 | input sel1; |
| 3235 | input sel2; |
| 3236 | input sel3; |
| 3237 | input sel4; |
| 3238 | output out; |
| 3239 | |
| 3240 | `ifdef LIB |
| 3241 | assign out = ((sel0 & in0) | |
| 3242 | (sel1 & in1) | |
| 3243 | (sel2 & in2) | |
| 3244 | (sel3 & in3) | |
| 3245 | (sel4 & in4)); |
| 3246 | `endif |
| 3247 | |
| 3248 | endmodule |
| 3249 | module cl_a1gb_aomux5_8x ( |
| 3250 | in0, |
| 3251 | in1, |
| 3252 | in2, |
| 3253 | in3, |
| 3254 | in4, |
| 3255 | sel0, |
| 3256 | sel1, |
| 3257 | sel2, |
| 3258 | sel3, |
| 3259 | sel4, |
| 3260 | out |
| 3261 | ); |
| 3262 | input in0; |
| 3263 | input in1; |
| 3264 | input in2; |
| 3265 | input in3; |
| 3266 | input in4; |
| 3267 | input sel0; |
| 3268 | input sel1; |
| 3269 | input sel2; |
| 3270 | input sel3; |
| 3271 | input sel4; |
| 3272 | output out; |
| 3273 | |
| 3274 | `ifdef LIB |
| 3275 | assign out = ((sel0 & in0) | |
| 3276 | (sel1 & in1) | |
| 3277 | (sel2 & in2) | |
| 3278 | (sel3 & in3) | |
| 3279 | (sel4 & in4)); |
| 3280 | `endif |
| 3281 | |
| 3282 | endmodule |
| 3283 | module cl_a1gb_aomux6_12x ( |
| 3284 | in0, |
| 3285 | in1, |
| 3286 | in2, |
| 3287 | in3, |
| 3288 | in4, |
| 3289 | in5, |
| 3290 | sel0, |
| 3291 | sel1, |
| 3292 | sel2, |
| 3293 | sel3, |
| 3294 | sel4, |
| 3295 | sel5, |
| 3296 | out |
| 3297 | ); |
| 3298 | input in0; |
| 3299 | input in1; |
| 3300 | input in2; |
| 3301 | input in3; |
| 3302 | input in4; |
| 3303 | input in5; |
| 3304 | input sel0; |
| 3305 | input sel1; |
| 3306 | input sel2; |
| 3307 | input sel3; |
| 3308 | input sel4; |
| 3309 | input sel5; |
| 3310 | output out; |
| 3311 | |
| 3312 | `ifdef LIB |
| 3313 | assign out = ((sel0 & in0) | |
| 3314 | (sel1 & in1) | |
| 3315 | (sel2 & in2) | |
| 3316 | (sel3 & in3) | |
| 3317 | (sel4 & in4) | |
| 3318 | (sel5 & in5)); |
| 3319 | `endif |
| 3320 | |
| 3321 | endmodule |
| 3322 | module cl_a1gb_aomux6_16x ( |
| 3323 | in0, |
| 3324 | in1, |
| 3325 | in2, |
| 3326 | in3, |
| 3327 | in4, |
| 3328 | in5, |
| 3329 | sel0, |
| 3330 | sel1, |
| 3331 | sel2, |
| 3332 | sel3, |
| 3333 | sel4, |
| 3334 | sel5, |
| 3335 | out |
| 3336 | ); |
| 3337 | input in0; |
| 3338 | input in1; |
| 3339 | input in2; |
| 3340 | input in3; |
| 3341 | input in4; |
| 3342 | input in5; |
| 3343 | input sel0; |
| 3344 | input sel1; |
| 3345 | input sel2; |
| 3346 | input sel3; |
| 3347 | input sel4; |
| 3348 | input sel5; |
| 3349 | output out; |
| 3350 | |
| 3351 | `ifdef LIB |
| 3352 | assign out = ((sel0 & in0) | |
| 3353 | (sel1 & in1) | |
| 3354 | (sel2 & in2) | |
| 3355 | (sel3 & in3) | |
| 3356 | (sel4 & in4) | |
| 3357 | (sel5 & in5)); |
| 3358 | `endif |
| 3359 | |
| 3360 | endmodule |
| 3361 | module cl_a1gb_aomux6_1x ( |
| 3362 | in0, |
| 3363 | in1, |
| 3364 | in2, |
| 3365 | in3, |
| 3366 | in4, |
| 3367 | in5, |
| 3368 | sel0, |
| 3369 | sel1, |
| 3370 | sel2, |
| 3371 | sel3, |
| 3372 | sel4, |
| 3373 | sel5, |
| 3374 | out |
| 3375 | ); |
| 3376 | input in0; |
| 3377 | input in1; |
| 3378 | input in2; |
| 3379 | input in3; |
| 3380 | input in4; |
| 3381 | input in5; |
| 3382 | input sel0; |
| 3383 | input sel1; |
| 3384 | input sel2; |
| 3385 | input sel3; |
| 3386 | input sel4; |
| 3387 | input sel5; |
| 3388 | output out; |
| 3389 | |
| 3390 | `ifdef LIB |
| 3391 | assign out = ((sel0 & in0) | |
| 3392 | (sel1 & in1) | |
| 3393 | (sel2 & in2) | |
| 3394 | (sel3 & in3) | |
| 3395 | (sel4 & in4) | |
| 3396 | (sel5 & in5)); |
| 3397 | `endif |
| 3398 | |
| 3399 | endmodule |
| 3400 | module cl_a1gb_aomux6_2x ( |
| 3401 | in0, |
| 3402 | in1, |
| 3403 | in2, |
| 3404 | in3, |
| 3405 | in4, |
| 3406 | in5, |
| 3407 | sel0, |
| 3408 | sel1, |
| 3409 | sel2, |
| 3410 | sel3, |
| 3411 | sel4, |
| 3412 | sel5, |
| 3413 | out |
| 3414 | ); |
| 3415 | input in0; |
| 3416 | input in1; |
| 3417 | input in2; |
| 3418 | input in3; |
| 3419 | input in4; |
| 3420 | input in5; |
| 3421 | input sel0; |
| 3422 | input sel1; |
| 3423 | input sel2; |
| 3424 | input sel3; |
| 3425 | input sel4; |
| 3426 | input sel5; |
| 3427 | output out; |
| 3428 | |
| 3429 | `ifdef LIB |
| 3430 | assign out = ((sel0 & in0) | |
| 3431 | (sel1 & in1) | |
| 3432 | (sel2 & in2) | |
| 3433 | (sel3 & in3) | |
| 3434 | (sel4 & in4) | |
| 3435 | (sel5 & in5)); |
| 3436 | `endif |
| 3437 | |
| 3438 | endmodule |
| 3439 | module cl_a1gb_aomux6_4x ( |
| 3440 | in0, |
| 3441 | in1, |
| 3442 | in2, |
| 3443 | in3, |
| 3444 | in4, |
| 3445 | in5, |
| 3446 | sel0, |
| 3447 | sel1, |
| 3448 | sel2, |
| 3449 | sel3, |
| 3450 | sel4, |
| 3451 | sel5, |
| 3452 | out |
| 3453 | ); |
| 3454 | input in0; |
| 3455 | input in1; |
| 3456 | input in2; |
| 3457 | input in3; |
| 3458 | input in4; |
| 3459 | input in5; |
| 3460 | input sel0; |
| 3461 | input sel1; |
| 3462 | input sel2; |
| 3463 | input sel3; |
| 3464 | input sel4; |
| 3465 | input sel5; |
| 3466 | output out; |
| 3467 | |
| 3468 | `ifdef LIB |
| 3469 | assign out = ((sel0 & in0) | |
| 3470 | (sel1 & in1) | |
| 3471 | (sel2 & in2) | |
| 3472 | (sel3 & in3) | |
| 3473 | (sel4 & in4) | |
| 3474 | (sel5 & in5)); |
| 3475 | `endif |
| 3476 | |
| 3477 | endmodule |
| 3478 | module cl_a1gb_aomux6_6x ( |
| 3479 | in0, |
| 3480 | in1, |
| 3481 | in2, |
| 3482 | in3, |
| 3483 | in4, |
| 3484 | in5, |
| 3485 | sel0, |
| 3486 | sel1, |
| 3487 | sel2, |
| 3488 | sel3, |
| 3489 | sel4, |
| 3490 | sel5, |
| 3491 | out |
| 3492 | ); |
| 3493 | input in0; |
| 3494 | input in1; |
| 3495 | input in2; |
| 3496 | input in3; |
| 3497 | input in4; |
| 3498 | input in5; |
| 3499 | input sel0; |
| 3500 | input sel1; |
| 3501 | input sel2; |
| 3502 | input sel3; |
| 3503 | input sel4; |
| 3504 | input sel5; |
| 3505 | output out; |
| 3506 | |
| 3507 | `ifdef LIB |
| 3508 | assign out = ((sel0 & in0) | |
| 3509 | (sel1 & in1) | |
| 3510 | (sel2 & in2) | |
| 3511 | (sel3 & in3) | |
| 3512 | (sel4 & in4) | |
| 3513 | (sel5 & in5)); |
| 3514 | `endif |
| 3515 | |
| 3516 | endmodule |
| 3517 | module cl_a1gb_aomux6_8x ( |
| 3518 | in0, |
| 3519 | in1, |
| 3520 | in2, |
| 3521 | in3, |
| 3522 | in4, |
| 3523 | in5, |
| 3524 | sel0, |
| 3525 | sel1, |
| 3526 | sel2, |
| 3527 | sel3, |
| 3528 | sel4, |
| 3529 | sel5, |
| 3530 | out |
| 3531 | ); |
| 3532 | input in0; |
| 3533 | input in1; |
| 3534 | input in2; |
| 3535 | input in3; |
| 3536 | input in4; |
| 3537 | input in5; |
| 3538 | input sel0; |
| 3539 | input sel1; |
| 3540 | input sel2; |
| 3541 | input sel3; |
| 3542 | input sel4; |
| 3543 | input sel5; |
| 3544 | output out; |
| 3545 | |
| 3546 | `ifdef LIB |
| 3547 | assign out = ((sel0 & in0) | |
| 3548 | (sel1 & in1) | |
| 3549 | (sel2 & in2) | |
| 3550 | (sel3 & in3) | |
| 3551 | (sel4 & in4) | |
| 3552 | (sel5 & in5)); |
| 3553 | `endif |
| 3554 | |
| 3555 | endmodule |
| 3556 | module cl_a1gb_aomux6_by2_1x ( |
| 3557 | in0, |
| 3558 | in1, |
| 3559 | in2, |
| 3560 | in3, |
| 3561 | in4, |
| 3562 | in5, |
| 3563 | sel0, |
| 3564 | sel1, |
| 3565 | sel2, |
| 3566 | sel3, |
| 3567 | sel4, |
| 3568 | sel5, |
| 3569 | out |
| 3570 | ); |
| 3571 | input in0; |
| 3572 | input in1; |
| 3573 | input in2; |
| 3574 | input in3; |
| 3575 | input in4; |
| 3576 | input in5; |
| 3577 | input sel0; |
| 3578 | input sel1; |
| 3579 | input sel2; |
| 3580 | input sel3; |
| 3581 | input sel4; |
| 3582 | input sel5; |
| 3583 | output out; |
| 3584 | |
| 3585 | `ifdef LIB |
| 3586 | assign out = ((sel0 & in0) | |
| 3587 | (sel1 & in1) | |
| 3588 | (sel2 & in2) | |
| 3589 | (sel3 & in3) | |
| 3590 | (sel4 & in4) | |
| 3591 | (sel5 & in5)); |
| 3592 | `endif |
| 3593 | |
| 3594 | endmodule |
| 3595 | module cl_a1gb_aomux6_by2_2x ( |
| 3596 | in0, |
| 3597 | in1, |
| 3598 | in2, |
| 3599 | in3, |
| 3600 | in4, |
| 3601 | in5, |
| 3602 | sel0, |
| 3603 | sel1, |
| 3604 | sel2, |
| 3605 | sel3, |
| 3606 | sel4, |
| 3607 | sel5, |
| 3608 | out |
| 3609 | ); |
| 3610 | input in0; |
| 3611 | input in1; |
| 3612 | input in2; |
| 3613 | input in3; |
| 3614 | input in4; |
| 3615 | input in5; |
| 3616 | input sel0; |
| 3617 | input sel1; |
| 3618 | input sel2; |
| 3619 | input sel3; |
| 3620 | input sel4; |
| 3621 | input sel5; |
| 3622 | output out; |
| 3623 | |
| 3624 | `ifdef LIB |
| 3625 | assign out = ((sel0 & in0) | |
| 3626 | (sel1 & in1) | |
| 3627 | (sel2 & in2) | |
| 3628 | (sel3 & in3) | |
| 3629 | (sel4 & in4) | |
| 3630 | (sel5 & in5)); |
| 3631 | `endif |
| 3632 | |
| 3633 | endmodule |
| 3634 | module cl_a1gb_aomux7_12x ( |
| 3635 | in0, |
| 3636 | in1, |
| 3637 | in2, |
| 3638 | in3, |
| 3639 | in4, |
| 3640 | in5, |
| 3641 | in6, |
| 3642 | sel0, |
| 3643 | sel1, |
| 3644 | sel2, |
| 3645 | sel3, |
| 3646 | sel4, |
| 3647 | sel5, |
| 3648 | sel6, |
| 3649 | out |
| 3650 | ); |
| 3651 | input in0; |
| 3652 | input in1; |
| 3653 | input in2; |
| 3654 | input in3; |
| 3655 | input in4; |
| 3656 | input in5; |
| 3657 | input in6; |
| 3658 | input sel0; |
| 3659 | input sel1; |
| 3660 | input sel2; |
| 3661 | input sel3; |
| 3662 | input sel4; |
| 3663 | input sel5; |
| 3664 | input sel6; |
| 3665 | output out; |
| 3666 | |
| 3667 | `ifdef LIB |
| 3668 | assign out = ((sel0 & in0) | |
| 3669 | (sel1 & in1) | |
| 3670 | (sel2 & in2) | |
| 3671 | (sel3 & in3) | |
| 3672 | (sel4 & in4) | |
| 3673 | (sel5 & in5) | |
| 3674 | (sel6 & in6)); |
| 3675 | `endif |
| 3676 | |
| 3677 | endmodule |
| 3678 | module cl_a1gb_aomux7_16x ( |
| 3679 | in0, |
| 3680 | in1, |
| 3681 | in2, |
| 3682 | in3, |
| 3683 | in4, |
| 3684 | in5, |
| 3685 | in6, |
| 3686 | sel0, |
| 3687 | sel1, |
| 3688 | sel2, |
| 3689 | sel3, |
| 3690 | sel4, |
| 3691 | sel5, |
| 3692 | sel6, |
| 3693 | out |
| 3694 | ); |
| 3695 | input in0; |
| 3696 | input in1; |
| 3697 | input in2; |
| 3698 | input in3; |
| 3699 | input in4; |
| 3700 | input in5; |
| 3701 | input in6; |
| 3702 | input sel0; |
| 3703 | input sel1; |
| 3704 | input sel2; |
| 3705 | input sel3; |
| 3706 | input sel4; |
| 3707 | input sel5; |
| 3708 | input sel6; |
| 3709 | output out; |
| 3710 | |
| 3711 | `ifdef LIB |
| 3712 | assign out = ((sel0 & in0) | |
| 3713 | (sel1 & in1) | |
| 3714 | (sel2 & in2) | |
| 3715 | (sel3 & in3) | |
| 3716 | (sel4 & in4) | |
| 3717 | (sel5 & in5) | |
| 3718 | (sel6 & in6)); |
| 3719 | `endif |
| 3720 | |
| 3721 | endmodule |
| 3722 | module cl_a1gb_aomux7_1x ( |
| 3723 | in0, |
| 3724 | in1, |
| 3725 | in2, |
| 3726 | in3, |
| 3727 | in4, |
| 3728 | in5, |
| 3729 | in6, |
| 3730 | sel0, |
| 3731 | sel1, |
| 3732 | sel2, |
| 3733 | sel3, |
| 3734 | sel4, |
| 3735 | sel5, |
| 3736 | sel6, |
| 3737 | out |
| 3738 | ); |
| 3739 | input in0; |
| 3740 | input in1; |
| 3741 | input in2; |
| 3742 | input in3; |
| 3743 | input in4; |
| 3744 | input in5; |
| 3745 | input in6; |
| 3746 | input sel0; |
| 3747 | input sel1; |
| 3748 | input sel2; |
| 3749 | input sel3; |
| 3750 | input sel4; |
| 3751 | input sel5; |
| 3752 | input sel6; |
| 3753 | output out; |
| 3754 | |
| 3755 | `ifdef LIB |
| 3756 | assign out = ((sel0 & in0) | |
| 3757 | (sel1 & in1) | |
| 3758 | (sel2 & in2) | |
| 3759 | (sel3 & in3) | |
| 3760 | (sel4 & in4) | |
| 3761 | (sel5 & in5) | |
| 3762 | (sel6 & in6)); |
| 3763 | `endif |
| 3764 | |
| 3765 | endmodule |
| 3766 | module cl_a1gb_aomux7_2x ( |
| 3767 | in0, |
| 3768 | in1, |
| 3769 | in2, |
| 3770 | in3, |
| 3771 | in4, |
| 3772 | in5, |
| 3773 | in6, |
| 3774 | sel0, |
| 3775 | sel1, |
| 3776 | sel2, |
| 3777 | sel3, |
| 3778 | sel4, |
| 3779 | sel5, |
| 3780 | sel6, |
| 3781 | out |
| 3782 | ); |
| 3783 | input in0; |
| 3784 | input in1; |
| 3785 | input in2; |
| 3786 | input in3; |
| 3787 | input in4; |
| 3788 | input in5; |
| 3789 | input in6; |
| 3790 | input sel0; |
| 3791 | input sel1; |
| 3792 | input sel2; |
| 3793 | input sel3; |
| 3794 | input sel4; |
| 3795 | input sel5; |
| 3796 | input sel6; |
| 3797 | output out; |
| 3798 | |
| 3799 | `ifdef LIB |
| 3800 | assign out = ((sel0 & in0) | |
| 3801 | (sel1 & in1) | |
| 3802 | (sel2 & in2) | |
| 3803 | (sel3 & in3) | |
| 3804 | (sel4 & in4) | |
| 3805 | (sel5 & in5) | |
| 3806 | (sel6 & in6)); |
| 3807 | `endif |
| 3808 | |
| 3809 | endmodule |
| 3810 | module cl_a1gb_aomux7_4x ( |
| 3811 | in0, |
| 3812 | in1, |
| 3813 | in2, |
| 3814 | in3, |
| 3815 | in4, |
| 3816 | in5, |
| 3817 | in6, |
| 3818 | sel0, |
| 3819 | sel1, |
| 3820 | sel2, |
| 3821 | sel3, |
| 3822 | sel4, |
| 3823 | sel5, |
| 3824 | sel6, |
| 3825 | out |
| 3826 | ); |
| 3827 | input in0; |
| 3828 | input in1; |
| 3829 | input in2; |
| 3830 | input in3; |
| 3831 | input in4; |
| 3832 | input in5; |
| 3833 | input in6; |
| 3834 | input sel0; |
| 3835 | input sel1; |
| 3836 | input sel2; |
| 3837 | input sel3; |
| 3838 | input sel4; |
| 3839 | input sel5; |
| 3840 | input sel6; |
| 3841 | output out; |
| 3842 | |
| 3843 | `ifdef LIB |
| 3844 | assign out = ((sel0 & in0) | |
| 3845 | (sel1 & in1) | |
| 3846 | (sel2 & in2) | |
| 3847 | (sel3 & in3) | |
| 3848 | (sel4 & in4) | |
| 3849 | (sel5 & in5) | |
| 3850 | (sel6 & in6)); |
| 3851 | `endif |
| 3852 | |
| 3853 | endmodule |
| 3854 | module cl_a1gb_aomux7_6x ( |
| 3855 | in0, |
| 3856 | in1, |
| 3857 | in2, |
| 3858 | in3, |
| 3859 | in4, |
| 3860 | in5, |
| 3861 | in6, |
| 3862 | sel0, |
| 3863 | sel1, |
| 3864 | sel2, |
| 3865 | sel3, |
| 3866 | sel4, |
| 3867 | sel5, |
| 3868 | sel6, |
| 3869 | out |
| 3870 | ); |
| 3871 | input in0; |
| 3872 | input in1; |
| 3873 | input in2; |
| 3874 | input in3; |
| 3875 | input in4; |
| 3876 | input in5; |
| 3877 | input in6; |
| 3878 | input sel0; |
| 3879 | input sel1; |
| 3880 | input sel2; |
| 3881 | input sel3; |
| 3882 | input sel4; |
| 3883 | input sel5; |
| 3884 | input sel6; |
| 3885 | output out; |
| 3886 | |
| 3887 | `ifdef LIB |
| 3888 | assign out = ((sel0 & in0) | |
| 3889 | (sel1 & in1) | |
| 3890 | (sel2 & in2) | |
| 3891 | (sel3 & in3) | |
| 3892 | (sel4 & in4) | |
| 3893 | (sel5 & in5) | |
| 3894 | (sel6 & in6)); |
| 3895 | `endif |
| 3896 | |
| 3897 | endmodule |
| 3898 | module cl_a1gb_aomux7_8x ( |
| 3899 | in0, |
| 3900 | in1, |
| 3901 | in2, |
| 3902 | in3, |
| 3903 | in4, |
| 3904 | in5, |
| 3905 | in6, |
| 3906 | sel0, |
| 3907 | sel1, |
| 3908 | sel2, |
| 3909 | sel3, |
| 3910 | sel4, |
| 3911 | sel5, |
| 3912 | sel6, |
| 3913 | out |
| 3914 | ); |
| 3915 | input in0; |
| 3916 | input in1; |
| 3917 | input in2; |
| 3918 | input in3; |
| 3919 | input in4; |
| 3920 | input in5; |
| 3921 | input in6; |
| 3922 | input sel0; |
| 3923 | input sel1; |
| 3924 | input sel2; |
| 3925 | input sel3; |
| 3926 | input sel4; |
| 3927 | input sel5; |
| 3928 | input sel6; |
| 3929 | output out; |
| 3930 | |
| 3931 | `ifdef LIB |
| 3932 | assign out = ((sel0 & in0) | |
| 3933 | (sel1 & in1) | |
| 3934 | (sel2 & in2) | |
| 3935 | (sel3 & in3) | |
| 3936 | (sel4 & in4) | |
| 3937 | (sel5 & in5) | |
| 3938 | (sel6 & in6)); |
| 3939 | `endif |
| 3940 | |
| 3941 | endmodule |
| 3942 | module cl_a1gb_aomux7_by2_1x ( |
| 3943 | in0, |
| 3944 | in1, |
| 3945 | in2, |
| 3946 | in3, |
| 3947 | in4, |
| 3948 | in5, |
| 3949 | in6, |
| 3950 | sel0, |
| 3951 | sel1, |
| 3952 | sel2, |
| 3953 | sel3, |
| 3954 | sel4, |
| 3955 | sel5, |
| 3956 | sel6, |
| 3957 | out |
| 3958 | ); |
| 3959 | input in0; |
| 3960 | input in1; |
| 3961 | input in2; |
| 3962 | input in3; |
| 3963 | input in4; |
| 3964 | input in5; |
| 3965 | input in6; |
| 3966 | input sel0; |
| 3967 | input sel1; |
| 3968 | input sel2; |
| 3969 | input sel3; |
| 3970 | input sel4; |
| 3971 | input sel5; |
| 3972 | input sel6; |
| 3973 | output out; |
| 3974 | |
| 3975 | `ifdef LIB |
| 3976 | assign out = ((sel0 & in0) | |
| 3977 | (sel1 & in1) | |
| 3978 | (sel2 & in2) | |
| 3979 | (sel3 & in3) | |
| 3980 | (sel4 & in4) | |
| 3981 | (sel5 & in5) | |
| 3982 | (sel6 & in6)); |
| 3983 | `endif |
| 3984 | |
| 3985 | endmodule |
| 3986 | module cl_a1gb_aomux7_by2_2x ( |
| 3987 | in0, |
| 3988 | in1, |
| 3989 | in2, |
| 3990 | in3, |
| 3991 | in4, |
| 3992 | in5, |
| 3993 | in6, |
| 3994 | sel0, |
| 3995 | sel1, |
| 3996 | sel2, |
| 3997 | sel3, |
| 3998 | sel4, |
| 3999 | sel5, |
| 4000 | sel6, |
| 4001 | out |
| 4002 | ); |
| 4003 | input in0; |
| 4004 | input in1; |
| 4005 | input in2; |
| 4006 | input in3; |
| 4007 | input in4; |
| 4008 | input in5; |
| 4009 | input in6; |
| 4010 | input sel0; |
| 4011 | input sel1; |
| 4012 | input sel2; |
| 4013 | input sel3; |
| 4014 | input sel4; |
| 4015 | input sel5; |
| 4016 | input sel6; |
| 4017 | output out; |
| 4018 | |
| 4019 | `ifdef LIB |
| 4020 | assign out = ((sel0 & in0) | |
| 4021 | (sel1 & in1) | |
| 4022 | (sel2 & in2) | |
| 4023 | (sel3 & in3) | |
| 4024 | (sel4 & in4) | |
| 4025 | (sel5 & in5) | |
| 4026 | (sel6 & in6)); |
| 4027 | `endif |
| 4028 | |
| 4029 | endmodule |
| 4030 | module cl_a1gb_aomux8_12x ( |
| 4031 | in0, |
| 4032 | in1, |
| 4033 | in2, |
| 4034 | in3, |
| 4035 | in4, |
| 4036 | in5, |
| 4037 | in6, |
| 4038 | in7, |
| 4039 | sel0, |
| 4040 | sel1, |
| 4041 | sel2, |
| 4042 | sel3, |
| 4043 | sel4, |
| 4044 | sel5, |
| 4045 | sel6, |
| 4046 | sel7, |
| 4047 | out |
| 4048 | ); |
| 4049 | input in0; |
| 4050 | input in1; |
| 4051 | input in2; |
| 4052 | input in3; |
| 4053 | input in4; |
| 4054 | input in5; |
| 4055 | input in6; |
| 4056 | input in7; |
| 4057 | input sel0; |
| 4058 | input sel1; |
| 4059 | input sel2; |
| 4060 | input sel3; |
| 4061 | input sel4; |
| 4062 | input sel5; |
| 4063 | input sel6; |
| 4064 | input sel7; |
| 4065 | output out; |
| 4066 | |
| 4067 | `ifdef LIB |
| 4068 | assign out = ((sel0 & in0) | |
| 4069 | (sel1 & in1) | |
| 4070 | (sel2 & in2) | |
| 4071 | (sel3 & in3) | |
| 4072 | (sel4 & in4) | |
| 4073 | (sel5 & in5) | |
| 4074 | (sel6 & in6) | |
| 4075 | (sel7 & in7)); |
| 4076 | `endif |
| 4077 | |
| 4078 | |
| 4079 | endmodule |
| 4080 | module cl_a1gb_aomux8_16x ( |
| 4081 | in0, |
| 4082 | in1, |
| 4083 | in2, |
| 4084 | in3, |
| 4085 | in4, |
| 4086 | in5, |
| 4087 | in6, |
| 4088 | in7, |
| 4089 | sel0, |
| 4090 | sel1, |
| 4091 | sel2, |
| 4092 | sel3, |
| 4093 | sel4, |
| 4094 | sel5, |
| 4095 | sel6, |
| 4096 | sel7, |
| 4097 | out |
| 4098 | ); |
| 4099 | input in0; |
| 4100 | input in1; |
| 4101 | input in2; |
| 4102 | input in3; |
| 4103 | input in4; |
| 4104 | input in5; |
| 4105 | input in6; |
| 4106 | input in7; |
| 4107 | input sel0; |
| 4108 | input sel1; |
| 4109 | input sel2; |
| 4110 | input sel3; |
| 4111 | input sel4; |
| 4112 | input sel5; |
| 4113 | input sel6; |
| 4114 | input sel7; |
| 4115 | output out; |
| 4116 | |
| 4117 | `ifdef LIB |
| 4118 | assign out = ((sel0 & in0) | |
| 4119 | (sel1 & in1) | |
| 4120 | (sel2 & in2) | |
| 4121 | (sel3 & in3) | |
| 4122 | (sel4 & in4) | |
| 4123 | (sel5 & in5) | |
| 4124 | (sel6 & in6) | |
| 4125 | (sel7 & in7)); |
| 4126 | `endif |
| 4127 | |
| 4128 | |
| 4129 | endmodule |
| 4130 | module cl_a1gb_aomux8_1x ( |
| 4131 | in0, |
| 4132 | in1, |
| 4133 | in2, |
| 4134 | in3, |
| 4135 | in4, |
| 4136 | in5, |
| 4137 | in6, |
| 4138 | in7, |
| 4139 | sel0, |
| 4140 | sel1, |
| 4141 | sel2, |
| 4142 | sel3, |
| 4143 | sel4, |
| 4144 | sel5, |
| 4145 | sel6, |
| 4146 | sel7, |
| 4147 | out |
| 4148 | ); |
| 4149 | input in0; |
| 4150 | input in1; |
| 4151 | input in2; |
| 4152 | input in3; |
| 4153 | input in4; |
| 4154 | input in5; |
| 4155 | input in6; |
| 4156 | input in7; |
| 4157 | input sel0; |
| 4158 | input sel1; |
| 4159 | input sel2; |
| 4160 | input sel3; |
| 4161 | input sel4; |
| 4162 | input sel5; |
| 4163 | input sel6; |
| 4164 | input sel7; |
| 4165 | output out; |
| 4166 | |
| 4167 | `ifdef LIB |
| 4168 | assign out = ((sel0 & in0) | |
| 4169 | (sel1 & in1) | |
| 4170 | (sel2 & in2) | |
| 4171 | (sel3 & in3) | |
| 4172 | (sel4 & in4) | |
| 4173 | (sel5 & in5) | |
| 4174 | (sel6 & in6) | |
| 4175 | (sel7 & in7)); |
| 4176 | `endif |
| 4177 | |
| 4178 | |
| 4179 | endmodule |
| 4180 | module cl_a1gb_aomux8_2x ( |
| 4181 | in0, |
| 4182 | in1, |
| 4183 | in2, |
| 4184 | in3, |
| 4185 | in4, |
| 4186 | in5, |
| 4187 | in6, |
| 4188 | in7, |
| 4189 | sel0, |
| 4190 | sel1, |
| 4191 | sel2, |
| 4192 | sel3, |
| 4193 | sel4, |
| 4194 | sel5, |
| 4195 | sel6, |
| 4196 | sel7, |
| 4197 | out |
| 4198 | ); |
| 4199 | input in0; |
| 4200 | input in1; |
| 4201 | input in2; |
| 4202 | input in3; |
| 4203 | input in4; |
| 4204 | input in5; |
| 4205 | input in6; |
| 4206 | input in7; |
| 4207 | input sel0; |
| 4208 | input sel1; |
| 4209 | input sel2; |
| 4210 | input sel3; |
| 4211 | input sel4; |
| 4212 | input sel5; |
| 4213 | input sel6; |
| 4214 | input sel7; |
| 4215 | output out; |
| 4216 | |
| 4217 | `ifdef LIB |
| 4218 | assign out = ((sel0 & in0) | |
| 4219 | (sel1 & in1) | |
| 4220 | (sel2 & in2) | |
| 4221 | (sel3 & in3) | |
| 4222 | (sel4 & in4) | |
| 4223 | (sel5 & in5) | |
| 4224 | (sel6 & in6) | |
| 4225 | (sel7 & in7)); |
| 4226 | `endif |
| 4227 | |
| 4228 | |
| 4229 | endmodule |
| 4230 | module cl_a1gb_aomux8_4x ( |
| 4231 | in0, |
| 4232 | in1, |
| 4233 | in2, |
| 4234 | in3, |
| 4235 | in4, |
| 4236 | in5, |
| 4237 | in6, |
| 4238 | in7, |
| 4239 | sel0, |
| 4240 | sel1, |
| 4241 | sel2, |
| 4242 | sel3, |
| 4243 | sel4, |
| 4244 | sel5, |
| 4245 | sel6, |
| 4246 | sel7, |
| 4247 | out |
| 4248 | ); |
| 4249 | input in0; |
| 4250 | input in1; |
| 4251 | input in2; |
| 4252 | input in3; |
| 4253 | input in4; |
| 4254 | input in5; |
| 4255 | input in6; |
| 4256 | input in7; |
| 4257 | input sel0; |
| 4258 | input sel1; |
| 4259 | input sel2; |
| 4260 | input sel3; |
| 4261 | input sel4; |
| 4262 | input sel5; |
| 4263 | input sel6; |
| 4264 | input sel7; |
| 4265 | output out; |
| 4266 | |
| 4267 | `ifdef LIB |
| 4268 | assign out = ((sel0 & in0) | |
| 4269 | (sel1 & in1) | |
| 4270 | (sel2 & in2) | |
| 4271 | (sel3 & in3) | |
| 4272 | (sel4 & in4) | |
| 4273 | (sel5 & in5) | |
| 4274 | (sel6 & in6) | |
| 4275 | (sel7 & in7)); |
| 4276 | `endif |
| 4277 | |
| 4278 | |
| 4279 | endmodule |
| 4280 | module cl_a1gb_aomux8_6x ( |
| 4281 | in0, |
| 4282 | in1, |
| 4283 | in2, |
| 4284 | in3, |
| 4285 | in4, |
| 4286 | in5, |
| 4287 | in6, |
| 4288 | in7, |
| 4289 | sel0, |
| 4290 | sel1, |
| 4291 | sel2, |
| 4292 | sel3, |
| 4293 | sel4, |
| 4294 | sel5, |
| 4295 | sel6, |
| 4296 | sel7, |
| 4297 | out |
| 4298 | ); |
| 4299 | input in0; |
| 4300 | input in1; |
| 4301 | input in2; |
| 4302 | input in3; |
| 4303 | input in4; |
| 4304 | input in5; |
| 4305 | input in6; |
| 4306 | input in7; |
| 4307 | input sel0; |
| 4308 | input sel1; |
| 4309 | input sel2; |
| 4310 | input sel3; |
| 4311 | input sel4; |
| 4312 | input sel5; |
| 4313 | input sel6; |
| 4314 | input sel7; |
| 4315 | output out; |
| 4316 | |
| 4317 | `ifdef LIB |
| 4318 | assign out = ((sel0 & in0) | |
| 4319 | (sel1 & in1) | |
| 4320 | (sel2 & in2) | |
| 4321 | (sel3 & in3) | |
| 4322 | (sel4 & in4) | |
| 4323 | (sel5 & in5) | |
| 4324 | (sel6 & in6) | |
| 4325 | (sel7 & in7)); |
| 4326 | `endif |
| 4327 | |
| 4328 | |
| 4329 | endmodule |
| 4330 | module cl_a1gb_aomux8_8x ( |
| 4331 | in0, |
| 4332 | in1, |
| 4333 | in2, |
| 4334 | in3, |
| 4335 | in4, |
| 4336 | in5, |
| 4337 | in6, |
| 4338 | in7, |
| 4339 | sel0, |
| 4340 | sel1, |
| 4341 | sel2, |
| 4342 | sel3, |
| 4343 | sel4, |
| 4344 | sel5, |
| 4345 | sel6, |
| 4346 | sel7, |
| 4347 | out |
| 4348 | ); |
| 4349 | input in0; |
| 4350 | input in1; |
| 4351 | input in2; |
| 4352 | input in3; |
| 4353 | input in4; |
| 4354 | input in5; |
| 4355 | input in6; |
| 4356 | input in7; |
| 4357 | input sel0; |
| 4358 | input sel1; |
| 4359 | input sel2; |
| 4360 | input sel3; |
| 4361 | input sel4; |
| 4362 | input sel5; |
| 4363 | input sel6; |
| 4364 | input sel7; |
| 4365 | output out; |
| 4366 | |
| 4367 | `ifdef LIB |
| 4368 | assign out = ((sel0 & in0) | |
| 4369 | (sel1 & in1) | |
| 4370 | (sel2 & in2) | |
| 4371 | (sel3 & in3) | |
| 4372 | (sel4 & in4) | |
| 4373 | (sel5 & in5) | |
| 4374 | (sel6 & in6) | |
| 4375 | (sel7 & in7)); |
| 4376 | `endif |
| 4377 | |
| 4378 | |
| 4379 | endmodule |
| 4380 | module cl_a1gb_aomux8_by2_1x ( |
| 4381 | in0, |
| 4382 | in1, |
| 4383 | in2, |
| 4384 | in3, |
| 4385 | in4, |
| 4386 | in5, |
| 4387 | in6, |
| 4388 | in7, |
| 4389 | sel0, |
| 4390 | sel1, |
| 4391 | sel2, |
| 4392 | sel3, |
| 4393 | sel4, |
| 4394 | sel5, |
| 4395 | sel6, |
| 4396 | sel7, |
| 4397 | out |
| 4398 | ); |
| 4399 | input in0; |
| 4400 | input in1; |
| 4401 | input in2; |
| 4402 | input in3; |
| 4403 | input in4; |
| 4404 | input in5; |
| 4405 | input in6; |
| 4406 | input in7; |
| 4407 | input sel0; |
| 4408 | input sel1; |
| 4409 | input sel2; |
| 4410 | input sel3; |
| 4411 | input sel4; |
| 4412 | input sel5; |
| 4413 | input sel6; |
| 4414 | input sel7; |
| 4415 | output out; |
| 4416 | |
| 4417 | `ifdef LIB |
| 4418 | assign out = ((sel0 & in0) | |
| 4419 | (sel1 & in1) | |
| 4420 | (sel2 & in2) | |
| 4421 | (sel3 & in3) | |
| 4422 | (sel4 & in4) | |
| 4423 | (sel5 & in5) | |
| 4424 | (sel6 & in6) | |
| 4425 | (sel7 & in7)); |
| 4426 | `endif |
| 4427 | |
| 4428 | |
| 4429 | endmodule |
| 4430 | module cl_a1gb_aomux8_by2_2x ( |
| 4431 | in0, |
| 4432 | in1, |
| 4433 | in2, |
| 4434 | in3, |
| 4435 | in4, |
| 4436 | in5, |
| 4437 | in6, |
| 4438 | in7, |
| 4439 | sel0, |
| 4440 | sel1, |
| 4441 | sel2, |
| 4442 | sel3, |
| 4443 | sel4, |
| 4444 | sel5, |
| 4445 | sel6, |
| 4446 | sel7, |
| 4447 | out |
| 4448 | ); |
| 4449 | input in0; |
| 4450 | input in1; |
| 4451 | input in2; |
| 4452 | input in3; |
| 4453 | input in4; |
| 4454 | input in5; |
| 4455 | input in6; |
| 4456 | input in7; |
| 4457 | input sel0; |
| 4458 | input sel1; |
| 4459 | input sel2; |
| 4460 | input sel3; |
| 4461 | input sel4; |
| 4462 | input sel5; |
| 4463 | input sel6; |
| 4464 | input sel7; |
| 4465 | output out; |
| 4466 | |
| 4467 | `ifdef LIB |
| 4468 | assign out = ((sel0 & in0) | |
| 4469 | (sel1 & in1) | |
| 4470 | (sel2 & in2) | |
| 4471 | (sel3 & in3) | |
| 4472 | (sel4 & in4) | |
| 4473 | (sel5 & in5) | |
| 4474 | (sel6 & in6) | |
| 4475 | (sel7 & in7)); |
| 4476 | `endif |
| 4477 | |
| 4478 | |
| 4479 | endmodule |
| 4480 | |