| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_com_dp_32x84_cust.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module n2_com_dp_32x84_cust ( |
| 36 | wr_adr, |
| 37 | wr_en, |
| 38 | rd_adr, |
| 39 | rd_en, |
| 40 | din, |
| 41 | dout, |
| 42 | rdclk, |
| 43 | wrclk, |
| 44 | scan_in, |
| 45 | tcu_pce_ov, |
| 46 | tcu_aclk, |
| 47 | tcu_bclk, |
| 48 | tcu_array_wr_inhibit, |
| 49 | tcu_se_scancollar_in, |
| 50 | bist_clk_mux_sel, |
| 51 | rd_pce, |
| 52 | wr_pce, |
| 53 | scan_out); |
| 54 | wire rd_lce; |
| 55 | wire wr_lce; |
| 56 | wire rdclk_in; |
| 57 | wire wrclk_in; |
| 58 | wire rdclk_free; |
| 59 | wire wrclk_free; |
| 60 | wire dff_wr_addr_scanin; |
| 61 | wire dff_wr_addr_scanout; |
| 62 | wire [4:0] wr_adr_d1; |
| 63 | wire [4:1] dff_rd_addr_scan; |
| 64 | wire dff_rd_addr_scanin; |
| 65 | wire dff_rd_addr_scanout; |
| 66 | wire [4:0] rd_adr_d1; |
| 67 | wire [4:0] rd_adr_mq_l_unused; |
| 68 | wire [4:0] rd_adr_q_unused; |
| 69 | wire [4:0] rd_adr_q_l_unused; |
| 70 | wire dff_rd_en_scanin; |
| 71 | wire dff_rd_en_scanout; |
| 72 | wire rd_en_d1; |
| 73 | wire rd_en_mq_l_unused; |
| 74 | wire rd_en_q_unused; |
| 75 | wire rd_en_q_l_unused; |
| 76 | wire dff_wr_en_scanin; |
| 77 | wire dff_wr_en_scanout; |
| 78 | wire wr_en_d1; |
| 79 | wire [41:1] dff_din_hi_scan; |
| 80 | wire dff_din_hi_scanin; |
| 81 | wire dff_din_hi_scanout; |
| 82 | wire [83:0] din_d1; |
| 83 | wire [41:1] dff_din_lo_scan; |
| 84 | wire dff_din_lo_scanin; |
| 85 | wire dff_din_lo_scanout; |
| 86 | wire wr_inh_; |
| 87 | wire rd_en_d1_qual; |
| 88 | wire wr_en_d1_qual; |
| 89 | wire [83:0] local_dout; |
| 90 | wire dff_dout_scanout; |
| 91 | wire dff_dout_scanin; |
| 92 | |
| 93 | input [4:0] wr_adr; |
| 94 | input wr_en; |
| 95 | input [4:0] rd_adr; |
| 96 | input rd_en; |
| 97 | input [83:0] din; |
| 98 | output [83:0] dout; |
| 99 | input rdclk; |
| 100 | input wrclk; |
| 101 | input scan_in; |
| 102 | input tcu_pce_ov; |
| 103 | input tcu_aclk; |
| 104 | input tcu_bclk; |
| 105 | input tcu_array_wr_inhibit; |
| 106 | input tcu_se_scancollar_in; |
| 107 | |
| 108 | |
| 109 | input bist_clk_mux_sel; |
| 110 | input rd_pce; |
| 111 | input wr_pce; |
| 112 | output scan_out; |
| 113 | |
| 114 | |
| 115 | `ifndef FPGA |
| 116 | // JDL 05/17/07 |
| 117 | // synopsys translate_off |
| 118 | `endif |
| 119 | |
| 120 | wire pce_ov = tcu_pce_ov; |
| 121 | wire siclk = tcu_aclk; |
| 122 | wire soclk = tcu_bclk; |
| 123 | //================================================ |
| 124 | // Clock headers |
| 125 | //================================================ |
| 126 | cl_mc1_bistlatch_4x rd_pce_lat ( |
| 127 | .l2clk (rdclk), |
| 128 | .pce (rd_pce), |
| 129 | .pce_ov (pce_ov), |
| 130 | .lce (rd_lce) |
| 131 | ); |
| 132 | cl_mc1_bistlatch_4x wr_pce_lat ( |
| 133 | .l2clk (wrclk), |
| 134 | .pce (wr_pce), |
| 135 | .pce_ov (pce_ov), |
| 136 | .lce (wr_lce) |
| 137 | ); |
| 138 | cl_mc1_bistl1hdr_8x rch_in ( |
| 139 | .l2clk (rdclk), |
| 140 | .se (tcu_se_scancollar_in), |
| 141 | .clksel (bist_clk_mux_sel), |
| 142 | .bistclk(rdclk), |
| 143 | .lce (rd_lce), |
| 144 | .l1clk (rdclk_in) |
| 145 | ); |
| 146 | cl_mc1_bistl1hdr_8x wch_in ( |
| 147 | .l2clk (wrclk), |
| 148 | .se (tcu_se_scancollar_in), |
| 149 | .clksel (bist_clk_mux_sel), |
| 150 | .bistclk(rdclk), |
| 151 | .lce (wr_lce), |
| 152 | .l1clk (wrclk_in) |
| 153 | ); |
| 154 | cl_mc1_bistl1hdr_8x rch_free ( |
| 155 | .l2clk (rdclk), |
| 156 | .se (1'b0), |
| 157 | .clksel (bist_clk_mux_sel), |
| 158 | .bistclk(rdclk), |
| 159 | .lce (rd_lce), |
| 160 | .l1clk (rdclk_free) |
| 161 | ); |
| 162 | cl_mc1_bistl1hdr_8x wch_free ( |
| 163 | .l2clk (wrclk), |
| 164 | .se (1'b0), |
| 165 | .clksel (bist_clk_mux_sel), |
| 166 | .bistclk(rdclk), |
| 167 | .lce (wr_lce), |
| 168 | .l1clk (wrclk_free) |
| 169 | ); |
| 170 | |
| 171 | |
| 172 | /////////////////////////////////////////////////////////////// |
| 173 | // Flop the inputs // |
| 174 | /////////////////////////////////////////////////////////////// |
| 175 | n2_com_dp_32x84_cust_msff_ctl_macro__width_5 dff_wr_addr ( |
| 176 | .scan_in (dff_wr_addr_scanin), |
| 177 | .scan_out (dff_wr_addr_scanout), |
| 178 | .l1clk (wrclk_in), |
| 179 | .din (wr_adr[4:0]), |
| 180 | .dout (wr_adr_d1[4:0]), |
| 181 | .siclk(siclk), |
| 182 | .soclk(soclk) |
| 183 | ); |
| 184 | n2_com_dp_32x84_cust_sram_msff_mo_macro__fs_1__width_5 dff_rd_addr ( |
| 185 | .scan_in ({dff_rd_addr_scan[4:1],dff_rd_addr_scanin}), |
| 186 | .scan_out ({dff_rd_addr_scanout,dff_rd_addr_scan[4:1]}), |
| 187 | .l1clk (rdclk_in), |
| 188 | .and_clk (rdclk_in), |
| 189 | .d (rd_adr[4:0]), |
| 190 | .mq (rd_adr_d1[4:0]), |
| 191 | .mq_l (rd_adr_mq_l_unused[4:0]), |
| 192 | .q (rd_adr_q_unused[4:0]), |
| 193 | .q_l (rd_adr_q_l_unused[4:0]), |
| 194 | .siclk(siclk), |
| 195 | .soclk(soclk) |
| 196 | ); |
| 197 | n2_com_dp_32x84_cust_sram_msff_mo_macro__width_1 dff_rd_en ( |
| 198 | .scan_in (dff_rd_en_scanin), |
| 199 | .scan_out (dff_rd_en_scanout), |
| 200 | .l1clk (rdclk_in), |
| 201 | .and_clk (rdclk_in), |
| 202 | .d (rd_en), |
| 203 | .mq (rd_en_d1), |
| 204 | .mq_l (rd_en_mq_l_unused), |
| 205 | .q (rd_en_q_unused), |
| 206 | .q_l (rd_en_q_l_unused), |
| 207 | .siclk(siclk), |
| 208 | .soclk(soclk) |
| 209 | ); |
| 210 | n2_com_dp_32x84_cust_msff_ctl_macro__width_1 dff_wr_en ( |
| 211 | .scan_in (dff_wr_en_scanin), |
| 212 | .scan_out (dff_wr_en_scanout), |
| 213 | .l1clk (wrclk_in), |
| 214 | .din (wr_en), |
| 215 | .dout (wr_en_d1), |
| 216 | .siclk(siclk), |
| 217 | .soclk(soclk) |
| 218 | ); |
| 219 | n2_com_dp_32x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_hi ( |
| 220 | .scan_in ({dff_din_hi_scan[41:1],dff_din_hi_scanin}), |
| 221 | .scan_out ({dff_din_hi_scanout,dff_din_hi_scan[41:1]}), |
| 222 | .l1clk (wrclk_in), |
| 223 | .din (din[83:42]), |
| 224 | .dout (din_d1[83:42]), |
| 225 | .siclk(siclk), |
| 226 | .soclk(soclk) |
| 227 | ); |
| 228 | n2_com_dp_32x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_lo ( |
| 229 | .scan_in ({dff_din_lo_scan[41:1],dff_din_lo_scanin}), |
| 230 | .scan_out ({dff_din_lo_scanout,dff_din_lo_scan[41:1]}), |
| 231 | .l1clk (wrclk_in), |
| 232 | .din (din[41:0]), |
| 233 | .dout (din_d1[41:0]), |
| 234 | .siclk(siclk), |
| 235 | .soclk(soclk) |
| 236 | ); |
| 237 | n2_com_dp_32x84_cust_inv_macro__width_1 wr_inh_inv ( |
| 238 | .din (tcu_array_wr_inhibit), |
| 239 | .dout (wr_inh_) |
| 240 | ); |
| 241 | n2_com_dp_32x84_cust_and_macro__width_2 enable_qual ( |
| 242 | .din0 ({2{wr_inh_}}), |
| 243 | .din1 ({rd_en_d1,wr_en_d1}), |
| 244 | .dout ({rd_en_d1_qual,wr_en_d1_qual}) |
| 245 | ); |
| 246 | n2_com_dp_32x84_cust_n2_com_array_macro__rows_32__width_84__z_array array ( |
| 247 | .rclk (rdclk_free), |
| 248 | .wclk (wrclk_free), |
| 249 | .wr_adr (wr_adr_d1[4:0]), |
| 250 | .wr_en (wr_en_d1_qual), |
| 251 | .rd_adr (rd_adr_d1[4:0]), |
| 252 | .rd_en (rd_en_d1_qual), |
| 253 | .din (din_d1[83:0]), |
| 254 | .dout (local_dout[83:0]) |
| 255 | ); |
| 256 | |
| 257 | |
| 258 | assign dout[83:0] = local_dout[83:0]; |
| 259 | assign dff_dout_scanout = dff_dout_scanin; |
| 260 | |
| 261 | supply0 vss; |
| 262 | supply1 vdd; |
| 263 | |
| 264 | // fixscan start: |
| 265 | assign dff_wr_addr_scanin = scan_in ; |
| 266 | assign dff_rd_addr_scanin = dff_wr_addr_scanout ; |
| 267 | assign dff_wr_en_scanin = dff_rd_addr_scanout ; |
| 268 | assign dff_rd_en_scanin = dff_wr_en_scanout ; |
| 269 | assign dff_din_lo_scanin = dff_rd_en_scanout ; |
| 270 | assign dff_din_hi_scanin = dff_din_lo_scanout ; |
| 271 | assign dff_dout_scanin = dff_din_hi_scanout ; |
| 272 | assign scan_out = dff_dout_scanout ; |
| 273 | // fixscan end: |
| 274 | |
| 275 | |
| 276 | `ifndef FPGA |
| 277 | // JDL 05/17/07 |
| 278 | // synopsys translate_on |
| 279 | `endif |
| 280 | |
| 281 | endmodule |
| 282 | |
| 283 | |
| 284 | |
| 285 | |
| 286 | |
| 287 | |
| 288 | |
| 289 | // any PARAMS parms go into naming of macro |
| 290 | |
| 291 | module n2_com_dp_32x84_cust_msff_ctl_macro__width_5 ( |
| 292 | din, |
| 293 | l1clk, |
| 294 | scan_in, |
| 295 | siclk, |
| 296 | soclk, |
| 297 | dout, |
| 298 | scan_out); |
| 299 | wire [4:0] fdin; |
| 300 | wire [3:0] so; |
| 301 | |
| 302 | input [4:0] din; |
| 303 | input l1clk; |
| 304 | input scan_in; |
| 305 | |
| 306 | |
| 307 | input siclk; |
| 308 | input soclk; |
| 309 | |
| 310 | output [4:0] dout; |
| 311 | output scan_out; |
| 312 | assign fdin[4:0] = din[4:0]; |
| 313 | |
| 314 | |
| 315 | |
| 316 | |
| 317 | |
| 318 | |
| 319 | dff #(5) d0_0 ( |
| 320 | .l1clk(l1clk), |
| 321 | .siclk(siclk), |
| 322 | .soclk(soclk), |
| 323 | .d(fdin[4:0]), |
| 324 | .si({scan_in,so[3:0]}), |
| 325 | .so({so[3:0],scan_out}), |
| 326 | .q(dout[4:0]) |
| 327 | ); |
| 328 | |
| 329 | |
| 330 | |
| 331 | |
| 332 | |
| 333 | |
| 334 | |
| 335 | |
| 336 | |
| 337 | |
| 338 | |
| 339 | |
| 340 | endmodule |
| 341 | |
| 342 | |
| 343 | |
| 344 | |
| 345 | |
| 346 | |
| 347 | |
| 348 | |
| 349 | |
| 350 | // |
| 351 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops |
| 352 | // |
| 353 | // |
| 354 | |
| 355 | |
| 356 | |
| 357 | |
| 358 | |
| 359 | module n2_com_dp_32x84_cust_sram_msff_mo_macro__fs_1__width_5 ( |
| 360 | d, |
| 361 | scan_in, |
| 362 | l1clk, |
| 363 | and_clk, |
| 364 | siclk, |
| 365 | soclk, |
| 366 | mq, |
| 367 | mq_l, |
| 368 | scan_out, |
| 369 | q, |
| 370 | q_l); |
| 371 | input [4:0] d; |
| 372 | input [4:0] scan_in; |
| 373 | input l1clk; |
| 374 | input and_clk; |
| 375 | input siclk; |
| 376 | input soclk; |
| 377 | output [4:0] mq; |
| 378 | output [4:0] mq_l; |
| 379 | output [4:0] scan_out; |
| 380 | output [4:0] q; |
| 381 | output [4:0] q_l; |
| 382 | |
| 383 | |
| 384 | |
| 385 | |
| 386 | |
| 387 | |
| 388 | new_dlata #(5) d0_0 ( |
| 389 | .d(d[4:0]), |
| 390 | .si(scan_in[4:0]), |
| 391 | .so(scan_out[4:0]), |
| 392 | .l1clk(l1clk), |
| 393 | .and_clk(and_clk), |
| 394 | .siclk(siclk), |
| 395 | .soclk(soclk), |
| 396 | .q(q[4:0]), |
| 397 | .q_l(q_l[4:0]), |
| 398 | .mq(mq[4:0]), |
| 399 | .mq_l(mq_l[4:0]) |
| 400 | ); |
| 401 | |
| 402 | |
| 403 | |
| 404 | |
| 405 | |
| 406 | |
| 407 | |
| 408 | |
| 409 | |
| 410 | |
| 411 | //place::generic_place($width,$stack,$left); |
| 412 | |
| 413 | endmodule |
| 414 | |
| 415 | |
| 416 | |
| 417 | |
| 418 | |
| 419 | // |
| 420 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops |
| 421 | // |
| 422 | // |
| 423 | |
| 424 | |
| 425 | |
| 426 | |
| 427 | |
| 428 | module n2_com_dp_32x84_cust_sram_msff_mo_macro__width_1 ( |
| 429 | d, |
| 430 | scan_in, |
| 431 | l1clk, |
| 432 | and_clk, |
| 433 | siclk, |
| 434 | soclk, |
| 435 | mq, |
| 436 | mq_l, |
| 437 | scan_out, |
| 438 | q, |
| 439 | q_l); |
| 440 | input [0:0] d; |
| 441 | input scan_in; |
| 442 | input l1clk; |
| 443 | input and_clk; |
| 444 | input siclk; |
| 445 | input soclk; |
| 446 | output [0:0] mq; |
| 447 | output [0:0] mq_l; |
| 448 | output scan_out; |
| 449 | output [0:0] q; |
| 450 | output [0:0] q_l; |
| 451 | |
| 452 | |
| 453 | |
| 454 | |
| 455 | |
| 456 | |
| 457 | new_dlata #(1) d0_0 ( |
| 458 | .d(d[0:0]), |
| 459 | .si(scan_in), |
| 460 | .so(scan_out), |
| 461 | .l1clk(l1clk), |
| 462 | .and_clk(and_clk), |
| 463 | .siclk(siclk), |
| 464 | .soclk(soclk), |
| 465 | .q(q[0:0]), |
| 466 | .q_l(q_l[0:0]), |
| 467 | .mq(mq[0:0]), |
| 468 | .mq_l(mq_l[0:0]) |
| 469 | ); |
| 470 | |
| 471 | |
| 472 | |
| 473 | |
| 474 | |
| 475 | |
| 476 | |
| 477 | |
| 478 | |
| 479 | |
| 480 | //place::generic_place($width,$stack,$left); |
| 481 | |
| 482 | endmodule |
| 483 | |
| 484 | |
| 485 | |
| 486 | |
| 487 | |
| 488 | |
| 489 | |
| 490 | |
| 491 | |
| 492 | // any PARAMS parms go into naming of macro |
| 493 | |
| 494 | module n2_com_dp_32x84_cust_msff_ctl_macro__width_1 ( |
| 495 | din, |
| 496 | l1clk, |
| 497 | scan_in, |
| 498 | siclk, |
| 499 | soclk, |
| 500 | dout, |
| 501 | scan_out); |
| 502 | wire [0:0] fdin; |
| 503 | |
| 504 | input [0:0] din; |
| 505 | input l1clk; |
| 506 | input scan_in; |
| 507 | |
| 508 | |
| 509 | input siclk; |
| 510 | input soclk; |
| 511 | |
| 512 | output [0:0] dout; |
| 513 | output scan_out; |
| 514 | assign fdin[0:0] = din[0:0]; |
| 515 | |
| 516 | |
| 517 | |
| 518 | |
| 519 | |
| 520 | |
| 521 | dff #(1) d0_0 ( |
| 522 | .l1clk(l1clk), |
| 523 | .siclk(siclk), |
| 524 | .soclk(soclk), |
| 525 | .d(fdin[0:0]), |
| 526 | .si(scan_in), |
| 527 | .so(scan_out), |
| 528 | .q(dout[0:0]) |
| 529 | ); |
| 530 | |
| 531 | |
| 532 | |
| 533 | |
| 534 | |
| 535 | |
| 536 | |
| 537 | |
| 538 | |
| 539 | |
| 540 | |
| 541 | |
| 542 | endmodule |
| 543 | |
| 544 | |
| 545 | |
| 546 | |
| 547 | |
| 548 | |
| 549 | |
| 550 | |
| 551 | |
| 552 | |
| 553 | |
| 554 | |
| 555 | |
| 556 | // any PARAMS parms go into naming of macro |
| 557 | |
| 558 | module n2_com_dp_32x84_cust_msff_ctl_macro__fs_1__width_42 ( |
| 559 | din, |
| 560 | l1clk, |
| 561 | scan_in, |
| 562 | siclk, |
| 563 | soclk, |
| 564 | dout, |
| 565 | scan_out); |
| 566 | wire [41:0] fdin; |
| 567 | |
| 568 | input [41:0] din; |
| 569 | input l1clk; |
| 570 | input [41:0] scan_in; |
| 571 | |
| 572 | |
| 573 | input siclk; |
| 574 | input soclk; |
| 575 | |
| 576 | output [41:0] dout; |
| 577 | output [41:0] scan_out; |
| 578 | assign fdin[41:0] = din[41:0]; |
| 579 | |
| 580 | |
| 581 | |
| 582 | |
| 583 | |
| 584 | |
| 585 | dff #(42) d0_0 ( |
| 586 | .l1clk(l1clk), |
| 587 | .siclk(siclk), |
| 588 | .soclk(soclk), |
| 589 | .d(fdin[41:0]), |
| 590 | .si(scan_in[41:0]), |
| 591 | .so(scan_out[41:0]), |
| 592 | .q(dout[41:0]) |
| 593 | ); |
| 594 | |
| 595 | |
| 596 | |
| 597 | |
| 598 | |
| 599 | |
| 600 | |
| 601 | |
| 602 | |
| 603 | |
| 604 | |
| 605 | |
| 606 | endmodule |
| 607 | |
| 608 | |
| 609 | |
| 610 | |
| 611 | |
| 612 | |
| 613 | |
| 614 | |
| 615 | |
| 616 | // |
| 617 | // invert macro |
| 618 | // |
| 619 | // |
| 620 | |
| 621 | |
| 622 | |
| 623 | |
| 624 | |
| 625 | module n2_com_dp_32x84_cust_inv_macro__width_1 ( |
| 626 | din, |
| 627 | dout); |
| 628 | input [0:0] din; |
| 629 | output [0:0] dout; |
| 630 | |
| 631 | |
| 632 | |
| 633 | |
| 634 | |
| 635 | |
| 636 | inv #(1) d0_0 ( |
| 637 | .in(din[0:0]), |
| 638 | .out(dout[0:0]) |
| 639 | ); |
| 640 | |
| 641 | |
| 642 | |
| 643 | |
| 644 | |
| 645 | |
| 646 | |
| 647 | |
| 648 | |
| 649 | endmodule |
| 650 | |
| 651 | |
| 652 | |
| 653 | |
| 654 | |
| 655 | // |
| 656 | // and macro for ports = 2,3,4 |
| 657 | // |
| 658 | // |
| 659 | |
| 660 | |
| 661 | |
| 662 | |
| 663 | |
| 664 | module n2_com_dp_32x84_cust_and_macro__width_2 ( |
| 665 | din0, |
| 666 | din1, |
| 667 | dout); |
| 668 | input [1:0] din0; |
| 669 | input [1:0] din1; |
| 670 | output [1:0] dout; |
| 671 | |
| 672 | |
| 673 | |
| 674 | |
| 675 | |
| 676 | |
| 677 | and2 #(2) d0_0 ( |
| 678 | .in0(din0[1:0]), |
| 679 | .in1(din1[1:0]), |
| 680 | .out(dout[1:0]) |
| 681 | ); |
| 682 | |
| 683 | |
| 684 | |
| 685 | |
| 686 | |
| 687 | |
| 688 | |
| 689 | |
| 690 | |
| 691 | endmodule |
| 692 | |
| 693 | |
| 694 | |
| 695 | |
| 696 | |
| 697 | |
| 698 | |
| 699 | |
| 700 | |
| 701 | |
| 702 | module n2_com_dp_32x84_cust_n2_com_array_macro__rows_32__width_84__z_array ( |
| 703 | rclk, |
| 704 | wclk, |
| 705 | rd_adr, |
| 706 | rd_en, |
| 707 | wr_en, |
| 708 | wr_adr, |
| 709 | din, |
| 710 | dout); |
| 711 | |
| 712 | input rclk; |
| 713 | input wclk; |
| 714 | input [4:0] rd_adr; |
| 715 | input rd_en; |
| 716 | input wr_en; |
| 717 | input [4:0] wr_adr; |
| 718 | input [84-1:0] din; |
| 719 | output [84-1:0] dout; |
| 720 | |
| 721 | |
| 722 | |
| 723 | reg [84-1:0] mem[32-1:0]; |
| 724 | reg [84-1:0] local_dout; |
| 725 | |
| 726 | `ifndef NOINITMEM |
| 727 | // Emulate reset |
| 728 | integer i; |
| 729 | initial begin |
| 730 | for (i=0; i<32; i=i+1) begin |
| 731 | mem[i] = 84'b0; |
| 732 | end |
| 733 | local_dout = 84'b0; |
| 734 | end |
| 735 | `endif |
| 736 | ////////////////////// |
| 737 | // Read/write array |
| 738 | ////////////////////// |
| 739 | always @(negedge wclk) begin |
| 740 | if (wr_en) begin |
| 741 | mem[wr_adr] <= din; |
| 742 | |
| 743 | |
| 744 | end |
| 745 | end |
| 746 | always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin |
| 747 | if (rclk) begin |
| 748 | if (rd_en) begin |
| 749 | if (wr_en & (wr_adr[4:0] == rd_adr[4:0])) |
| 750 | local_dout[84-1:0] <= 84'hx; |
| 751 | else |
| 752 | local_dout[84-1:0] <= mem[rd_adr] ; |
| 753 | end |
| 754 | else |
| 755 | local_dout[84-1:0] <= ~(84'h0); |
| 756 | end |
| 757 | end |
| 758 | assign dout[84-1:0] = local_dout[84-1:0]; |
| 759 | supply0 vss; |
| 760 | supply1 vdd; |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | endmodule |
| 766 | |