| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_frf_mp_256x78_cust.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module n2_frf_mp_256x78_cust ( |
| 36 | frf_r1_data, |
| 37 | frf_r1_ecc, |
| 38 | frf_r2_data, |
| 39 | frf_r2_ecc, |
| 40 | l2clk, |
| 41 | scan_in, |
| 42 | pce, |
| 43 | tcu_pce_ov, |
| 44 | tcu_aclk, |
| 45 | tcu_bclk, |
| 46 | tcu_array_wr_inhibit, |
| 47 | tcu_scan_en, |
| 48 | tcu_se_scancollar_in, |
| 49 | main_clken, |
| 50 | scan_out, |
| 51 | r_tid, |
| 52 | r1_valid, |
| 53 | r1_addr, |
| 54 | r2_valid, |
| 55 | r2_addr, |
| 56 | w1_tid, |
| 57 | w1_valid, |
| 58 | w1_addr, |
| 59 | w2_tid, |
| 60 | w2_valid, |
| 61 | w2_addr, |
| 62 | w1_data, |
| 63 | w1_ecc, |
| 64 | w2_data, |
| 65 | w2_ecc); |
| 66 | wire siclk; |
| 67 | wire soclk; |
| 68 | wire l1clk; |
| 69 | wire l1clk_main; |
| 70 | wire [13:0] w1_ecc_synd_fb_to_fw_scanin; |
| 71 | wire [13:0] w1_ecc_synd_fb_to_fw_scanout; |
| 72 | wire [13:0] w1_ecc_fw; |
| 73 | wire [13:0] w2_ecc_synd_fb_to_fw_scanin; |
| 74 | wire [13:0] w2_ecc_synd_fb_to_fw_scanout; |
| 75 | wire [13:0] w2_ecc_fw; |
| 76 | wire [14:0] frf_read_ctl_in2ph2_scanin; |
| 77 | wire [14:0] frf_read_ctl_in2ph2_scanout; |
| 78 | wire [4:0] r1_addr_ph2; |
| 79 | wire [4:0] r2_addr_ph2; |
| 80 | wire r1_valid_ph2; |
| 81 | wire r2_valid_ph2; |
| 82 | wire [2:0] r_tid_ph2; |
| 83 | wire [63:0] fw_w2data_scanin; |
| 84 | wire [63:0] fw_w2data_scanout; |
| 85 | wire [63:0] w2_data_fw; |
| 86 | wire [63:0] fw_w1data_scanin; |
| 87 | wire [63:0] fw_w1data_scanout; |
| 88 | wire [63:0] w1_data_fw; |
| 89 | wire [19:0] frf_write_input_ctl_in2fb_scanin; |
| 90 | wire [19:0] frf_write_input_ctl_in2fb_scanout; |
| 91 | wire [2:0] w1_tid_fw; |
| 92 | wire [1:0] w1_valid_fw; |
| 93 | wire [4:0] w1_addr_fw; |
| 94 | wire [2:0] w2_tid_fw; |
| 95 | wire [1:0] w2_valid_fw; |
| 96 | wire [4:0] w2_addr_fw; |
| 97 | wire l1clk_free; |
| 98 | |
| 99 | |
| 100 | // ----------------------------------------------------------------------- |
| 101 | // Read output ports |
| 102 | // ----------------------------------------------------------------------- |
| 103 | output [63:0] frf_r1_data; |
| 104 | output [13:0] frf_r1_ecc; |
| 105 | output [63:0] frf_r2_data; |
| 106 | output [13:0] frf_r2_ecc; |
| 107 | |
| 108 | // ----------------------------------------------------------------------- |
| 109 | // global signals |
| 110 | // ----------------------------------------------------------------------- |
| 111 | |
| 112 | input l2clk; |
| 113 | input scan_in; |
| 114 | input pce; |
| 115 | input tcu_pce_ov; |
| 116 | input tcu_aclk; |
| 117 | input tcu_bclk; |
| 118 | input tcu_array_wr_inhibit; |
| 119 | input tcu_scan_en; |
| 120 | input tcu_se_scancollar_in; |
| 121 | |
| 122 | input main_clken; |
| 123 | |
| 124 | output scan_out; |
| 125 | |
| 126 | |
| 127 | // ----------------------------------------------------------------------- |
| 128 | // Reading controls |
| 129 | // ----------------------------------------------------------------------- |
| 130 | input [2:0] r_tid; |
| 131 | input r1_valid; |
| 132 | input [4:0] r1_addr; |
| 133 | input r2_valid; |
| 134 | input [4:0] r2_addr; |
| 135 | |
| 136 | // ----------------------------------------------------------------------- |
| 137 | // Writing controls |
| 138 | // ----------------------------------------------------------------------- |
| 139 | input [2:0] w1_tid; |
| 140 | input [1:0] w1_valid; |
| 141 | input [4:0] w1_addr; |
| 142 | input [2:0] w2_tid; |
| 143 | input [1:0] w2_valid; |
| 144 | input [4:0] w2_addr; |
| 145 | |
| 146 | // ----------------------------------------------------------------------- |
| 147 | // Write data ports |
| 148 | // ----------------------------------------------------------------------- |
| 149 | input [63:0] w1_data; |
| 150 | input [13:0] w1_ecc; |
| 151 | input [63:0] w2_data; |
| 152 | input [13:0] w2_ecc; |
| 153 | |
| 154 | `ifndef FPGA |
| 155 | // synopsys translate_off |
| 156 | `endif |
| 157 | |
| 158 | assign siclk = tcu_aclk; |
| 159 | assign soclk = tcu_bclk; |
| 160 | |
| 161 | n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro clkgen ( |
| 162 | .l2clk (l2clk ), |
| 163 | .l1en (pce ), |
| 164 | .pce_ov (tcu_pce_ov ), |
| 165 | .stop (1'b0 ), |
| 166 | .se (tcu_se_scancollar_in ), |
| 167 | .l1clk (l1clk )); |
| 168 | |
| 169 | |
| 170 | n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro clkgen_main ( |
| 171 | .l2clk (l2clk ), |
| 172 | .l1en (main_clken ), |
| 173 | .pce_ov (tcu_pce_ov ), |
| 174 | .stop (1'b0 ), |
| 175 | .se (tcu_se_scancollar_in ), |
| 176 | .l1clk (l1clk_main )); |
| 177 | |
| 178 | |
| 179 | |
| 180 | n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_14 w1_ecc_synd_fb_to_fw ( |
| 181 | .scan_in(w1_ecc_synd_fb_to_fw_scanin[13:0]), |
| 182 | .scan_out(w1_ecc_synd_fb_to_fw_scanout[13:0]), |
| 183 | .l1clk (l1clk_main), |
| 184 | .din (w1_ecc [13:0]), |
| 185 | .dout (w1_ecc_fw[13:0]), |
| 186 | .siclk(siclk), |
| 187 | .soclk(soclk)); |
| 188 | |
| 189 | n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_14 w2_ecc_synd_fb_to_fw ( |
| 190 | .scan_in(w2_ecc_synd_fb_to_fw_scanin[13:0]), |
| 191 | .scan_out(w2_ecc_synd_fb_to_fw_scanout[13:0]), |
| 192 | .l1clk (l1clk_main), |
| 193 | .din (w2_ecc [13:0]), |
| 194 | .dout (w2_ecc_fw[13:0]), |
| 195 | .siclk(siclk), |
| 196 | .soclk(soclk)); |
| 197 | |
| 198 | n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_15 frf_read_ctl_in2ph2 ( |
| 199 | .scan_in(frf_read_ctl_in2ph2_scanin[14:0]), |
| 200 | .scan_out(frf_read_ctl_in2ph2_scanout[14:0]), |
| 201 | .l1clk (l1clk), |
| 202 | .din ({r1_addr [4:0], // requires free running clk or dec_fgu_decode_d en |
| 203 | r2_addr [4:0], // requires free running clk or dec_fgu_decode_d en |
| 204 | r1_valid , // requires free running clk or dec_fgu_decode_d en |
| 205 | r2_valid , // requires free running clk or dec_fgu_decode_d en |
| 206 | r_tid [2:0]}), // requires free running clk or dec_fgu_decode_d en |
| 207 | .dout ({r1_addr_ph2[4:0], |
| 208 | r2_addr_ph2[4:0], |
| 209 | r1_valid_ph2 , |
| 210 | r2_valid_ph2 , |
| 211 | r_tid_ph2 [2:0]}), |
| 212 | .siclk(siclk), |
| 213 | .soclk(soclk)); |
| 214 | |
| 215 | |
| 216 | n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_64 fw_w2data ( |
| 217 | .scan_in(fw_w2data_scanin[63:0]), |
| 218 | .scan_out(fw_w2data_scanout[63:0]), |
| 219 | .l1clk (l1clk_main), |
| 220 | .din (w2_data [63:0]), |
| 221 | .dout (w2_data_fw[63:0]), |
| 222 | .siclk(siclk), |
| 223 | .soclk(soclk)); |
| 224 | |
| 225 | n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_64 fw_w1data ( |
| 226 | .scan_in(fw_w1data_scanin[63:0]), |
| 227 | .scan_out(fw_w1data_scanout[63:0]), |
| 228 | .l1clk (l1clk_main), |
| 229 | .din (w1_data [63:0]), |
| 230 | .dout (w1_data_fw[63:0]), |
| 231 | .siclk(siclk), |
| 232 | .soclk(soclk)); |
| 233 | |
| 234 | |
| 235 | n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_20 frf_write_input_ctl_in2fb ( |
| 236 | .scan_in(frf_write_input_ctl_in2fb_scanin[19:0]), |
| 237 | .scan_out(frf_write_input_ctl_in2fb_scanout[19:0]), |
| 238 | .l1clk (l1clk_main), |
| 239 | .din ({w1_tid [2:0], |
| 240 | w1_valid [1:0], |
| 241 | w1_addr [4:0], |
| 242 | w2_tid [2:0], |
| 243 | w2_valid [1:0], |
| 244 | w2_addr [4:0]}), |
| 245 | .dout ({w1_tid_fw [2:0], |
| 246 | w1_valid_fw [1:0], |
| 247 | w1_addr_fw [4:0], |
| 248 | w2_tid_fw [2:0], |
| 249 | w2_valid_fw [1:0], |
| 250 | w2_addr_fw [4:0]}), |
| 251 | .siclk(siclk), |
| 252 | .soclk(soclk)); |
| 253 | |
| 254 | |
| 255 | |
| 256 | |
| 257 | // L2 clock "free-running" clock |
| 258 | n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro clkgen_free ( |
| 259 | .l2clk (l2clk ), |
| 260 | .l1en (pce ), |
| 261 | .pce_ov (tcu_pce_ov ), |
| 262 | .stop (1'b0 ), |
| 263 | .se (tcu_scan_en ), |
| 264 | .l1clk (l1clk_free )); |
| 265 | |
| 266 | fgu_frf_array frf_array_o ( |
| 267 | .clk ( l1clk_free ), |
| 268 | .r1_valid ( r1_valid_ph2 ), |
| 269 | .r1_addr ({r_tid_ph2[2:0] , r1_addr_ph2[4:0]} ), |
| 270 | .r2_valid ( r2_valid_ph2 ), |
| 271 | .r2_addr ({r_tid_ph2[2:0] , r2_addr_ph2[4:0]} ), |
| 272 | .w1_valid ( w1_valid_fw[0] ), |
| 273 | .w1_addr ({w1_tid_fw[2:0] , w1_addr_fw[4:0]} ), |
| 274 | .w1_data ({w1_ecc_fw[6:0] , w1_data_fw[31:0]} ), |
| 275 | .w2_valid ( w2_valid_fw[0] ), |
| 276 | .w2_addr ({w2_tid_fw[2:0] , w2_addr_fw[4:0]} ), |
| 277 | .w2_data ({w2_ecc_fw[6:0] , w2_data_fw[31:0]} ), |
| 278 | .r1_data ({frf_r1_ecc[6:0] , frf_r1_data[31:0]} ), |
| 279 | .r2_data ({frf_r2_ecc[6:0] , frf_r2_data[31:0]} ), |
| 280 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit)); |
| 281 | |
| 282 | |
| 283 | |
| 284 | fgu_frf_array frf_array_e ( |
| 285 | .clk ( l1clk_free ), |
| 286 | .r1_valid ( r1_valid_ph2 ), |
| 287 | .r1_addr ({r_tid_ph2[2:0] , r1_addr_ph2[4:0]} ), |
| 288 | .r2_valid ( r2_valid_ph2 ), |
| 289 | .r2_addr ({r_tid_ph2[2:0] , r2_addr_ph2[4:0]} ), |
| 290 | .w1_valid ( w1_valid_fw[1] ), |
| 291 | .w1_addr ({w1_tid_fw[2:0] , w1_addr_fw[4:0]} ), |
| 292 | .w1_data ({w1_ecc_fw[13:7] , w1_data_fw[63:32]} ), |
| 293 | .w2_valid ( w2_valid_fw[1] ), |
| 294 | .w2_addr ({w2_tid_fw[2:0] , w2_addr_fw[4:0]} ), |
| 295 | .w2_data ({w2_ecc_fw[13:7] , w2_data_fw[63:32]} ), |
| 296 | .r1_data ({frf_r1_ecc[13:7] , frf_r1_data[63:32]} ), |
| 297 | .r2_data ({frf_r2_ecc[13:7] , frf_r2_data[63:32]} ), |
| 298 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit)); |
| 299 | |
| 300 | |
| 301 | |
| 302 | |
| 303 | |
| 304 | supply0 vss; |
| 305 | supply1 vdd; |
| 306 | |
| 307 | |
| 308 | |
| 309 | |
| 310 | |
| 311 | // scanorder start |
| 312 | // w1_ecc_synd_fb_to_fw_scanin[13:7] |
| 313 | // fw_w1data_scanin[63:32] |
| 314 | // frf_write_input_ctl_in2fb_scanin[16] |
| 315 | // frf_read_ctl_in2ph2_scanin[14:10] |
| 316 | // frf_write_input_ctl_in2fb_scanin[9:7] |
| 317 | // frf_write_input_ctl_in2fb_scanin[0] |
| 318 | // frf_read_ctl_in2ph2_scanin[2:0] |
| 319 | // frf_read_ctl_in2ph2_scanin[9:5] |
| 320 | // frf_write_input_ctl_in2fb_scanin[4] |
| 321 | // frf_write_input_ctl_in2fb_scanin[5] |
| 322 | // w1_ecc_synd_fb_to_fw_scanin[6:0] |
| 323 | // fw_w1data_scanin[31:0] |
| 324 | // fw_w2data_scanin[0:31] |
| 325 | // w2_ecc_synd_fb_to_fw_scanin[0:6] |
| 326 | // frf_write_input_ctl_in2fb_scanin[15] |
| 327 | // frf_write_input_ctl_in2fb_scanin[1] |
| 328 | // frf_write_input_ctl_in2fb_scanin[2] |
| 329 | // frf_write_input_ctl_in2fb_scanin[3] |
| 330 | // frf_read_ctl_in2ph2_scanin[3] |
| 331 | // frf_read_ctl_in2ph2_scanin[4] |
| 332 | // frf_write_input_ctl_in2fb_scanin[10] |
| 333 | // frf_write_input_ctl_in2fb_scanin[11] |
| 334 | // frf_write_input_ctl_in2fb_scanin[12] |
| 335 | // frf_write_input_ctl_in2fb_scanin[13] |
| 336 | // frf_write_input_ctl_in2fb_scanin[14] |
| 337 | // frf_write_input_ctl_in2fb_scanin[17] |
| 338 | // frf_write_input_ctl_in2fb_scanin[18] |
| 339 | // frf_write_input_ctl_in2fb_scanin[19] |
| 340 | // frf_write_input_ctl_in2fb_scanin[6] |
| 341 | // fw_w2data_scanin[32:63] |
| 342 | // w2_ecc_synd_fb_to_fw_scanin[7:13] |
| 343 | // scanorder end |
| 344 | // fixscan start |
| 345 | assign w1_ecc_synd_fb_to_fw_scanin[13]=scan_in; |
| 346 | assign w1_ecc_synd_fb_to_fw_scanin[12]=w1_ecc_synd_fb_to_fw_scanout[13]; |
| 347 | assign w1_ecc_synd_fb_to_fw_scanin[11]=w1_ecc_synd_fb_to_fw_scanout[12]; |
| 348 | assign w1_ecc_synd_fb_to_fw_scanin[10]=w1_ecc_synd_fb_to_fw_scanout[11]; |
| 349 | assign w1_ecc_synd_fb_to_fw_scanin[9]=w1_ecc_synd_fb_to_fw_scanout[10]; |
| 350 | assign w1_ecc_synd_fb_to_fw_scanin[8]=w1_ecc_synd_fb_to_fw_scanout[9]; |
| 351 | assign w1_ecc_synd_fb_to_fw_scanin[7]=w1_ecc_synd_fb_to_fw_scanout[8]; |
| 352 | assign fw_w1data_scanin[63]=w1_ecc_synd_fb_to_fw_scanout[7]; |
| 353 | assign fw_w1data_scanin[62]=fw_w1data_scanout[63]; |
| 354 | assign fw_w1data_scanin[61]=fw_w1data_scanout[62]; |
| 355 | assign fw_w1data_scanin[60]=fw_w1data_scanout[61]; |
| 356 | assign fw_w1data_scanin[59]=fw_w1data_scanout[60]; |
| 357 | assign fw_w1data_scanin[58]=fw_w1data_scanout[59]; |
| 358 | assign fw_w1data_scanin[57]=fw_w1data_scanout[58]; |
| 359 | assign fw_w1data_scanin[56]=fw_w1data_scanout[57]; |
| 360 | assign fw_w1data_scanin[55]=fw_w1data_scanout[56]; |
| 361 | assign fw_w1data_scanin[54]=fw_w1data_scanout[55]; |
| 362 | assign fw_w1data_scanin[53]=fw_w1data_scanout[54]; |
| 363 | assign fw_w1data_scanin[52]=fw_w1data_scanout[53]; |
| 364 | assign fw_w1data_scanin[51]=fw_w1data_scanout[52]; |
| 365 | assign fw_w1data_scanin[50]=fw_w1data_scanout[51]; |
| 366 | assign fw_w1data_scanin[49]=fw_w1data_scanout[50]; |
| 367 | assign fw_w1data_scanin[48]=fw_w1data_scanout[49]; |
| 368 | assign fw_w1data_scanin[47]=fw_w1data_scanout[48]; |
| 369 | assign fw_w1data_scanin[46]=fw_w1data_scanout[47]; |
| 370 | assign fw_w1data_scanin[45]=fw_w1data_scanout[46]; |
| 371 | assign fw_w1data_scanin[44]=fw_w1data_scanout[45]; |
| 372 | assign fw_w1data_scanin[43]=fw_w1data_scanout[44]; |
| 373 | assign fw_w1data_scanin[42]=fw_w1data_scanout[43]; |
| 374 | assign fw_w1data_scanin[41]=fw_w1data_scanout[42]; |
| 375 | assign fw_w1data_scanin[40]=fw_w1data_scanout[41]; |
| 376 | assign fw_w1data_scanin[39]=fw_w1data_scanout[40]; |
| 377 | assign fw_w1data_scanin[38]=fw_w1data_scanout[39]; |
| 378 | assign fw_w1data_scanin[37]=fw_w1data_scanout[38]; |
| 379 | assign fw_w1data_scanin[36]=fw_w1data_scanout[37]; |
| 380 | assign fw_w1data_scanin[35]=fw_w1data_scanout[36]; |
| 381 | assign fw_w1data_scanin[34]=fw_w1data_scanout[35]; |
| 382 | assign fw_w1data_scanin[33]=fw_w1data_scanout[34]; |
| 383 | assign fw_w1data_scanin[32]=fw_w1data_scanout[33]; |
| 384 | assign frf_write_input_ctl_in2fb_scanin[16]=fw_w1data_scanout[32]; |
| 385 | assign frf_read_ctl_in2ph2_scanin[14]=frf_write_input_ctl_in2fb_scanout[16]; |
| 386 | assign frf_read_ctl_in2ph2_scanin[13]=frf_read_ctl_in2ph2_scanout[14]; |
| 387 | assign frf_read_ctl_in2ph2_scanin[12]=frf_read_ctl_in2ph2_scanout[13]; |
| 388 | assign frf_read_ctl_in2ph2_scanin[11]=frf_read_ctl_in2ph2_scanout[12]; |
| 389 | assign frf_read_ctl_in2ph2_scanin[10]=frf_read_ctl_in2ph2_scanout[11]; |
| 390 | assign frf_write_input_ctl_in2fb_scanin[9]=frf_read_ctl_in2ph2_scanout[10]; |
| 391 | assign frf_write_input_ctl_in2fb_scanin[8]=frf_write_input_ctl_in2fb_scanout[9]; |
| 392 | assign frf_write_input_ctl_in2fb_scanin[7]=frf_write_input_ctl_in2fb_scanout[8]; |
| 393 | assign frf_write_input_ctl_in2fb_scanin[0]=frf_write_input_ctl_in2fb_scanout[7]; |
| 394 | assign frf_read_ctl_in2ph2_scanin[2]=frf_write_input_ctl_in2fb_scanout[0]; |
| 395 | assign frf_read_ctl_in2ph2_scanin[1]=frf_read_ctl_in2ph2_scanout[2]; |
| 396 | assign frf_read_ctl_in2ph2_scanin[0]=frf_read_ctl_in2ph2_scanout[1]; |
| 397 | assign frf_read_ctl_in2ph2_scanin[9]=frf_read_ctl_in2ph2_scanout[0]; |
| 398 | assign frf_read_ctl_in2ph2_scanin[8]=frf_read_ctl_in2ph2_scanout[9]; |
| 399 | assign frf_read_ctl_in2ph2_scanin[7]=frf_read_ctl_in2ph2_scanout[8]; |
| 400 | assign frf_read_ctl_in2ph2_scanin[6]=frf_read_ctl_in2ph2_scanout[7]; |
| 401 | assign frf_read_ctl_in2ph2_scanin[5]=frf_read_ctl_in2ph2_scanout[6]; |
| 402 | assign frf_write_input_ctl_in2fb_scanin[4]=frf_read_ctl_in2ph2_scanout[5]; |
| 403 | assign frf_write_input_ctl_in2fb_scanin[5]=frf_write_input_ctl_in2fb_scanout[4]; |
| 404 | assign w1_ecc_synd_fb_to_fw_scanin[6]=frf_write_input_ctl_in2fb_scanout[5]; |
| 405 | assign w1_ecc_synd_fb_to_fw_scanin[5]=w1_ecc_synd_fb_to_fw_scanout[6]; |
| 406 | assign w1_ecc_synd_fb_to_fw_scanin[4]=w1_ecc_synd_fb_to_fw_scanout[5]; |
| 407 | assign w1_ecc_synd_fb_to_fw_scanin[3]=w1_ecc_synd_fb_to_fw_scanout[4]; |
| 408 | assign w1_ecc_synd_fb_to_fw_scanin[2]=w1_ecc_synd_fb_to_fw_scanout[3]; |
| 409 | assign w1_ecc_synd_fb_to_fw_scanin[1]=w1_ecc_synd_fb_to_fw_scanout[2]; |
| 410 | assign w1_ecc_synd_fb_to_fw_scanin[0]=w1_ecc_synd_fb_to_fw_scanout[1]; |
| 411 | assign fw_w1data_scanin[31]=w1_ecc_synd_fb_to_fw_scanout[0]; |
| 412 | assign fw_w1data_scanin[30]=fw_w1data_scanout[31]; |
| 413 | assign fw_w1data_scanin[29]=fw_w1data_scanout[30]; |
| 414 | assign fw_w1data_scanin[28]=fw_w1data_scanout[29]; |
| 415 | assign fw_w1data_scanin[27]=fw_w1data_scanout[28]; |
| 416 | assign fw_w1data_scanin[26]=fw_w1data_scanout[27]; |
| 417 | assign fw_w1data_scanin[25]=fw_w1data_scanout[26]; |
| 418 | assign fw_w1data_scanin[24]=fw_w1data_scanout[25]; |
| 419 | assign fw_w1data_scanin[23]=fw_w1data_scanout[24]; |
| 420 | assign fw_w1data_scanin[22]=fw_w1data_scanout[23]; |
| 421 | assign fw_w1data_scanin[21]=fw_w1data_scanout[22]; |
| 422 | assign fw_w1data_scanin[20]=fw_w1data_scanout[21]; |
| 423 | assign fw_w1data_scanin[19]=fw_w1data_scanout[20]; |
| 424 | assign fw_w1data_scanin[18]=fw_w1data_scanout[19]; |
| 425 | assign fw_w1data_scanin[17]=fw_w1data_scanout[18]; |
| 426 | assign fw_w1data_scanin[16]=fw_w1data_scanout[17]; |
| 427 | assign fw_w1data_scanin[15]=fw_w1data_scanout[16]; |
| 428 | assign fw_w1data_scanin[14]=fw_w1data_scanout[15]; |
| 429 | assign fw_w1data_scanin[13]=fw_w1data_scanout[14]; |
| 430 | assign fw_w1data_scanin[12]=fw_w1data_scanout[13]; |
| 431 | assign fw_w1data_scanin[11]=fw_w1data_scanout[12]; |
| 432 | assign fw_w1data_scanin[10]=fw_w1data_scanout[11]; |
| 433 | assign fw_w1data_scanin[9]=fw_w1data_scanout[10]; |
| 434 | assign fw_w1data_scanin[8]=fw_w1data_scanout[9]; |
| 435 | assign fw_w1data_scanin[7]=fw_w1data_scanout[8]; |
| 436 | assign fw_w1data_scanin[6]=fw_w1data_scanout[7]; |
| 437 | assign fw_w1data_scanin[5]=fw_w1data_scanout[6]; |
| 438 | assign fw_w1data_scanin[4]=fw_w1data_scanout[5]; |
| 439 | assign fw_w1data_scanin[3]=fw_w1data_scanout[4]; |
| 440 | assign fw_w1data_scanin[2]=fw_w1data_scanout[3]; |
| 441 | assign fw_w1data_scanin[1]=fw_w1data_scanout[2]; |
| 442 | assign fw_w1data_scanin[0]=fw_w1data_scanout[1]; |
| 443 | assign fw_w2data_scanin[0]=fw_w1data_scanout[0]; |
| 444 | assign fw_w2data_scanin[1]=fw_w2data_scanout[0]; |
| 445 | assign fw_w2data_scanin[2]=fw_w2data_scanout[1]; |
| 446 | assign fw_w2data_scanin[3]=fw_w2data_scanout[2]; |
| 447 | assign fw_w2data_scanin[4]=fw_w2data_scanout[3]; |
| 448 | assign fw_w2data_scanin[5]=fw_w2data_scanout[4]; |
| 449 | assign fw_w2data_scanin[6]=fw_w2data_scanout[5]; |
| 450 | assign fw_w2data_scanin[7]=fw_w2data_scanout[6]; |
| 451 | assign fw_w2data_scanin[8]=fw_w2data_scanout[7]; |
| 452 | assign fw_w2data_scanin[9]=fw_w2data_scanout[8]; |
| 453 | assign fw_w2data_scanin[10]=fw_w2data_scanout[9]; |
| 454 | assign fw_w2data_scanin[11]=fw_w2data_scanout[10]; |
| 455 | assign fw_w2data_scanin[12]=fw_w2data_scanout[11]; |
| 456 | assign fw_w2data_scanin[13]=fw_w2data_scanout[12]; |
| 457 | assign fw_w2data_scanin[14]=fw_w2data_scanout[13]; |
| 458 | assign fw_w2data_scanin[15]=fw_w2data_scanout[14]; |
| 459 | assign fw_w2data_scanin[16]=fw_w2data_scanout[15]; |
| 460 | assign fw_w2data_scanin[17]=fw_w2data_scanout[16]; |
| 461 | assign fw_w2data_scanin[18]=fw_w2data_scanout[17]; |
| 462 | assign fw_w2data_scanin[19]=fw_w2data_scanout[18]; |
| 463 | assign fw_w2data_scanin[20]=fw_w2data_scanout[19]; |
| 464 | assign fw_w2data_scanin[21]=fw_w2data_scanout[20]; |
| 465 | assign fw_w2data_scanin[22]=fw_w2data_scanout[21]; |
| 466 | assign fw_w2data_scanin[23]=fw_w2data_scanout[22]; |
| 467 | assign fw_w2data_scanin[24]=fw_w2data_scanout[23]; |
| 468 | assign fw_w2data_scanin[25]=fw_w2data_scanout[24]; |
| 469 | assign fw_w2data_scanin[26]=fw_w2data_scanout[25]; |
| 470 | assign fw_w2data_scanin[27]=fw_w2data_scanout[26]; |
| 471 | assign fw_w2data_scanin[28]=fw_w2data_scanout[27]; |
| 472 | assign fw_w2data_scanin[29]=fw_w2data_scanout[28]; |
| 473 | assign fw_w2data_scanin[30]=fw_w2data_scanout[29]; |
| 474 | assign fw_w2data_scanin[31]=fw_w2data_scanout[30]; |
| 475 | assign w2_ecc_synd_fb_to_fw_scanin[0]=fw_w2data_scanout[31]; |
| 476 | assign w2_ecc_synd_fb_to_fw_scanin[1]=w2_ecc_synd_fb_to_fw_scanout[0]; |
| 477 | assign w2_ecc_synd_fb_to_fw_scanin[2]=w2_ecc_synd_fb_to_fw_scanout[1]; |
| 478 | assign w2_ecc_synd_fb_to_fw_scanin[3]=w2_ecc_synd_fb_to_fw_scanout[2]; |
| 479 | assign w2_ecc_synd_fb_to_fw_scanin[4]=w2_ecc_synd_fb_to_fw_scanout[3]; |
| 480 | assign w2_ecc_synd_fb_to_fw_scanin[5]=w2_ecc_synd_fb_to_fw_scanout[4]; |
| 481 | assign w2_ecc_synd_fb_to_fw_scanin[6]=w2_ecc_synd_fb_to_fw_scanout[5]; |
| 482 | assign frf_write_input_ctl_in2fb_scanin[15]=w2_ecc_synd_fb_to_fw_scanout[6]; |
| 483 | assign frf_write_input_ctl_in2fb_scanin[1]=frf_write_input_ctl_in2fb_scanout[15]; |
| 484 | assign frf_write_input_ctl_in2fb_scanin[2]=frf_write_input_ctl_in2fb_scanout[1]; |
| 485 | assign frf_write_input_ctl_in2fb_scanin[3]=frf_write_input_ctl_in2fb_scanout[2]; |
| 486 | assign frf_read_ctl_in2ph2_scanin[3]=frf_write_input_ctl_in2fb_scanout[3]; |
| 487 | assign frf_read_ctl_in2ph2_scanin[4]=frf_read_ctl_in2ph2_scanout[3]; |
| 488 | assign frf_write_input_ctl_in2fb_scanin[10]=frf_read_ctl_in2ph2_scanout[4]; |
| 489 | assign frf_write_input_ctl_in2fb_scanin[11]=frf_write_input_ctl_in2fb_scanout[10]; |
| 490 | assign frf_write_input_ctl_in2fb_scanin[12]=frf_write_input_ctl_in2fb_scanout[11]; |
| 491 | assign frf_write_input_ctl_in2fb_scanin[13]=frf_write_input_ctl_in2fb_scanout[12]; |
| 492 | assign frf_write_input_ctl_in2fb_scanin[14]=frf_write_input_ctl_in2fb_scanout[13]; |
| 493 | assign frf_write_input_ctl_in2fb_scanin[17]=frf_write_input_ctl_in2fb_scanout[14]; |
| 494 | assign frf_write_input_ctl_in2fb_scanin[18]=frf_write_input_ctl_in2fb_scanout[17]; |
| 495 | assign frf_write_input_ctl_in2fb_scanin[19]=frf_write_input_ctl_in2fb_scanout[18]; |
| 496 | assign frf_write_input_ctl_in2fb_scanin[6]=frf_write_input_ctl_in2fb_scanout[19]; |
| 497 | assign fw_w2data_scanin[32]=frf_write_input_ctl_in2fb_scanout[6]; |
| 498 | assign fw_w2data_scanin[33]=fw_w2data_scanout[32]; |
| 499 | assign fw_w2data_scanin[34]=fw_w2data_scanout[33]; |
| 500 | assign fw_w2data_scanin[35]=fw_w2data_scanout[34]; |
| 501 | assign fw_w2data_scanin[36]=fw_w2data_scanout[35]; |
| 502 | assign fw_w2data_scanin[37]=fw_w2data_scanout[36]; |
| 503 | assign fw_w2data_scanin[38]=fw_w2data_scanout[37]; |
| 504 | assign fw_w2data_scanin[39]=fw_w2data_scanout[38]; |
| 505 | assign fw_w2data_scanin[40]=fw_w2data_scanout[39]; |
| 506 | assign fw_w2data_scanin[41]=fw_w2data_scanout[40]; |
| 507 | assign fw_w2data_scanin[42]=fw_w2data_scanout[41]; |
| 508 | assign fw_w2data_scanin[43]=fw_w2data_scanout[42]; |
| 509 | assign fw_w2data_scanin[44]=fw_w2data_scanout[43]; |
| 510 | assign fw_w2data_scanin[45]=fw_w2data_scanout[44]; |
| 511 | assign fw_w2data_scanin[46]=fw_w2data_scanout[45]; |
| 512 | assign fw_w2data_scanin[47]=fw_w2data_scanout[46]; |
| 513 | assign fw_w2data_scanin[48]=fw_w2data_scanout[47]; |
| 514 | assign fw_w2data_scanin[49]=fw_w2data_scanout[48]; |
| 515 | assign fw_w2data_scanin[50]=fw_w2data_scanout[49]; |
| 516 | assign fw_w2data_scanin[51]=fw_w2data_scanout[50]; |
| 517 | assign fw_w2data_scanin[52]=fw_w2data_scanout[51]; |
| 518 | assign fw_w2data_scanin[53]=fw_w2data_scanout[52]; |
| 519 | assign fw_w2data_scanin[54]=fw_w2data_scanout[53]; |
| 520 | assign fw_w2data_scanin[55]=fw_w2data_scanout[54]; |
| 521 | assign fw_w2data_scanin[56]=fw_w2data_scanout[55]; |
| 522 | assign fw_w2data_scanin[57]=fw_w2data_scanout[56]; |
| 523 | assign fw_w2data_scanin[58]=fw_w2data_scanout[57]; |
| 524 | assign fw_w2data_scanin[59]=fw_w2data_scanout[58]; |
| 525 | assign fw_w2data_scanin[60]=fw_w2data_scanout[59]; |
| 526 | assign fw_w2data_scanin[61]=fw_w2data_scanout[60]; |
| 527 | assign fw_w2data_scanin[62]=fw_w2data_scanout[61]; |
| 528 | assign fw_w2data_scanin[63]=fw_w2data_scanout[62]; |
| 529 | assign w2_ecc_synd_fb_to_fw_scanin[7]=fw_w2data_scanout[63]; |
| 530 | assign w2_ecc_synd_fb_to_fw_scanin[8]=w2_ecc_synd_fb_to_fw_scanout[7]; |
| 531 | assign w2_ecc_synd_fb_to_fw_scanin[9]=w2_ecc_synd_fb_to_fw_scanout[8]; |
| 532 | assign w2_ecc_synd_fb_to_fw_scanin[10]=w2_ecc_synd_fb_to_fw_scanout[9]; |
| 533 | assign w2_ecc_synd_fb_to_fw_scanin[11]=w2_ecc_synd_fb_to_fw_scanout[10]; |
| 534 | assign w2_ecc_synd_fb_to_fw_scanin[12]=w2_ecc_synd_fb_to_fw_scanout[11]; |
| 535 | assign w2_ecc_synd_fb_to_fw_scanin[13]=w2_ecc_synd_fb_to_fw_scanout[12]; |
| 536 | assign scan_out=w2_ecc_synd_fb_to_fw_scanout[13]; |
| 537 | // fixscan end |
| 538 | |
| 539 | `ifndef FPGA |
| 540 | // synopsys translate_on |
| 541 | `endif |
| 542 | |
| 543 | endmodule // fgu_frf_cust |
| 544 | |
| 545 | |
| 546 | |
| 547 | |
| 548 | |
| 549 | |
| 550 | // any PARAMS parms go into naming of macro |
| 551 | |
| 552 | module n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro ( |
| 553 | l2clk, |
| 554 | l1en, |
| 555 | pce_ov, |
| 556 | stop, |
| 557 | se, |
| 558 | l1clk); |
| 559 | |
| 560 | |
| 561 | input l2clk; |
| 562 | input l1en; |
| 563 | input pce_ov; |
| 564 | input stop; |
| 565 | input se; |
| 566 | output l1clk; |
| 567 | |
| 568 | |
| 569 | |
| 570 | |
| 571 | |
| 572 | cl_sc1_l1hdr_8x c_0 ( |
| 573 | |
| 574 | |
| 575 | .l2clk(l2clk), |
| 576 | .pce(l1en), |
| 577 | .l1clk(l1clk), |
| 578 | .se(se), |
| 579 | .pce_ov(pce_ov), |
| 580 | .stop(stop) |
| 581 | ); |
| 582 | |
| 583 | |
| 584 | |
| 585 | endmodule |
| 586 | |
| 587 | |
| 588 | |
| 589 | |
| 590 | |
| 591 | |
| 592 | |
| 593 | |
| 594 | |
| 595 | |
| 596 | |
| 597 | |
| 598 | |
| 599 | // any PARAMS parms go into naming of macro |
| 600 | |
| 601 | module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_14 ( |
| 602 | din, |
| 603 | l1clk, |
| 604 | scan_in, |
| 605 | siclk, |
| 606 | soclk, |
| 607 | dout, |
| 608 | scan_out); |
| 609 | wire [13:0] fdin; |
| 610 | |
| 611 | input [13:0] din; |
| 612 | input l1clk; |
| 613 | input [13:0] scan_in; |
| 614 | |
| 615 | |
| 616 | input siclk; |
| 617 | input soclk; |
| 618 | |
| 619 | output [13:0] dout; |
| 620 | output [13:0] scan_out; |
| 621 | assign fdin[13:0] = din[13:0]; |
| 622 | |
| 623 | |
| 624 | |
| 625 | |
| 626 | |
| 627 | |
| 628 | dff #(14) d0_0 ( |
| 629 | .l1clk(l1clk), |
| 630 | .siclk(siclk), |
| 631 | .soclk(soclk), |
| 632 | .d(fdin[13:0]), |
| 633 | .si(scan_in[13:0]), |
| 634 | .so(scan_out[13:0]), |
| 635 | .q(dout[13:0]) |
| 636 | ); |
| 637 | |
| 638 | |
| 639 | |
| 640 | |
| 641 | |
| 642 | |
| 643 | |
| 644 | |
| 645 | |
| 646 | |
| 647 | |
| 648 | |
| 649 | endmodule |
| 650 | |
| 651 | |
| 652 | |
| 653 | |
| 654 | |
| 655 | |
| 656 | |
| 657 | |
| 658 | |
| 659 | |
| 660 | |
| 661 | |
| 662 | |
| 663 | // any PARAMS parms go into naming of macro |
| 664 | |
| 665 | module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_14 ( |
| 666 | din, |
| 667 | l1clk, |
| 668 | scan_in, |
| 669 | siclk, |
| 670 | soclk, |
| 671 | dout, |
| 672 | scan_out); |
| 673 | wire [13:0] fdin; |
| 674 | |
| 675 | input [13:0] din; |
| 676 | input l1clk; |
| 677 | input [13:0] scan_in; |
| 678 | |
| 679 | |
| 680 | input siclk; |
| 681 | input soclk; |
| 682 | |
| 683 | output [13:0] dout; |
| 684 | output [13:0] scan_out; |
| 685 | assign fdin[13:0] = din[13:0]; |
| 686 | |
| 687 | |
| 688 | |
| 689 | |
| 690 | |
| 691 | |
| 692 | dff #(14) d0_0 ( |
| 693 | .l1clk(l1clk), |
| 694 | .siclk(siclk), |
| 695 | .soclk(soclk), |
| 696 | .d(fdin[13:0]), |
| 697 | .si(scan_in[13:0]), |
| 698 | .so(scan_out[13:0]), |
| 699 | .q(dout[13:0]) |
| 700 | ); |
| 701 | |
| 702 | |
| 703 | |
| 704 | |
| 705 | |
| 706 | |
| 707 | |
| 708 | |
| 709 | |
| 710 | |
| 711 | |
| 712 | |
| 713 | endmodule |
| 714 | |
| 715 | |
| 716 | |
| 717 | |
| 718 | |
| 719 | |
| 720 | |
| 721 | |
| 722 | |
| 723 | |
| 724 | |
| 725 | |
| 726 | |
| 727 | // any PARAMS parms go into naming of macro |
| 728 | |
| 729 | module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_15 ( |
| 730 | din, |
| 731 | l1clk, |
| 732 | scan_in, |
| 733 | siclk, |
| 734 | soclk, |
| 735 | dout, |
| 736 | scan_out); |
| 737 | wire [14:0] fdin; |
| 738 | |
| 739 | input [14:0] din; |
| 740 | input l1clk; |
| 741 | input [14:0] scan_in; |
| 742 | |
| 743 | |
| 744 | input siclk; |
| 745 | input soclk; |
| 746 | |
| 747 | output [14:0] dout; |
| 748 | output [14:0] scan_out; |
| 749 | assign fdin[14:0] = din[14:0]; |
| 750 | |
| 751 | |
| 752 | |
| 753 | |
| 754 | |
| 755 | |
| 756 | dff #(15) d0_0 ( |
| 757 | .l1clk(l1clk), |
| 758 | .siclk(siclk), |
| 759 | .soclk(soclk), |
| 760 | .d(fdin[14:0]), |
| 761 | .si(scan_in[14:0]), |
| 762 | .so(scan_out[14:0]), |
| 763 | .q(dout[14:0]) |
| 764 | ); |
| 765 | |
| 766 | |
| 767 | |
| 768 | |
| 769 | |
| 770 | |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | endmodule |
| 778 | |
| 779 | |
| 780 | |
| 781 | |
| 782 | |
| 783 | |
| 784 | |
| 785 | |
| 786 | |
| 787 | |
| 788 | |
| 789 | |
| 790 | |
| 791 | // any PARAMS parms go into naming of macro |
| 792 | |
| 793 | module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_64 ( |
| 794 | din, |
| 795 | l1clk, |
| 796 | scan_in, |
| 797 | siclk, |
| 798 | soclk, |
| 799 | dout, |
| 800 | scan_out); |
| 801 | wire [63:0] fdin; |
| 802 | |
| 803 | input [63:0] din; |
| 804 | input l1clk; |
| 805 | input [63:0] scan_in; |
| 806 | |
| 807 | |
| 808 | input siclk; |
| 809 | input soclk; |
| 810 | |
| 811 | output [63:0] dout; |
| 812 | output [63:0] scan_out; |
| 813 | assign fdin[63:0] = din[63:0]; |
| 814 | |
| 815 | |
| 816 | |
| 817 | |
| 818 | |
| 819 | |
| 820 | dff #(64) d0_0 ( |
| 821 | .l1clk(l1clk), |
| 822 | .siclk(siclk), |
| 823 | .soclk(soclk), |
| 824 | .d(fdin[63:0]), |
| 825 | .si(scan_in[63:0]), |
| 826 | .so(scan_out[63:0]), |
| 827 | .q(dout[63:0]) |
| 828 | ); |
| 829 | |
| 830 | |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | |
| 836 | |
| 837 | |
| 838 | |
| 839 | |
| 840 | |
| 841 | endmodule |
| 842 | |
| 843 | |
| 844 | |
| 845 | |
| 846 | |
| 847 | |
| 848 | |
| 849 | |
| 850 | |
| 851 | |
| 852 | |
| 853 | |
| 854 | |
| 855 | // any PARAMS parms go into naming of macro |
| 856 | |
| 857 | module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_64 ( |
| 858 | din, |
| 859 | l1clk, |
| 860 | scan_in, |
| 861 | siclk, |
| 862 | soclk, |
| 863 | dout, |
| 864 | scan_out); |
| 865 | wire [63:0] fdin; |
| 866 | |
| 867 | input [63:0] din; |
| 868 | input l1clk; |
| 869 | input [63:0] scan_in; |
| 870 | |
| 871 | |
| 872 | input siclk; |
| 873 | input soclk; |
| 874 | |
| 875 | output [63:0] dout; |
| 876 | output [63:0] scan_out; |
| 877 | assign fdin[63:0] = din[63:0]; |
| 878 | |
| 879 | |
| 880 | |
| 881 | |
| 882 | |
| 883 | |
| 884 | dff #(64) d0_0 ( |
| 885 | .l1clk(l1clk), |
| 886 | .siclk(siclk), |
| 887 | .soclk(soclk), |
| 888 | .d(fdin[63:0]), |
| 889 | .si(scan_in[63:0]), |
| 890 | .so(scan_out[63:0]), |
| 891 | .q(dout[63:0]) |
| 892 | ); |
| 893 | |
| 894 | |
| 895 | |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | |
| 902 | |
| 903 | |
| 904 | |
| 905 | endmodule |
| 906 | |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | |
| 914 | |
| 915 | |
| 916 | |
| 917 | |
| 918 | |
| 919 | // any PARAMS parms go into naming of macro |
| 920 | |
| 921 | module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_20 ( |
| 922 | din, |
| 923 | l1clk, |
| 924 | scan_in, |
| 925 | siclk, |
| 926 | soclk, |
| 927 | dout, |
| 928 | scan_out); |
| 929 | wire [19:0] fdin; |
| 930 | |
| 931 | input [19:0] din; |
| 932 | input l1clk; |
| 933 | input [19:0] scan_in; |
| 934 | |
| 935 | |
| 936 | input siclk; |
| 937 | input soclk; |
| 938 | |
| 939 | output [19:0] dout; |
| 940 | output [19:0] scan_out; |
| 941 | assign fdin[19:0] = din[19:0]; |
| 942 | |
| 943 | |
| 944 | |
| 945 | |
| 946 | |
| 947 | |
| 948 | dff #(20) d0_0 ( |
| 949 | .l1clk(l1clk), |
| 950 | .siclk(siclk), |
| 951 | .soclk(soclk), |
| 952 | .d(fdin[19:0]), |
| 953 | .si(scan_in[19:0]), |
| 954 | .so(scan_out[19:0]), |
| 955 | .q(dout[19:0]) |
| 956 | ); |
| 957 | |
| 958 | |
| 959 | |
| 960 | |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | |
| 966 | |
| 967 | |
| 968 | |
| 969 | endmodule |
| 970 | |
| 971 | |
| 972 | |
| 973 | |
| 974 | `ifndef FPGA |
| 975 | module fgu_frf_array ( |
| 976 | clk, |
| 977 | tcu_array_wr_inhibit, |
| 978 | r1_valid, |
| 979 | r1_addr, |
| 980 | r2_valid, |
| 981 | r2_addr, |
| 982 | w1_valid, |
| 983 | w1_addr, |
| 984 | w2_valid, |
| 985 | w2_addr, |
| 986 | w1_data, |
| 987 | w2_data, |
| 988 | r1_data, |
| 989 | r2_data); |
| 990 | wire masked_r1_valid; |
| 991 | wire masked_r2_valid; |
| 992 | |
| 993 | |
| 994 | input clk; |
| 995 | |
| 996 | input tcu_array_wr_inhibit; |
| 997 | |
| 998 | // ----------------------------------------------------------------------- |
| 999 | // Reading controls |
| 1000 | // ----------------------------------------------------------------------- |
| 1001 | input r1_valid; |
| 1002 | input [7:0] r1_addr; |
| 1003 | input r2_valid; |
| 1004 | input [7:0] r2_addr; |
| 1005 | |
| 1006 | // ----------------------------------------------------------------------- |
| 1007 | // Writing controls |
| 1008 | // ----------------------------------------------------------------------- |
| 1009 | input w1_valid; |
| 1010 | input [7:0] w1_addr; |
| 1011 | input w2_valid; |
| 1012 | input [7:0] w2_addr; |
| 1013 | |
| 1014 | // ----------------------------------------------------------------------- |
| 1015 | // Write data ports |
| 1016 | // ----------------------------------------------------------------------- |
| 1017 | input [38:0] w1_data; |
| 1018 | input [38:0] w2_data; |
| 1019 | |
| 1020 | |
| 1021 | // ----------------------------------------------------------------------- |
| 1022 | // Read output ports |
| 1023 | // ----------------------------------------------------------------------- |
| 1024 | output [38:0] r1_data; |
| 1025 | output [38:0] r2_data; |
| 1026 | |
| 1027 | reg [38:0] r1_data; // *** Temporary array read regs (no physical flops involved) *** |
| 1028 | reg [38:0] r2_data; // *** Temporary array read regs (no physical flops involved) *** |
| 1029 | |
| 1030 | assign masked_r1_valid = r1_valid & ~(w1_valid & (r1_addr[7:0] == w1_addr[7:0])) |
| 1031 | & ~(w2_valid & (r1_addr[7:0] == w2_addr[7:0])); |
| 1032 | |
| 1033 | assign masked_r2_valid = r2_valid & ~(w1_valid & (r2_addr[7:0] == w1_addr[7:0])) |
| 1034 | & ~(w2_valid & (r2_addr[7:0] == w2_addr[7:0])); |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | |
| 1041 | |
| 1042 | |
| 1043 | |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | reg [38:0] data_array[255:0]; |
| 1049 | |
| 1050 | // *** Initialize section *** |
| 1051 | `ifndef NOINITMEM |
| 1052 | integer i; |
| 1053 | initial begin |
| 1054 | for (i=0; i<=255; i=i+1) begin |
| 1055 | data_array[i] = {39{1'b0}}; |
| 1056 | end |
| 1057 | end |
| 1058 | `endif |
| 1059 | |
| 1060 | |
| 1061 | |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | |
| 1068 | |
| 1069 | |
| 1070 | |
| 1071 | |
| 1072 | |
| 1073 | |
| 1074 | |
| 1075 | |
| 1076 | |
| 1077 | |
| 1078 | |
| 1079 | always @ (posedge clk) begin |
| 1080 | |
| 1081 | r1_data[38:0] <= {39{1'b0}}; |
| 1082 | r2_data[38:0] <= {39{1'b0}}; |
| 1083 | |
| 1084 | end // posedge always |
| 1085 | |
| 1086 | |
| 1087 | always @ (negedge clk) begin |
| 1088 | |
| 1089 | |
| 1090 | // ----------------------------------------------------------------------- |
| 1091 | // *** Read Section *** |
| 1092 | // ----------------------------------------------------------------------- |
| 1093 | |
| 1094 | if (masked_r1_valid) begin |
| 1095 | r1_data[38:0] <= data_array[r1_addr[7:0]]; |
| 1096 | end |
| 1097 | |
| 1098 | |
| 1099 | if (masked_r2_valid) begin |
| 1100 | r2_data[38:0] <= data_array[r2_addr[7:0]]; |
| 1101 | end |
| 1102 | |
| 1103 | |
| 1104 | // ----------------------------------------------------------------------- |
| 1105 | // *** Write Section *** |
| 1106 | // ----------------------------------------------------------------------- |
| 1107 | |
| 1108 | |
| 1109 | // 0in assert -active (w1_valid & w2_valid) -var (w1_addr[7:0] != w2_addr[7:0]) -message "FGU FRF Multiple Write" |
| 1110 | |
| 1111 | |
| 1112 | if (w1_valid & ~tcu_array_wr_inhibit) begin |
| 1113 | data_array[w1_addr[7:0]] <= w1_data[38:0]; |
| 1114 | end |
| 1115 | |
| 1116 | |
| 1117 | if (w2_valid & ~tcu_array_wr_inhibit) begin |
| 1118 | data_array[w2_addr[7:0]] <= w2_data[38:0]; |
| 1119 | end |
| 1120 | |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | |
| 1125 | |
| 1126 | |
| 1127 | |
| 1128 | end // negedge always |
| 1129 | |
| 1130 | |
| 1131 | supply0 vss; |
| 1132 | supply1 vdd; |
| 1133 | |
| 1134 | endmodule // fgu_frf_array |
| 1135 | |
| 1136 | `endif |
| 1137 | |
| 1138 | `ifdef FPGA |
| 1139 | module fgu_frf_array(clk, tcu_array_wr_inhibit, r1_valid, r1_addr, r2_valid, |
| 1140 | r2_addr, w1_valid, w1_addr, w2_valid, w2_addr, w1_data, w2_data, |
| 1141 | r1_data, r2_data); |
| 1142 | |
| 1143 | input clk; |
| 1144 | input tcu_array_wr_inhibit; |
| 1145 | input r1_valid; |
| 1146 | input [7:0] r1_addr; |
| 1147 | input r2_valid; |
| 1148 | input [7:0] r2_addr; |
| 1149 | input w1_valid; |
| 1150 | input [7:0] w1_addr; |
| 1151 | input w2_valid; |
| 1152 | input [7:0] w2_addr; |
| 1153 | input [38:0] w1_data; |
| 1154 | input [38:0] w2_data; |
| 1155 | output [38:0] r1_data; |
| 1156 | output [38:0] r2_data; |
| 1157 | |
| 1158 | wire masked_r1_valid; |
| 1159 | wire masked_r2_valid; |
| 1160 | reg [38:0] r1_data; |
| 1161 | reg [38:0] r2_data; |
| 1162 | |
| 1163 | |
| 1164 | reg [38:0] data_array[255:0]; |
| 1165 | integer i; |
| 1166 | |
| 1167 | assign masked_r1_valid = ((r1_valid & (~(w1_valid & (r1_addr[7:0] == |
| 1168 | w1_addr[7:0])))) & (~(w2_valid & (r1_addr[7:0] == w2_addr[7:0])) |
| 1169 | )); |
| 1170 | assign masked_r2_valid = ((r2_valid & (~(w1_valid & (r2_addr[7:0] == |
| 1171 | w1_addr[7:0])))) & (~(w2_valid & (r2_addr[7:0] == w2_addr[7:0])) |
| 1172 | )); |
| 1173 | |
| 1174 | initial begin |
| 1175 | for (i = 0; (i <= 255); i = (i + 1)) begin |
| 1176 | data_array[i] = {39 {1'b0}}; |
| 1177 | end |
| 1178 | end |
| 1179 | always @(negedge clk) begin |
| 1180 | if (masked_r1_valid) begin |
| 1181 | r1_data[38:0] <= data_array[r1_addr[7:0]]; |
| 1182 | end |
| 1183 | else |
| 1184 | begin |
| 1185 | r1_data[38:0] <= {39 {1'b0}}; |
| 1186 | end |
| 1187 | if (masked_r2_valid) begin |
| 1188 | r2_data[38:0] <= data_array[r2_addr[7:0]]; |
| 1189 | end |
| 1190 | else |
| 1191 | begin |
| 1192 | r2_data[38:0] <= {39 {1'b0}}; |
| 1193 | end |
| 1194 | if (w1_valid & (~tcu_array_wr_inhibit)) begin |
| 1195 | data_array[w1_addr[7:0]] <= w1_data[38:0]; |
| 1196 | end |
| 1197 | if (w2_valid & (~tcu_array_wr_inhibit)) begin |
| 1198 | data_array[w2_addr[7:0]] <= w2_data[38:0]; |
| 1199 | end |
| 1200 | end |
| 1201 | |
| 1202 | endmodule |
| 1203 | |
| 1204 | `endif |
| 1205 | |