| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_ncu_ucb_csrs.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | |
| 42 | #define DRAM0_ERROR_COUNTER_REG 0x8400000298 |
| 43 | #define DRAM1_ERROR_COUNTER_REG 0x8400001298 |
| 44 | #define DRAM2_ERROR_COUNTER_REG 0x8400002298 |
| 45 | #define DRAM3_ERROR_COUNTER_REG 0x8400003298 |
| 46 | |
| 47 | #define L2_BANK_ENABLE_REG 0x8000001020 |
| 48 | #define NCU_CREG_DBGTRIG_EN 0x8000004000 |
| 49 | |
| 50 | #include "hboot.s" |
| 51 | #include "asi_s.h" |
| 52 | #include "err_defines.h" |
| 53 | #include "tcu_defines.h" |
| 54 | |
| 55 | |
| 56 | .text |
| 57 | .global main |
| 58 | |
| 59 | |
| 60 | main: |
| 61 | ta T_CHANGE_HPRIV |
| 62 | |
| 63 | /******************************** |
| 64 | * Write-Read DRAM ERROR COUNT REG |
| 65 | *********************************/ |
| 66 | mcu0_wr_rd: |
| 67 | setx DRAM0_ERROR_COUNTER_REG, %g7, %g1 |
| 68 | set 0xffff, %g2 |
| 69 | stx %g2, [%g1] |
| 70 | ldx [%g1], %g3 |
| 71 | cmp %g3, %g2 |
| 72 | bne %xcc, test_failed |
| 73 | nop |
| 74 | |
| 75 | stx %g0, [%g1] |
| 76 | ldx [%g1], %g3 |
| 77 | cmp %g3, %g0 |
| 78 | bne %xcc, test_failed |
| 79 | nop |
| 80 | |
| 81 | set 0xaaaa, %g2 |
| 82 | stx %g2, [%g1] |
| 83 | |
| 84 | mcu1_wr_rd: |
| 85 | setx DRAM1_ERROR_COUNTER_REG, %g7, %g1 |
| 86 | set 0xffff, %g2 |
| 87 | stx %g2, [%g1] |
| 88 | ldx [%g1], %g3 |
| 89 | cmp %g3, %g2 |
| 90 | bne %xcc, test_failed |
| 91 | nop |
| 92 | |
| 93 | stx %g0, [%g1] |
| 94 | ldx [%g1], %g3 |
| 95 | cmp %g3, %g0 |
| 96 | bne %xcc, test_failed |
| 97 | nop |
| 98 | |
| 99 | set 0xaaaa, %g2 |
| 100 | stx %g2, [%g1] |
| 101 | |
| 102 | |
| 103 | mcu2_wr_rd: |
| 104 | setx DRAM2_ERROR_COUNTER_REG, %g7, %g1 |
| 105 | set 0xffff, %g2 |
| 106 | stx %g2, [%g1] |
| 107 | ldx [%g1], %g3 |
| 108 | cmp %g3, %g2 |
| 109 | bne %xcc, test_failed |
| 110 | nop |
| 111 | |
| 112 | stx %g0, [%g1] |
| 113 | ldx [%g1], %g3 |
| 114 | cmp %g3, %g0 |
| 115 | bne %xcc, test_failed |
| 116 | nop |
| 117 | |
| 118 | set 0xaaaa, %g2 |
| 119 | stx %g2, [%g1] |
| 120 | |
| 121 | |
| 122 | mcu3_wr_rd: |
| 123 | setx DRAM3_ERROR_COUNTER_REG, %g7, %g1 |
| 124 | set 0xffff, %g2 |
| 125 | stx %g2, [%g1] |
| 126 | ldx [%g1], %g3 |
| 127 | cmp %g3, %g2 |
| 128 | bne %xcc, test_failed |
| 129 | nop |
| 130 | |
| 131 | stx %g0, [%g1] |
| 132 | ldx [%g1], %g3 |
| 133 | cmp %g3, %g0 |
| 134 | bne %xcc, test_failed |
| 135 | nop |
| 136 | |
| 137 | set 0xaaaa, %g2 |
| 138 | stx %g2, [%g1] |
| 139 | |
| 140 | |
| 141 | mcu0_rd: |
| 142 | setx DRAM0_ERROR_COUNTER_REG, %g7, %g1 |
| 143 | call loop_rd |
| 144 | nop |
| 145 | nop |
| 146 | nop |
| 147 | |
| 148 | mcu1_rd: |
| 149 | setx DRAM1_ERROR_COUNTER_REG, %g7, %g1 |
| 150 | call loop_rd |
| 151 | nop |
| 152 | nop |
| 153 | nop |
| 154 | |
| 155 | mcu2_rd: |
| 156 | setx DRAM2_ERROR_COUNTER_REG, %g7, %g1 |
| 157 | call loop_rd |
| 158 | nop |
| 159 | nop |
| 160 | nop |
| 161 | |
| 162 | mcu3_rd: |
| 163 | setx DRAM3_ERROR_COUNTER_REG, %g7, %g1 |
| 164 | call loop_rd |
| 165 | nop |
| 166 | nop |
| 167 | nop |
| 168 | |
| 169 | |
| 170 | tcu_mbist_mode_reg: |
| 171 | setx MBIST_MODE_REG, %g7, %g1 |
| 172 | set 0xf, %g2 |
| 173 | stx %g2, [%g1] |
| 174 | ldx [%g1], %g3 |
| 175 | cmp %g3, %g2 |
| 176 | bne %xcc, test_failed |
| 177 | nop |
| 178 | |
| 179 | stx %g0, [%g1] |
| 180 | ldx [%g1], %g3 |
| 181 | cmp %g3, %g0 |
| 182 | bne %xcc, test_failed |
| 183 | nop |
| 184 | |
| 185 | |
| 186 | tcu_cyc_cntr_reg: |
| 187 | setx TCU_CYCLE_COUNTER_REG, %g7, %g1 |
| 188 | setx 0xffffffffffffffff, %g7, %g2 |
| 189 | stx %g2, [%g1] |
| 190 | ldx [%g1], %g3 |
| 191 | cmp %g3, %g2 |
| 192 | bne %xcc, test_failed |
| 193 | nop |
| 194 | |
| 195 | stx %g0, [%g1] |
| 196 | ldx [%g1], %g3 |
| 197 | cmp %g3, %g0 |
| 198 | bne %xcc, test_failed |
| 199 | nop |
| 200 | |
| 201 | set 0xaaaa, %g2 |
| 202 | stx %g2, [%g1] |
| 203 | |
| 204 | tcu_rd: |
| 205 | call loop_rd |
| 206 | nop |
| 207 | nop |
| 208 | nop |
| 209 | |
| 210 | |
| 211 | |
| 212 | ncu_creg_dbgtrig_en_Reg: |
| 213 | setx NCU_CREG_DBGTRIG_EN, %g7, %g1 |
| 214 | set 0x1, %g2 |
| 215 | stx %g2, [%g1] |
| 216 | ldx [%g1], %g3 |
| 217 | nop |
| 218 | |
| 219 | |
| 220 | test_passesd: |
| 221 | |
| 222 | |
| 223 | test_passed: |
| 224 | EXIT_GOOD |
| 225 | |
| 226 | test_failed: |
| 227 | EXIT_BAD |
| 228 | |
| 229 | |
| 230 | |
| 231 | loop_rd: |
| 232 | ldx [%g1], %g2 |
| 233 | ldx [%g1], %g2 |
| 234 | ldx [%g1], %g2 |
| 235 | ldx [%g1], %g2 |
| 236 | ldx [%g1], %g2 |
| 237 | ldx [%g1], %g2 |
| 238 | ldx [%g1], %g2 |
| 239 | ldx [%g1], %g2 |
| 240 | ldx [%g1], %g2 |
| 241 | ldx [%g1], %g2 |
| 242 | ldx [%g1], %g2 |
| 243 | ldx [%g1], %g2 |
| 244 | ldx [%g1], %g2 |
| 245 | ldx [%g1], %g2 |
| 246 | ldx [%g1], %g2 |
| 247 | ldx [%g1], %g2 |
| 248 | ldx [%g1], %g2 |
| 249 | ldx [%g1], %g2 |
| 250 | ldx [%g1], %g2 |
| 251 | ldx [%g1], %g2 |
| 252 | ldx [%g1], %g2 |
| 253 | ldx [%g1], %g2 |
| 254 | ldx [%g1], %g2 |
| 255 | ldx [%g1], %g2 |
| 256 | ldx [%g1], %g2 |
| 257 | ldx [%g1], %g2 |
| 258 | ldx [%g1], %g2 |
| 259 | ldx [%g1], %g2 |
| 260 | ldx [%g1], %g2 |
| 261 | ldx [%g1], %g2 |
| 262 | ldx [%g1], %g2 |
| 263 | ldx [%g1], %g2 |
| 264 | ldx [%g1], %g2 |
| 265 | ldx [%g1], %g2 |
| 266 | ldx [%g1], %g2 |
| 267 | ldx [%g1], %g2 |
| 268 | ldx [%g1], %g2 |
| 269 | ldx [%g1], %g2 |
| 270 | ldx [%g1], %g2 |
| 271 | ldx [%g1], %g2 |
| 272 | ldx [%g1], %g2 |
| 273 | ldx [%g1], %g2 |
| 274 | ldx [%g1], %g2 |
| 275 | ldx [%g1], %g2 |
| 276 | ldx [%g1], %g2 |
| 277 | ldx [%g1], %g2 |
| 278 | ldx [%g1], %g2 |
| 279 | ldx [%g1], %g2 |
| 280 | ldx [%g1], %g2 |
| 281 | ldx [%g1], %g2 |
| 282 | ldx [%g1], %g2 |
| 283 | ldx [%g1], %g2 |
| 284 | ldx [%g1], %g2 |
| 285 | ldx [%g1], %g2 |
| 286 | ldx [%g1], %g2 |
| 287 | ldx [%g1], %g2 |
| 288 | ldx [%g1], %g2 |
| 289 | ldx [%g1], %g2 |
| 290 | ldx [%g1], %g2 |
| 291 | ldx [%g1], %g2 |
| 292 | ldx [%g1], %g2 |
| 293 | |
| 294 | set 0xaaaa, %g3 |
| 295 | cmp %g3, %g2 |
| 296 | bne %xcc, test_failed |
| 297 | |
| 298 | jmpl %o7+8, %g0 |
| 299 | nop |
| 300 | |