| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: ncu_cmp.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #include "hboot.s" |
| 42 | #include "asi_s.h" |
| 43 | |
| 44 | #ifndef CORE_AVAIL |
| 45 | #define CORE_AVAIL 0xff |
| 46 | #endif |
| 47 | |
| 48 | .text |
| 49 | .global main |
| 50 | |
| 51 | |
| 52 | main: |
| 53 | ta T_CHANGE_HPRIV |
| 54 | |
| 55 | get_th_id: |
| 56 | ta T_RD_THID |
| 57 | wr %g0,ASI_CMP_CORE,%asi |
| 58 | |
| 59 | cmp %o1,0x0 |
| 60 | be core_0 |
| 61 | nop |
| 62 | cmp %o1,0x8 |
| 63 | be core_1 |
| 64 | nop |
| 65 | ba core_others |
| 66 | nop |
| 67 | |
| 68 | core_0: |
| 69 | setx 0x0000ff000000ff00,%g7,%g1 |
| 70 | stxa %g1,[ASI_CMP_CORE_ENABLE]%asi |
| 71 | setx 0x8900000808,%g7,%g1 |
| 72 | set 0x1,%g2 |
| 73 | stx %g2,[%g1] |
| 74 | |
| 75 | halt: |
| 76 | ba halt |
| 77 | nop |
| 78 | |
| 79 | core_1: |
| 80 | setx 0xa9872bfcde25fff0,%g7,%g1 |
| 81 | stxa %g1,[ASI_CMP_XIR_STEERING]%asi |
| 82 | |
| 83 | stxa %g0,[ASI_CMP_TICK_ENABLE]%asi |
| 84 | |
| 85 | setx 0xf5720163feab01cc,%g7,%g1 |
| 86 | stxa %g1,[ASI_CMP_CORE_RUNNING_RW]%asi |
| 87 | |
| 88 | setx 0xacfa01afadc20186,%g7,%g1 |
| 89 | stxa %g1,[ASI_CMP_CORE_RUNNING_W1S]%asi |
| 90 | |
| 91 | setx 0x1001fe846926fe23,%g7,%g1 |
| 92 | stxa %g1,[ASI_CMP_CORE_RUNNING_W1C]%asi |
| 93 | |
| 94 | setx 0xffffff0000,%g7,%g1 |
| 95 | set 0x1,%g2 |
| 96 | stx %g2,[%g1] |
| 97 | |
| 98 | setx CORE_AVAIL,%g7,%g1 |
| 99 | call compute_core_avail ! return in %g1 |
| 100 | nop |
| 101 | ldxa [ASI_CMP_CORE_AVAIL]%asi,%g2 |
| 102 | cmp %g1,%g2 |
| 103 | bne %xcc,test_fail |
| 104 | nop |
| 105 | setx 0x0000ff000000ff00,%g7,%g1 |
| 106 | ldxa [ASI_CMP_CORE_ENABLE]%asi,%g2 |
| 107 | cmp %g1,%g2 |
| 108 | bne %xcc,test_fail |
| 109 | nop |
| 110 | ldxa [ASI_CMP_CORE_ENABLED]%asi,%g2 |
| 111 | cmp %g1,%g2 |
| 112 | bne %xcc,test_fail |
| 113 | nop |
| 114 | |
| 115 | ba test_pass |
| 116 | nop |
| 117 | |
| 118 | core_others: |
| 119 | setx 0xffffff0000,%g7,%g1 |
| 120 | ldx [%g1],%g2 |
| 121 | cmp %g2,0x1 |
| 122 | bne core_others |
| 123 | nop |
| 124 | |
| 125 | setx 0x00002b000000ff00,%g7,%g1 |
| 126 | ldxa [ASI_CMP_XIR_STEERING]%asi,%g2 |
| 127 | cmp %g1,%g2 |
| 128 | bne %xcc,test_fail |
| 129 | nop |
| 130 | |
| 131 | setx 0x0000010000000100,%g7,%g1 |
| 132 | ldxa [ASI_CMP_CORE_RUNNING_RW]%asi,%g2 |
| 133 | cmp %g1,%g2 |
| 134 | bne %xcc,test_fail |
| 135 | nop |
| 136 | ldxa [ASI_CMP_CORE_RUNNING_STATUS]%asi,%g2 |
| 137 | cmp %g1,%g2 |
| 138 | bne %xcc,test_fail |
| 139 | nop |
| 140 | |
| 141 | ldxa [ASI_CMP_TICK_ENABLE]%asi,%g2 |
| 142 | cmp %g2,%g0 |
| 143 | bne %xcc,test_fail |
| 144 | nop |
| 145 | |
| 146 | setx CORE_AVAIL,%g7,%g1 |
| 147 | call compute_core_avail ! return in %g1 |
| 148 | nop |
| 149 | ldxa [ASI_CMP_CORE_AVAIL]%asi,%g2 |
| 150 | cmp %g1,%g2 |
| 151 | bne %xcc,test_fail |
| 152 | nop |
| 153 | setx 0x0000ff000000ff00,%g7,%g1 |
| 154 | ldxa [ASI_CMP_CORE_ENABLE]%asi,%g2 |
| 155 | cmp %g1,%g2 |
| 156 | bne %xcc,test_fail |
| 157 | nop |
| 158 | ldxa [ASI_CMP_CORE_ENABLED]%asi,%g2 |
| 159 | cmp %g1,%g2 |
| 160 | bne %xcc,test_fail |
| 161 | nop |
| 162 | |
| 163 | ba test_pass |
| 164 | nop |
| 165 | |
| 166 | /****************************************************** |
| 167 | * Subroutine code |
| 168 | *******************************************************/ |
| 169 | |
| 170 | compute_core_avail: |
| 171 | or %g0,%g1,%l0 |
| 172 | or %g0,%g0,%g1 |
| 173 | set 0x8,%l1 |
| 174 | comp_loop: |
| 175 | sllx %g1,8,%g1 |
| 176 | andcc %l0,0x80,%l2 |
| 177 | bz skip |
| 178 | nop |
| 179 | or %g1,0xff,%g1 |
| 180 | skip: |
| 181 | sllx %l0,1,%l0 |
| 182 | subcc %l1,1,%l1 |
| 183 | bnz comp_loop |
| 184 | nop |
| 185 | retl |
| 186 | nop |
| 187 | |
| 188 | /****************************************************** |
| 189 | * Exit code |
| 190 | *******************************************************/ |
| 191 | |
| 192 | test_pass: |
| 193 | EXIT_GOOD |
| 194 | |
| 195 | test_fail: |
| 196 | EXIT_BAD |
| 197 | |