| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: interrupt_niu_device_id.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | #define H_HT0_Interrupt_0x60 |
| 41 | #define My_HT0_Interrupt_0x60 \ |
| 42 | call my_trap_code; \ |
| 43 | nop; \ |
| 44 | retry; \ |
| 45 | nop; |
| 46 | |
| 47 | #include "hboot.s" |
| 48 | #include "niu_defines.h" |
| 49 | #include "ncu_defines.h" |
| 50 | #include "niu_macros.h" |
| 51 | |
| 52 | |
| 53 | |
| 54 | /************************************************************************ |
| 55 | Test case code start |
| 56 | ************************************************************************/ |
| 57 | .text |
| 58 | .global main |
| 59 | |
| 60 | main: |
| 61 | ta T_CHANGE_HPRIV |
| 62 | nop |
| 63 | |
| 64 | /* Initialize the NCU for the interrupt. */ |
| 65 | |
| 66 | ! Disable interrupts |
| 67 | |
| 68 | no_intr: |
| 69 | rdpr %pstate, %g7 |
| 70 | xor %g7, 0x2, %g7 ! Reset interrupt enable |
| 71 | wrpr %g7, %pstate |
| 72 | |
| 73 | ncu_init1: |
| 74 | ! Initially set all the Interrupt Management Registers |
| 75 | |
| 76 | setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr. |
| 77 | setx INT_MAN_COUNT, %g1, %g3 ! %g3 = INT_MAN reg. count value |
| 78 | srax %g3, 1, %g4 |
| 79 | mov %g0, %g7 |
| 80 | |
| 81 | ncu_init_loop_top1: |
| 82 | stx %g7, [%g2] |
| 83 | add %g7, 1, %g7 ! increment the vector number |
| 84 | addx %g2, INT_MAN_STEP, %g2 |
| 85 | cmp %g4, 1 |
| 86 | bne ncu_init_loop_top1 |
| 87 | add %g4, -1, %g4 |
| 88 | |
| 89 | ! The second half of the Interrupt Management Registers |
| 90 | ! get a decrementing value for vector number. |
| 91 | |
| 92 | ncu_init2: |
| 93 | srax %g3, 1, %g4 |
| 94 | setx 63, %g1, %g7 |
| 95 | |
| 96 | ncu_init_loop_top2: |
| 97 | stx %g7, [%g2] |
| 98 | sub %g7, 1, %g7 ! decrement the vector number |
| 99 | addx %g2, INT_MAN_STEP, %g2 |
| 100 | cmp %g4, 1 |
| 101 | bne ncu_init_loop_top2 |
| 102 | add %g4, -1, %g4 |
| 103 | |
| 104 | |
| 105 | ! Initialize the NIU for TX DMA interrupt. |
| 106 | |
| 107 | NIU_TX_LD_IM0_INTR_ON_MARK( 0, %g1, %g2, %g3, %g4, 0, 64 ) |
| 108 | |
| 109 | setx user_data_start, %g1, %2 |
| 110 | set 0x3f, %g1 |
| 111 | st %g1, [%g2] ! Record first device number used |
| 112 | |
| 113 | ! Enable interrupts |
| 114 | |
| 115 | yes_intr: |
| 116 | rdpr %pstate, %g7 |
| 117 | or %g7, 0x2, %g7 ! Set interrupt enable |
| 118 | wrpr %g7, %pstate |
| 119 | |
| 120 | ! Generate the interrupt via PIO write |
| 121 | |
| 122 | gen_intr: |
| 123 | setx TDMC_INTR_DBG, %g1, %g2 |
| 124 | setx 0x8000, %g1, %g4 ! Force the MK flag |
| 125 | stxa %g4, [%g2]ASI_PRIMARY_LITTLE |
| 126 | |
| 127 | ! Have 16 interrupts occured? |
| 128 | |
| 129 | intr_check: |
| 130 | setx 0x1000, %g1, %g4 ! timeout loop count |
| 131 | setx user_data_start, %g1, %g2 |
| 132 | |
| 133 | intr_check_loop: |
| 134 | ld [%g2], %g7 |
| 135 | cmp %g7, 49 |
| 136 | be test_passed |
| 137 | dec %g4 |
| 138 | |
| 139 | cmp %g4, 0 |
| 140 | bne intr_check_loop |
| 141 | nop |
| 142 | |
| 143 | ba local_test_failed |
| 144 | nop |
| 145 | |
| 146 | |
| 147 | ! ! Now do 64 more interrupts to use reset of Interrupt Management regs. |
| 148 | ! |
| 149 | ! ! Generate the interrupt via PIO write |
| 150 | ! |
| 151 | !part_two: |
| 152 | ! setx half_time_flag, %g1, %g2 |
| 153 | ! set 1, %g3 |
| 154 | ! st %g3, [%g2] |
| 155 | ! |
| 156 | ! ! Have 65 more interrupts occured? |
| 157 | |
| 158 | !intr_check_2: |
| 159 | ! setx 0x1000, %g1, %g4 ! timeout loop count |
| 160 | ! setx user_data_start, %g1, %g2 |
| 161 | ! |
| 162 | !intr_check_loop_2: |
| 163 | ! ld [%g2], %g7 |
| 164 | ! cmp %g7, 0 |
| 165 | ! be test_passed |
| 166 | ! dec %g4 |
| 167 | ! |
| 168 | ! cmp %g4, 0 |
| 169 | ! bne intr_check_loop_2 |
| 170 | ! nop |
| 171 | ! |
| 172 | ! ba local_test_failed |
| 173 | ! nop |
| 174 | |
| 175 | |
| 176 | |
| 177 | test_passed: |
| 178 | EXIT_GOOD |
| 179 | |
| 180 | local_test_failed: |
| 181 | EXIT_BAD |
| 182 | |
| 183 | |
| 184 | /********************************************************************** |
| 185 | Interrupt trap handler. |
| 186 | **********************************************************************/ |
| 187 | |
| 188 | .global my_trap_code |
| 189 | |
| 190 | my_trap_code: |
| 191 | |
| 192 | !!! Careful when changing this interrupt trap handler code |
| 193 | !!! Several registers need to keep their values throughout |
| 194 | !!! the whole trap handler. So check before making changes!!! |
| 195 | |
| 196 | ! Get the expected vector number. |
| 197 | |
| 198 | ldxa [%g0]ASI_INTR_RECEIVE, %g1 |
| 199 | setx user_data_start, %l2, %l6 |
| 200 | ld [%l6], %l5 |
| 201 | |
| 202 | ! Clear the interrupt in the core & get vector number |
| 203 | Trap1: |
| 204 | ldxa [%g0]ASI_SWVR_INTR_R, %l3 |
| 205 | cmp %l3, %l5 |
| 206 | bne local_test_failed |
| 207 | nop |
| 208 | |
| 209 | ! ! Increment/decrement the expected vector number. |
| 210 | !Trap2: |
| 211 | ! setx half_time_flag, %l1, %l2 |
| 212 | ! ld [%l2], %l3 |
| 213 | ! cmp %l3, 1 |
| 214 | ! be Trap_dec |
| 215 | ! nop |
| 216 | ! |
| 217 | ! ! Increment |
| 218 | ! |
| 219 | ! cmp %l5, 63 ! If 63 & !half_time yet, don't change |
| 220 | ! be Trap3 |
| 221 | ! nop |
| 222 | ! |
| 223 | ! add %l5, 1, %l5 |
| 224 | ! ba Trap_store |
| 225 | ! nop |
| 226 | |
| 227 | ! Decrement |
| 228 | |
| 229 | Trap_dec: |
| 230 | sub %l5, 1, %l5 |
| 231 | |
| 232 | Trap_store: |
| 233 | st %l5, [%l6] |
| 234 | membar #Sync |
| 235 | |
| 236 | ! Change the TX dma channel & logical device group to use. |
| 237 | |
| 238 | ! Increment the Tx dma channel number |
| 239 | |
| 240 | Trap3: setx tx_dma_num, %g1, %g2 |
| 241 | ld [%g2], %g3 |
| 242 | |
| 243 | ! But first clear the interrupt in the NIU's Tx DMA channel |
| 244 | |
| 245 | setx TDMC_STEP, %g1, %g5 |
| 246 | mulx %g5, %g3, %g5 |
| 247 | setx TX_CS, %g1, %g6 |
| 248 | addx %g6, %g5, %g6 |
| 249 | ldxa [%g6]ASI_PRIMARY_LITTLE, %g5 ! Read clears interrupt, MK bit |
| 250 | |
| 251 | Trap3_30: |
| 252 | add %g3, 1, %g3 |
| 253 | set 0xf, %g1 |
| 254 | and %g3, %g1, %g3 ! Only values 0->15 are value |
| 255 | st %g3, [%g2] ! for Tx dma channel numbers |
| 256 | |
| 257 | ! Increment the logical device group number |
| 258 | |
| 259 | Trap4: |
| 260 | setx my_ldg_num, %g1, %g2 |
| 261 | ld [%g2], %g4 |
| 262 | add %g4, 1, %g4 |
| 263 | st %g4, [%g2] |
| 264 | |
| 265 | ! Assign the Tx dma channel to the logical device group |
| 266 | |
| 267 | Trap5: |
| 268 | add %g3, 32, %g7 ! Convert Tx dma channel number |
| 269 | ! to logical device number |
| 270 | setx LDG_NUM_STEP, %g1, %g6 |
| 271 | mulx %g6, %g7, %g6 |
| 272 | setx LDG_NUM, %g1, %g5 |
| 273 | addx %g5, %g6, %g5 |
| 274 | stxa %g4, [%g5]ASI_PRIMARY_LITTLE |
| 275 | |
| 276 | ! Enable interrupts for the logical device |
| 277 | |
| 278 | Trap6: |
| 279 | setx LD_IM0_STEP, %g1, %g5 |
| 280 | mulx %g5, %g7, %g5 |
| 281 | setx LD_IM0, %g1, %g2 |
| 282 | addx %g2, %g5, %g2 |
| 283 | stxa %g0, [%g2]ASI_PRIMARY_LITTLE |
| 284 | |
| 285 | ! Arm interrupts in the logical device group |
| 286 | |
| 287 | Trap7: |
| 288 | setx LDGIMGN_STEP, %g1, %g6 |
| 289 | mulx %g6, %g4, %g6 |
| 290 | setx LDGIMGN, %g1, %g2 ! LDGIMGN |
| 291 | addx %g2, %g6, %g2 |
| 292 | setx 0x80000001, %g1, %g5 |
| 293 | stxa %g5, [%g2]ASI_PRIMARY_LITTLE |
| 294 | nop |
| 295 | |
| 296 | ! Increment and set the device ID to send to the NCU |
| 297 | |
| 298 | Trap8: |
| 299 | setx user_data_start, %g1, %g2 |
| 300 | ld [%g2], %g6 |
| 301 | setx SID_STEP, %g1, %g5 |
| 302 | mulx %g5, %g4, %g5 |
| 303 | setx SID, %g1, %g2 |
| 304 | addx %g2, %g5, %g2 |
| 305 | stxa %g6, [%g2]ASI_PRIMARY_LITTLE |
| 306 | |
| 307 | ! Enable interrupts in th TX dma channel |
| 308 | |
| 309 | Trap9: |
| 310 | setx TDMC_STEP, %g1, %g5 |
| 311 | mulx %g5, %g3, %g5 |
| 312 | setx TX_ENT_MSK, %g1, %g2 |
| 313 | addx %g2, %g5, %g2 |
| 314 | stxa %g0, [%g2]ASI_PRIMARY_LITTLE |
| 315 | |
| 316 | ! Generate another interrupt, but no more that 16 |
| 317 | Trap10: |
| 318 | cmp %l5, 48 |
| 319 | be Trap12 ! Branch if already done 16 |
| 320 | nop |
| 321 | |
| 322 | Trap11: |
| 323 | setx TDMC_STEP, %g1, %g7 |
| 324 | mulx %g7, %g3, %g7 |
| 325 | setx TDMC_INTR_DBG, %g1, %g2 |
| 326 | add %g2, %g7, %g2 |
| 327 | |
| 328 | setx 0x8000, %g1, %g5 ! Force the MK flag |
| 329 | stxa %g5, [%g2]ASI_PRIMARY_LITTLE |
| 330 | |
| 331 | ! Done |
| 332 | |
| 333 | Trap12: |
| 334 | jmpl %o7+0x8, %g0 |
| 335 | nop |
| 336 | |
| 337 | |
| 338 | |
| 339 | |
| 340 | /************************************************************************ |
| 341 | Test case data start |
| 342 | ************************************************************************/ |
| 343 | .align 1024 |
| 344 | .data |
| 345 | user_data_start: |
| 346 | .word 0x0 |
| 347 | .word 0x0 |
| 348 | .word 0x0 |
| 349 | .word 0x0 |
| 350 | tx_dma_num: |
| 351 | .word 0x0 |
| 352 | .word 0x0 |
| 353 | .word 0x0 |
| 354 | .word 0x0 |
| 355 | my_ldg_num: |
| 356 | .word 0x0 |
| 357 | .word 0x0 |
| 358 | .word 0x0 |
| 359 | .word 0x0 |
| 360 | half_time_flag: |
| 361 | .word 0x0 |
| 362 | .word 0x0 |
| 363 | .word 0x0 |
| 364 | .word 0x0 |
| 365 | |
| 366 | |
| 367 | |