| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_pm_mcu_cmda_2bank.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | |
| 42 | #include "hboot.s" |
| 43 | #include "asi_s.h" |
| 44 | |
| 45 | #ifdef BANK0 |
| 46 | #define L2_0_ADDR0 0x220000000 |
| 47 | #endif |
| 48 | |
| 49 | #ifdef BANK1 |
| 50 | #define L2_0_ADDR0 0x220000040 |
| 51 | #endif |
| 52 | |
| 53 | #define L2_0_ADDR1 0xff000 |
| 54 | |
| 55 | #define TAG_SHIFT 22 |
| 56 | |
| 57 | #ifdef L2_OFF |
| 58 | #define L2_ON_OFF_DM 0x1 |
| 59 | #else |
| 60 | #define L2_ON_OFF_DM 0x0 |
| 61 | #endif |
| 62 | |
| 63 | #define BANK_LOOP 0x8 |
| 64 | #define DIMM_RANK_LOOP 0x10 |
| 65 | |
| 66 | .text |
| 67 | .global main |
| 68 | |
| 69 | |
| 70 | main: |
| 71 | ta T_CHANGE_HPRIV |
| 72 | nop |
| 73 | setx 0x1, %g7, %g5 |
| 74 | setx 0x8400000040, %g7, %g3 |
| 75 | stx %g5, [%g3] |
| 76 | setx 0x8400001040, %g7, %g3 |
| 77 | stx %g5, [%g3] |
| 78 | setx 0x8400002040, %g7, %g3 |
| 79 | stx %g5, [%g3] |
| 80 | setx 0x8400003040, %g7, %g3 |
| 81 | stx %g5, [%g3] |
| 82 | setx 0x8400000238, %g7, %g3 |
| 83 | stx %g5, [%g3] |
| 84 | setx 0x8400001238, %g7, %g3 |
| 85 | stx %g5, [%g3] |
| 86 | setx 0x8400002238, %g7, %g3 |
| 87 | stx %g5, [%g3] |
| 88 | setx 0x8400003238, %g7, %g3 |
| 89 | stx %g5, [%g3] |
| 90 | |
| 91 | setx 0x200, %g7, %g5 |
| 92 | setx 0x8400000018, %g7, %g3 |
| 93 | stx %g5, [%g3] |
| 94 | setx 0x200, %g7, %g5 |
| 95 | setx 0x8400001018, %g7, %g3 |
| 96 | stx %g5, [%g3] |
| 97 | setx 0x200, %g7, %g5 |
| 98 | setx 0x8400002018, %g7, %g3 |
| 99 | stx %g5, [%g3] |
| 100 | setx 0x200, %g7, %g5 |
| 101 | setx 0x8400003018, %g7, %g3 |
| 102 | stx %g5, [%g3] |
| 103 | |
| 104 | |
| 105 | /****************************************** |
| 106 | Memory Read/Write |
| 107 | ******************************************/ |
| 108 | ld_st: |
| 109 | setx L2_0_ADDR1, %g7, %g3 |
| 110 | |
| 111 | setx 0x0, %g7, %g1 |
| 112 | setx 0x0, %g7, %l1 |
| 113 | setx 0x0, %g7, %l2 |
| 114 | setx 0x40, %g7, %l3 |
| 115 | setx 0x200000000, %g7, %l4 |
| 116 | setx DIMM_RANK_LOOP, %g7, %l5 |
| 117 | setx BANK_LOOP, %g7, %l6 |
| 118 | |
| 119 | dimm_rank_loop: |
| 120 | nop |
| 121 | |
| 122 | bank_loop: |
| 123 | stx %g1, [%g3] |
| 124 | inc %g1 |
| 125 | ldx [%g3], %o1 |
| 126 | add %l3, %g3, %g3 |
| 127 | inc %l2 |
| 128 | cmp %l2, %l6 |
| 129 | bne bank_loop |
| 130 | nop |
| 131 | |
| 132 | |
| 133 | mov 0x0, %l2 |
| 134 | add %l4, %g3, %g3 |
| 135 | |
| 136 | inc %l1 |
| 137 | cmp %l1, %l5 |
| 138 | bne dimm_rank_loop |
| 139 | |
| 140 | |
| 141 | |
| 142 | |
| 143 | /****************************************************** |
| 144 | * Exit code |
| 145 | *******************************************************/ |
| 146 | |
| 147 | test_pass: |
| 148 | EXIT_GOOD |
| 149 | |
| 150 | test_fail: |
| 151 | EXIT_BAD |
| 152 | |