| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: tcu_clkstp_socdbgevent.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define Soc_Decr_Pa 0x8600000010 |
| 42 | |
| 43 | |
| 44 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 45 | #define L2_ERR_ADDR_REG 0xAC00000000 |
| 46 | |
| 47 | #define TEST_DATA0 0x1000100081c3e008 |
| 48 | #define TEST_DATA1 0x2000200081c3e008 |
| 49 | #define TEST_DATA2 0x3000300081c3e008 |
| 50 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 51 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 52 | |
| 53 | #ifdef MCU0 |
| 54 | #define L2_BANK_ADDR 0x0 |
| 55 | #define MCU_BANK_ADDR 0x0 |
| 56 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 57 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 58 | #define ERROR_ADDR 0x20200000 |
| 59 | #define DBG_ERR_PA 0xAA00000000 |
| 60 | #define DBG_ERR_VAL 0x4 |
| 61 | #ifdef SOC_TRIGOUT |
| 62 | #define Soc_Decr_Val 0x00000000000003 |
| 63 | #else |
| 64 | #define Soc_Decr_Val 0x00000000000002 |
| 65 | #endif |
| 66 | #define L2_Addr_Mask_Reg 0xAF00000000 |
| 67 | #define L2_Addr_Mask_Val 0x000000002200aa00 |
| 68 | #define L2_Addr_Cmp_Reg 0xBF00000000 |
| 69 | #define L2_Addr_Cmp_Val 0x000000002200aa00 |
| 70 | #endif |
| 71 | |
| 72 | #ifdef MCU1 |
| 73 | #define L2_BANK_ADDR 0x80 |
| 74 | #define MCU_BANK_ADDR 0x80 |
| 75 | #define DRAM_ERR_INJ_REG 0x8400001290 |
| 76 | #define DRAM_ERR_STAT_REG 0x8400001280 |
| 77 | #define DBG_ERR_PA 0xAA00000080 |
| 78 | #define DBG_ERR_VAL 0x4 |
| 79 | #ifdef SOC_TRIGOUT |
| 80 | #define Soc_Decr_Val 0x00000000000030 |
| 81 | #else |
| 82 | #define Soc_Decr_Val 0x00000000000020 |
| 83 | #endif |
| 84 | #define L2_Addr_Mask_Reg 0xAF00000080 |
| 85 | #define L2_Addr_Mask_Val 0x000000002200aa00 |
| 86 | #define L2_Addr_Cmp_Reg 0xBF00000080 |
| 87 | #define L2_Addr_Cmp_Val 0x000000002200aa00 |
| 88 | |
| 89 | #endif |
| 90 | |
| 91 | #ifdef MCU2 |
| 92 | #define L2_BANK_ADDR 0x100 |
| 93 | #define MCU_BANK_ADDR 0x100 |
| 94 | #define DRAM_ERR_INJ_REG 0x8400002290 |
| 95 | #define DRAM_ERR_STAT_REG 0x8400002280 |
| 96 | #define ERROR_ADDR 0x20200100 |
| 97 | #define DBG_ERR_PA 0xAA00000100 |
| 98 | #define DBG_ERR_VAL 0x4 |
| 99 | #ifdef SOC_TRIGOUT |
| 100 | #define Soc_Decr_Val 0x00000000000300 |
| 101 | #else |
| 102 | #define Soc_Decr_Val 0x00000000000200 |
| 103 | #endif |
| 104 | #define L2_Addr_Mask_Reg 0xAF00000100 |
| 105 | #define L2_Addr_Mask_Val 0x000000002200aa00 |
| 106 | #define L2_Addr_Cmp_Reg 0xBF00000100 |
| 107 | #define L2_Addr_Cmp_Val 0x000000002200aa00 |
| 108 | #endif |
| 109 | |
| 110 | #ifdef MCU3 |
| 111 | #define L2_BANK_ADDR 0x180 |
| 112 | #define MCU_BANK_ADDR 0x180 |
| 113 | #define DRAM_ERR_INJ_REG 0x8400003290 |
| 114 | #define DRAM_ERR_STAT_REG 0x8400003280 |
| 115 | #define DBG_ERR_PA 0xAA00000180 |
| 116 | #define DBG_ERR_VAL 0x4 |
| 117 | #ifdef SOC_TRIGOUT |
| 118 | #define Soc_Decr_Val 0x00000000003000 |
| 119 | #else |
| 120 | #define Soc_Decr_Val 0x00000000002000 |
| 121 | #endif |
| 122 | #define L2_Addr_Mask_Reg 0xAF00000180 |
| 123 | #define L2_Addr_Mask_Val 0x000000002200aa00 |
| 124 | #define L2_Addr_Cmp_Reg 0xBF00000180 |
| 125 | #define L2_Addr_Cmp_Val 0x000000002200aa00 |
| 126 | #endif |
| 127 | |
| 128 | |
| 129 | #include "hboot.s" |
| 130 | #include "asi_s.h" |
| 131 | #include "err_defines.h" |
| 132 | #include "rst_defines.h" |
| 133 | |
| 134 | |
| 135 | .text |
| 136 | .global main |
| 137 | .global My_Corrected_ECC_error_trap |
| 138 | |
| 139 | |
| 140 | |
| 141 | main: |
| 142 | ta T_CHANGE_HPRIV |
| 143 | |
| 144 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 145 | !!!!! Check if this is the first time or after WMR reset |
| 146 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 147 | |
| 148 | setx wmr_flag, %g1, %g2 |
| 149 | ldx [%g2], %g3 |
| 150 | brnz %g3, After_Warm_Reset |
| 151 | nop |
| 152 | dec %g3 ! First time thru, Store a non-zero value |
| 153 | stx %g3, [%g2] |
| 154 | membar #Sync |
| 155 | |
| 156 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 157 | !!!!!! before WMR reset: delay loop for Vera programming !!!!!!! |
| 158 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 159 | |
| 160 | #ifdef PREWMR_VERA_PROG_DEL |
| 161 | setx PREWMR_VERA_PROG_DEL, %g1, %g2 |
| 162 | 1: |
| 163 | dec %g2 |
| 164 | brnz %g2, 1b |
| 165 | nop |
| 166 | #endif |
| 167 | |
| 168 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 169 | !!!! Bring FBD links down and do WMR reset |
| 170 | !!!! Warning: ensure the code is in the cache before bringing down the links |
| 171 | !!!! since cannot fetch from DRAM when the links is down. |
| 172 | !!!! NOTE: use %g2 and %g3 for WMR. Use %g4, %g5, %g6 and %g7 for MCU0/1/2/3 FBD_CHANNEL_STATE_REG |
| 173 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 174 | |
| 175 | mov 0x84, %g1 ! upper bits of MCU0's FBD_CHANNEL_STATE_REG address is 0x8400000800 |
| 176 | mov 0x800, %g2 ! lower bits of MCU0's FBD_CHANNEL_STATE_REG address is 0x8400000800 |
| 177 | sllx %g1, 32, %g3 |
| 178 | or %g2, %g3, %g4 ! %g4 contains MCU0's FBD_CHANNEL_STATE_REG address or 0x8400000800 |
| 179 | add %g4, 0x1000, %g5 ! %g5 contains MCU1's FBD_CHANNEL_STATE_REG address which is 0x1000 higher than MCU0 |
| 180 | add %g5, 0x1000, %g6 ! %g6 contains MCU2's FBD_CHANNEL_STATE_REG address which is 0x1000 higher than MCU1 |
| 181 | add %g6, 0x1000, %g7 ! %g7 contains MCU3's FBD_CHANNEL_STATE_REG address which is 0x1000 higher than MCU2 |
| 182 | |
| 183 | setx RST_RESET_GEN, %g1, %g2 ! %g2 is addr of RESET_GEN register |
| 184 | mov RST_RESET_GEN__WMR_GEN, %g3 ! %g3 is write data for WMR_GEN bit or bit 0 of RESET_GEN reg |
| 185 | |
| 186 | mov 0x1, %g1 ! will set %g1 to 0 at end of branching |
| 187 | ba 2f ! need this since can have garbage code between here and next aligned label |
| 188 | nop |
| 189 | |
| 190 | .align 64 |
| 191 | 2: brnz %g1, 1f |
| 192 | nop |
| 193 | clrx [%g4] ! set MCU0's FBD_CHANNEL_STATE_REG to 0 |
| 194 | |
| 195 | 1: brnz %g1, 1f |
| 196 | nop |
| 197 | clrx [%g5] ! set MCU1's FBD_CHANNEL_STATE_REG to 0 |
| 198 | |
| 199 | 1: brnz %g1, 1f |
| 200 | nop |
| 201 | clrx [%g6] ! set MCU2's FBD_CHANNEL_STATE_REG to 0 |
| 202 | |
| 203 | 1: brnz %g1, 1f |
| 204 | nop |
| 205 | clrx [%g7] ! set MCU3's FBD_CHANNEL_STATE_REG to 0 |
| 206 | |
| 207 | 1: brnz %g1, 1f |
| 208 | nop |
| 209 | stx %g3, [%g2] ! Write 0x1 to RESET_GEN to start Warm Reset |
| 210 | |
| 211 | 1: brz %g1, 1f |
| 212 | nop |
| 213 | mov %g0, %g1 |
| 214 | nop |
| 215 | |
| 216 | 1: brz %g0, 2b |
| 217 | nop |
| 218 | |
| 219 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 220 | !!!!!! after WMR reset !!!!!!!!!!!!!!! |
| 221 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 222 | |
| 223 | After_Warm_Reset: |
| 224 | or %g0, %g0, %g1 ! few dummy instructions |
| 225 | or %g0, %g0, %g1 ! few dummy instructions |
| 226 | |
| 227 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 228 | !!!!!! after WMR reset: delay loop for Vera programming !!!!!!! |
| 229 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 230 | |
| 231 | #ifdef POSTWMR_VERA_PROG_DEL |
| 232 | setx POSTWMR_VERA_PROG_DEL, %l2, %l1 |
| 233 | 1: |
| 234 | dec %l1 |
| 235 | brnz %l1, 1b |
| 236 | nop |
| 237 | #endif |
| 238 | membar #Sync |
| 239 | |
| 240 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 241 | !!!!!! from here down is the original diag |
| 242 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 243 | |
| 244 | setup_soc_decr_reg: |
| 245 | setx L2_Addr_Mask_Reg,%l1,%l4 |
| 246 | add %l4,L2_BANK_ADDR,%l4 |
| 247 | setx L2_Addr_Mask_Val,%l2,%l3 |
| 248 | add %l3,L2_BANK_ADDR,%l3 |
| 249 | stx %l3,[%l4] |
| 250 | nop |
| 251 | membar 0x40 |
| 252 | |
| 253 | setx L2_Addr_Cmp_Reg,%l4,%l5 |
| 254 | add %l5,L2_BANK_ADDR,%l5 |
| 255 | setx L2_Addr_Cmp_Val,%g5,%g4 |
| 256 | add %g4,L2_BANK_ADDR,%g4 |
| 257 | stx %g4,[%l5] |
| 258 | nop |
| 259 | membar 0x40 |
| 260 | |
| 261 | nop |
| 262 | setx Soc_Decr_Pa,%l1,%g4 |
| 263 | setx Soc_Decr_Val,%l7,%g5 |
| 264 | stx %g5,[%g4] |
| 265 | nop |
| 266 | membar 0x40 |
| 267 | |
| 268 | |
| 269 | disable_l1: |
| 270 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 271 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 272 | andn %l0, 0x3, %l0 |
| 273 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 274 | |
| 275 | |
| 276 | clear_dram_esr_0: |
| 277 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 278 | setx DRAM_ES_W1C_VALUE, %l0, %l5 |
| 279 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 280 | ! add %g5, MCU_BANK_ADDR, %g5 |
| 281 | stx %l5, [%g5] |
| 282 | |
| 283 | set_DRAM_error_inject_ch0: |
| 284 | mov 0x606, %l1 ! ECC Mask (Multi-bit error) |
| 285 | mov 0x1, %l2 |
| 286 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 287 | Or %l1, %l3, %l1 ! Set single shot ; |
| 288 | mov 0x1, %l2 |
| 289 | sllx %l2, DRAM_EI_ENB, %l3 |
| 290 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 291 | setx DRAM_ERR_INJ_REG, %l3, %g6 |
| 292 | ! add %g6, MCU_BANK_ADDR, %g6 |
| 293 | stx %l1, [%g6] |
| 294 | membar 0x40 |
| 295 | |
| 296 | enable_err_reporting: |
| 297 | setx L2EE_PA0, %l0, %l1 |
| 298 | add %l1, L2_BANK_ADDR, %l1 |
| 299 | ldx [%l1], %l2 |
| 300 | mov 0x3, %l0 |
| 301 | or %l2, %l0, %l2 |
| 302 | stx %l2, [%l1] |
| 303 | |
| 304 | |
| 305 | ! Write 1 to clear L2 Error status registers |
| 306 | clear_l2_ESR: |
| 307 | setx L2ES_PA0, %l3, %l4 |
| 308 | add %l4, L2_BANK_ADDR, %l4 |
| 309 | stx %l5, [%l4] |
| 310 | nop |
| 311 | |
| 312 | set_L2_Off_Mode: |
| 313 | setx L2CS_PA0, %l6, %g1 |
| 314 | add %g1, L2_BANK_ADDR, %g1 |
| 315 | mov 0x1, %l0 |
| 316 | stx %l0, [%g1] |
| 317 | |
| 318 | |
| 319 | store_to_L2_way0: |
| 320 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way |
| 321 | add %g2, L2_BANK_ADDR, %g2 |
| 322 | stx %g5, [%g2] |
| 323 | membar #Sync |
| 324 | read_error_address_ch0: |
| 325 | ldx [%g2], %l1 |
| 326 | membar #Sync |
| 327 | |
| 328 | |
| 329 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 330 | write_mcu_channel_0: |
| 331 | setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way |
| 332 | add %g3, L2_BANK_ADDR, %g3 |
| 333 | stx %g5, [%g3] |
| 334 | membar #Sync |
| 335 | |
| 336 | /** |
| 337 | *read_error_address_ch0: |
| 338 | * ldx [%g2], %l1 |
| 339 | * membar #Sync |
| 340 | *! ldx [%g3], %l2 |
| 341 | *! membar #Sync |
| 342 | **/ |
| 343 | |
| 344 | |
| 345 | check_DRAM_ESR_0: |
| 346 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 347 | ! add %g5, MCU_BANK_ADDR, %g5 |
| 348 | ldx [%g5], %l6 |
| 349 | setx 0xffc0000000000000, %l0,%o2 |
| 350 | and %l6,%o2,%l6 |
| 351 | |
| 352 | |
| 353 | compute_dram_ESR: |
| 354 | mov 0x1, %l1 |
| 355 | sllx %l1, DRAM_ES_DAU, %l0 |
| 356 | |
| 357 | |
| 358 | verify_dram_ESR: |
| 359 | cmp %l0, %l6 |
| 360 | // bne %xcc, test_fail |
| 361 | nop |
| 362 | |
| 363 | check_L2_ESR_0: |
| 364 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 365 | add %g5, L2_BANK_ADDR, %g5 |
| 366 | ldx [%g5], %l6 |
| 367 | |
| 368 | compute_L2_ESR: |
| 369 | setx 0xfffffffff0000000, %l3, %l0 |
| 370 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits |
| 371 | mov 0x1, %l1 |
| 372 | sllx %l1, L2ES_DAU, %l0 |
| 373 | mov 0x1, %l1 |
| 374 | sllx %l1, L2ES_VEU, %l2 |
| 375 | or %l0, %l2, %l3 |
| 376 | |
| 377 | verify_L2_ESR: |
| 378 | cmp %l6, %l3 |
| 379 | bne %xcc, test_fail |
| 380 | nop |
| 381 | |
| 382 | |
| 383 | setx L2EA_PA0, %l2, %l3 |
| 384 | add %l3, L2_BANK_ADDR, %l3 |
| 385 | check_l2_EAR: |
| 386 | ldx [%l3], %l4 |
| 387 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 388 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way |
| 389 | add %g2, L2_BANK_ADDR, %g2 |
| 390 | |
| 391 | setx 0xffffffffc0, %l0,%o2 |
| 392 | and %l4, %o2, %l4 |
| 393 | cmp %l4, %g2 |
| 394 | // bne %xcc, test_fail |
| 395 | nop |
| 396 | |
| 397 | check_Corr_err_trap: |
| 398 | ! Check if a Corrected ECC Error Trap happened |
| 399 | set EXECUTED, %l0 |
| 400 | cmp %o0, %l0 |
| 401 | // bne test_fail |
| 402 | nop |
| 403 | mov TT_Data_Access_Error, %l0 |
| 404 | cmp %o1, %l0 |
| 405 | // bne test_fail |
| 406 | nop |
| 407 | |
| 408 | |
| 409 | ba test_pass |
| 410 | nop |
| 411 | |
| 412 | My_Corrected_ECC_error_trap: |
| 413 | |
| 414 | !My_Recoverable_Sw_error_trap: |
| 415 | ! Signal trap taken |
| 416 | setx EXECUTED, %l0, %o0 |
| 417 | ! save trap type value |
| 418 | rdpr %tt, %o1 |
| 419 | retry |
| 420 | nop |
| 421 | |
| 422 | |
| 423 | /******************************************************* |
| 424 | * Exit code |
| 425 | *******************************************************/ |
| 426 | |
| 427 | test_pass: |
| 428 | ta T_GOOD_TRAP |
| 429 | |
| 430 | |
| 431 | test_fail: |
| 432 | ta T_BAD_TRAP |
| 433 | |
| 434 | /************************************************************************ |
| 435 | * Test case data start |
| 436 | ************************************************************************/ |
| 437 | .data |
| 438 | wmr_flag: |
| 439 | .xword 0x0000000000000000 ! set this to non-zero before start WMR |
| 440 | .xword 0x0000000000000000 |
| 441 | .xword 0x0000000000000000 |
| 442 | .xword 0x0000000000000000 |
| 443 | .end |