| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: tcu_regs_dram.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define TEST_DATA0 0x4c3fdead4c3fbeef |
| 42 | #define tmp1 %l2 |
| 43 | #define tmp2 %l3 |
| 44 | #define tmp3 %l4 |
| 45 | #define tmp4 %l5 |
| 46 | |
| 47 | |
| 48 | #include "asi_s.h" |
| 49 | #include "mcu_defines.h" |
| 50 | #include "tcu_defines.h" |
| 51 | |
| 52 | /************************************************************************ |
| 53 | Test case code start |
| 54 | ************************************************************************/ |
| 55 | |
| 56 | #ifdef FAST_BOOT |
| 57 | #define RESET_VEC 0x0000000000000000 |
| 58 | #else |
| 59 | #define RESET_VEC 0xfffffffff0000000 |
| 60 | #endif |
| 61 | |
| 62 | SECTION .RED_SEC TEXT_VA = RESET_VEC |
| 63 | attr_text { |
| 64 | Name=.RED_SEC, |
| 65 | hypervisor |
| 66 | } |
| 67 | |
| 68 | .text |
| 69 | nop |
| 70 | nop |
| 71 | nop |
| 72 | nop |
| 73 | nop |
| 74 | nop |
| 75 | nop |
| 76 | nop |
| 77 | |
| 78 | .global main |
| 79 | |
| 80 | ! DRAM REFRESH COUNTER |
| 81 | L1: |
| 82 | setx 0x8400000000, %l5, %l6 |
| 83 | add %l6, 0x0038, %g7 |
| 84 | ldx [%g7], %g3 |
| 85 | cmp %g3, %g0 |
| 86 | bne bad_trap |
| 87 | membar #Sync |
| 88 | |
| 89 | ! DRAM ERROR STATUS REG |
| 90 | L2: |
| 91 | setx 0x8400000000, %l5, %l6 |
| 92 | add %l6, 0x0280, %g7 |
| 93 | ldx [%g7], %g3 |
| 94 | cmp %g3, %g0 |
| 95 | bne bad_trap |
| 96 | membar #Sync |
| 97 | |
| 98 | ! DRAM ERROR ADDRESS |
| 99 | L3: |
| 100 | setx 0x8400000000, %l5, %l6 |
| 101 | add %l6, 0x0288, %g7 |
| 102 | ldx [%g7], %g3 |
| 103 | cmp %g3, %g0 |
| 104 | bne bad_trap |
| 105 | membar #Sync |
| 106 | |
| 107 | ! DRAM ERROR INJECT REG |
| 108 | L4: |
| 109 | setx 0x8400000000, %l5, %l6 |
| 110 | add %l6, 0x0290, %g7 |
| 111 | ldx [%g7], %g3 |
| 112 | cmp %g3, %g0 |
| 113 | bne bad_trap |
| 114 | membar #Sync |
| 115 | |
| 116 | ! DRAM ERROR COUNTER REG |
| 117 | L5: |
| 118 | setx 0x8400000000, %l5, %l6 |
| 119 | add %l6, 0x0298, %g7 |
| 120 | ldx [%g7], %g3 |
| 121 | cmp %g3, %g0 |
| 122 | bne bad_trap |
| 123 | membar #Sync |
| 124 | |
| 125 | ! DRAM FBD ERROR SYNDROME |
| 126 | L6: |
| 127 | setx 0x8400000000, %l5, %l6 |
| 128 | add %l6, 0x0c00, %g7 |
| 129 | ldx [%g7], %g3 |
| 130 | cmp %g3, %g0 |
| 131 | bne bad_trap |
| 132 | membar #Sync |
| 133 | |
| 134 | ! DRAM ERROR LOCATION REG |
| 135 | L7: |
| 136 | setx 0x8400000000, %l5, %l6 |
| 137 | add %l6, 0x02A0, %g7 |
| 138 | ldx [%g7], %g3 |
| 139 | cmp %g3, %g0 |
| 140 | bne bad_trap |
| 141 | membar #Sync |
| 142 | |
| 143 | ! DRAM DEBUG TRIGGER |
| 144 | L8: |
| 145 | setx 0x8400000000, %l5, %l6 |
| 146 | add %l6, 0x0230, %g7 |
| 147 | ldx [%g7], %g3 |
| 148 | cmp %g3, %g0 |
| 149 | bne bad_trap |
| 150 | membar #Sync |
| 151 | |
| 152 | ! DRAM CAS ADDRESS WIDTH |
| 153 | L9: |
| 154 | set 0xb, %i3 |
| 155 | setx 0x8400000000, %l5, %l6 |
| 156 | ldx [%l6], %g7 |
| 157 | cmp %g7, %i3 |
| 158 | bne bad_trap |
| 159 | membar #Sync |
| 160 | |
| 161 | ! DRAM RAS ADDRESS WIDTH |
| 162 | L10: |
| 163 | set 0xf, %i3 |
| 164 | setx 0x8400000000, %l5, %l6 |
| 165 | add %l6, 0x8, %g7 |
| 166 | ldx [%g7], %g3 |
| 167 | cmp %g3, %i3 |
| 168 | bne bad_trap |
| 169 | membar #Sync |
| 170 | |
| 171 | ! DRAM CAS LATENCY |
| 172 | L11: |
| 173 | set 0x3, %i3 |
| 174 | setx 0x8400000000, %l5, %l6 |
| 175 | add %l6, 0x10, %g7 |
| 176 | ldx [%g7], %g3 |
| 177 | cmp %g3, %i3 |
| 178 | bne bad_trap |
| 179 | membar #Sync |
| 180 | |
| 181 | ! DRAM CAS SCRUB FREQUENCY |
| 182 | L12: |
| 183 | set 0xfff, %i3 |
| 184 | setx 0x8400000000, %l5, %l6 |
| 185 | add %l6, 0x18, %g7 |
| 186 | ldx [%g7], %g3 |
| 187 | cmp %g3, %i3 |
| 188 | bne bad_trap |
| 189 | membar #Sync |
| 190 | |
| 191 | ! DRAM REFRESH FREQUENCY |
| 192 | L13: |
| 193 | set 0x820, %i3 |
| 194 | setx 0x8400000000, %l5, %l6 |
| 195 | add %l6, 0x20, %g7 |
| 196 | ldx [%g7], %g3 |
| 197 | cmp %g3, %i3 |
| 198 | bne bad_trap |
| 199 | membar #Sync |
| 200 | |
| 201 | ! DRAM OPEN BANK |
| 202 | L14: |
| 203 | setx 0x1ffff, tmp1, tmp2 |
| 204 | setx 0x8400000000, %l5, %l6 |
| 205 | add %l6, 0x28, %g7 |
| 206 | ldx [%g7], %g3 |
| 207 | cmp %g3, %l3 |
| 208 | bne bad_trap |
| 209 | membar #Sync |
| 210 | |
| 211 | ! DRAM SCRUB ENABLE |
| 212 | L15: |
| 213 | setx 0x8400000000, %l5, %l6 |
| 214 | add %l6, 0x40, %g7 |
| 215 | ldx [%g7], %g3 |
| 216 | cmp %g3, %g0 |
| 217 | bne bad_trap |
| 218 | membar #Sync |
| 219 | |
| 220 | ! DRAM PROGRAMMABLE TIME |
| 221 | L16: |
| 222 | set 0xffff, %i3 |
| 223 | setx 0x8400000000, %l5, %l6 |
| 224 | add %l6, 0x48, %g7 |
| 225 | ldx [%g7], %g3 |
| 226 | cmp %g3, %i3 |
| 227 | bne bad_trap |
| 228 | membar #Sync |
| 229 | |
| 230 | |
| 231 | ! DRAM RAS TO RAS DIFFERENT BANK DELAY |
| 232 | L17: |
| 233 | set 0x2, %i3 |
| 234 | setx 0x8400000000, %l5, %l6 |
| 235 | add %l6, 0x80, %g7 |
| 236 | ldx [%g7], %g3 |
| 237 | cmp %g3, %i3 |
| 238 | bne bad_trap |
| 239 | membar #Sync |
| 240 | |
| 241 | ! DRAM RAS TO RAS SAME BANK DELAY |
| 242 | L18: |
| 243 | set 0xc, %i3 |
| 244 | setx 0x8400000000, %l5, %l6 |
| 245 | add %l6, 0x88, %g7 |
| 246 | ldx [%g7], %g3 |
| 247 | cmp %g3, %i3 |
| 248 | bne bad_trap |
| 249 | membar #Sync |
| 250 | |
| 251 | ! DRAM RAS TO CAS DELAY |
| 252 | L19: |
| 253 | set 0x3, %i3 |
| 254 | setx 0x8400000000, %l5, %l6 |
| 255 | add %l6, 0x90, %g7 |
| 256 | ldx [%g7], %g3 |
| 257 | cmp %g3, %i3 |
| 258 | bne bad_trap |
| 259 | membar #Sync |
| 260 | |
| 261 | ! DRAM WRITE TO READ CAS DELAY |
| 262 | L20: |
| 263 | setx 0x8400000000, %l5, %l6 |
| 264 | add %l6, 0x98, %g7 |
| 265 | ldx [%g7], %g3 |
| 266 | cmp %g3, %g0 |
| 267 | bne bad_trap |
| 268 | membar #Sync |
| 269 | |
| 270 | ! DRAM READ TO WRITE CAS DELAY |
| 271 | L21: |
| 272 | setx 0x8400000000, %l5, %l6 |
| 273 | add %l6, 0xa0, %g7 |
| 274 | ldx [%g7], %g3 |
| 275 | cmp %g3, %g0 |
| 276 | bne bad_trap |
| 277 | membar #Sync |
| 278 | |
| 279 | ! DRAM INTERNAL READ TO PRECHARGE DELAY |
| 280 | L22: |
| 281 | set 0x2, %i3 |
| 282 | setx 0x8400000000, %l5, %l6 |
| 283 | add %l6, 0xa8, %g7 |
| 284 | ldx [%g7], %g3 |
| 285 | cmp %g3, %i3 |
| 286 | bne bad_trap |
| 287 | membar #Sync |
| 288 | |
| 289 | ! DRAM ACTIVE TO PRECHARGE DELAY |
| 290 | L23: |
| 291 | set 0x9, %i3 |
| 292 | setx 0x8400000000, %l5, %l6 |
| 293 | add %l6, 0xb0, %g7 |
| 294 | ldx [%g7], %g3 |
| 295 | cmp %g3, %i3 |
| 296 | bne bad_trap |
| 297 | membar #Sync |
| 298 | |
| 299 | |
| 300 | good_trap: |
| 301 | ba good_trap |
| 302 | nop |
| 303 | nop |
| 304 | bad_trap: |
| 305 | ba bad_trap |
| 306 | nop |
| 307 | |
| 308 | |
| 309 | /************************************************************************ |
| 310 | Test case data start |
| 311 | ************************************************************************/ |
| 312 | .data |
| 313 | .word 0x0 |
| 314 | user_data_start: |
| 315 | .end |
| 316 | |