| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: dump_regs.h |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #include "checkp_offsets.h" |
| 39 | /*overwrites %g5, %g4 used as store for %cwp, uses g3 as buffer pointer and increments it to end of data buffer*/ |
| 40 | /*assumes we're using alternate globals */ |
| 41 | /*replay side overwrites scratch regs at VA0, VA8 of asi 4f */ |
| 42 | #ifdef DUMP |
| 43 | rdpr %tl,%g3 |
| 44 | stx %g3,[%g5] |
| 45 | rdpr %gl,%g3 |
| 46 | stx %g3,[%g5+8] |
| 47 | #else |
| 48 | ldx [%g5], %g3 |
| 49 | wrpr %g3, %tl |
| 50 | ldx [%g5+8], %g3 |
| 51 | wrpr %g3, %gl |
| 52 | #endif |
| 53 | add %g5, 0x10, %g5 |
| 54 | ! 5 words |
| 55 | /*{{{ up window state*/ |
| 56 | #ifdef DUMP |
| 57 | rdpr %cwp,%g4 |
| 58 | stx %g4,[%g5+0] |
| 59 | rdpr %cansave,%g3 |
| 60 | stx %g3,[%g5+8] |
| 61 | rdpr %canrestore,%g3 |
| 62 | stx %g3,[%g5+0x10] |
| 63 | rdpr %otherwin,%g3 |
| 64 | stx %g3,[%g5+0x18] |
| 65 | rdpr %cleanwin,%g3 |
| 66 | stx %g3,[%g5+0x20] |
| 67 | rdpr %wstate,%g3 |
| 68 | stx %g3,[%g5+0x28] |
| 69 | #else |
| 70 | ldx [%g5+0], %g4 |
| 71 | wrpr %g4,%cwp |
| 72 | ldx [%g5+8], %g3 |
| 73 | wrpr %g3,%cansave |
| 74 | ldx [%g5+0x10], %g3 |
| 75 | wrpr %g3,%canrestore |
| 76 | ldx [%g5+0x18], %g3 |
| 77 | wrpr %g3,%otherwin |
| 78 | ldx [%g5+0x20], %g3 |
| 79 | wrpr %g3,%cleanwin |
| 80 | ldx [%g5+0x28], %g3 |
| 81 | wrpr %g3,%wstate |
| 82 | #endif |
| 83 | add %g5, 0x30, %g5 |
| 84 | /*}}} */ |
| 85 | |
| 86 | |
| 87 | mov 8, %g3 |
| 88 | arf_loop: |
| 89 | subcc %g3, 1, %g3 |
| 90 | wrpr %g0, %g3, %cwp |
| 91 | /*{{{ dump arf*/ |
| 92 | #ifdef DUMP |
| 93 | stx %l0,[%g5+(0*CHECKP_LOCALS_INCR)] |
| 94 | stx %l1,[%g5+(1*CHECKP_LOCALS_INCR)] |
| 95 | stx %l2,[%g5+(2*CHECKP_LOCALS_INCR)] |
| 96 | stx %l3,[%g5+(3*CHECKP_LOCALS_INCR)] |
| 97 | stx %l4,[%g5+(4*CHECKP_LOCALS_INCR)] |
| 98 | stx %l5,[%g5+(5*CHECKP_LOCALS_INCR)] |
| 99 | stx %l6,[%g5+(6*CHECKP_LOCALS_INCR)] |
| 100 | stx %l7,[%g5+(7*CHECKP_LOCALS_INCR)] |
| 101 | add %g5, (CHECKP_LOCALS_INCR*8), %g5 |
| 102 | stx %i0,[%g5+(0*CHECKP_INS_INCR)] |
| 103 | stx %i1,[%g5+(1*CHECKP_INS_INCR)] |
| 104 | stx %i2,[%g5+(2*CHECKP_INS_INCR)] |
| 105 | stx %i3,[%g5+(3*CHECKP_INS_INCR)] |
| 106 | stx %i4,[%g5+(4*CHECKP_INS_INCR)] |
| 107 | stx %i5,[%g5+(5*CHECKP_INS_INCR)] |
| 108 | stx %i6,[%g5+(6*CHECKP_INS_INCR)] |
| 109 | stx %i7,[%g5+(7*CHECKP_INS_INCR)] |
| 110 | add %g5, (CHECKP_INS_INCR*8), %g5 |
| 111 | #else |
| 112 | ldx [%g5+(0*CHECKP_LOCALS_INCR)],%l0 |
| 113 | ldx [%g5+(1*CHECKP_LOCALS_INCR)],%l1 |
| 114 | ldx [%g5+(2*CHECKP_LOCALS_INCR)],%l2 |
| 115 | ldx [%g5+(3*CHECKP_LOCALS_INCR)],%l3 |
| 116 | ldx [%g5+(4*CHECKP_LOCALS_INCR)],%l4 |
| 117 | ldx [%g5+(5*CHECKP_LOCALS_INCR)],%l5 |
| 118 | ldx [%g5+(6*CHECKP_LOCALS_INCR)],%l6 |
| 119 | ldx [%g5+(7*CHECKP_LOCALS_INCR)],%l7 |
| 120 | add %g5, (CHECKP_LOCALS_INCR*8), %g5 |
| 121 | ldx [%g5+(0*CHECKP_INS_INCR)],%i0 |
| 122 | ldx [%g5+(1*CHECKP_INS_INCR)],%i1 |
| 123 | ldx [%g5+(2*CHECKP_INS_INCR)],%i2 |
| 124 | ldx [%g5+(3*CHECKP_INS_INCR)],%i3 |
| 125 | ldx [%g5+(4*CHECKP_INS_INCR)],%i4 |
| 126 | ldx [%g5+(5*CHECKP_INS_INCR)],%i5 |
| 127 | ldx [%g5+(6*CHECKP_INS_INCR)],%i6 |
| 128 | ldx [%g5+(7*CHECKP_INS_INCR)],%i7 |
| 129 | add %g5, (CHECKP_INS_INCR*8), %g5 |
| 130 | #endif |
| 131 | /*}}} */ |
| 132 | brnz %g3,arf_loop |
| 133 | add %g5, (CHECKP_INS_INCR*16), %g5 |
| 134 | !restore cwp |
| 135 | wrpr %g0, %g4, %cwp |
| 136 | |
| 137 | ! 0x32 words x 8 = 256 bytes |
| 138 | #if 0 |
| 139 | rdpr %pstate, %g3 |
| 140 | andcc %g3, 0x10, %g0 |
| 141 | bne 1f |
| 142 | nop |
| 143 | wrpr %g3, 0x10, %pstate |
| 144 | 1: |
| 145 | /*{{{ dump fpu regs*/ |
| 146 | #ifdef DUMP |
| 147 | std %f0, [%g5 + 0] |
| 148 | std %f2, [%g5 + (1*CHECKP_FLOATS_INCR)] |
| 149 | std %f4, [%g5 + (2*CHECKP_FLOATS_INCR)] |
| 150 | std %f6, [%g5 + (3*CHECKP_FLOATS_INCR)] |
| 151 | std %f8, [%g5 + (4*CHECKP_FLOATS_INCR)] |
| 152 | std %f10, [%g5 + (5*CHECKP_FLOATS_INCR)] |
| 153 | std %f12, [%g5 + (6*CHECKP_FLOATS_INCR)] |
| 154 | std %f14, [%g5 + (7*CHECKP_FLOATS_INCR)] |
| 155 | std %f16, [%g5 + (8*CHECKP_FLOATS_INCR)] |
| 156 | std %f18, [%g5 + (9*CHECKP_FLOATS_INCR)] |
| 157 | std %f20, [%g5 + (10*CHECKP_FLOATS_INCR)] |
| 158 | std %f22, [%g5 + (11*CHECKP_FLOATS_INCR)] |
| 159 | std %f24, [%g5 + (12*CHECKP_FLOATS_INCR)] |
| 160 | std %f26, [%g5 + (13*CHECKP_FLOATS_INCR)] |
| 161 | std %f28, [%g5 + (14*CHECKP_FLOATS_INCR)] |
| 162 | std %f30, [%g5 + (15*CHECKP_FLOATS_INCR)] |
| 163 | std %f32, [%g5 + (16*CHECKP_FLOATS_INCR)] |
| 164 | std %f34, [%g5 + (17*CHECKP_FLOATS_INCR)] |
| 165 | std %f36, [%g5 + (18*CHECKP_FLOATS_INCR)] |
| 166 | std %f38, [%g5 + (19*CHECKP_FLOATS_INCR)] |
| 167 | std %f40, [%g5 + (20*CHECKP_FLOATS_INCR)] |
| 168 | std %f42, [%g5 + (21*CHECKP_FLOATS_INCR)] |
| 169 | std %f44, [%g5 + (22*CHECKP_FLOATS_INCR)] |
| 170 | std %f46, [%g5 + (23*CHECKP_FLOATS_INCR)] |
| 171 | std %f48, [%g5 + (24*CHECKP_FLOATS_INCR)] |
| 172 | std %f50, [%g5 + (25*CHECKP_FLOATS_INCR)] |
| 173 | std %f52, [%g5 + (26*CHECKP_FLOATS_INCR)] |
| 174 | std %f54, [%g5 + (27*CHECKP_FLOATS_INCR)] |
| 175 | std %f56, [%g5 + (28*CHECKP_FLOATS_INCR)] |
| 176 | std %f58, [%g5 + (29*CHECKP_FLOATS_INCR)] |
| 177 | std %f60, [%g5 + (30*CHECKP_FLOATS_INCR)] |
| 178 | std %f62, [%g5 + (31*CHECKP_FLOATS_INCR)] |
| 179 | #else |
| 180 | ldd [%g5+0], %f0 |
| 181 | ldd [%g5+(1*CHECKP_FLOATS_INCR)], %f2 |
| 182 | ldd [%g5+(2*CHECKP_FLOATS_INCR)], %f4 |
| 183 | ldd [%g5+(3*CHECKP_FLOATS_INCR)], %f6 |
| 184 | ldd [%g5+(4*CHECKP_FLOATS_INCR)], %f8 |
| 185 | ldd [%g5+(5*CHECKP_FLOATS_INCR)], %f10 |
| 186 | ldd [%g5+(6*CHECKP_FLOATS_INCR)], %f12 |
| 187 | ldd [%g5+(7*CHECKP_FLOATS_INCR)], %f14 |
| 188 | ldd [%g5+(8*CHECKP_FLOATS_INCR)], %f16 |
| 189 | ldd [%g5+(9*CHECKP_FLOATS_INCR)], %f18 |
| 190 | ldd [%g5+(10*CHECKP_FLOATS_INCR)], %f20 |
| 191 | ldd [%g5+(11*CHECKP_FLOATS_INCR)], %f22 |
| 192 | ldd [%g5+(12*CHECKP_FLOATS_INCR)], %f24 |
| 193 | ldd [%g5+(13*CHECKP_FLOATS_INCR)], %f26 |
| 194 | ldd [%g5+(14*CHECKP_FLOATS_INCR)], %f28 |
| 195 | ldd [%g5+(15*CHECKP_FLOATS_INCR)], %f30 |
| 196 | ldd [%g5+(16*CHECKP_FLOATS_INCR)], %f32 |
| 197 | ldd [%g5+(17*CHECKP_FLOATS_INCR)], %f34 |
| 198 | ldd [%g5+(18*CHECKP_FLOATS_INCR)], %f36 |
| 199 | ldd [%g5+(19*CHECKP_FLOATS_INCR)], %f38 |
| 200 | ldd [%g5+(20*CHECKP_FLOATS_INCR)], %f40 |
| 201 | ldd [%g5+(21*CHECKP_FLOATS_INCR)], %f42 |
| 202 | ldd [%g5+(22*CHECKP_FLOATS_INCR)], %f44 |
| 203 | ldd [%g5+(23*CHECKP_FLOATS_INCR)], %f46 |
| 204 | ldd [%g5+(24*CHECKP_FLOATS_INCR)], %f48 |
| 205 | ldd [%g5+(25*CHECKP_FLOATS_INCR)], %f50 |
| 206 | ldd [%g5+(26*CHECKP_FLOATS_INCR)], %f52 |
| 207 | ldd [%g5+(27*CHECKP_FLOATS_INCR)], %f54 |
| 208 | ldd [%g5+(28*CHECKP_FLOATS_INCR)], %f56 |
| 209 | ldd [%g5+(29*CHECKP_FLOATS_INCR)], %f58 |
| 210 | ldd [%g5+(30*CHECKP_FLOATS_INCR)], %f60 |
| 211 | ldd [%g5+(31*CHECKP_FLOATS_INCR)], %f62 |
| 212 | #endif |
| 213 | /*}}} */ |
| 214 | wrpr %g3, 0x0, %pstate |
| 215 | #endif |
| 216 | add %g5, (32*CHECKP_FLOATS_INCR), %g5 |
| 217 | |
| 218 | /*{{{ dump program state also trap state regs*/ |
| 219 | #ifdef DUMP |
| 220 | ! 0x50 bytes |
| 221 | rd %y,%g3 |
| 222 | stx %g3,[%g5+0] |
| 223 | ! stx %fsr,[%g5+8] |
| 224 | rd %asi,%g3 |
| 225 | stx %g3,[%g5+0x10] |
| 226 | |
| 227 | |
| 228 | rdpr %pstate,%g3 |
| 229 | stx %g3,[%g5+0x20] |
| 230 | |
| 231 | rdpr %pil,%g3 |
| 232 | stx %g3,[%g5+0x28] |
| 233 | |
| 234 | rdpr %tba,%g3 |
| 235 | stx %g3,[%g5+0x30] |
| 236 | mov %asr24, %g3 !stick |
| 237 | stx %g3,[%g5+0x38] |
| 238 | mov %asr25, %g3 !stick_cmp |
| 239 | stx %g3,[%g5+0x40] |
| 240 | rdpr %tick, %g3 |
| 241 | stx %g3,[%g5+0x48] |
| 242 | rd %tick_cmpr, %g3 |
| 243 | stx %g3,[%g5+0x50] |
| 244 | |
| 245 | ! mov %gsr, %g3 |
| 246 | stx %g3,[%g5+0x58] |
| 247 | rd %softint,%g3 |
| 248 | stx %g3,[%g5+0x60] |
| 249 | |
| 250 | add %g5, 0x68, %g5 |
| 251 | |
| 252 | |
| 253 | /*{{{ dump trap state regs for TL 1 thru 6*/ |
| 254 | rdpr %tl,%g4 |
| 255 | |
| 256 | mov 1, %g3 |
| 257 | 1: |
| 258 | wrpr %g3, %tl |
| 259 | |
| 260 | rdpr %tstate,%g3 |
| 261 | stx %g3,[%g5+0x0] |
| 262 | rdpr %tpc,%g3 |
| 263 | stx %g3,[%g5+0x8] |
| 264 | rdpr %tnpc,%g3 |
| 265 | stx %g3,[%g5+0x10] |
| 266 | rdpr %tt,%g3 |
| 267 | stx %g3,[%g5+0x18] |
| 268 | rdhpr %htstate,%g3 |
| 269 | stx %g3,[%g5+0x20] |
| 270 | add %g5, 0x28, %g5 |
| 271 | rdpr %tl,%g3 |
| 272 | subcc %g3, 6, %g0 |
| 273 | bne 1b |
| 274 | add %g3, 1, %g3 |
| 275 | |
| 276 | wrpr %g4, %tl |
| 277 | /*}}} */ |
| 278 | |
| 279 | |
| 280 | ! 0x68 bytes + 32*num TL bytes |
| 281 | #else |
| 282 | |
| 283 | ldx [%g5+0],%g3 |
| 284 | wr %g3, %y |
| 285 | ! ldx [%g5+8], %fsr |
| 286 | ldx [%g5+0x10], %g3 |
| 287 | wr %g3, %g0, %asi |
| 288 | ldx [%g5+0x20], %g3 |
| 289 | wrpr %g3, %pstate |
| 290 | ldx [%g5+0x28], %g3 |
| 291 | wrpr %g3, %pil |
| 292 | ldx [%g5+0x30], %g3 |
| 293 | wrpr %g3, %tba |
| 294 | ldx [%g5+0x38], %g3 |
| 295 | mov %g3, %asr24 |
| 296 | ldx [%g5+0x40], %g3 |
| 297 | mov %g3, %asr25 |
| 298 | ldx [%g5+0x48], %g3 |
| 299 | wrpr %g3, %tick |
| 300 | ldx [%g5+0x50], %g3 |
| 301 | wr %g3, %g0, %tick_cmpr |
| 302 | ldx [%g5+0x58], %g3 |
| 303 | !mov %g3, %gsr |
| 304 | ldx [%g5+0x60], %g3 |
| 305 | wr %g3, %g0, %set_softint |
| 306 | add %g5, 0x68, %g5 |
| 307 | |
| 308 | /*{{{ read trap regs*/ |
| 309 | rdpr %tl,%g4 |
| 310 | mov 1, %g3 |
| 311 | tl_loop: |
| 312 | wrpr %g3, %tl |
| 313 | |
| 314 | ldx [%g5+0x0], %g3 |
| 315 | wrpr %g3, %tstate |
| 316 | ldx [%g5+0x8], %g3 |
| 317 | wrpr %g3, %tpc |
| 318 | ldx [%g5+0x10], %g3 |
| 319 | wrpr %g3, %tnpc |
| 320 | ldx [%g5+0x18], %g3 |
| 321 | wrpr %g3, %tt |
| 322 | ldx [%g5+0x20], %g3 |
| 323 | wrhpr %g3, %htstate |
| 324 | add %g5, 0x28, %g5 |
| 325 | |
| 326 | rdpr %tl,%g3 |
| 327 | subcc %g3, 6, %g0 |
| 328 | bne tl_loop |
| 329 | add %g3, 1, %g3 |
| 330 | |
| 331 | wrpr %g4, %tl |
| 332 | /*}}} */ |
| 333 | |
| 334 | #endif |
| 335 | /*}}} */ |
| 336 | |
| 337 | /*{{{ hpriv*/ |
| 338 | #ifdef DUMP |
| 339 | rdhpr %hpstate,%g3 |
| 340 | stx %g3,[%g5+0x0] |
| 341 | rdhpr %htstate,%g3 |
| 342 | stx %g3,[%g5+0x8] |
| 343 | rdhpr %htba,%g3 |
| 344 | stx %g3,[%g5+0x10] |
| 345 | !rd %asr31,%g3 |
| 346 | !.word 0x874fc000 |
| 347 | stx %g3,[%g5+0x18] |
| 348 | add %g5, 0x20, %g5 |
| 349 | #else |
| 350 | ldx [%g5+0x0], %g3 |
| 351 | wrhpr %g3, %hpstate |
| 352 | ldx [%g5+0x8], %g3 |
| 353 | wrhpr %g3, %htstate |
| 354 | ldx [%g5+0x10], %g3 |
| 355 | wrhpr %g3, %htba |
| 356 | ldx [%g5+0x18], %g3 |
| 357 | ! wrhpr %g2, %g0, %asr31 |
| 358 | add %g5, 0x20, %g5 |
| 359 | #endif |
| 360 | /*}}} */ |
| 361 | |
| 362 | /*{{{ globals*/ |
| 363 | ! 0x40 bytes normal |
| 364 | #ifdef DUMP |
| 365 | !save l1,l2 into globals g3,g5,l2 becomes g5 ptr |
| 366 | mov %l2, %g3 |
| 367 | mov %g5, %l2 |
| 368 | mov %l1, %g5 |
| 369 | #else |
| 370 | !assume bottom two scratch regs aren't used yet |
| 371 | wr %g0, 0x4f, %asi |
| 372 | stxa %l1, [%g0]%asi |
| 373 | stxa %l2, [%g0+8]%asi |
| 374 | mov %g5, %l2 |
| 375 | #endif |
| 376 | rdpr %gl, %l1 |
| 377 | wrpr %g0, 0, %gl |
| 378 | #ifdef DUMP |
| 379 | stx %g0, [%l2+(0*CHECKP_GLOBALS_INCR)] |
| 380 | stx %g1, [%l2+(1*CHECKP_GLOBALS_INCR)] |
| 381 | stx %g2, [%l2+(2*CHECKP_GLOBALS_INCR)] |
| 382 | stx %g3, [%l2+(3*CHECKP_GLOBALS_INCR)] |
| 383 | stx %g4, [%l2+(4*CHECKP_GLOBALS_INCR)] |
| 384 | stx %g5, [%l2+(5*CHECKP_GLOBALS_INCR)] |
| 385 | stx %g6, [%l2+(6*CHECKP_GLOBALS_INCR)] |
| 386 | stx %g7, [%l2+(7*CHECKP_GLOBALS_INCR)] |
| 387 | #else |
| 388 | ldx [%l2+(0*CHECKP_GLOBALS_INCR)], %g0 |
| 389 | ldx [%l2+(1*CHECKP_GLOBALS_INCR)], %g1 |
| 390 | ldx [%l2+(2*CHECKP_GLOBALS_INCR)], %g2 |
| 391 | ldx [%l2+(3*CHECKP_GLOBALS_INCR)], %g3 |
| 392 | ldx [%l2+(4*CHECKP_GLOBALS_INCR)], %g4 |
| 393 | ldx [%l2+(5*CHECKP_GLOBALS_INCR)], %g5 |
| 394 | ldx [%l2+(6*CHECKP_GLOBALS_INCR)], %g6 |
| 395 | ldx [%l2+(7*CHECKP_GLOBALS_INCR)], %g7 |
| 396 | #endif |
| 397 | add %l2, (8*CHECKP_GLOBALS_INCR), %l2 |
| 398 | |
| 399 | |
| 400 | wrpr %g0, 1, %gl |
| 401 | |
| 402 | #ifdef DUMP |
| 403 | stx %g0,[%l2+(0*CHECKP_GLOBALS_INCR)] |
| 404 | stx %g1,[%l2+(1*CHECKP_GLOBALS_INCR)] |
| 405 | stx %g2,[%l2+(2*CHECKP_GLOBALS_INCR)] |
| 406 | stx %g3,[%l2+(3*CHECKP_GLOBALS_INCR)] |
| 407 | stx %g4,[%l2+(4*CHECKP_GLOBALS_INCR)] |
| 408 | stx %g5,[%l2+(5*CHECKP_GLOBALS_INCR)] |
| 409 | stx %g6,[%l2+(6*CHECKP_GLOBALS_INCR)] |
| 410 | stx %g7,[%l2+(7*CHECKP_GLOBALS_INCR)] |
| 411 | #else |
| 412 | ldx [%l2+(0*CHECKP_GLOBALS_INCR)], %g0 |
| 413 | ldx [%l2+(1*CHECKP_GLOBALS_INCR)], %g1 |
| 414 | ldx [%l2+(2*CHECKP_GLOBALS_INCR)], %g2 |
| 415 | ldx [%l2+(3*CHECKP_GLOBALS_INCR)], %g3 |
| 416 | ldx [%l2+(4*CHECKP_GLOBALS_INCR)], %g4 |
| 417 | ldx [%l2+(5*CHECKP_GLOBALS_INCR)], %g5 |
| 418 | ldx [%l2+(6*CHECKP_GLOBALS_INCR)], %g6 |
| 419 | ldx [%l2+(7*CHECKP_GLOBALS_INCR)], %g7 |
| 420 | #endif |
| 421 | add %l2, (8*CHECKP_GLOBALS_INCR), %l2 |
| 422 | |
| 423 | wrpr %g0, 2, %gl |
| 424 | #ifdef DUMP |
| 425 | stx %g0,[%l2+(0*CHECKP_GLOBALS_INCR)] |
| 426 | stx %g1,[%l2+(1*CHECKP_GLOBALS_INCR)] |
| 427 | stx %g2,[%l2+(2*CHECKP_GLOBALS_INCR)] |
| 428 | stx %g3,[%l2+(3*CHECKP_GLOBALS_INCR)] |
| 429 | stx %g4,[%l2+(4*CHECKP_GLOBALS_INCR)] |
| 430 | stx %g5,[%l2+(5*CHECKP_GLOBALS_INCR)] |
| 431 | stx %g6,[%l2+(6*CHECKP_GLOBALS_INCR)] |
| 432 | stx %g7,[%l2+(7*CHECKP_GLOBALS_INCR)] |
| 433 | #else |
| 434 | ldx [%l2+(0*CHECKP_GLOBALS_INCR)], %g0 |
| 435 | ldx [%l2+(1*CHECKP_GLOBALS_INCR)], %g1 |
| 436 | ldx [%l2+(2*CHECKP_GLOBALS_INCR)], %g2 |
| 437 | ldx [%l2+(3*CHECKP_GLOBALS_INCR)], %g3 |
| 438 | ldx [%l2+(4*CHECKP_GLOBALS_INCR)], %g4 |
| 439 | ldx [%l2+(5*CHECKP_GLOBALS_INCR)], %g5 |
| 440 | ldx [%l2+(6*CHECKP_GLOBALS_INCR)], %g6 |
| 441 | ldx [%l2+(7*CHECKP_GLOBALS_INCR)], %g7 |
| 442 | #endif |
| 443 | add %l2, (8*CHECKP_GLOBALS_INCR), %l2 |
| 444 | |
| 445 | |
| 446 | wrpr %g0, 3, %gl |
| 447 | #ifdef DUMP |
| 448 | stx %g0,[%l2+(0*CHECKP_GLOBALS_INCR)] |
| 449 | stx %g1,[%l2+(1*CHECKP_GLOBALS_INCR)] |
| 450 | stx %g2,[%l2+(2*CHECKP_GLOBALS_INCR)] |
| 451 | stx %g3,[%l2+(3*CHECKP_GLOBALS_INCR)] |
| 452 | stx %g4,[%l2+(4*CHECKP_GLOBALS_INCR)] |
| 453 | stx %g5,[%l2+(5*CHECKP_GLOBALS_INCR)] |
| 454 | stx %g6,[%l2+(6*CHECKP_GLOBALS_INCR)] |
| 455 | stx %g7,[%l2+(7*CHECKP_GLOBALS_INCR)] |
| 456 | #else |
| 457 | ldx [%l2+(0*CHECKP_GLOBALS_INCR)], %g0 |
| 458 | ldx [%l2+(1*CHECKP_GLOBALS_INCR)], %g1 |
| 459 | ldx [%l2+(2*CHECKP_GLOBALS_INCR)], %g2 |
| 460 | ldx [%l2+(3*CHECKP_GLOBALS_INCR)], %g3 |
| 461 | ldx [%l2+(4*CHECKP_GLOBALS_INCR)], %g4 |
| 462 | ldx [%l2+(5*CHECKP_GLOBALS_INCR)], %g5 |
| 463 | ldx [%l2+(6*CHECKP_GLOBALS_INCR)], %g6 |
| 464 | ldx [%l2+(7*CHECKP_GLOBALS_INCR)], %g7 |
| 465 | #endif |
| 466 | |
| 467 | |
| 468 | add %l2, (8*CHECKP_GLOBALS_INCR), %l2 |
| 469 | wrpr %l1, %g0, %gl |
| 470 | |
| 471 | #ifdef DUMP |
| 472 | mov %g5, %l1 |
| 473 | mov %l2, %g5 |
| 474 | mov %g3, %l2 |
| 475 | #else |
| 476 | mov %l2, %g5 |
| 477 | wr %g0, 0x4f, %asi |
| 478 | ldxa [%g0]%asi, %l1 |
| 479 | ldxa [%g0+8]%asi, %l2 |
| 480 | #endif |
| 481 | |
| 482 | |
| 483 | /*}}} */ |
| 484 | |
| 485 | #define ASI_IMMU 0x50 |
| 486 | #define ASI_IMMU_TAG_TARGET_REG 0x50 |
| 487 | #define ASI_IMMU_TAG_TARGET_REG_VAL 0x000 |
| 488 | #define ASI_IMMU_SFSR 0x50 |
| 489 | #define ASI_IMMU_SFSR_VAL 0x018 |
| 490 | #define ASI_IMMU_TSB_BASE_Z_PS0 0x35 |
| 491 | #define ASI_IMMU_TSB_BASE_Z_PS1 0x36 |
| 492 | #define ASI_IMMU_Z_CONFIG 0x37 |
| 493 | #define ASI_IMMU_TSB_BASE_NZ_PS0 0x3D |
| 494 | #define ASI_IMMU_TSB_BASE_NZ_PS1 0x3E |
| 495 | #define ASI_IMMU_NZ_CONFIG 0x3F |
| 496 | |
| 497 | |
| 498 | #define ASI_IMMU_TAG_ACCESS 0x50 |
| 499 | #define ASI_IMMU_TAG_ACCESS_VAL 0x030 |
| 500 | |
| 501 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
| 502 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
| 503 | |
| 504 | #define ASI_PRIMARY_CONTEXT0_REG 0x21 |
| 505 | #define ASI_PRIMARY_CONTEXT0_REG_VAL 0x008 |
| 506 | #define ASI_SECONDARY_CONTEXT0_REG 0x21 |
| 507 | #define ASI_SECONDARY_CONTEXT0_REG_VAL 0x010 |
| 508 | #define ASI_PRIMARY_CONTEXT1_REG 0x21 |
| 509 | #define ASI_PRIMARY_CONTEXT1_REG_VAL 0x108 |
| 510 | #define ASI_SECONDARY_CONTEXT1_REG 0x21 |
| 511 | #define ASI_SECONDARY_CONTEXT1_REG_VAL 0x110 |
| 512 | #define ASI_DMMU_SFSR 0x58 |
| 513 | #define ASI_DMMU_SFSR_VAL 0x018 |
| 514 | #define ASI_DMMU_SFAR 0x58 |
| 515 | #define ASI_DMMU_SFAR_VAL 0x020 |
| 516 | |
| 517 | #define ASI_DMMU_PARTITION_ID 0x58 |
| 518 | #define ASI_DMMU_HWTW_CONFIG 0x40 |
| 519 | #define ASI_DMMU_PARTITION_ID_VAL 0x80 |
| 520 | #define ASI_MMU_RANGE_OFFSET 0x52 |
| 521 | #define MMU_REAL_RANGE_BASE 0x108 |
| 522 | #define MMU_PHYS_OFFSET 0x208 |
| 523 | #define ASI_MMU_MISC 0x54 |
| 524 | #define MMU_MISC_MIN_VA 0x10 |
| 525 | #define MMU_MISC_MAX_VA 0x48 |
| 526 | |
| 527 | |
| 528 | |
| 529 | #ifdef DUMP |
| 530 | /*{{{ dump new n2 regs*/ |
| 531 | mov MMU_MISC_MIN_VA, %g3 |
| 532 | 1: |
| 533 | ldxa [%g3]ASI_MMU_MISC, %g4 |
| 534 | stx %g4, [%g5] |
| 535 | add %g5, 0x8, %g5 |
| 536 | subcc %g3, MMU_MISC_MAX_VA, %g0 |
| 537 | bne 1b |
| 538 | add %g3, 0x8, %g3 |
| 539 | |
| 540 | wr %g0, ASI_MMU_RANGE_OFFSET, %asi |
| 541 | mov MMU_REAL_RANGE_BASE, %g3 |
| 542 | ldxa [%g3]%asi, %g4 |
| 543 | stx %g4, [%g5] |
| 544 | ldxa [%g3+8]%asi, %g4 |
| 545 | stx %g4, [%g5+8] |
| 546 | ldxa [%g3+0x10]%asi, %g4 |
| 547 | stx %g4, [%g5+0x10] |
| 548 | ldxa [%g3+0x18]%asi, %g4 |
| 549 | stx %g4, [%g5+0x18] |
| 550 | add %g5, 0x20, %g5 |
| 551 | |
| 552 | mov MMU_PHYS_OFFSET, %g3 |
| 553 | ldxa [%g3]%asi, %g4 |
| 554 | stx %g4, [%g5] |
| 555 | ldxa [%g3+8]%asi, %g4 |
| 556 | stx %g4, [%g5+8] |
| 557 | ldxa [%g3+0x10]%asi, %g4 |
| 558 | stx %g4, [%g5+0x10] |
| 559 | ldxa [%g3+0x18]%asi, %g4 |
| 560 | stx %g4, [%g5+0x18] |
| 561 | add %g5, 0x20, %g5 |
| 562 | /*}}} */ |
| 563 | /*{{{ */ |
| 564 | ! rdpr %ver, %g4 |
| 565 | stx %g0, [%g5] |
| 566 | add %g5, 0x8, %g5 |
| 567 | ! 0x28 bytes |
| 568 | mov ASI_PRIMARY_CONTEXT0_REG_VAL, %g3 |
| 569 | ldxa [%g3]ASI_PRIMARY_CONTEXT0_REG, %g4 |
| 570 | stx %g4, [%g5] |
| 571 | membar #Sync |
| 572 | mov ASI_SECONDARY_CONTEXT0_REG_VAL, %g3 |
| 573 | ldxa [%g3]ASI_SECONDARY_CONTEXT0_REG, %g4 |
| 574 | stx %g4, [%g5+8] |
| 575 | membar #Sync |
| 576 | add %g5, 0x10, %g5 |
| 577 | mov ASI_PRIMARY_CONTEXT1_REG_VAL, %g3 |
| 578 | ldxa [%g3]ASI_PRIMARY_CONTEXT1_REG, %g4 |
| 579 | stx %g4, [%g5] |
| 580 | membar #Sync |
| 581 | mov ASI_SECONDARY_CONTEXT1_REG_VAL, %g3 |
| 582 | ldxa [%g3]ASI_SECONDARY_CONTEXT1_REG, %g4 |
| 583 | stx %g4, [%g5+8] |
| 584 | membar #Sync |
| 585 | add %g5, 0x10, %g5 |
| 586 | |
| 587 | mov ASI_DMMU_PARTITION_ID_VAL, %g3 |
| 588 | ldxa [%g3]ASI_DMMU_PARTITION_ID, %g4 |
| 589 | stx %g4, [%g5] |
| 590 | add %g5, 0x8, %g5 |
| 591 | mov ASI_DMMU_HWTW_CONFIG, %g3 |
| 592 | ldxa [%g3]ASI_DMMU_PARTITION_ID, %g4 |
| 593 | stx %g4, [%g5] |
| 594 | add %g5, 0x8, %g5 |
| 595 | |
| 596 | |
| 597 | add %g5, 0x20, %g5 |
| 598 | !rdpr %ver, %g4 |
| 599 | stx %g0, [%g5] |
| 600 | add %g5, 0x8, %g5 |
| 601 | |
| 602 | |
| 603 | |
| 604 | |
| 605 | /*}}} */ |
| 606 | #else |
| 607 | /*{{{ load new n2 regs*/ |
| 608 | mov MMU_MISC_MIN_VA, %g3 |
| 609 | 1: |
| 610 | ldx [%g5],%g4 |
| 611 | stxa %g4,[%g3]ASI_MMU_MISC |
| 612 | add %g5, 0x8, %g5 |
| 613 | subcc %g3, MMU_MISC_MAX_VA, %g0 |
| 614 | bne 1b |
| 615 | add %g3, 0x8, %g3 |
| 616 | |
| 617 | wr %g0, ASI_MMU_RANGE_OFFSET, %asi |
| 618 | ldx [%g5],%g4 |
| 619 | mov MMU_REAL_RANGE_BASE, %g3 |
| 620 | stxa %g4,[%g3]%asi |
| 621 | ldx [%g5+8],%g4 |
| 622 | stxa %g4,[%g3+8]%asi |
| 623 | ldx [%g5+0x10],%g4 |
| 624 | stxa %g4,[%g3+0x10]%asi |
| 625 | ldx [%g5+0x18],%g4 |
| 626 | stxa %g4,[%g3+0x18]%asi |
| 627 | add %g5, 0x20, %g5 |
| 628 | |
| 629 | mov MMU_PHYS_OFFSET, %g3 |
| 630 | ldx [%g5],%g4 |
| 631 | stxa %g4,[%g3]%asi |
| 632 | ldx [%g5+8],%g4 |
| 633 | stxa %g4,[%g3+8]%asi |
| 634 | ldx [%g5+0x10],%g4 |
| 635 | stxa %g4,[%g3+0x10]%asi |
| 636 | ldx [%g5+0x18],%g4 |
| 637 | stxa %g4,[%g3+0x18]%asi |
| 638 | add %g5, 0x20, %g5 |
| 639 | /*}}} */ |
| 640 | /*{{{ */ |
| 641 | ! rdpr %ver, %g4 |
| 642 | ! stx %g0, [%g5] |
| 643 | add %g5, 0x8, %g5 |
| 644 | ! 0x28 bytes |
| 645 | mov ASI_PRIMARY_CONTEXT0_REG_VAL, %g3 |
| 646 | ldx [%g5],%g4 |
| 647 | stxa %g4,[%g3]ASI_PRIMARY_CONTEXT0_REG |
| 648 | membar #Sync |
| 649 | mov ASI_SECONDARY_CONTEXT0_REG_VAL, %g3 |
| 650 | ldx [%g5+8],%g4 |
| 651 | stxa %g4,[%g3]ASI_SECONDARY_CONTEXT0_REG |
| 652 | membar #Sync |
| 653 | add %g5, 0x10, %g5 |
| 654 | mov ASI_PRIMARY_CONTEXT1_REG_VAL, %g3 |
| 655 | ldx [%g5] ,%g4 |
| 656 | stxa %g4,[%g3]ASI_PRIMARY_CONTEXT1_REG |
| 657 | membar #Sync |
| 658 | mov ASI_SECONDARY_CONTEXT1_REG_VAL, %g3 |
| 659 | ldx [%g5+8] ,%g4 |
| 660 | stxa %g4,[%g3]ASI_SECONDARY_CONTEXT1_REG |
| 661 | membar #Sync |
| 662 | add %g5, 0x10, %g5 |
| 663 | |
| 664 | mov ASI_DMMU_PARTITION_ID_VAL, %g3 |
| 665 | ldx [%g5] ,%g4 |
| 666 | stxa %g4,[%g3]ASI_DMMU_PARTITION_ID |
| 667 | add %g5, 0x8, %g5 |
| 668 | mov ASI_DMMU_HWTW_CONFIG, %g3 |
| 669 | ldx [%g5] ,%g4 |
| 670 | stxa %g4,[%g3]ASI_DMMU_PARTITION_ID |
| 671 | add %g5, 0x8, %g5 |
| 672 | |
| 673 | |
| 674 | add %g5, 0x20, %g5 |
| 675 | !rdpr %ver, %g4 |
| 676 | ! ldx %g0, [%g5] |
| 677 | add %g5, 0x8, %g5 |
| 678 | |
| 679 | |
| 680 | |
| 681 | |
| 682 | /*}}} */ |
| 683 | #endif |
| 684 | |